blob: d5aacf137e4096fe43b1a99034e648a557b32c6d [file] [log] [blame]
Andrew Lunne2eaa332014-02-15 13:59:53 +01001/*
2 * Marvell RD88F6181 Common Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions that are common between the two
11 * variants of the Marvell Kirkwood Development Board.
12 */
13
14#include "kirkwood.dtsi"
15#include "kirkwood-6281.dtsi"
16
17/ {
18 memory {
19 device_type = "memory";
20 reg = <0x00000000 0x20000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS0,115200n8";
Sebastian Hesselbarthab833612014-04-30 14:56:30 +020025 stdout-path = &uart0;
Andrew Lunne2eaa332014-02-15 13:59:53 +010026 };
27
Andrew Lunne2eaa332014-02-15 13:59:53 +010028 ocp@f1000000 {
Sebastian Hesselbartha9483962014-04-30 14:56:32 +020029 pinctrl: pin-controller@10000 {
Andrew Lunne2eaa332014-02-15 13:59:53 +010030 pinctrl-names = "default";
31
32 pmx_sdio_cd: pmx-sdio-cd {
33 marvell,pins = "mpp28";
34 marvell,function = "gpio";
35 };
36 };
37
38 serial@12000 {
39 status = "okay";
40
41 };
42
43 sata@80000 {
44 status = "okay";
45 nr-ports = <2>;
46 };
47 mvsdio@90000 {
48 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
49 pinctrl-names = "default";
50 status = "okay";
51 cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
52 /* No WP GPIO */
53 };
54 };
55
Andrew Lunn689168a2016-04-03 04:03:45 +020056 dsa {
Andrew Lunne2eaa332014-02-15 13:59:53 +010057 compatible = "marvell,dsa";
58 #address-cells = <2>;
59 #size-cells = <0>;
60
Andrew Lunn4f5e01e2014-09-01 19:35:41 +020061 dsa,ethernet = <&eth0port>;
62 dsa,mii-bus = <&mdio>;
Andrew Lunne2eaa332014-02-15 13:59:53 +010063
64 switch@0 {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 port@0 {
69 reg = <0>;
70 label = "lan1";
71 };
72
73 port@1 {
74 reg = <1>;
75 label = "lan2";
76 };
77
78 port@2 {
79 reg = <2>;
80 label = "lan3";
81 };
82
83 port@3 {
84 reg = <3>;
85 label = "lan4";
86 };
87
88 port@5 {
89 reg = <5>;
90 label = "cpu";
91 };
92 };
93 };
94};
95
96&nand {
97 status = "okay";
98
99 partition@0 {
100 label = "u-boot";
101 reg = <0x0000000 0x100000>;
102 read-only;
103 };
104
105 partition@100000 {
106 label = "uImage";
107 reg = <0x0100000 0x200000>;
108 };
109
110 partition@300000 {
Andrew Lunn4f5e01e2014-09-01 19:35:41 +0200111 label = "rootfs";
Andrew Lunne2eaa332014-02-15 13:59:53 +0100112 reg = <0x0300000 0x500000>;
113 };
114};
115
116&mdio {
117 status = "okay";
Andrew Lunne2eaa332014-02-15 13:59:53 +0100118};
119
120&eth0 {
121 status = "okay";
122 ethernet0-port@0 {
Andrew Lunn4f5e01e2014-09-01 19:35:41 +0200123 speed = <1000>;
124 duplex = <1>;
Andrew Lunne2eaa332014-02-15 13:59:53 +0100125 };
126};
Andrew Lunneb13cf82016-04-03 04:03:47 +0200127
128&pciec {
129 status = "okay";
130};
131
132&pcie0 {
133 status = "okay";
134};