Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * NXP LPC32xx SoC |
| 3 | * |
| 4 | * Copyright 2012 Roland Stigge <stigge@antcom.de> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
Vladimir Zapolskiy | 1a24edd | 2015-10-18 00:35:50 +0300 | [diff] [blame] | 14 | #include "skeleton.dtsi" |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 15 | |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 16 | #include <dt-bindings/clock/lpc32xx-clock.h> |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 17 | #include <dt-bindings/interrupt-controller/irq.h> |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 18 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 19 | / { |
| 20 | compatible = "nxp,lpc3220"; |
| 21 | interrupt-parent = <&mic>; |
| 22 | |
| 23 | cpus { |
Vladimir Zapolskiy | 246d8fc | 2015-10-18 00:35:52 +0300 | [diff] [blame] | 24 | #address-cells = <1>; |
Lorenzo Pieralisi | 73158b7 | 2013-04-18 18:34:51 +0100 | [diff] [blame] | 25 | #size-cells = <0>; |
| 26 | |
Vladimir Zapolskiy | 246d8fc | 2015-10-18 00:35:52 +0300 | [diff] [blame] | 27 | cpu@0 { |
Lorenzo Pieralisi | 73158b7 | 2013-04-18 18:34:51 +0100 | [diff] [blame] | 28 | compatible = "arm,arm926ej-s"; |
| 29 | device_type = "cpu"; |
Vladimir Zapolskiy | 246d8fc | 2015-10-18 00:35:52 +0300 | [diff] [blame] | 30 | reg = <0x0>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 31 | }; |
| 32 | }; |
| 33 | |
Vladimir Zapolskiy | ef5f885 | 2015-11-20 03:05:04 +0200 | [diff] [blame] | 34 | clocks { |
| 35 | xtal_32k: xtal_32k { |
| 36 | compatible = "fixed-clock"; |
| 37 | #clock-cells = <0>; |
| 38 | clock-frequency = <32768>; |
| 39 | clock-output-names = "xtal_32k"; |
| 40 | }; |
| 41 | |
| 42 | xtal: xtal { |
| 43 | compatible = "fixed-clock"; |
| 44 | #clock-cells = <0>; |
| 45 | clock-frequency = <13000000>; |
| 46 | clock-output-names = "xtal"; |
| 47 | }; |
| 48 | }; |
| 49 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 50 | ahb { |
| 51 | #address-cells = <1>; |
| 52 | #size-cells = <1>; |
| 53 | compatible = "simple-bus"; |
Vladimir Zapolskiy | f83ee67 | 2015-10-18 00:35:55 +0300 | [diff] [blame] | 54 | ranges = <0x20000000 0x20000000 0x30000000>, |
| 55 | <0xe0000000 0xe0000000 0x04000000>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 56 | |
| 57 | /* |
| 58 | * Enable either SLC or MLC |
| 59 | */ |
| 60 | slc: flash@20020000 { |
| 61 | compatible = "nxp,lpc3220-slc"; |
| 62 | reg = <0x20020000 0x1000>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 63 | clocks = <&clk LPC32XX_CLK_SLC>; |
Roland Stigge | cb85a9e | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 64 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 65 | }; |
| 66 | |
Roland Stigge | 6d1c3e9 | 2012-06-14 16:16:17 +0200 | [diff] [blame] | 67 | mlc: flash@200a8000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 68 | compatible = "nxp,lpc3220-mlc"; |
Roland Stigge | 6d1c3e9 | 2012-06-14 16:16:17 +0200 | [diff] [blame] | 69 | reg = <0x200a8000 0x11000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 70 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 71 | clocks = <&clk LPC32XX_CLK_MLC>; |
Roland Stigge | cb85a9e | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 72 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 73 | }; |
| 74 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 75 | dma: dma@31000000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 76 | compatible = "arm,pl080", "arm,primecell"; |
| 77 | reg = <0x31000000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 78 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 79 | clocks = <&clk LPC32XX_CLK_DMA>; |
| 80 | clock-names = "apb_pclk"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 81 | }; |
| 82 | |
Vladimir Zapolskiy | aa29efb | 2015-10-18 00:35:57 +0300 | [diff] [blame] | 83 | usb { |
| 84 | #address-cells = <1>; |
| 85 | #size-cells = <1>; |
| 86 | compatible = "simple-bus"; |
| 87 | ranges = <0x0 0x31020000 0x00001000>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 88 | |
Vladimir Zapolskiy | aa29efb | 2015-10-18 00:35:57 +0300 | [diff] [blame] | 89 | /* |
| 90 | * Enable either ohci or usbd (gadget)! |
| 91 | */ |
| 92 | ohci: ohci@0 { |
| 93 | compatible = "nxp,ohci-nxp", "usb-ohci"; |
| 94 | reg = <0x0 0x300>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 95 | interrupt-parent = <&sic1>; |
| 96 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 865e900 | 2015-11-20 03:05:07 +0200 | [diff] [blame] | 97 | clocks = <&usbclk LPC32XX_USB_CLK_HOST>; |
Vladimir Zapolskiy | aa29efb | 2015-10-18 00:35:57 +0300 | [diff] [blame] | 98 | status = "disabled"; |
| 99 | }; |
| 100 | |
| 101 | usbd: usbd@0 { |
| 102 | compatible = "nxp,lpc3220-udc"; |
| 103 | reg = <0x0 0x300>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 104 | interrupt-parent = <&sic1>; |
| 105 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <30 IRQ_TYPE_LEVEL_HIGH>, |
| 107 | <28 IRQ_TYPE_LEVEL_HIGH>, |
| 108 | <26 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | 865e900 | 2015-11-20 03:05:07 +0200 | [diff] [blame] | 109 | clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; |
Vladimir Zapolskiy | aa29efb | 2015-10-18 00:35:57 +0300 | [diff] [blame] | 110 | status = "disabled"; |
| 111 | }; |
| 112 | |
| 113 | i2cusb: i2c@300 { |
| 114 | compatible = "nxp,pnx-i2c"; |
| 115 | reg = <0x300 0x100>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 116 | interrupt-parent = <&sic1>; |
| 117 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 865e900 | 2015-11-20 03:05:07 +0200 | [diff] [blame] | 118 | clocks = <&usbclk LPC32XX_USB_CLK_I2C>; |
Vladimir Zapolskiy | aa29efb | 2015-10-18 00:35:57 +0300 | [diff] [blame] | 119 | #address-cells = <1>; |
| 120 | #size-cells = <0>; |
| 121 | pnx,timeout = <0x64>; |
| 122 | }; |
Vladimir Zapolskiy | 865e900 | 2015-11-20 03:05:07 +0200 | [diff] [blame] | 123 | |
| 124 | usbclk: clock-controller@f00 { |
| 125 | compatible = "nxp,lpc3220-usb-clk"; |
| 126 | reg = <0xf00 0x100>; |
| 127 | #clock-cells = <1>; |
| 128 | }; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 129 | }; |
| 130 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 131 | clcd: clcd@31040000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 132 | compatible = "arm,pl110", "arm,primecell"; |
| 133 | reg = <0x31040000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 134 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 135 | clocks = <&clk LPC32XX_CLK_LCD>; |
| 136 | clock-names = "apb_pclk"; |
Roland Stigge | cb85a9e | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 137 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | mac: ethernet@31060000 { |
| 141 | compatible = "nxp,lpc-eth"; |
| 142 | reg = <0x31060000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 143 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 144 | clocks = <&clk LPC32XX_CLK_MAC>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 145 | }; |
| 146 | |
Vladimir Zapolskiy | f83ee67 | 2015-10-18 00:35:55 +0300 | [diff] [blame] | 147 | emc: memory-controller@31080000 { |
| 148 | compatible = "arm,pl175", "arm,primecell"; |
| 149 | reg = <0x31080000 0x1000>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 150 | clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; |
| 151 | clock-names = "mpmcclk", "apb_pclk"; |
Vladimir Zapolskiy | f83ee67 | 2015-10-18 00:35:55 +0300 | [diff] [blame] | 152 | #address-cells = <1>; |
| 153 | #size-cells = <1>; |
| 154 | |
| 155 | ranges = <0 0xe0000000 0x01000000>, |
| 156 | <1 0xe1000000 0x01000000>, |
| 157 | <2 0xe2000000 0x01000000>, |
| 158 | <3 0xe3000000 0x01000000>; |
| 159 | status = "disabled"; |
| 160 | }; |
| 161 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 162 | apb { |
| 163 | #address-cells = <1>; |
| 164 | #size-cells = <1>; |
| 165 | compatible = "simple-bus"; |
| 166 | ranges = <0x20000000 0x20000000 0x30000000>; |
| 167 | |
Sylvain Lemieux | 961212e | 2016-04-20 09:21:00 -0400 | [diff] [blame] | 168 | /* |
| 169 | * ssp0 and spi1 are shared pins; |
| 170 | * enable one in your board dts, as needed. |
| 171 | */ |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 172 | ssp0: ssp@20084000 { |
| 173 | compatible = "arm,pl022", "arm,primecell"; |
| 174 | reg = <0x20084000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 175 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 176 | clocks = <&clk LPC32XX_CLK_SSP0>; |
| 177 | clock-names = "apb_pclk"; |
Sylvain Lemieux | 961212e | 2016-04-20 09:21:00 -0400 | [diff] [blame] | 178 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | spi1: spi@20088000 { |
| 182 | compatible = "nxp,lpc3220-spi"; |
| 183 | reg = <0x20088000 0x1000>; |
Sylvain Lemieux | 73fdaa0 | 2016-04-20 09:20:58 -0400 | [diff] [blame] | 184 | clocks = <&clk LPC32XX_CLK_SPI1>; |
Sylvain Lemieux | 961212e | 2016-04-20 09:21:00 -0400 | [diff] [blame] | 185 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 186 | }; |
| 187 | |
Sylvain Lemieux | 961212e | 2016-04-20 09:21:00 -0400 | [diff] [blame] | 188 | /* |
| 189 | * ssp1 and spi2 are shared pins; |
| 190 | * enable one in your board dts, as needed. |
| 191 | */ |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 192 | ssp1: ssp@2008c000 { |
| 193 | compatible = "arm,pl022", "arm,primecell"; |
| 194 | reg = <0x2008c000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 195 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 196 | clocks = <&clk LPC32XX_CLK_SSP1>; |
| 197 | clock-names = "apb_pclk"; |
Sylvain Lemieux | 961212e | 2016-04-20 09:21:00 -0400 | [diff] [blame] | 198 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | spi2: spi@20090000 { |
| 202 | compatible = "nxp,lpc3220-spi"; |
| 203 | reg = <0x20090000 0x1000>; |
Sylvain Lemieux | 73fdaa0 | 2016-04-20 09:20:58 -0400 | [diff] [blame] | 204 | clocks = <&clk LPC32XX_CLK_SPI2>; |
Sylvain Lemieux | 961212e | 2016-04-20 09:21:00 -0400 | [diff] [blame] | 205 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | i2s0: i2s@20094000 { |
| 209 | compatible = "nxp,lpc3220-i2s"; |
| 210 | reg = <0x20094000 0x1000>; |
| 211 | }; |
| 212 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 213 | sd: sd@20098000 { |
Roland Stigge | 2c7fa28 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 214 | compatible = "arm,pl18x", "arm,primecell"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 215 | reg = <0x20098000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 216 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, |
| 217 | <13 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 218 | clocks = <&clk LPC32XX_CLK_SD>; |
| 219 | clock-names = "apb_pclk"; |
Roland Stigge | 2c7fa28 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 220 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | i2s1: i2s@2009C000 { |
| 224 | compatible = "nxp,lpc3220-i2s"; |
| 225 | reg = <0x2009C000 0x1000>; |
| 226 | }; |
| 227 | |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 228 | /* UART5 first since it is the default console, ttyS0 */ |
| 229 | uart5: serial@40090000 { |
| 230 | /* actually, ns16550a w/ 64 byte fifos! */ |
| 231 | compatible = "nxp,lpc3220-uart"; |
| 232 | reg = <0x40090000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 233 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 234 | reg-shift = <2>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 235 | clocks = <&clk LPC32XX_CLK_UART5>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 236 | status = "disabled"; |
| 237 | }; |
| 238 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 239 | uart3: serial@40080000 { |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 240 | compatible = "nxp,lpc3220-uart"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 241 | reg = <0x40080000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 242 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 243 | reg-shift = <2>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 244 | clocks = <&clk LPC32XX_CLK_UART3>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 245 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | uart4: serial@40088000 { |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 249 | compatible = "nxp,lpc3220-uart"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 250 | reg = <0x40088000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 251 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 252 | reg-shift = <2>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 253 | clocks = <&clk LPC32XX_CLK_UART4>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 254 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | uart6: serial@40098000 { |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 258 | compatible = "nxp,lpc3220-uart"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 259 | reg = <0x40098000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 260 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 261 | reg-shift = <2>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 262 | clocks = <&clk LPC32XX_CLK_UART6>; |
Roland Stigge | c70426f | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 263 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 264 | }; |
| 265 | |
| 266 | i2c1: i2c@400A0000 { |
| 267 | compatible = "nxp,pnx-i2c"; |
| 268 | reg = <0x400A0000 0x100>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 269 | interrupt-parent = <&sic1>; |
| 270 | interrupts = <19 IRQ_TYPE_LEVEL_LOW>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 271 | #address-cells = <1>; |
| 272 | #size-cells = <0>; |
| 273 | pnx,timeout = <0x64>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 274 | clocks = <&clk LPC32XX_CLK_I2C1>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 275 | }; |
| 276 | |
| 277 | i2c2: i2c@400A8000 { |
| 278 | compatible = "nxp,pnx-i2c"; |
| 279 | reg = <0x400A8000 0x100>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 280 | interrupt-parent = <&sic1>; |
| 281 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 282 | #address-cells = <1>; |
| 283 | #size-cells = <0>; |
| 284 | pnx,timeout = <0x64>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 285 | clocks = <&clk LPC32XX_CLK_I2C2>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 286 | }; |
| 287 | |
Alban Bedel | b7d41c9 | 2012-11-14 13:59:45 +0100 | [diff] [blame] | 288 | mpwm: mpwm@400E8000 { |
| 289 | compatible = "nxp,lpc3220-motor-pwm"; |
| 290 | reg = <0x400E8000 0x78>; |
| 291 | status = "disabled"; |
| 292 | #pwm-cells = <2>; |
| 293 | }; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | fab { |
| 297 | #address-cells = <1>; |
| 298 | #size-cells = <1>; |
| 299 | compatible = "simple-bus"; |
| 300 | ranges = <0x20000000 0x20000000 0x30000000>; |
| 301 | |
Vladimir Zapolskiy | fe86131 | 2015-11-20 03:05:05 +0200 | [diff] [blame] | 302 | /* System Control Block */ |
| 303 | scb { |
| 304 | compatible = "simple-bus"; |
| 305 | ranges = <0x0 0x040004000 0x00001000>; |
| 306 | #address-cells = <1>; |
| 307 | #size-cells = <1>; |
| 308 | |
| 309 | clk: clock-controller@0 { |
| 310 | compatible = "nxp,lpc3220-clk"; |
| 311 | reg = <0x00 0x114>; |
| 312 | #clock-cells = <1>; |
| 313 | |
| 314 | clocks = <&xtal_32k>, <&xtal>; |
| 315 | clock-names = "xtal_32k", "xtal"; |
Vladimir Zapolskiy | c17e937 | 2016-04-18 07:12:00 +0300 | [diff] [blame] | 316 | |
| 317 | assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; |
| 318 | assigned-clock-rates = <208000000>; |
Vladimir Zapolskiy | fe86131 | 2015-11-20 03:05:05 +0200 | [diff] [blame] | 319 | }; |
| 320 | }; |
| 321 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 322 | mic: interrupt-controller@40008000 { |
| 323 | compatible = "nxp,lpc3220-mic"; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 324 | reg = <0x40008000 0x4000>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 325 | interrupt-controller; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 326 | #interrupt-cells = <2>; |
| 327 | }; |
| 328 | |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 329 | sic1: interrupt-controller@4000c000 { |
| 330 | compatible = "nxp,lpc3220-sic"; |
| 331 | reg = <0x4000c000 0x4000>; |
| 332 | interrupt-controller; |
| 333 | #interrupt-cells = <2>; |
| 334 | |
| 335 | interrupt-parent = <&mic>; |
| 336 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>, |
| 337 | <30 IRQ_TYPE_LEVEL_LOW>; |
| 338 | }; |
| 339 | |
| 340 | sic2: interrupt-controller@40010000 { |
| 341 | compatible = "nxp,lpc3220-sic"; |
| 342 | reg = <0x40010000 0x4000>; |
| 343 | interrupt-controller; |
| 344 | #interrupt-cells = <2>; |
| 345 | |
| 346 | interrupt-parent = <&mic>; |
| 347 | interrupts = <1 IRQ_TYPE_LEVEL_LOW>, |
| 348 | <31 IRQ_TYPE_LEVEL_LOW>; |
| 349 | }; |
| 350 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 351 | uart1: serial@40014000 { |
Roland Stigge | ac5ced9 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 352 | compatible = "nxp,lpc3220-hsuart"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 353 | reg = <0x40014000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 354 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | ac5ced9 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 355 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 356 | }; |
| 357 | |
| 358 | uart2: serial@40018000 { |
Roland Stigge | ac5ced9 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 359 | compatible = "nxp,lpc3220-hsuart"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 360 | reg = <0x40018000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 361 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | ac5ced9 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 362 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 363 | }; |
| 364 | |
Roland Stigge | ac5ced9 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 365 | uart7: serial@4001c000 { |
| 366 | compatible = "nxp,lpc3220-hsuart"; |
| 367 | reg = <0x4001c000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 368 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | ac5ced9 | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 369 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 370 | }; |
| 371 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 372 | rtc: rtc@40024000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 373 | compatible = "nxp,lpc3220-rtc"; |
| 374 | reg = <0x40024000 0x1000>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 375 | interrupt-parent = <&sic1>; |
| 376 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 377 | clocks = <&clk LPC32XX_CLK_RTC>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 378 | }; |
| 379 | |
| 380 | gpio: gpio@40028000 { |
| 381 | compatible = "nxp,lpc3220-gpio"; |
| 382 | reg = <0x40028000 0x1000>; |
Roland Stigge | a035254 | 2012-05-19 12:28:53 +0200 | [diff] [blame] | 383 | gpio-controller; |
| 384 | #gpio-cells = <3>; /* bank, pin, flags */ |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 385 | }; |
| 386 | |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 387 | timer4: timer@4002C000 { |
| 388 | compatible = "nxp,lpc3220-timer"; |
| 389 | reg = <0x4002C000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 390 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 391 | clocks = <&clk LPC32XX_CLK_TIMER4>; |
| 392 | clock-names = "timerclk"; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 393 | status = "disabled"; |
| 394 | }; |
| 395 | |
| 396 | timer5: timer@40030000 { |
| 397 | compatible = "nxp,lpc3220-timer"; |
| 398 | reg = <0x40030000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 399 | interrupts = <4 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 400 | clocks = <&clk LPC32XX_CLK_TIMER5>; |
| 401 | clock-names = "timerclk"; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 402 | status = "disabled"; |
| 403 | }; |
| 404 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 405 | watchdog: watchdog@4003C000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 406 | compatible = "nxp,pnx4008-wdt"; |
| 407 | reg = <0x4003C000 0x1000>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 408 | clocks = <&clk LPC32XX_CLK_WDOG>; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 409 | }; |
| 410 | |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 411 | timer0: timer@40044000 { |
| 412 | compatible = "nxp,lpc3220-timer"; |
| 413 | reg = <0x40044000 0x1000>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 414 | clocks = <&clk LPC32XX_CLK_TIMER0>; |
| 415 | clock-names = "timerclk"; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 416 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 417 | }; |
| 418 | |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 419 | /* |
| 420 | * TSC vs. ADC: Since those two share the same |
| 421 | * hardware, you need to choose from one of the |
| 422 | * following two and do 'status = "okay";' for one of |
| 423 | * them |
| 424 | */ |
| 425 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 426 | adc: adc@40048000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 427 | compatible = "nxp,lpc3220-adc"; |
| 428 | reg = <0x40048000 0x1000>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 429 | interrupt-parent = <&sic1>; |
| 430 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 431 | clocks = <&clk LPC32XX_CLK_ADC>; |
Roland Stigge | cb85a9e | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 432 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 433 | }; |
| 434 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 435 | tsc: tsc@40048000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 436 | compatible = "nxp,lpc3220-tsc"; |
| 437 | reg = <0x40048000 0x1000>; |
Vladimir Zapolskiy | 9b8ad3fb | 2016-04-26 00:02:23 +0300 | [diff] [blame] | 438 | interrupt-parent = <&sic1>; |
| 439 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 440 | clocks = <&clk LPC32XX_CLK_ADC>; |
Roland Stigge | cb85a9e | 2012-06-14 16:16:18 +0200 | [diff] [blame] | 441 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 442 | }; |
| 443 | |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 444 | timer1: timer@4004C000 { |
| 445 | compatible = "nxp,lpc3220-timer"; |
| 446 | reg = <0x4004C000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 447 | interrupts = <17 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 448 | clocks = <&clk LPC32XX_CLK_TIMER1>; |
| 449 | clock-names = "timerclk"; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 450 | }; |
| 451 | |
Vladimir Zapolskiy | 25de7c9 | 2015-10-18 00:35:51 +0300 | [diff] [blame] | 452 | key: key@40050000 { |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 453 | compatible = "nxp,lpc3220-key"; |
| 454 | reg = <0x40050000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 455 | interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; |
Roland Stigge | a6d1be0 | 2012-06-14 16:16:17 +0200 | [diff] [blame] | 456 | status = "disabled"; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 457 | }; |
| 458 | |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 459 | timer2: timer@40058000 { |
| 460 | compatible = "nxp,lpc3220-timer"; |
| 461 | reg = <0x40058000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 462 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 463 | clocks = <&clk LPC32XX_CLK_TIMER2>; |
| 464 | clock-names = "timerclk"; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 465 | status = "disabled"; |
| 466 | }; |
| 467 | |
Vladimir Zapolskiy | 2a6c656 | 2015-10-18 00:35:53 +0300 | [diff] [blame] | 468 | pwm1: pwm@4005C000 { |
Alexandre Pereira da Silva | de63985 | 2012-07-20 13:33:09 +0200 | [diff] [blame] | 469 | compatible = "nxp,lpc3220-pwm"; |
Vladimir Zapolskiy | 2a6c656 | 2015-10-18 00:35:53 +0300 | [diff] [blame] | 470 | reg = <0x4005C000 0x4>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 471 | clocks = <&clk LPC32XX_CLK_PWM1>; |
Vladimir Zapolskiy | 2a6c656 | 2015-10-18 00:35:53 +0300 | [diff] [blame] | 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
| 475 | pwm2: pwm@4005C004 { |
| 476 | compatible = "nxp,lpc3220-pwm"; |
| 477 | reg = <0x4005C004 0x4>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 478 | clocks = <&clk LPC32XX_CLK_PWM2>; |
Alexandre Pereira da Silva | de63985 | 2012-07-20 13:33:09 +0200 | [diff] [blame] | 479 | status = "disabled"; |
| 480 | }; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 481 | |
| 482 | timer3: timer@40060000 { |
| 483 | compatible = "nxp,lpc3220-timer"; |
| 484 | reg = <0x40060000 0x1000>; |
Vladimir Zapolskiy | b715802 | 2015-11-20 03:28:40 +0200 | [diff] [blame] | 485 | interrupts = <19 IRQ_TYPE_LEVEL_LOW>; |
Vladimir Zapolskiy | 93898eb | 2015-11-20 03:05:06 +0200 | [diff] [blame] | 486 | clocks = <&clk LPC32XX_CLK_TIMER3>; |
| 487 | clock-names = "timerclk"; |
Vladimir Zapolskiy | c1aa700 | 2015-10-18 00:41:06 +0300 | [diff] [blame] | 488 | status = "disabled"; |
| 489 | }; |
Roland Stigge | e04920d | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 490 | }; |
| 491 | }; |
| 492 | }; |