Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7794 SoC |
| 3 | * |
| 4 | * Copyright (C) 2014 Renesas Electronics Corporation |
| 5 | * Copyright (C) 2014 Ulrich Hecht |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 9 | * kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #include <dt-bindings/clock/r8a7794-clock.h> |
| 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
Geert Uytterhoeven | 0761ff2 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 15 | #include <dt-bindings/power/r8a7794-sysc.h> |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 16 | |
| 17 | / { |
| 18 | compatible = "renesas,r8a7794"; |
| 19 | interrupt-parent = <&gic>; |
| 20 | #address-cells = <2>; |
| 21 | #size-cells = <2>; |
| 22 | |
Sergei Shtylyov | 740b4a9 | 2015-08-11 00:59:24 +0300 | [diff] [blame] | 23 | aliases { |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 24 | i2c0 = &i2c0; |
| 25 | i2c1 = &i2c1; |
| 26 | i2c2 = &i2c2; |
| 27 | i2c3 = &i2c3; |
| 28 | i2c4 = &i2c4; |
| 29 | i2c5 = &i2c5; |
Simon Horman | aa9b992 | 2016-03-17 16:35:17 +0900 | [diff] [blame] | 30 | i2c6 = &i2c6; |
| 31 | i2c7 = &i2c7; |
Sergei Shtylyov | 740b4a9 | 2015-08-11 00:59:24 +0300 | [diff] [blame] | 32 | spi0 = &qspi; |
Sergei Shtylyov | 1afe77c | 2015-08-20 01:22:24 +0300 | [diff] [blame] | 33 | vin0 = &vin0; |
| 34 | vin1 = &vin1; |
Sergei Shtylyov | 740b4a9 | 2015-08-11 00:59:24 +0300 | [diff] [blame] | 35 | }; |
| 36 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 37 | cpus { |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <0>; |
| 40 | |
| 41 | cpu0: cpu@0 { |
| 42 | device_type = "cpu"; |
| 43 | compatible = "arm,cortex-a7"; |
| 44 | reg = <0>; |
| 45 | clock-frequency = <1000000000>; |
Geert Uytterhoeven | 0761ff2 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 46 | power-domains = <&sysc R8A7794_PD_CA7_CPU0>; |
Geert Uytterhoeven | d12a384 | 2015-06-02 14:34:35 +0200 | [diff] [blame] | 47 | next-level-cache = <&L2_CA7>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | cpu1: cpu@1 { |
| 51 | device_type = "cpu"; |
| 52 | compatible = "arm,cortex-a7"; |
| 53 | reg = <1>; |
| 54 | clock-frequency = <1000000000>; |
Geert Uytterhoeven | 0761ff2 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 55 | power-domains = <&sysc R8A7794_PD_CA7_CPU1>; |
Geert Uytterhoeven | d12a384 | 2015-06-02 14:34:35 +0200 | [diff] [blame] | 56 | next-level-cache = <&L2_CA7>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 57 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 58 | |
Geert Uytterhoeven | 34ea4b4 | 2016-05-20 09:09:59 +0200 | [diff] [blame] | 59 | L2_CA7: cache-controller@0 { |
| 60 | compatible = "cache"; |
| 61 | reg = <0>; |
| 62 | power-domains = <&sysc R8A7794_PD_CA7_SCU>; |
| 63 | cache-unified; |
| 64 | cache-level = <2>; |
| 65 | }; |
Geert Uytterhoeven | d12a384 | 2015-06-02 14:34:35 +0200 | [diff] [blame] | 66 | }; |
| 67 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 68 | gic: interrupt-controller@f1001000 { |
Geert Uytterhoeven | c73ddf4 | 2015-06-17 15:03:36 +0200 | [diff] [blame] | 69 | compatible = "arm,gic-400"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 70 | #interrupt-cells = <3>; |
| 71 | #address-cells = <0>; |
| 72 | interrupt-controller; |
| 73 | reg = <0 0xf1001000 0 0x1000>, |
| 74 | <0 0xf1002000 0 0x1000>, |
| 75 | <0 0xf1004000 0 0x2000>, |
| 76 | <0 0xf1006000 0 0x2000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 77 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 80 | gpio0: gpio@e6050000 { |
| 81 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 82 | reg = <0 0xe6050000 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 83 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 84 | #gpio-cells = <2>; |
| 85 | gpio-controller; |
| 86 | gpio-ranges = <&pfc 0 0 32>; |
| 87 | #interrupt-cells = <2>; |
| 88 | interrupt-controller; |
| 89 | clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 90 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | gpio1: gpio@e6051000 { |
| 94 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 95 | reg = <0 0xe6051000 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 96 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 97 | #gpio-cells = <2>; |
| 98 | gpio-controller; |
| 99 | gpio-ranges = <&pfc 0 32 26>; |
| 100 | #interrupt-cells = <2>; |
| 101 | interrupt-controller; |
| 102 | clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 103 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | gpio2: gpio@e6052000 { |
| 107 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 108 | reg = <0 0xe6052000 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 109 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 110 | #gpio-cells = <2>; |
| 111 | gpio-controller; |
| 112 | gpio-ranges = <&pfc 0 64 32>; |
| 113 | #interrupt-cells = <2>; |
| 114 | interrupt-controller; |
| 115 | clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 116 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | gpio3: gpio@e6053000 { |
| 120 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 121 | reg = <0 0xe6053000 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 122 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 123 | #gpio-cells = <2>; |
| 124 | gpio-controller; |
| 125 | gpio-ranges = <&pfc 0 96 32>; |
| 126 | #interrupt-cells = <2>; |
| 127 | interrupt-controller; |
| 128 | clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 129 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | gpio4: gpio@e6054000 { |
| 133 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 134 | reg = <0 0xe6054000 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 135 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 136 | #gpio-cells = <2>; |
| 137 | gpio-controller; |
| 138 | gpio-ranges = <&pfc 0 128 32>; |
| 139 | #interrupt-cells = <2>; |
| 140 | interrupt-controller; |
| 141 | clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 142 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | gpio5: gpio@e6055000 { |
| 146 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 147 | reg = <0 0xe6055000 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 148 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 149 | #gpio-cells = <2>; |
| 150 | gpio-controller; |
| 151 | gpio-ranges = <&pfc 0 160 28>; |
| 152 | #interrupt-cells = <2>; |
| 153 | interrupt-controller; |
| 154 | clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 155 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | gpio6: gpio@e6055400 { |
| 159 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; |
| 160 | reg = <0 0xe6055400 0 0x50>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 161 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 162 | #gpio-cells = <2>; |
| 163 | gpio-controller; |
| 164 | gpio-ranges = <&pfc 0 192 26>; |
| 165 | #interrupt-cells = <2>; |
| 166 | interrupt-controller; |
| 167 | clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 168 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | e8f5de3 | 2015-08-09 01:09:31 +0300 | [diff] [blame] | 169 | }; |
| 170 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 171 | cmt0: timer@ffca0000 { |
| 172 | compatible = "renesas,cmt-48-gen2"; |
| 173 | reg = <0 0xffca0000 0 0x1004>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 174 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 175 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 176 | clocks = <&mstp1_clks R8A7794_CLK_CMT0>; |
| 177 | clock-names = "fck"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 178 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 179 | |
| 180 | renesas,channels-mask = <0x60>; |
| 181 | |
| 182 | status = "disabled"; |
| 183 | }; |
| 184 | |
| 185 | cmt1: timer@e6130000 { |
| 186 | compatible = "renesas,cmt-48-gen2"; |
| 187 | reg = <0 0xe6130000 0 0x1004>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 188 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 189 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 190 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| 191 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| 192 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| 193 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| 194 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| 195 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 196 | clocks = <&mstp3_clks R8A7794_CLK_CMT1>; |
| 197 | clock-names = "fck"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 198 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 199 | |
| 200 | renesas,channels-mask = <0xff>; |
| 201 | |
| 202 | status = "disabled"; |
| 203 | }; |
| 204 | |
Hisashi Nakamura | da33648 | 2014-09-12 10:52:06 +0200 | [diff] [blame] | 205 | timer { |
| 206 | compatible = "arm,armv7-timer"; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 207 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 208 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 209 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 210 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Hisashi Nakamura | da33648 | 2014-09-12 10:52:06 +0200 | [diff] [blame] | 211 | }; |
| 212 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 213 | irqc0: interrupt-controller@e61c0000 { |
| 214 | compatible = "renesas,irqc-r8a7794", "renesas,irqc"; |
| 215 | #interrupt-cells = <2>; |
| 216 | interrupt-controller; |
| 217 | reg = <0 0xe61c0000 0 0x200>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 218 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 219 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 220 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| 221 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 222 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 223 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 224 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 225 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 226 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| 227 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | 1c5ca5d | 2015-03-18 19:56:01 +0100 | [diff] [blame] | 228 | clocks = <&mstp4_clks R8A7794_CLK_IRQC>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 229 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 230 | }; |
| 231 | |
Sergei Shtylyov | fd1683c | 2015-07-28 01:29:31 +0300 | [diff] [blame] | 232 | pfc: pin-controller@e6060000 { |
| 233 | compatible = "renesas,pfc-r8a7794"; |
| 234 | reg = <0 0xe6060000 0 0x11c>; |
Sergei Shtylyov | fd1683c | 2015-07-28 01:29:31 +0300 | [diff] [blame] | 235 | }; |
| 236 | |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 237 | dmac0: dma-controller@e6700000 { |
Simon Horman | 0a3d058 | 2015-11-13 11:23:51 +0900 | [diff] [blame] | 238 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 239 | reg = <0 0xe6700000 0 0x20000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 240 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
| 241 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| 242 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| 243 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| 244 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| 245 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| 246 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| 247 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| 248 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| 249 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| 250 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| 251 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| 252 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| 253 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| 254 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| 255 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 256 | interrupt-names = "error", |
| 257 | "ch0", "ch1", "ch2", "ch3", |
| 258 | "ch4", "ch5", "ch6", "ch7", |
| 259 | "ch8", "ch9", "ch10", "ch11", |
| 260 | "ch12", "ch13", "ch14"; |
| 261 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; |
| 262 | clock-names = "fck"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 263 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 264 | #dma-cells = <1>; |
| 265 | dma-channels = <15>; |
| 266 | }; |
| 267 | |
| 268 | dmac1: dma-controller@e6720000 { |
Simon Horman | 0a3d058 | 2015-11-13 11:23:51 +0900 | [diff] [blame] | 269 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 270 | reg = <0 0xe6720000 0 0x20000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 271 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| 272 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| 273 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| 274 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| 275 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| 276 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| 277 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| 278 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| 279 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| 280 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| 281 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| 282 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| 283 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| 284 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| 285 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| 286 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 287 | interrupt-names = "error", |
| 288 | "ch0", "ch1", "ch2", "ch3", |
| 289 | "ch4", "ch5", "ch6", "ch7", |
| 290 | "ch8", "ch9", "ch10", "ch11", |
| 291 | "ch12", "ch13", "ch14"; |
| 292 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; |
| 293 | clock-names = "fck"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 294 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Laurent Pinchart | bd84748 | 2015-01-27 19:12:17 +0200 | [diff] [blame] | 295 | #dma-cells = <1>; |
| 296 | dma-channels = <15>; |
| 297 | }; |
| 298 | |
Sergei Shtylyov | 298e4ee | 2016-07-28 00:02:18 +0300 | [diff] [blame] | 299 | audma0: dma-controller@ec700000 { |
| 300 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
| 301 | reg = <0 0xec700000 0 0x10000>; |
| 302 | interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH |
| 303 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH |
| 304 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH |
| 305 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH |
| 306 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH |
| 307 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH |
| 308 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH |
| 309 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH |
| 310 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH |
| 311 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH |
| 312 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH |
| 313 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH |
| 314 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH |
| 315 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; |
| 316 | interrupt-names = "error", |
| 317 | "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", |
| 318 | "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", |
| 319 | "ch12"; |
| 320 | clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; |
| 321 | clock-names = "fck"; |
| 322 | power-domains = <&cpg_clocks>; |
| 323 | #dma-cells = <1>; |
| 324 | dma-channels = <13>; |
| 325 | }; |
| 326 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 327 | scifa0: serial@e6c40000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 328 | compatible = "renesas,scifa-r8a7794", |
| 329 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 330 | reg = <0 0xe6c40000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 331 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 332 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 333 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 334 | dmas = <&dmac0 0x21>, <&dmac0 0x22>, |
| 335 | <&dmac1 0x21>, <&dmac1 0x22>; |
| 336 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 337 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 338 | status = "disabled"; |
| 339 | }; |
| 340 | |
| 341 | scifa1: serial@e6c50000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 342 | compatible = "renesas,scifa-r8a7794", |
| 343 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 344 | reg = <0 0xe6c50000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 345 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 346 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 347 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 348 | dmas = <&dmac0 0x25>, <&dmac0 0x26>, |
| 349 | <&dmac1 0x25>, <&dmac1 0x26>; |
| 350 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 351 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 352 | status = "disabled"; |
| 353 | }; |
| 354 | |
| 355 | scifa2: serial@e6c60000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 356 | compatible = "renesas,scifa-r8a7794", |
| 357 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 358 | reg = <0 0xe6c60000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 359 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 360 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 361 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 362 | dmas = <&dmac0 0x27>, <&dmac0 0x28>, |
| 363 | <&dmac1 0x27>, <&dmac1 0x28>; |
| 364 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 365 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 366 | status = "disabled"; |
| 367 | }; |
| 368 | |
| 369 | scifa3: serial@e6c70000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 370 | compatible = "renesas,scifa-r8a7794", |
| 371 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 372 | reg = <0 0xe6c70000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 373 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 374 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 375 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 376 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, |
| 377 | <&dmac1 0x1b>, <&dmac1 0x1c>; |
| 378 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 379 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 380 | status = "disabled"; |
| 381 | }; |
| 382 | |
| 383 | scifa4: serial@e6c78000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 384 | compatible = "renesas,scifa-r8a7794", |
| 385 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 386 | reg = <0 0xe6c78000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 387 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 388 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 389 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 390 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>, |
| 391 | <&dmac1 0x1f>, <&dmac1 0x20>; |
| 392 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 393 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 394 | status = "disabled"; |
| 395 | }; |
| 396 | |
| 397 | scifa5: serial@e6c80000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 398 | compatible = "renesas,scifa-r8a7794", |
| 399 | "renesas,rcar-gen2-scifa", "renesas,scifa"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 400 | reg = <0 0xe6c80000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 401 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 402 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 403 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 404 | dmas = <&dmac0 0x23>, <&dmac0 0x24>, |
| 405 | <&dmac1 0x23>, <&dmac1 0x24>; |
| 406 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 407 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 408 | status = "disabled"; |
| 409 | }; |
| 410 | |
| 411 | scifb0: serial@e6c20000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 412 | compatible = "renesas,scifb-r8a7794", |
| 413 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 414 | reg = <0 0xe6c20000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 415 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 416 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 417 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 418 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, |
| 419 | <&dmac1 0x3d>, <&dmac1 0x3e>; |
| 420 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 421 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 422 | status = "disabled"; |
| 423 | }; |
| 424 | |
| 425 | scifb1: serial@e6c30000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 426 | compatible = "renesas,scifb-r8a7794", |
| 427 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 428 | reg = <0 0xe6c30000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 429 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 430 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 431 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 432 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>, |
| 433 | <&dmac1 0x19>, <&dmac1 0x1a>; |
| 434 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 435 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 436 | status = "disabled"; |
| 437 | }; |
| 438 | |
| 439 | scifb2: serial@e6ce0000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 440 | compatible = "renesas,scifb-r8a7794", |
| 441 | "renesas,rcar-gen2-scifb", "renesas,scifb"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 442 | reg = <0 0xe6ce0000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 443 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 444 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; |
Laurent Pinchart | 1b463bd | 2016-01-29 10:47:40 +0100 | [diff] [blame] | 445 | clock-names = "fck"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 446 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, |
| 447 | <&dmac1 0x1d>, <&dmac1 0x1e>; |
| 448 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 449 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 450 | status = "disabled"; |
| 451 | }; |
| 452 | |
| 453 | scif0: serial@e6e60000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 454 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
| 455 | "renesas,scif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 456 | reg = <0 0xe6e60000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 457 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 458 | clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, |
| 459 | <&scif_clk>; |
| 460 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 461 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>, |
| 462 | <&dmac1 0x29>, <&dmac1 0x2a>; |
| 463 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 464 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 465 | status = "disabled"; |
| 466 | }; |
| 467 | |
| 468 | scif1: serial@e6e68000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 469 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
| 470 | "renesas,scif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 471 | reg = <0 0xe6e68000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 472 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 473 | clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, |
| 474 | <&scif_clk>; |
| 475 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 476 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, |
| 477 | <&dmac1 0x2d>, <&dmac1 0x2e>; |
| 478 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 479 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 480 | status = "disabled"; |
| 481 | }; |
| 482 | |
| 483 | scif2: serial@e6e58000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 484 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
| 485 | "renesas,scif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 486 | reg = <0 0xe6e58000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 487 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 488 | clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, |
| 489 | <&scif_clk>; |
| 490 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 491 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, |
| 492 | <&dmac1 0x2b>, <&dmac1 0x2c>; |
| 493 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 494 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 495 | status = "disabled"; |
| 496 | }; |
| 497 | |
| 498 | scif3: serial@e6ea8000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 499 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
| 500 | "renesas,scif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 501 | reg = <0 0xe6ea8000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 502 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 503 | clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, |
| 504 | <&scif_clk>; |
| 505 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 506 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>, |
| 507 | <&dmac1 0x2f>, <&dmac1 0x30>; |
| 508 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 509 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 510 | status = "disabled"; |
| 511 | }; |
| 512 | |
| 513 | scif4: serial@e6ee0000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 514 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
| 515 | "renesas,scif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 516 | reg = <0 0xe6ee0000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 517 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 518 | clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, |
| 519 | <&scif_clk>; |
| 520 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 521 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, |
| 522 | <&dmac1 0xfb>, <&dmac1 0xfc>; |
| 523 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 524 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 525 | status = "disabled"; |
| 526 | }; |
| 527 | |
| 528 | scif5: serial@e6ee8000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 529 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
| 530 | "renesas,scif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 531 | reg = <0 0xe6ee8000 0 64>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 532 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 533 | clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, |
| 534 | <&scif_clk>; |
| 535 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 536 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, |
| 537 | <&dmac1 0xfd>, <&dmac1 0xfe>; |
| 538 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 539 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 540 | status = "disabled"; |
| 541 | }; |
| 542 | |
| 543 | hscif0: serial@e62c0000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 544 | compatible = "renesas,hscif-r8a7794", |
| 545 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 546 | reg = <0 0xe62c0000 0 96>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 547 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 548 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, |
| 549 | <&scif_clk>; |
| 550 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 551 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>, |
| 552 | <&dmac1 0x39>, <&dmac1 0x3a>; |
| 553 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 554 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | hscif1: serial@e62c8000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 559 | compatible = "renesas,hscif-r8a7794", |
| 560 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 561 | reg = <0 0xe62c8000 0 96>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 562 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 563 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, |
| 564 | <&scif_clk>; |
| 565 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 566 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, |
| 567 | <&dmac1 0x4d>, <&dmac1 0x4e>; |
| 568 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 569 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 570 | status = "disabled"; |
| 571 | }; |
| 572 | |
| 573 | hscif2: serial@e62d0000 { |
Geert Uytterhoeven | 06930a1 | 2016-01-29 10:32:07 +0100 | [diff] [blame] | 574 | compatible = "renesas,hscif-r8a7794", |
| 575 | "renesas,rcar-gen2-hscif", "renesas,hscif"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 576 | reg = <0 0xe62d0000 0 96>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 577 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 578 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, |
| 579 | <&scif_clk>; |
| 580 | clock-names = "fck", "brg_int", "scif_clk"; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 581 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, |
| 582 | <&dmac1 0x3b>, <&dmac1 0x3c>; |
| 583 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 584 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 585 | status = "disabled"; |
| 586 | }; |
| 587 | |
Laurent Pinchart | 82818d3 | 2015-01-27 10:45:55 +0200 | [diff] [blame] | 588 | ether: ethernet@ee700000 { |
| 589 | compatible = "renesas,ether-r8a7794"; |
| 590 | reg = <0 0xee700000 0 0x400>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 591 | interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 82818d3 | 2015-01-27 10:45:55 +0200 | [diff] [blame] | 592 | clocks = <&mstp8_clks R8A7794_CLK_ETHER>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 593 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Laurent Pinchart | 82818d3 | 2015-01-27 10:45:55 +0200 | [diff] [blame] | 594 | phy-mode = "rmii"; |
| 595 | #address-cells = <1>; |
| 596 | #size-cells = <0>; |
| 597 | status = "disabled"; |
| 598 | }; |
| 599 | |
Sergei Shtylyov | 89aac8a | 2016-02-17 23:45:10 +0300 | [diff] [blame] | 600 | avb: ethernet@e6800000 { |
| 601 | compatible = "renesas,etheravb-r8a7794", |
| 602 | "renesas,etheravb-rcar-gen2"; |
| 603 | reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; |
| 604 | interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
| 605 | clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 606 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 89aac8a | 2016-02-17 23:45:10 +0300 | [diff] [blame] | 607 | #address-cells = <1>; |
| 608 | #size-cells = <0>; |
| 609 | status = "disabled"; |
| 610 | }; |
| 611 | |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 612 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
| 613 | i2c0: i2c@e6508000 { |
| 614 | compatible = "renesas,i2c-r8a7794"; |
| 615 | reg = <0 0xe6508000 0 0x40>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 616 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 617 | clocks = <&mstp9_clks R8A7794_CLK_I2C0>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 618 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 619 | #address-cells = <1>; |
| 620 | #size-cells = <0>; |
Wolfram Sang | 691cd0a | 2015-12-08 10:37:52 +0100 | [diff] [blame] | 621 | i2c-scl-internal-delay-ns = <6>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 622 | status = "disabled"; |
| 623 | }; |
| 624 | |
| 625 | i2c1: i2c@e6518000 { |
| 626 | compatible = "renesas,i2c-r8a7794"; |
| 627 | reg = <0 0xe6518000 0 0x40>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 628 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 629 | clocks = <&mstp9_clks R8A7794_CLK_I2C1>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 630 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 631 | #address-cells = <1>; |
| 632 | #size-cells = <0>; |
Wolfram Sang | 691cd0a | 2015-12-08 10:37:52 +0100 | [diff] [blame] | 633 | i2c-scl-internal-delay-ns = <6>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 634 | status = "disabled"; |
| 635 | }; |
| 636 | |
| 637 | i2c2: i2c@e6530000 { |
| 638 | compatible = "renesas,i2c-r8a7794"; |
| 639 | reg = <0 0xe6530000 0 0x40>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 640 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 641 | clocks = <&mstp9_clks R8A7794_CLK_I2C2>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 642 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 643 | #address-cells = <1>; |
| 644 | #size-cells = <0>; |
Wolfram Sang | 691cd0a | 2015-12-08 10:37:52 +0100 | [diff] [blame] | 645 | i2c-scl-internal-delay-ns = <6>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 646 | status = "disabled"; |
| 647 | }; |
| 648 | |
| 649 | i2c3: i2c@e6540000 { |
| 650 | compatible = "renesas,i2c-r8a7794"; |
| 651 | reg = <0 0xe6540000 0 0x40>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 652 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 653 | clocks = <&mstp9_clks R8A7794_CLK_I2C3>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 654 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 655 | #address-cells = <1>; |
| 656 | #size-cells = <0>; |
Wolfram Sang | 691cd0a | 2015-12-08 10:37:52 +0100 | [diff] [blame] | 657 | i2c-scl-internal-delay-ns = <6>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 658 | status = "disabled"; |
| 659 | }; |
| 660 | |
| 661 | i2c4: i2c@e6520000 { |
| 662 | compatible = "renesas,i2c-r8a7794"; |
| 663 | reg = <0 0xe6520000 0 0x40>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 664 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 665 | clocks = <&mstp9_clks R8A7794_CLK_I2C4>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 666 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 667 | #address-cells = <1>; |
| 668 | #size-cells = <0>; |
Wolfram Sang | 691cd0a | 2015-12-08 10:37:52 +0100 | [diff] [blame] | 669 | i2c-scl-internal-delay-ns = <6>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 670 | status = "disabled"; |
| 671 | }; |
| 672 | |
| 673 | i2c5: i2c@e6528000 { |
| 674 | compatible = "renesas,i2c-r8a7794"; |
| 675 | reg = <0 0xe6528000 0 0x40>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 676 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 677 | clocks = <&mstp9_clks R8A7794_CLK_I2C5>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 678 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 679 | #address-cells = <1>; |
| 680 | #size-cells = <0>; |
Wolfram Sang | 691cd0a | 2015-12-08 10:37:52 +0100 | [diff] [blame] | 681 | i2c-scl-internal-delay-ns = <6>; |
Sergei Shtylyov | 5428521 | 2015-08-20 01:00:09 +0300 | [diff] [blame] | 682 | status = "disabled"; |
| 683 | }; |
| 684 | |
Simon Horman | aa9b992 | 2016-03-17 16:35:17 +0900 | [diff] [blame] | 685 | i2c6: i2c@e6500000 { |
| 686 | compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; |
| 687 | reg = <0 0xe6500000 0 0x425>; |
| 688 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| 689 | clocks = <&mstp3_clks R8A7794_CLK_IIC0>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 690 | dmas = <&dmac0 0x61>, <&dmac0 0x62>, |
| 691 | <&dmac1 0x61>, <&dmac1 0x62>; |
| 692 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 693 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Simon Horman | aa9b992 | 2016-03-17 16:35:17 +0900 | [diff] [blame] | 694 | #address-cells = <1>; |
| 695 | #size-cells = <0>; |
| 696 | status = "disabled"; |
| 697 | }; |
| 698 | |
| 699 | i2c7: i2c@e6510000 { |
| 700 | compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; |
| 701 | reg = <0 0xe6510000 0 0x425>; |
| 702 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
| 703 | clocks = <&mstp3_clks R8A7794_CLK_IIC1>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 704 | dmas = <&dmac0 0x65>, <&dmac0 0x66>, |
| 705 | <&dmac1 0x65>, <&dmac1 0x66>; |
| 706 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 707 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Simon Horman | aa9b992 | 2016-03-17 16:35:17 +0900 | [diff] [blame] | 708 | #address-cells = <1>; |
| 709 | #size-cells = <0>; |
| 710 | status = "disabled"; |
| 711 | }; |
| 712 | |
Sergei Shtylyov | 6cdf6ba | 2015-07-31 00:54:05 +0300 | [diff] [blame] | 713 | mmcif0: mmc@ee200000 { |
| 714 | compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; |
| 715 | reg = <0 0xee200000 0 0x80>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 716 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 6cdf6ba | 2015-07-31 00:54:05 +0300 | [diff] [blame] | 717 | clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 718 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, |
| 719 | <&dmac1 0xd1>, <&dmac1 0xd2>; |
| 720 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 721 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 6cdf6ba | 2015-07-31 00:54:05 +0300 | [diff] [blame] | 722 | reg-io-width = <4>; |
| 723 | status = "disabled"; |
| 724 | }; |
| 725 | |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 726 | sdhi0: sd@ee100000 { |
| 727 | compatible = "renesas,sdhi-r8a7794"; |
Simon Horman | 83701e0 | 2016-07-21 08:44:08 +0900 | [diff] [blame] | 728 | reg = <0 0xee100000 0 0x328>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 729 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 730 | clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 731 | dmas = <&dmac0 0xcd>, <&dmac0 0xce>, |
| 732 | <&dmac1 0xcd>, <&dmac1 0xce>; |
| 733 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 734 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 735 | status = "disabled"; |
| 736 | }; |
| 737 | |
| 738 | sdhi1: sd@ee140000 { |
| 739 | compatible = "renesas,sdhi-r8a7794"; |
| 740 | reg = <0 0xee140000 0 0x100>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 741 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 742 | clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 743 | dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, |
| 744 | <&dmac1 0xc1>, <&dmac1 0xc2>; |
| 745 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 746 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 747 | status = "disabled"; |
| 748 | }; |
| 749 | |
| 750 | sdhi2: sd@ee160000 { |
| 751 | compatible = "renesas,sdhi-r8a7794"; |
| 752 | reg = <0 0xee160000 0 0x100>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 753 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 754 | clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 755 | dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, |
| 756 | <&dmac1 0xd3>, <&dmac1 0xd4>; |
| 757 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 758 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | b8e8ea1 | 2015-02-22 01:26:37 +0300 | [diff] [blame] | 759 | status = "disabled"; |
| 760 | }; |
| 761 | |
Sergei Shtylyov | 740b4a9 | 2015-08-11 00:59:24 +0300 | [diff] [blame] | 762 | qspi: spi@e6b10000 { |
| 763 | compatible = "renesas,qspi-r8a7794", "renesas,qspi"; |
| 764 | reg = <0 0xe6b10000 0 0x2c>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 765 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 740b4a9 | 2015-08-11 00:59:24 +0300 | [diff] [blame] | 766 | clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; |
Niklas Söderlund | b38605e | 2016-05-12 10:54:45 +0200 | [diff] [blame] | 767 | dmas = <&dmac0 0x17>, <&dmac0 0x18>, |
| 768 | <&dmac1 0x17>, <&dmac1 0x18>; |
| 769 | dma-names = "tx", "rx", "tx", "rx"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 770 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 740b4a9 | 2015-08-11 00:59:24 +0300 | [diff] [blame] | 771 | num-cs = <1>; |
| 772 | #address-cells = <1>; |
| 773 | #size-cells = <0>; |
| 774 | status = "disabled"; |
| 775 | }; |
| 776 | |
Sergei Shtylyov | 1afe77c | 2015-08-20 01:22:24 +0300 | [diff] [blame] | 777 | vin0: video@e6ef0000 { |
| 778 | compatible = "renesas,vin-r8a7794"; |
| 779 | reg = <0 0xe6ef0000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 780 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 1afe77c | 2015-08-20 01:22:24 +0300 | [diff] [blame] | 781 | clocks = <&mstp8_clks R8A7794_CLK_VIN0>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 782 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 1afe77c | 2015-08-20 01:22:24 +0300 | [diff] [blame] | 783 | status = "disabled"; |
| 784 | }; |
| 785 | |
| 786 | vin1: video@e6ef1000 { |
| 787 | compatible = "renesas,vin-r8a7794"; |
| 788 | reg = <0 0xe6ef1000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 789 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 1afe77c | 2015-08-20 01:22:24 +0300 | [diff] [blame] | 790 | clocks = <&mstp8_clks R8A7794_CLK_VIN1>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 791 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 1afe77c | 2015-08-20 01:22:24 +0300 | [diff] [blame] | 792 | status = "disabled"; |
| 793 | }; |
| 794 | |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 795 | pci0: pci@ee090000 { |
Simon Horman | c99fbe6 | 2015-12-18 11:42:39 +0900 | [diff] [blame] | 796 | compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 797 | device_type = "pci"; |
| 798 | reg = <0 0xee090000 0 0xc00>, |
| 799 | <0 0xee080000 0 0x1100>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 800 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 801 | clocks = <&mstp7_clks R8A7794_CLK_EHCI>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 802 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 803 | status = "disabled"; |
| 804 | |
| 805 | bus-range = <0 0>; |
| 806 | #address-cells = <3>; |
| 807 | #size-cells = <2>; |
| 808 | #interrupt-cells = <1>; |
| 809 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; |
| 810 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 811 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
| 812 | 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
| 813 | 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 45cb0bd | 2015-09-13 02:00:19 +0300 | [diff] [blame] | 814 | |
| 815 | usb@0,1 { |
| 816 | reg = <0x800 0 0 0 0>; |
| 817 | device_type = "pci"; |
| 818 | phys = <&usb0 0>; |
| 819 | phy-names = "usb"; |
| 820 | }; |
| 821 | |
| 822 | usb@0,2 { |
| 823 | reg = <0x1000 0 0 0 0>; |
| 824 | device_type = "pci"; |
| 825 | phys = <&usb0 0>; |
| 826 | phy-names = "usb"; |
| 827 | }; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 828 | }; |
| 829 | |
| 830 | pci1: pci@ee0d0000 { |
Simon Horman | c99fbe6 | 2015-12-18 11:42:39 +0900 | [diff] [blame] | 831 | compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 832 | device_type = "pci"; |
| 833 | reg = <0 0xee0d0000 0 0xc00>, |
| 834 | <0 0xee0c0000 0 0x1100>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 835 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 836 | clocks = <&mstp7_clks R8A7794_CLK_EHCI>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 837 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 838 | status = "disabled"; |
| 839 | |
| 840 | bus-range = <1 1>; |
| 841 | #address-cells = <3>; |
| 842 | #size-cells = <2>; |
| 843 | #interrupt-cells = <1>; |
| 844 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; |
| 845 | interrupt-map-mask = <0xff00 0 0 0x7>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 846 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| 847 | 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
| 848 | 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 45cb0bd | 2015-09-13 02:00:19 +0300 | [diff] [blame] | 849 | |
| 850 | usb@0,1 { |
| 851 | reg = <0x800 0 0 0 0>; |
| 852 | device_type = "pci"; |
| 853 | phys = <&usb2 0>; |
| 854 | phy-names = "usb"; |
| 855 | }; |
| 856 | |
| 857 | usb@0,2 { |
| 858 | reg = <0x1000 0 0 0 0>; |
| 859 | device_type = "pci"; |
| 860 | phys = <&usb2 0>; |
| 861 | phy-names = "usb"; |
| 862 | }; |
Sergei Shtylyov | a6a130b | 2015-09-13 01:30:05 +0300 | [diff] [blame] | 863 | }; |
| 864 | |
Sergei Shtylyov | 2f33b9f | 2015-09-17 02:53:58 +0300 | [diff] [blame] | 865 | hsusb: usb@e6590000 { |
Simon Horman | 1472ffa | 2015-12-08 14:24:50 +0900 | [diff] [blame] | 866 | compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; |
Sergei Shtylyov | 2f33b9f | 2015-09-17 02:53:58 +0300 | [diff] [blame] | 867 | reg = <0 0xe6590000 0 0x100>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 868 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
Sergei Shtylyov | 2f33b9f | 2015-09-17 02:53:58 +0300 | [diff] [blame] | 869 | clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 870 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 2f33b9f | 2015-09-17 02:53:58 +0300 | [diff] [blame] | 871 | renesas,buswait = <4>; |
| 872 | phys = <&usb0 1>; |
| 873 | phy-names = "usb"; |
| 874 | status = "disabled"; |
| 875 | }; |
| 876 | |
Sergei Shtylyov | 74ef457 | 2015-10-02 01:05:12 +0300 | [diff] [blame] | 877 | usbphy: usb-phy@e6590100 { |
| 878 | compatible = "renesas,usb-phy-r8a7794"; |
| 879 | reg = <0 0xe6590100 0 0x100>; |
| 880 | #address-cells = <1>; |
| 881 | #size-cells = <0>; |
| 882 | clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; |
| 883 | clock-names = "usbhs"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 884 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Sergei Shtylyov | 74ef457 | 2015-10-02 01:05:12 +0300 | [diff] [blame] | 885 | status = "disabled"; |
| 886 | |
| 887 | usb0: usb-channel@0 { |
| 888 | reg = <0>; |
| 889 | #phy-cells = <1>; |
| 890 | }; |
| 891 | usb2: usb-channel@2 { |
| 892 | reg = <2>; |
| 893 | #phy-cells = <1>; |
| 894 | }; |
| 895 | }; |
| 896 | |
Sergei Shtylyov | bb249cd | 2016-08-16 00:52:58 +0300 | [diff] [blame] | 897 | vsp1@fe928000 { |
| 898 | compatible = "renesas,vsp1"; |
| 899 | reg = <0 0xfe928000 0 0x8000>; |
| 900 | interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
| 901 | clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; |
| 902 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
| 903 | }; |
| 904 | |
| 905 | vsp1@fe930000 { |
| 906 | compatible = "renesas,vsp1"; |
| 907 | reg = <0 0xfe930000 0 0x8000>; |
| 908 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
| 909 | clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; |
| 910 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
| 911 | }; |
| 912 | |
Laurent Pinchart | 46c4f13 | 2015-11-16 17:57:20 +0900 | [diff] [blame] | 913 | du: display@feb00000 { |
| 914 | compatible = "renesas,du-r8a7794"; |
| 915 | reg = <0 0xfeb00000 0 0x40000>; |
| 916 | reg-names = "du"; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 917 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 918 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 46c4f13 | 2015-11-16 17:57:20 +0900 | [diff] [blame] | 919 | clocks = <&mstp7_clks R8A7794_CLK_DU0>, |
| 920 | <&mstp7_clks R8A7794_CLK_DU0>; |
| 921 | clock-names = "du.0", "du.1"; |
| 922 | status = "disabled"; |
| 923 | |
| 924 | ports { |
| 925 | #address-cells = <1>; |
| 926 | #size-cells = <0>; |
| 927 | |
| 928 | port@0 { |
| 929 | reg = <0>; |
| 930 | du_out_rgb0: endpoint { |
| 931 | }; |
| 932 | }; |
| 933 | port@1 { |
| 934 | reg = <1>; |
| 935 | du_out_rgb1: endpoint { |
| 936 | }; |
| 937 | }; |
| 938 | }; |
| 939 | }; |
| 940 | |
Simon Horman | 9f1c1a2 | 2016-03-15 09:26:34 +0900 | [diff] [blame] | 941 | can0: can@e6e80000 { |
| 942 | compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; |
| 943 | reg = <0 0xe6e80000 0 0x1000>; |
| 944 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
| 945 | clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, |
| 946 | <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; |
| 947 | clock-names = "clkp1", "clkp2", "can_clk"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 948 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Simon Horman | 9f1c1a2 | 2016-03-15 09:26:34 +0900 | [diff] [blame] | 949 | status = "disabled"; |
| 950 | }; |
| 951 | |
| 952 | can1: can@e6e88000 { |
| 953 | compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; |
| 954 | reg = <0 0xe6e88000 0 0x1000>; |
| 955 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| 956 | clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, |
| 957 | <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; |
| 958 | clock-names = "clkp1", "clkp2", "can_clk"; |
Geert Uytterhoeven | 25611e4 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 959 | power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; |
Simon Horman | 9f1c1a2 | 2016-03-15 09:26:34 +0900 | [diff] [blame] | 960 | status = "disabled"; |
| 961 | }; |
| 962 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 963 | clocks { |
| 964 | #address-cells = <2>; |
| 965 | #size-cells = <2>; |
| 966 | ranges; |
| 967 | |
| 968 | /* External root clock */ |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 969 | extal_clk: extal { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 970 | compatible = "fixed-clock"; |
| 971 | #clock-cells = <0>; |
| 972 | /* This value must be overriden by the board. */ |
| 973 | clock-frequency = <0>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 974 | }; |
| 975 | |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 976 | /* External USB clock - can be overridden by the board */ |
| 977 | usb_extal_clk: usb_extal { |
| 978 | compatible = "fixed-clock"; |
| 979 | #clock-cells = <0>; |
| 980 | clock-frequency = <48000000>; |
| 981 | }; |
| 982 | |
| 983 | /* External CAN clock */ |
| 984 | can_clk: can { |
| 985 | compatible = "fixed-clock"; |
| 986 | #clock-cells = <0>; |
| 987 | /* This value must be overridden by the board. */ |
| 988 | clock-frequency = <0>; |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 989 | }; |
| 990 | |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 991 | /* External SCIF clock */ |
| 992 | scif_clk: scif { |
| 993 | compatible = "fixed-clock"; |
| 994 | #clock-cells = <0>; |
| 995 | /* This value must be overridden by the board. */ |
| 996 | clock-frequency = <0>; |
Geert Uytterhoeven | a864446 | 2016-01-29 11:04:42 +0100 | [diff] [blame] | 997 | }; |
| 998 | |
Sergei Shtylyov | 0b1f0e3 | 2016-07-27 23:59:18 +0300 | [diff] [blame] | 999 | /* |
| 1000 | * The external audio clocks are configured as 0 Hz fixed |
| 1001 | * frequency clocks by default. Boards that provide audio |
| 1002 | * clocks should override them. |
| 1003 | */ |
| 1004 | audio_clka: audio_clka { |
| 1005 | compatible = "fixed-clock"; |
| 1006 | #clock-cells = <0>; |
| 1007 | clock-frequency = <0>; |
| 1008 | }; |
| 1009 | audio_clkb: audio_clkb { |
| 1010 | compatible = "fixed-clock"; |
| 1011 | #clock-cells = <0>; |
| 1012 | clock-frequency = <0>; |
| 1013 | }; |
| 1014 | audio_clkc: audio_clkc { |
| 1015 | compatible = "fixed-clock"; |
| 1016 | #clock-cells = <0>; |
| 1017 | clock-frequency = <0>; |
| 1018 | }; |
| 1019 | |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1020 | /* Special CPG clocks */ |
| 1021 | cpg_clocks: cpg_clocks@e6150000 { |
| 1022 | compatible = "renesas,r8a7794-cpg-clocks", |
| 1023 | "renesas,rcar-gen2-cpg-clocks"; |
| 1024 | reg = <0 0xe6150000 0 0x1000>; |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 1025 | clocks = <&extal_clk &usb_extal_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1026 | #clock-cells = <1>; |
| 1027 | clock-output-names = "main", "pll0", "pll1", "pll3", |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 1028 | "lb", "qspi", "sdh", "sd0", "z", |
| 1029 | "rcan"; |
Geert Uytterhoeven | 60c0745 | 2015-08-04 14:28:13 +0200 | [diff] [blame] | 1030 | #power-domain-cells = <0>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1031 | }; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1032 | /* Variable factor clocks */ |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1033 | sd2_clk: sd2@e6150078 { |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1034 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
| 1035 | reg = <0 0xe6150078 0 4>; |
| 1036 | clocks = <&pll1_div2_clk>; |
| 1037 | #clock-cells = <0>; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1038 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1039 | sd3_clk: sd3@e615026c { |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1040 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 1041 | reg = <0 0xe615026c 0 4>; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1042 | clocks = <&pll1_div2_clk>; |
| 1043 | #clock-cells = <0>; |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1044 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1045 | mmc0_clk: mmc0@e6150240 { |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 1046 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
| 1047 | reg = <0 0xe6150240 0 4>; |
| 1048 | clocks = <&pll1_div2_clk>; |
| 1049 | #clock-cells = <0>; |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 1050 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1051 | |
| 1052 | /* Fixed factor clocks */ |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1053 | pll1_div2_clk: pll1_div2 { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1054 | compatible = "fixed-factor-clock"; |
| 1055 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1056 | #clock-cells = <0>; |
| 1057 | clock-div = <2>; |
| 1058 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1059 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1060 | zg_clk: zg { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1061 | compatible = "fixed-factor-clock"; |
| 1062 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1063 | #clock-cells = <0>; |
| 1064 | clock-div = <6>; |
| 1065 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1066 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1067 | zx_clk: zx { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1068 | compatible = "fixed-factor-clock"; |
| 1069 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1070 | #clock-cells = <0>; |
| 1071 | clock-div = <3>; |
| 1072 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1073 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1074 | zs_clk: zs { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1075 | compatible = "fixed-factor-clock"; |
| 1076 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1077 | #clock-cells = <0>; |
| 1078 | clock-div = <6>; |
| 1079 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1080 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1081 | hp_clk: hp { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1082 | compatible = "fixed-factor-clock"; |
| 1083 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1084 | #clock-cells = <0>; |
| 1085 | clock-div = <12>; |
| 1086 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1087 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1088 | i_clk: i { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1089 | compatible = "fixed-factor-clock"; |
| 1090 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1091 | #clock-cells = <0>; |
| 1092 | clock-div = <2>; |
| 1093 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1094 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1095 | b_clk: b { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1096 | compatible = "fixed-factor-clock"; |
| 1097 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1098 | #clock-cells = <0>; |
| 1099 | clock-div = <12>; |
| 1100 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1101 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1102 | p_clk: p { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1103 | compatible = "fixed-factor-clock"; |
| 1104 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1105 | #clock-cells = <0>; |
| 1106 | clock-div = <24>; |
| 1107 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1108 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1109 | cl_clk: cl { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1110 | compatible = "fixed-factor-clock"; |
| 1111 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1112 | #clock-cells = <0>; |
| 1113 | clock-div = <48>; |
| 1114 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1115 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1116 | m2_clk: m2 { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1117 | compatible = "fixed-factor-clock"; |
| 1118 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1119 | #clock-cells = <0>; |
| 1120 | clock-div = <8>; |
| 1121 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1122 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1123 | rclk_clk: rclk { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1124 | compatible = "fixed-factor-clock"; |
| 1125 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1126 | #clock-cells = <0>; |
| 1127 | clock-div = <(48 * 1024)>; |
| 1128 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1129 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1130 | oscclk_clk: oscclk { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1131 | compatible = "fixed-factor-clock"; |
| 1132 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1133 | #clock-cells = <0>; |
| 1134 | clock-div = <(12 * 1024)>; |
| 1135 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1136 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1137 | zb3_clk: zb3 { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1138 | compatible = "fixed-factor-clock"; |
| 1139 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; |
| 1140 | #clock-cells = <0>; |
| 1141 | clock-div = <4>; |
| 1142 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1143 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1144 | zb3d2_clk: zb3d2 { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1145 | compatible = "fixed-factor-clock"; |
| 1146 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; |
| 1147 | #clock-cells = <0>; |
| 1148 | clock-div = <8>; |
| 1149 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1150 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1151 | ddr_clk: ddr { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1152 | compatible = "fixed-factor-clock"; |
| 1153 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; |
| 1154 | #clock-cells = <0>; |
| 1155 | clock-div = <8>; |
| 1156 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1157 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1158 | mp_clk: mp { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1159 | compatible = "fixed-factor-clock"; |
| 1160 | clocks = <&pll1_div2_clk>; |
| 1161 | #clock-cells = <0>; |
| 1162 | clock-div = <15>; |
| 1163 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1164 | }; |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1165 | cp_clk: cp { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1166 | compatible = "fixed-factor-clock"; |
| 1167 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; |
| 1168 | #clock-cells = <0>; |
| 1169 | clock-div = <48>; |
| 1170 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1171 | }; |
| 1172 | |
Simon Horman | 337f6be | 2016-03-18 08:17:57 +0900 | [diff] [blame] | 1173 | acp_clk: acp { |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1174 | compatible = "fixed-factor-clock"; |
| 1175 | clocks = <&extal_clk>; |
| 1176 | #clock-cells = <0>; |
| 1177 | clock-div = <2>; |
| 1178 | clock-mult = <1>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1179 | }; |
| 1180 | |
| 1181 | /* Gate clocks */ |
| 1182 | mstp0_clks: mstp0_clks@e6150130 { |
| 1183 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1184 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| 1185 | clocks = <&mp_clk>; |
| 1186 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1187 | clock-indices = <R8A7794_CLK_MSIOF0>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1188 | clock-output-names = "msiof0"; |
| 1189 | }; |
| 1190 | mstp1_clks: mstp1_clks@e6150134 { |
| 1191 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1192 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
Yoshifumi Hosoya | dc3cf93 | 2014-11-12 17:55:57 +0900 | [diff] [blame] | 1193 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
| 1194 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, |
| 1195 | <&zs_clk>, <&zs_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1196 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1197 | clock-indices = < |
Yoshifumi Hosoya | dc3cf93 | 2014-11-12 17:55:57 +0900 | [diff] [blame] | 1198 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
| 1199 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 |
| 1200 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 |
| 1201 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1202 | >; |
| 1203 | clock-output-names = |
Yoshifumi Hosoya | dc3cf93 | 2014-11-12 17:55:57 +0900 | [diff] [blame] | 1204 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
| 1205 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1206 | }; |
| 1207 | mstp2_clks: mstp2_clks@e6150138 { |
| 1208 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1209 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 1210 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
Hiroyuki Yokoyama | be16cd3 | 2014-12-10 10:21:12 +0900 | [diff] [blame] | 1211 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 1212 | <&zs_clk>, <&zs_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1213 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1214 | clock-indices = < |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1215 | R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 |
| 1216 | R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 |
| 1217 | R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 |
Hiroyuki Yokoyama | be16cd3 | 2014-12-10 10:21:12 +0900 | [diff] [blame] | 1218 | R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1219 | >; |
| 1220 | clock-output-names = |
| 1221 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
Hiroyuki Yokoyama | be16cd3 | 2014-12-10 10:21:12 +0900 | [diff] [blame] | 1222 | "scifb1", "msiof1", "scifb2", |
| 1223 | "sys-dmac1", "sys-dmac0"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1224 | }; |
| 1225 | mstp3_clks: mstp3_clks@e615013c { |
| 1226 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1227 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
Simon Horman | 5e7e155 | 2015-01-05 09:40:49 +0900 | [diff] [blame] | 1228 | clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, |
Simon Horman | a856b19 | 2016-03-17 16:33:10 +0900 | [diff] [blame] | 1229 | <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, |
| 1230 | <&hp_clk>, <&hp_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1231 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1232 | clock-indices = < |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1233 | R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 |
Simon Horman | a856b19 | 2016-03-17 16:33:10 +0900 | [diff] [blame] | 1234 | R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 |
| 1235 | R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 |
Shinobu Uehara | deac150 | 2014-05-27 10:39:26 +0900 | [diff] [blame] | 1236 | R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1237 | >; |
| 1238 | clock-output-names = |
Shinobu Uehara | 8e18163 | 2014-05-23 11:37:45 +0900 | [diff] [blame] | 1239 | "sdhi2", "sdhi1", "sdhi0", |
Simon Horman | a856b19 | 2016-03-17 16:33:10 +0900 | [diff] [blame] | 1240 | "mmcif0", "i2c6", "i2c7", |
| 1241 | "cmt1", "usbdmac0", "usbdmac1"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1242 | }; |
Geert Uytterhoeven | 1c5ca5d | 2015-03-18 19:56:01 +0100 | [diff] [blame] | 1243 | mstp4_clks: mstp4_clks@e6150140 { |
| 1244 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1245 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 1246 | clocks = <&cp_clk>; |
| 1247 | #clock-cells = <1>; |
| 1248 | clock-indices = <R8A7794_CLK_IRQC>; |
| 1249 | clock-output-names = "irqc"; |
| 1250 | }; |
Sergei Shtylyov | 2a29f9d | 2016-07-27 23:59:59 +0300 | [diff] [blame] | 1251 | mstp5_clks: mstp5_clks@e6150144 { |
| 1252 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1253 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
Sergei Shtylyov | 059baea | 2016-09-04 22:55:37 +0300 | [diff] [blame] | 1254 | clocks = <&hp_clk>, <&p_clk>; |
Sergei Shtylyov | 2a29f9d | 2016-07-27 23:59:59 +0300 | [diff] [blame] | 1255 | #clock-cells = <1>; |
| 1256 | clock-indices = <R8A7794_CLK_AUDIO_DMAC0 |
| 1257 | R8A7794_CLK_PWM>; |
| 1258 | clock-output-names = "audmac0", "pwm"; |
| 1259 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1260 | mstp7_clks: mstp7_clks@e615014c { |
| 1261 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1262 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
Shinobu Uehara | c7bab9f | 2014-12-05 12:01:12 +0900 | [diff] [blame] | 1263 | clocks = <&mp_clk>, <&mp_clk>, |
| 1264 | <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
Laurent Pinchart | 9859cd3 | 2015-11-16 17:57:11 +0900 | [diff] [blame] | 1265 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1266 | <&zx_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1267 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1268 | clock-indices = < |
Shinobu Uehara | c7bab9f | 2014-12-05 12:01:12 +0900 | [diff] [blame] | 1269 | R8A7794_CLK_EHCI R8A7794_CLK_HSUSB |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1270 | R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 |
| 1271 | R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 |
| 1272 | R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 |
Laurent Pinchart | 9859cd3 | 2015-11-16 17:57:11 +0900 | [diff] [blame] | 1273 | R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1274 | >; |
| 1275 | clock-output-names = |
Shinobu Uehara | c7bab9f | 2014-12-05 12:01:12 +0900 | [diff] [blame] | 1276 | "ehci", "hsusb", |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1277 | "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
Laurent Pinchart | 9859cd3 | 2015-11-16 17:57:11 +0900 | [diff] [blame] | 1278 | "scif3", "scif2", "scif1", "scif0", "du0"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1279 | }; |
| 1280 | mstp8_clks: mstp8_clks@e6150990 { |
| 1281 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1282 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
Sergei Shtylyov | 255a404 | 2016-02-17 23:43:41 +0300 | [diff] [blame] | 1283 | clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1284 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1285 | clock-indices = < |
Sergei Shtylyov | 255a404 | 2016-02-17 23:43:41 +0300 | [diff] [blame] | 1286 | R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 |
| 1287 | R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1288 | >; |
| 1289 | clock-output-names = |
Sergei Shtylyov | 255a404 | 2016-02-17 23:43:41 +0300 | [diff] [blame] | 1290 | "vin1", "vin0", "etheravb", "ether"; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1291 | }; |
Hisashi Nakamura | 3281480 | 2014-12-11 12:21:14 +0900 | [diff] [blame] | 1292 | mstp9_clks: mstp9_clks@e6150994 { |
| 1293 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1294 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
Sergei Shtylyov | 3f37e01 | 2015-08-09 01:08:21 +0300 | [diff] [blame] | 1295 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 1296 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, |
| 1297 | <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, |
| 1298 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
| 1299 | <&hp_clk>, <&hp_clk>; |
Hisashi Nakamura | 3281480 | 2014-12-11 12:21:14 +0900 | [diff] [blame] | 1300 | #clock-cells = <1>; |
Sergei Shtylyov | 3f37e01 | 2015-08-09 01:08:21 +0300 | [diff] [blame] | 1301 | clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 |
| 1302 | R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 |
| 1303 | R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 1304 | R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1 |
| 1305 | R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD |
Sergei Shtylyov | 3f37e01 | 2015-08-09 01:08:21 +0300 | [diff] [blame] | 1306 | R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 |
| 1307 | R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 |
| 1308 | R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; |
Koji Matsuoka | c5d82c9 | 2014-05-23 18:37:04 +0900 | [diff] [blame] | 1309 | clock-output-names = |
Sergei Shtylyov | 3f37e01 | 2015-08-09 01:08:21 +0300 | [diff] [blame] | 1310 | "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", |
Simon Horman | e980f94 | 2016-03-15 09:26:33 +0900 | [diff] [blame] | 1311 | "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", |
Sergei Shtylyov | 3f37e01 | 2015-08-09 01:08:21 +0300 | [diff] [blame] | 1312 | "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; |
Hisashi Nakamura | 3281480 | 2014-12-11 12:21:14 +0900 | [diff] [blame] | 1313 | }; |
Sergei Shtylyov | 975fb77 | 2016-07-27 14:01:01 -0700 | [diff] [blame] | 1314 | mstp10_clks: mstp10_clks@e6150998 { |
| 1315 | compatible = "renesas,r8a7794-mstp-clocks", |
| 1316 | "renesas,cpg-mstp-clocks"; |
| 1317 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; |
| 1318 | clocks = <&p_clk>, |
| 1319 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1320 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1321 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1322 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1323 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1324 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1325 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1326 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1327 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1328 | <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1329 | <&p_clk>, |
| 1330 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1331 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1332 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1333 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1334 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1335 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1336 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1337 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1338 | <&mstp10_clks R8A7794_CLK_SCU_ALL>, |
| 1339 | <&mstp10_clks R8A7794_CLK_SCU_ALL>; |
| 1340 | #clock-cells = <1>; |
| 1341 | clock-indices = <R8A7794_CLK_SSI_ALL |
| 1342 | R8A7794_CLK_SSI9 R8A7794_CLK_SSI8 |
| 1343 | R8A7794_CLK_SSI7 R8A7794_CLK_SSI6 |
| 1344 | R8A7794_CLK_SSI5 R8A7794_CLK_SSI4 |
| 1345 | R8A7794_CLK_SSI3 R8A7794_CLK_SSI2 |
| 1346 | R8A7794_CLK_SSI1 R8A7794_CLK_SSI0 |
| 1347 | R8A7794_CLK_SCU_ALL |
| 1348 | R8A7794_CLK_SCU_DVC1 |
| 1349 | R8A7794_CLK_SCU_DVC0 |
| 1350 | R8A7794_CLK_SCU_CTU1_MIX1 |
| 1351 | R8A7794_CLK_SCU_CTU0_MIX0 |
| 1352 | R8A7794_CLK_SCU_SRC6 |
| 1353 | R8A7794_CLK_SCU_SRC5 |
| 1354 | R8A7794_CLK_SCU_SRC4 |
| 1355 | R8A7794_CLK_SCU_SRC3 |
| 1356 | R8A7794_CLK_SCU_SRC2 |
| 1357 | R8A7794_CLK_SCU_SRC1>; |
| 1358 | clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", |
| 1359 | "ssi6", "ssi5", "ssi4", "ssi3", |
| 1360 | "ssi2", "ssi1", "ssi0", |
| 1361 | "scu-all", "scu-dvc1", "scu-dvc0", |
| 1362 | "scu-ctu1-mix1", "scu-ctu0-mix0", |
| 1363 | "scu-src6", "scu-src5", "scu-src4", |
| 1364 | "scu-src3", "scu-src2", "scu-src1"; |
| 1365 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1366 | mstp11_clks: mstp11_clks@e615099c { |
| 1367 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 1368 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; |
| 1369 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; |
| 1370 | #clock-cells = <1>; |
Geert Uytterhoeven | 1045d06 | 2014-11-10 19:49:39 +0100 | [diff] [blame] | 1371 | clock-indices = < |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1372 | R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 |
| 1373 | >; |
| 1374 | clock-output-names = "scifa3", "scifa4", "scifa5"; |
| 1375 | }; |
| 1376 | }; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1377 | |
Geert Uytterhoeven | 0761ff2 | 2015-01-20 14:44:58 +0100 | [diff] [blame] | 1378 | sysc: system-controller@e6180000 { |
| 1379 | compatible = "renesas,r8a7794-sysc"; |
| 1380 | reg = <0 0xe6180000 0 0x0200>; |
| 1381 | #power-domain-cells = <1>; |
| 1382 | }; |
| 1383 | |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1384 | ipmmu_sy0: mmu@e6280000 { |
Magnus Damm | 0da4cfd | 2015-11-17 13:31:22 +0900 | [diff] [blame] | 1385 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1386 | reg = <0 0xe6280000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 1387 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
| 1388 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1389 | #iommu-cells = <1>; |
| 1390 | status = "disabled"; |
| 1391 | }; |
| 1392 | |
| 1393 | ipmmu_sy1: mmu@e6290000 { |
Magnus Damm | 0da4cfd | 2015-11-17 13:31:22 +0900 | [diff] [blame] | 1394 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1395 | reg = <0 0xe6290000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 1396 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1397 | #iommu-cells = <1>; |
| 1398 | status = "disabled"; |
| 1399 | }; |
| 1400 | |
| 1401 | ipmmu_ds: mmu@e6740000 { |
Magnus Damm | 0da4cfd | 2015-11-17 13:31:22 +0900 | [diff] [blame] | 1402 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1403 | reg = <0 0xe6740000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 1404 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 1405 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1406 | #iommu-cells = <1>; |
Magnus Damm | 832d3e4 | 2015-10-18 14:26:56 +0900 | [diff] [blame] | 1407 | status = "disabled"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1408 | }; |
| 1409 | |
| 1410 | ipmmu_mp: mmu@ec680000 { |
Magnus Damm | 0da4cfd | 2015-11-17 13:31:22 +0900 | [diff] [blame] | 1411 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1412 | reg = <0 0xec680000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 1413 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1414 | #iommu-cells = <1>; |
| 1415 | status = "disabled"; |
| 1416 | }; |
| 1417 | |
| 1418 | ipmmu_mx: mmu@fe951000 { |
Magnus Damm | 0da4cfd | 2015-11-17 13:31:22 +0900 | [diff] [blame] | 1419 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1420 | reg = <0 0xfe951000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 1421 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
| 1422 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1423 | #iommu-cells = <1>; |
Magnus Damm | 832d3e4 | 2015-10-18 14:26:56 +0900 | [diff] [blame] | 1424 | status = "disabled"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1425 | }; |
| 1426 | |
| 1427 | ipmmu_gp: mmu@e62a0000 { |
Magnus Damm | 0da4cfd | 2015-11-17 13:31:22 +0900 | [diff] [blame] | 1428 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1429 | reg = <0 0xe62a0000 0 0x1000>; |
Simon Horman | 8d47e6a | 2016-01-18 14:18:44 +0900 | [diff] [blame] | 1430 | interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
| 1431 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 1cb2794 | 2015-01-27 11:13:25 +0200 | [diff] [blame] | 1432 | #iommu-cells = <1>; |
| 1433 | status = "disabled"; |
| 1434 | }; |
Sergei Shtylyov | 320d6c5 | 2016-07-28 00:03:10 +0300 | [diff] [blame] | 1435 | |
| 1436 | rcar_sound: sound@ec500000 { |
| 1437 | /* |
| 1438 | * #sound-dai-cells is required |
| 1439 | * |
| 1440 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; |
| 1441 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; |
| 1442 | */ |
| 1443 | compatible = "renesas,rcar_sound-r8a7794", |
| 1444 | "renesas,rcar_sound-gen2"; |
| 1445 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1446 | <0 0xec5a0000 0 0x100>, /* ADG */ |
| 1447 | <0 0xec540000 0 0x1000>, /* SSIU */ |
| 1448 | <0 0xec541000 0 0x280>, /* SSI */ |
| 1449 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ |
| 1450 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
| 1451 | |
| 1452 | clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, |
| 1453 | <&mstp10_clks R8A7794_CLK_SSI9>, |
| 1454 | <&mstp10_clks R8A7794_CLK_SSI8>, |
| 1455 | <&mstp10_clks R8A7794_CLK_SSI7>, |
| 1456 | <&mstp10_clks R8A7794_CLK_SSI6>, |
| 1457 | <&mstp10_clks R8A7794_CLK_SSI5>, |
| 1458 | <&mstp10_clks R8A7794_CLK_SSI4>, |
| 1459 | <&mstp10_clks R8A7794_CLK_SSI3>, |
| 1460 | <&mstp10_clks R8A7794_CLK_SSI2>, |
| 1461 | <&mstp10_clks R8A7794_CLK_SSI1>, |
| 1462 | <&mstp10_clks R8A7794_CLK_SSI0>, |
| 1463 | <&mstp10_clks R8A7794_CLK_SCU_SRC6>, |
| 1464 | <&mstp10_clks R8A7794_CLK_SCU_SRC5>, |
| 1465 | <&mstp10_clks R8A7794_CLK_SCU_SRC4>, |
| 1466 | <&mstp10_clks R8A7794_CLK_SCU_SRC3>, |
| 1467 | <&mstp10_clks R8A7794_CLK_SCU_SRC2>, |
| 1468 | <&mstp10_clks R8A7794_CLK_SCU_SRC1>, |
| 1469 | <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, |
| 1470 | <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, |
| 1471 | <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, |
| 1472 | <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, |
| 1473 | <&mstp10_clks R8A7794_CLK_SCU_DVC0>, |
| 1474 | <&mstp10_clks R8A7794_CLK_SCU_DVC1>, |
| 1475 | <&audio_clka>, <&audio_clkb>, <&audio_clkc>, |
| 1476 | <&m2_clk>; |
| 1477 | clock-names = "ssi-all", |
| 1478 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", |
| 1479 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", |
| 1480 | "src.6", "src.5", "src.4", "src.3", "src.2", |
| 1481 | "src.1", |
| 1482 | "ctu.0", "ctu.1", |
| 1483 | "mix.0", "mix.1", |
| 1484 | "dvc.0", "dvc.1", |
| 1485 | "clk_a", "clk_b", "clk_c", "clk_i"; |
| 1486 | power-domains = <&cpg_clocks>; |
| 1487 | |
| 1488 | status = "disabled"; |
| 1489 | |
| 1490 | rcar_sound,dvc { |
| 1491 | dvc0: dvc@0 { |
| 1492 | dmas = <&audma0 0xbc>; |
| 1493 | dma-names = "tx"; |
| 1494 | }; |
| 1495 | dvc1: dvc@1 { |
| 1496 | dmas = <&audma0 0xbe>; |
| 1497 | dma-names = "tx"; |
| 1498 | }; |
| 1499 | }; |
| 1500 | |
| 1501 | rcar_sound,mix { |
| 1502 | mix0: mix@0 { }; |
| 1503 | mix1: mix@1 { }; |
| 1504 | }; |
| 1505 | |
| 1506 | rcar_sound,ctu { |
| 1507 | ctu00: ctu@0 { }; |
| 1508 | ctu01: ctu@1 { }; |
| 1509 | ctu02: ctu@2 { }; |
| 1510 | ctu03: ctu@3 { }; |
| 1511 | ctu10: ctu@4 { }; |
| 1512 | ctu11: ctu@5 { }; |
| 1513 | ctu12: ctu@6 { }; |
| 1514 | ctu13: ctu@7 { }; |
| 1515 | }; |
| 1516 | |
| 1517 | rcar_sound,src { |
| 1518 | src@0 { |
| 1519 | status = "disabled"; |
| 1520 | }; |
| 1521 | src1: src@1 { |
| 1522 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| 1523 | dmas = <&audma0 0x87>, <&audma0 0x9c>; |
| 1524 | dma-names = "rx", "tx"; |
| 1525 | }; |
| 1526 | src2: src@2 { |
| 1527 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| 1528 | dmas = <&audma0 0x89>, <&audma0 0x9e>; |
| 1529 | dma-names = "rx", "tx"; |
| 1530 | }; |
| 1531 | src3: src@3 { |
| 1532 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| 1533 | dmas = <&audma0 0x8b>, <&audma0 0xa0>; |
| 1534 | dma-names = "rx", "tx"; |
| 1535 | }; |
| 1536 | src4: src@4 { |
| 1537 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| 1538 | dmas = <&audma0 0x8d>, <&audma0 0xb0>; |
| 1539 | dma-names = "rx", "tx"; |
| 1540 | }; |
| 1541 | src5: src@5 { |
| 1542 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| 1543 | dmas = <&audma0 0x8f>, <&audma0 0xb2>; |
| 1544 | dma-names = "rx", "tx"; |
| 1545 | }; |
| 1546 | src6: src@6 { |
| 1547 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| 1548 | dmas = <&audma0 0x91>, <&audma0 0xb4>; |
| 1549 | dma-names = "rx", "tx"; |
| 1550 | }; |
| 1551 | }; |
| 1552 | |
| 1553 | rcar_sound,ssi { |
| 1554 | ssi0: ssi@0 { |
| 1555 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
| 1556 | dmas = <&audma0 0x01>, <&audma0 0x02>, |
| 1557 | <&audma0 0x15>, <&audma0 0x16>; |
| 1558 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1559 | }; |
| 1560 | ssi1: ssi@1 { |
| 1561 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
| 1562 | dmas = <&audma0 0x03>, <&audma0 0x04>, |
| 1563 | <&audma0 0x49>, <&audma0 0x4a>; |
| 1564 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1565 | }; |
| 1566 | ssi2: ssi@2 { |
| 1567 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
| 1568 | dmas = <&audma0 0x05>, <&audma0 0x06>, |
| 1569 | <&audma0 0x63>, <&audma0 0x64>; |
| 1570 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1571 | }; |
| 1572 | ssi3: ssi@3 { |
| 1573 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| 1574 | dmas = <&audma0 0x07>, <&audma0 0x08>, |
| 1575 | <&audma0 0x6f>, <&audma0 0x70>; |
| 1576 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1577 | }; |
| 1578 | ssi4: ssi@4 { |
| 1579 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
| 1580 | dmas = <&audma0 0x09>, <&audma0 0x0a>, |
| 1581 | <&audma0 0x71>, <&audma0 0x72>; |
| 1582 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1583 | }; |
| 1584 | ssi5: ssi@5 { |
| 1585 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
| 1586 | dmas = <&audma0 0x0b>, <&audma0 0x0c>, |
| 1587 | <&audma0 0x73>, <&audma0 0x74>; |
| 1588 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1589 | }; |
| 1590 | ssi6: ssi@6 { |
| 1591 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
| 1592 | dmas = <&audma0 0x0d>, <&audma0 0x0e>, |
| 1593 | <&audma0 0x75>, <&audma0 0x76>; |
| 1594 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1595 | }; |
| 1596 | ssi7: ssi@7 { |
| 1597 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
| 1598 | dmas = <&audma0 0x0f>, <&audma0 0x10>, |
| 1599 | <&audma0 0x79>, <&audma0 0x7a>; |
| 1600 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1601 | }; |
| 1602 | ssi8: ssi@8 { |
| 1603 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
| 1604 | dmas = <&audma0 0x11>, <&audma0 0x12>, |
| 1605 | <&audma0 0x7b>, <&audma0 0x7c>; |
| 1606 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1607 | }; |
| 1608 | ssi9: ssi@9 { |
| 1609 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
| 1610 | dmas = <&audma0 0x13>, <&audma0 0x14>, |
| 1611 | <&audma0 0x7d>, <&audma0 0x7e>; |
| 1612 | dma-names = "rx", "tx", "rxu", "txu"; |
| 1613 | }; |
| 1614 | }; |
| 1615 | }; |
Ulrich Hecht | 0dce545 | 2014-09-05 12:23:48 +0200 | [diff] [blame] | 1616 | }; |