blob: 381747f114a92300938ec1a060a50e7fcafcee88 [file] [log] [blame]
Stephen Warrena7db2c12011-10-25 02:01:28 +00001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Stephen Warrena7db2c12011-10-25 02:01:28 +00005
6/ {
7 model = "Compulab TrimSlice board";
8 compatible = "compulab,trimslice", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000c500/rtc@56";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070014 };
15
Jon Hunterf5bbb322016-02-09 13:51:59 +000016 chosen {
17 stdout-path = "serial0:115200n8";
18 };
19
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060020 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060021 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000022 };
23
Stephen Warren58ecb232013-11-25 17:53:16 -070024 host1x@50000000 {
25 hdmi@54280000 {
Thierry Redingdced3e32012-09-20 10:39:20 +020026 status = "okay";
27
28 vdd-supply = <&hdmi_vdd_reg>;
29 pll-supply = <&hdmi_pll_reg>;
30
31 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070032 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
33 GPIO_ACTIVE_HIGH>;
Thierry Redingdced3e32012-09-20 10:39:20 +020034 };
35 };
36
Stephen Warren58ecb232013-11-25 17:53:16 -070037 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060038 pinctrl-names = "default";
39 pinctrl-0 = <&state_default>;
40
41 state_default: pinmux {
42 ata {
43 nvidia,pins = "ata";
44 nvidia,function = "ide";
45 };
46 atb {
47 nvidia,pins = "atb", "gma";
48 nvidia,function = "sdio4";
49 };
50 atc {
51 nvidia,pins = "atc", "gmb";
52 nvidia,function = "nand";
53 };
54 atd {
55 nvidia,pins = "atd", "ate", "gme", "pta";
56 nvidia,function = "gmi";
57 };
58 cdev1 {
59 nvidia,pins = "cdev1";
60 nvidia,function = "plla_out";
61 };
62 cdev2 {
63 nvidia,pins = "cdev2";
64 nvidia,function = "pllp_out4";
65 };
66 crtp {
67 nvidia,pins = "crtp";
68 nvidia,function = "crt";
69 };
70 csus {
71 nvidia,pins = "csus";
72 nvidia,function = "vi_sensor_clk";
73 };
74 dap1 {
75 nvidia,pins = "dap1";
76 nvidia,function = "dap1";
77 };
78 dap2 {
79 nvidia,pins = "dap2";
80 nvidia,function = "dap2";
81 };
82 dap3 {
83 nvidia,pins = "dap3";
84 nvidia,function = "dap3";
85 };
86 dap4 {
87 nvidia,pins = "dap4";
88 nvidia,function = "dap4";
89 };
90 ddc {
91 nvidia,pins = "ddc";
92 nvidia,function = "i2c2";
93 };
94 dta {
95 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
96 nvidia,function = "vi";
97 };
98 dtf {
99 nvidia,pins = "dtf";
100 nvidia,function = "i2c3";
101 };
102 gmc {
103 nvidia,pins = "gmc", "gmd";
104 nvidia,function = "sflash";
105 };
106 gpu {
107 nvidia,pins = "gpu";
108 nvidia,function = "uarta";
109 };
110 gpu7 {
111 nvidia,pins = "gpu7";
112 nvidia,function = "rtck";
113 };
114 gpv {
115 nvidia,pins = "gpv", "slxa", "slxk";
116 nvidia,function = "pcie";
117 };
118 hdint {
119 nvidia,pins = "hdint";
120 nvidia,function = "hdmi";
121 };
122 i2cp {
123 nvidia,pins = "i2cp";
124 nvidia,function = "i2cp";
125 };
126 irrx {
127 nvidia,pins = "irrx", "irtx";
128 nvidia,function = "uartb";
129 };
130 kbca {
131 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
132 "kbce", "kbcf";
133 nvidia,function = "kbc";
134 };
135 lcsn {
136 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
137 "ld3", "ld4", "ld5", "ld6", "ld7",
138 "ld8", "ld9", "ld10", "ld11", "ld12",
139 "ld13", "ld14", "ld15", "ld16", "ld17",
140 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
141 "lhs", "lm0", "lm1", "lpp", "lpw0",
142 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
143 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
144 "lvs";
145 nvidia,function = "displaya";
146 };
147 owc {
148 nvidia,pins = "owc", "uac";
149 nvidia,function = "rsvd2";
150 };
151 pmc {
152 nvidia,pins = "pmc";
153 nvidia,function = "pwr_on";
154 };
155 rm {
156 nvidia,pins = "rm";
157 nvidia,function = "i2c1";
158 };
159 sdb {
160 nvidia,pins = "sdb", "sdc", "sdd";
161 nvidia,function = "pwm";
162 };
163 sdio1 {
164 nvidia,pins = "sdio1";
165 nvidia,function = "sdio1";
166 };
167 slxc {
168 nvidia,pins = "slxc", "slxd";
169 nvidia,function = "sdio3";
170 };
171 spdi {
172 nvidia,pins = "spdi", "spdo";
173 nvidia,function = "spdif";
174 };
175 spia {
176 nvidia,pins = "spia", "spib", "spic";
177 nvidia,function = "spi2";
178 };
179 spid {
180 nvidia,pins = "spid", "spie", "spif";
181 nvidia,function = "spi1";
182 };
183 spig {
184 nvidia,pins = "spig", "spih";
185 nvidia,function = "spi2_alt";
186 };
187 uaa {
188 nvidia,pins = "uaa", "uab", "uda";
189 nvidia,function = "ulpi";
190 };
191 uad {
192 nvidia,pins = "uad";
193 nvidia,function = "irda";
194 };
195 uca {
196 nvidia,pins = "uca", "ucb";
197 nvidia,function = "uartc";
198 };
199 conf_ata {
200 nvidia,pins = "ata", "atc", "atd", "ate",
201 "crtp", "dap2", "dap3", "dap4", "dta",
202 "dtb", "dtc", "dtd", "dte", "gmb",
203 "gme", "i2cp", "pta", "slxc", "slxd",
204 "spdi", "spdo", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600207 };
208 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600209 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
210 "gma", "gmc", "gmd", "gpu", "gpu7",
211 "gpv", "sdio1", "slxa", "slxk", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530212 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600214 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600215 conf_ck32 {
216 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
217 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600219 };
Stephen Warren563da212012-04-13 16:35:20 -0600220 conf_csus {
221 nvidia,pins = "csus", "spia", "spib",
222 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530223 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600225 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600226 conf_ddc {
227 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530228 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600230 };
231 conf_hdint {
232 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
233 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
234 "lvp0", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600236 };
237 conf_irrx {
238 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
239 "kbcc", "kbcd", "kbce", "kbcf", "owc",
240 "spic", "spie", "spig", "spih", "uaa",
241 "uab", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530242 nvidia,pull = <TEGRA_PIN_PULL_UP>;
243 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600244 };
245 conf_lc {
246 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530247 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600248 };
249 conf_ld0 {
250 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
251 "ld5", "ld6", "ld7", "ld8", "ld9",
252 "ld10", "ld11", "ld12", "ld13", "ld14",
253 "ld15", "ld16", "ld17", "ldi", "lhp0",
254 "lhp1", "lhp2", "lhs", "lm0", "lpp",
255 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
256 "lvs", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600258 };
259 conf_ld17_0 {
260 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
261 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600263 };
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700264 conf_spif {
265 nvidia,pins = "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530266 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
267 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700268 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600269 };
270 };
271
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600272 i2s@70002800 {
273 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600274 };
275
276 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600277 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600278 };
279
Thierry Redingdced3e32012-09-20 10:39:20 +0200280 dvi_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600281 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200282 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000283 };
284
Stephen Warrenfea221e2012-11-12 12:51:22 -0700285 spi@7000c380 {
286 status = "okay";
287 spi-max-frequency = <48000000>;
288 spi-flash@0 {
289 compatible = "winbond,w25q80bl";
290 reg = <0>;
291 spi-max-frequency = <48000000>;
292 };
293 };
294
Thierry Redingdced3e32012-09-20 10:39:20 +0200295 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600296 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200297 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000298 };
299
300 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600301 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000302 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600303
Stephen Warren22bfe102012-04-27 13:24:03 -0600304 codec: codec@1a {
305 compatible = "ti,tlv320aic23";
306 reg = <0x1a>;
307 };
308
Stephen Warren081cc0a2012-04-27 09:22:44 -0600309 rtc@56 {
310 compatible = "emmicro,em3027";
311 reg = <0x56>;
312 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000313 };
314
Stephen Warren58ecb232013-11-25 17:53:16 -0700315 pmc@7000e400 {
Joseph Lo47d2d632013-08-12 17:40:07 +0800316 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800317 nvidia,cpu-pwr-good-time = <5000>;
318 nvidia,cpu-pwr-off-time = <5000>;
319 nvidia,core-pwr-good-time = <3845 3845>;
320 nvidia,core-pwr-off-time = <3875>;
321 nvidia,sys-clock-req-active-high;
322 };
323
Stephen Warren58ecb232013-11-25 17:53:16 -0700324 pcie-controller@80003000 {
Thierry Reding1798efd2013-08-09 16:49:23 +0200325 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200326
327 avdd-pex-supply = <&pci_vdd_reg>;
328 vdd-pex-supply = <&pci_vdd_reg>;
329 avdd-pex-pll-supply = <&pci_vdd_reg>;
330 avdd-plle-supply = <&pci_vdd_reg>;
331 vddio-pex-clk-supply = <&pci_clk_reg>;
332
Thierry Reding1798efd2013-08-09 16:49:23 +0200333 pci@1,0 {
334 status = "okay";
335 };
336 };
337
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600338 usb@c5000000 {
339 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700340 };
341
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530342 usb-phy@c5000000 {
343 status = "okay";
344 vbus-supply = <&vbus_reg>;
345 };
346
Stephen Warrenc04abb32012-05-11 17:03:26 -0600347 usb@c5004000 {
Stephen Warrena6a3dd12012-07-25 14:02:43 -0600348 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700349 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
350 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530351 };
352
353 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530354 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700355 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
356 GPIO_ACTIVE_LOW>;
Stephen Warren31c1ec92011-11-21 14:44:10 -0700357 };
358
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600359 usb@c5008000 {
360 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700361 };
362
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530363 usb-phy@c5008000 {
364 status = "okay";
365 };
366
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600367 sdhci@c8000000 {
368 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200369 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700370 };
371
Stephen Warrena7db2c12011-10-25 02:01:28 +0000372 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600373 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700374 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
375 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200376 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000377 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600378
Joseph Lo7021d122013-04-03 19:31:27 +0800379 clocks {
380 compatible = "simple-bus";
381 #address-cells = <1>;
382 #size-cells = <0>;
383
Stephen Warren58ecb232013-11-25 17:53:16 -0700384 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800385 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200386 reg = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800387 #clock-cells = <0>;
388 clock-frequency = <32768>;
389 };
390 };
391
Joseph Lo5741a252013-04-03 19:31:48 +0800392 gpio-keys {
393 compatible = "gpio-keys";
394
395 power {
396 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700397 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530398 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000399 wakeup-source;
Joseph Lo5741a252013-04-03 19:31:48 +0800400 };
401 };
402
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700403 poweroff {
404 compatible = "gpio-poweroff";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700405 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700406 };
407
Thierry Redingdced3e32012-09-20 10:39:20 +0200408 regulators {
409 compatible = "simple-bus";
410 #address-cells = <1>;
411 #size-cells = <0>;
412
413 hdmi_vdd_reg: regulator@0 {
414 compatible = "regulator-fixed";
415 reg = <0>;
416 regulator-name = "avdd_hdmi";
417 regulator-min-microvolt = <3300000>;
418 regulator-max-microvolt = <3300000>;
419 regulator-always-on;
420 };
421
422 hdmi_pll_reg: regulator@1 {
423 compatible = "regulator-fixed";
424 reg = <1>;
425 regulator-name = "avdd_hdmi_pll";
426 regulator-min-microvolt = <1800000>;
427 regulator-max-microvolt = <1800000>;
428 regulator-always-on;
429 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530430
431 vbus_reg: regulator@2 {
432 compatible = "regulator-fixed";
433 reg = <2>;
434 regulator-name = "usb1_vbus";
435 regulator-min-microvolt = <5000000>;
436 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600437 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600438 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600439 regulator-always-on;
440 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530441 };
Thierry Reding1798efd2013-08-09 16:49:23 +0200442
443 pci_clk_reg: regulator@3 {
444 compatible = "regulator-fixed";
445 reg = <3>;
446 regulator-name = "pci_clk";
447 regulator-min-microvolt = <3300000>;
448 regulator-max-microvolt = <3300000>;
449 regulator-always-on;
450 };
451
452 pci_vdd_reg: regulator@4 {
453 compatible = "regulator-fixed";
454 reg = <4>;
455 regulator-name = "pci_vdd";
456 regulator-min-microvolt = <1050000>;
457 regulator-max-microvolt = <1050000>;
458 regulator-always-on;
459 };
Thierry Redingdced3e32012-09-20 10:39:20 +0200460 };
461
Stephen Warrenc04abb32012-05-11 17:03:26 -0600462 sound {
463 compatible = "nvidia,tegra-audio-trimslice";
464 nvidia,i2s-controller = <&tegra_i2s1>;
465 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600466
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300467 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
468 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
469 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600470 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600471 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000472};