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gerrit-public.fairphone.software / kernel / msm-4.9 / 4719d8f9356a9ea8287ebdac04d759482524e67c / . / arch / arm / boot / dts / vt8500.dtsi
blob: 1929ad390d88feb0ec42bce29ad1b174823ed55b [file] [log] [blame]
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]1/*
2 * vt8500.dtsi - Device tree file for VIA VT8500 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "via,vt8500";
13
Tony Prisk7ec13d42013-04-23 10:33:44 +1200[diff] [blame]14 cpus {
15 #address-cells = <0>;
16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm926ej-s";
21 };
22 };
23
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 };
30
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]31 soc {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "simple-bus";
35 ranges;
36 interrupt-parent = <&intc>;
37
38 intc: interrupt-controller@d8140000 {
39 compatible = "via,vt8500-intc";
40 interrupt-controller;
41 reg = <0xd8140000 0x10000>;
42 #interrupt-cells = <1>;
43 };
44
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]45 pinctrl: pinctrl@d8110000 {
46 compatible = "via,vt8500-pinctrl";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]47 reg = <0xd8110000 0x10000>;
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]48 interrupt-controller;
49 #interrupt-cells = <2>;
50 gpio-controller;
51 #gpio-cells = <2>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]52 };
53
54 pmc@d8130000 {
55 compatible = "via,vt8500-pmc";
56 reg = <0xd8130000 0x1000>;
57
58 clocks {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 ref24: ref24M {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 };
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]67
68 clkuart0: uart0 {
69 #clock-cells = <0>;
70 compatible = "via,vt8500-device-clock";
71 clocks = <&ref24>;
72 enable-reg = <0x250>;
73 enable-bit = <1>;
74 };
75
76 clkuart1: uart1 {
77 #clock-cells = <0>;
78 compatible = "via,vt8500-device-clock";
79 clocks = <&ref24>;
80 enable-reg = <0x250>;
81 enable-bit = <2>;
82 };
83
84 clkuart2: uart2 {
85 #clock-cells = <0>;
86 compatible = "via,vt8500-device-clock";
87 clocks = <&ref24>;
88 enable-reg = <0x250>;
89 enable-bit = <3>;
90 };
91
92 clkuart3: uart3 {
93 #clock-cells = <0>;
94 compatible = "via,vt8500-device-clock";
95 clocks = <&ref24>;
96 enable-reg = <0x250>;
97 enable-bit = <4>;
98 };
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]99 };
100 };
101
102 timer@d8130100 {
103 compatible = "via,vt8500-timer";
104 reg = <0xd8130100 0x28>;
105 interrupts = <36>;
106 };
107
108 ehci@d8007900 {
109 compatible = "via,vt8500-ehci";
110 reg = <0xd8007900 0x200>;
111 interrupts = <43>;
112 };
113
114 uhci@d8007b00 {
115 compatible = "platform-uhci";
116 reg = <0xd8007b00 0x200>;
117 interrupts = <43>;
118 };
119
Tony Prisk7ab0a482013-04-03 07:20:38 +1300[diff] [blame]120 fb: fb@d8050800 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]121 compatible = "via,vt8500-fb";
122 reg = <0xd800e400 0x400>;
123 interrupts = <12>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]124 };
125
126 ge_rops@d8050400 {
127 compatible = "wm,prizm-ge-rops";
128 reg = <0xd8050400 0x100>;
129 };
130
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]131 uart0: serial@d8200000 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]132 compatible = "via,vt8500-uart";
133 reg = <0xd8200000 0x1040>;
134 interrupts = <32>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]135 clocks = <&clkuart0>;
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]136 status = "disabled";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]137 };
138
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]139 uart1: serial@d82b0000 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]140 compatible = "via,vt8500-uart";
141 reg = <0xd82b0000 0x1040>;
142 interrupts = <33>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]143 clocks = <&clkuart1>;
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]144 status = "disabled";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]145 };
146
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]147 uart2: serial@d8210000 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]148 compatible = "via,vt8500-uart";
149 reg = <0xd8210000 0x1040>;
150 interrupts = <47>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]151 clocks = <&clkuart2>;
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]152 status = "disabled";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]153 };
154
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]155 uart3: serial@d82c0000 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]156 compatible = "via,vt8500-uart";
157 reg = <0xd82c0000 0x1040>;
158 interrupts = <50>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]159 clocks = <&clkuart3>;
Tony Prisk55954f82013-04-23 14:23:26 +1200[diff] [blame]160 status = "disabled";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]161 };
162
163 rtc@d8100000 {
164 compatible = "via,vt8500-rtc";
165 reg = <0xd8100000 0x10000>;
166 interrupts = <48>;
167 };
Alexey Charkov2d283862014-04-22 19:28:09 +0400[diff] [blame]168
169 ethernet@d8004000 {
170 compatible = "via,vt8500-rhine";
171 reg = <0xd8004000 0x100>;
172 interrupts = <10>;
173 };
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]174 };
175};