Rafał Miłecki | d7520b1 | 2011-06-13 16:20:06 +0200 | [diff] [blame] | 1 | #ifndef B43_PHY_HT_H_ |
| 2 | #define B43_PHY_HT_H_ |
| 3 | |
| 4 | #include "phy_common.h" |
| 5 | |
| 6 | |
Rafał Miłecki | 19240f3 | 2011-08-12 13:13:46 +0200 | [diff] [blame] | 7 | #define B43_PHY_HT_BBCFG 0x001 /* BB config */ |
| 8 | #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ |
| 9 | #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ |
Rafał Miłecki | bdb2dfb | 2011-06-27 14:58:51 +0200 | [diff] [blame] | 10 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
Rafał Miłecki | 19240f3 | 2011-08-12 13:13:46 +0200 | [diff] [blame] | 11 | #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ |
Rafał Miłecki | d7520b1 | 2011-06-13 16:20:06 +0200 | [diff] [blame] | 12 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
| 13 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ |
| 14 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ |
Rafał Miłecki | bdb2dfb | 2011-06-27 14:58:51 +0200 | [diff] [blame] | 15 | #define B43_PHY_HT_BW1 0x1CE |
| 16 | #define B43_PHY_HT_BW2 0x1CF |
| 17 | #define B43_PHY_HT_BW3 0x1D0 |
| 18 | #define B43_PHY_HT_BW4 0x1D1 |
| 19 | #define B43_PHY_HT_BW5 0x1D2 |
| 20 | #define B43_PHY_HT_BW6 0x1D3 |
Rafał Miłecki | d7520b1 | 2011-06-13 16:20:06 +0200 | [diff] [blame] | 21 | |
Rafał Miłecki | ea5a08c | 2011-08-24 11:52:35 +0200 | [diff] [blame] | 22 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) |
| 23 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) |
| 24 | #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) |
| 25 | |
Rafał Miłecki | c750f79 | 2011-08-24 11:52:34 +0200 | [diff] [blame] | 26 | #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) |
| 27 | #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) |
| 28 | #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ |
| 29 | #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ |
| 30 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ |
| 31 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ |
| 32 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ |
| 33 | #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ |
| 34 | #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) |
| 35 | /* Values for the status are the same as for the trigger */ |
| 36 | |
Rafał Miłecki | e7c6255 | 2011-06-19 02:18:11 +0200 | [diff] [blame] | 37 | #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010) |
| 38 | |
Rafał Miłecki | 4760692 | 2013-03-09 13:43:49 +0100 | [diff] [blame^] | 39 | #define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110) |
| 40 | #define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111) |
| 41 | #define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114) |
| 42 | #define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115) |
| 43 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) |
| 44 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) |
Rafał Miłecki | a8e8274 | 2011-06-16 01:59:20 +0200 | [diff] [blame] | 45 | |
Rafał Miłecki | d7520b1 | 2011-06-13 16:20:06 +0200 | [diff] [blame] | 46 | |
Rafał Miłecki | 5192bf5 | 2011-06-19 12:17:19 +0200 | [diff] [blame] | 47 | /* Values for PHY registers used on channel switching */ |
| 48 | struct b43_phy_ht_channeltab_e_phy { |
Rafał Miłecki | bdb2dfb | 2011-06-27 14:58:51 +0200 | [diff] [blame] | 49 | u16 bw1; |
| 50 | u16 bw2; |
| 51 | u16 bw3; |
| 52 | u16 bw4; |
| 53 | u16 bw5; |
| 54 | u16 bw6; |
Rafał Miłecki | 5192bf5 | 2011-06-19 12:17:19 +0200 | [diff] [blame] | 55 | }; |
| 56 | |
| 57 | |
Rafał Miłecki | d7520b1 | 2011-06-13 16:20:06 +0200 | [diff] [blame] | 58 | struct b43_phy_ht { |
| 59 | }; |
| 60 | |
| 61 | |
| 62 | struct b43_phy_operations; |
| 63 | extern const struct b43_phy_operations b43_phyops_ht; |
| 64 | |
| 65 | #endif /* B43_PHY_HT_H_ */ |