blob: bdf6dadf87906f2e6933abcb1443740dd53785e4 [file] [log] [blame]
Kukjin Kim8eadcf72012-04-15 21:57:38 -07001/*
Jaecheol Lee16638952011-03-10 13:33:59 +09002 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
Abhilash Kesavane2e13622011-10-04 20:25:51 +09005 * Common S5P Sleep Code
6 * Based on S3C64XX sleep code by:
7 * Ben Dooks, (c) 2008 Simtec Electronics
Jaecheol Lee16638952011-03-10 13:33:59 +09008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/linkage.h>
Amit Daniel Kachhap7c6035b2012-03-08 02:07:34 -080025#include <asm/asm-offsets.h>
26#include <asm/hardware/cache-l2x0.h>
Jaecheol Lee16638952011-03-10 13:33:59 +090027
Amit Daniel Kachhap7c6035b2012-03-08 02:07:34 -080028/*
29 * The following code is located into the .data section. This is to
30 * allow l2x0_regs_phys to be accessed with a relative load while we
31 * can't rely on any MMU translation. We could have put l2x0_regs_phys
32 * in the .text section as well, but some setups might insist on it to
33 * be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
34 */
35 .data
36 .align
Jaecheol Lee16638952011-03-10 13:33:59 +090037
38 /*
Jaecheol Lee16638952011-03-10 13:33:59 +090039 * sleep magic, to allow the bootloader to check for an valid
40 * image to resume to. Must be the first word before the
41 * s3c_cpu_resume entry.
42 */
43
44 .word 0x2bedf00d
45
46 /*
47 * s3c_cpu_resume
48 *
49 * resume code entry for bootloader to call
Jaecheol Lee16638952011-03-10 13:33:59 +090050 */
51
52ENTRY(s3c_cpu_resume)
Amit Daniel Kachhap7c6035b2012-03-08 02:07:34 -080053#ifdef CONFIG_CACHE_L2X0
54 adr r0, l2x0_regs_phys
55 ldr r0, [r0]
56 ldr r1, [r0, #L2X0_R_PHY_BASE]
57 ldr r2, [r1, #L2X0_CTRL]
58 tst r2, #0x1
59 bne resume_l2on
60 ldr r2, [r0, #L2X0_R_AUX_CTRL]
61 str r2, [r1, #L2X0_AUX_CTRL]
62 ldr r2, [r0, #L2X0_R_TAG_LATENCY]
63 str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
64 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
65 str r2, [r1, #L2X0_DATA_LATENCY_CTRL]
66 ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
67 str r2, [r1, #L2X0_PREFETCH_CTRL]
68 ldr r2, [r0, #L2X0_R_PWR_CTRL]
69 str r2, [r1, #L2X0_POWER_CTRL]
70 mov r2, #1
71 str r2, [r1, #L2X0_CTRL]
72resume_l2on:
73#endif
Jaecheol Lee16638952011-03-10 13:33:59 +090074 b cpu_resume
Amit Daniel Kachhap7c6035b2012-03-08 02:07:34 -080075ENDPROC(s3c_cpu_resume)
76#ifdef CONFIG_CACHE_L2X0
77 .globl l2x0_regs_phys
78l2x0_regs_phys:
79 .long 0
80#endif