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Ben Skeggs50254072015-01-14 14:11:21 +10001#ifndef __NVKM_DEVICE_H__
2#define __NVKM_DEVICE_H__
Ben Skeggs9274f4a2012-07-06 07:36:43 +10003#include <core/engine.h>
Ben Skeggsed76a872014-06-13 12:42:21 +10004#include <core/event.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +10005
Ben Skeggs9ace4042015-08-20 14:54:06 +10006enum nvkm_devidx {
7 NVDEV_ENGINE_DEVICE,
8 NVDEV_SUBDEV_VBIOS,
9
10 /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
11 * *any* of them are initialised. This subdev category is used
12 * for any subdevs that the VBIOS init table parsing may call out
13 * to during POST.
14 */
15 NVDEV_SUBDEV_DEVINIT,
16 NVDEV_SUBDEV_IBUS,
17 NVDEV_SUBDEV_GPIO,
18 NVDEV_SUBDEV_I2C,
19 NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
20
21 /* This grouping of subdevs are initialised right after they've
22 * been created, and are allowed to assume any subdevs in the
23 * list above them exist and have been initialised.
24 */
25 NVDEV_SUBDEV_FUSE,
26 NVDEV_SUBDEV_MXM,
27 NVDEV_SUBDEV_MC,
28 NVDEV_SUBDEV_BUS,
29 NVDEV_SUBDEV_TIMER,
30 NVDEV_SUBDEV_FB,
31 NVDEV_SUBDEV_LTC,
32 NVDEV_SUBDEV_INSTMEM,
33 NVDEV_SUBDEV_MMU,
34 NVDEV_SUBDEV_BAR,
35 NVDEV_SUBDEV_PMU,
36 NVDEV_SUBDEV_VOLT,
37 NVDEV_SUBDEV_THERM,
38 NVDEV_SUBDEV_CLK,
39
40 NVDEV_ENGINE_FIRST,
41 NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
42 NVDEV_ENGINE_IFB,
43 NVDEV_ENGINE_FIFO,
44 NVDEV_ENGINE_SW,
45 NVDEV_ENGINE_GR,
46 NVDEV_ENGINE_MPEG,
47 NVDEV_ENGINE_ME,
48 NVDEV_ENGINE_VP,
49 NVDEV_ENGINE_CIPHER,
50 NVDEV_ENGINE_BSP,
51 NVDEV_ENGINE_MSPPP,
52 NVDEV_ENGINE_CE0,
53 NVDEV_ENGINE_CE1,
54 NVDEV_ENGINE_CE2,
55 NVDEV_ENGINE_VIC,
56 NVDEV_ENGINE_MSENC,
57 NVDEV_ENGINE_DISP,
58 NVDEV_ENGINE_PM,
59 NVDEV_ENGINE_MSVLD,
60 NVDEV_ENGINE_SEC,
61 NVDEV_ENGINE_MSPDEC,
62
63 NVDEV_SUBDEV_NR,
64};
65
Ben Skeggs50254072015-01-14 14:11:21 +100066struct nvkm_device {
67 struct nvkm_engine engine;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100068 struct list_head head;
69
70 struct pci_dev *pdev;
Alexandre Courbot420b9462014-02-17 15:17:26 +090071 struct platform_device *platformdev;
Ben Skeggs6d0d40e2015-08-20 14:54:06 +100072 struct device *dev;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100073 u64 handle;
74
Ben Skeggs2ebfa1b2015-08-20 14:54:10 +100075 void __iomem *pri;
76
Ben Skeggs79ca2772014-08-10 04:10:20 +100077 struct nvkm_event event;
Ben Skeggsed76a872014-06-13 12:42:21 +100078
Ben Skeggs9274f4a2012-07-06 07:36:43 +100079 const char *cfgopt;
80 const char *dbgopt;
81 const char *name;
82 const char *cname;
Ilia Mirkinf0d13e32014-01-09 21:19:11 -050083 u64 disable_mask;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100084
85 enum {
86 NV_04 = 0x04,
87 NV_10 = 0x10,
Ilia Mirkin4a0ff752013-09-05 04:45:02 -040088 NV_11 = 0x11,
Ben Skeggs9274f4a2012-07-06 07:36:43 +100089 NV_20 = 0x20,
90 NV_30 = 0x30,
91 NV_40 = 0x40,
92 NV_50 = 0x50,
93 NV_C0 = 0xc0,
Ben Skeggs9274f4a2012-07-06 07:36:43 +100094 NV_E0 = 0xe0,
Ben Skeggs3f204642014-02-24 11:28:37 +100095 GM100 = 0x110,
Ben Skeggs9274f4a2012-07-06 07:36:43 +100096 } card_type;
97 u32 chipset;
Ben Skeggs37047912014-11-17 22:56:37 +100098 u8 chiprev;
Ben Skeggs9274f4a2012-07-06 07:36:43 +100099 u32 crystal;
100
Ben Skeggs50254072015-01-14 14:11:21 +1000101 struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
102 struct nvkm_object *subdev[NVDEV_SUBDEV_NR];
Ben Skeggsed76a872014-06-13 12:42:21 +1000103
104 struct {
105 struct notifier_block nb;
106 } acpi;
Ben Skeggs741d7782015-08-20 14:54:05 +1000107
108 struct nvkm_bar *bar;
109 struct nvkm_bios *bios;
110 struct nvkm_bus *bus;
111 struct nvkm_clk *clk;
112 struct nvkm_devinit *devinit;
113 struct nvkm_fb *fb;
114 struct nvkm_fuse *fuse;
115 struct nvkm_gpio *gpio;
116 struct nvkm_i2c *i2c;
117 struct nvkm_subdev *ibus;
118 struct nvkm_instmem *imem;
119 struct nvkm_ltc *ltc;
120 struct nvkm_mc *mc;
121 struct nvkm_mmu *mmu;
122 struct nvkm_subdev *mxm;
123 struct nvkm_pmu *pmu;
124 struct nvkm_therm *therm;
125 struct nvkm_timer *timer;
126 struct nvkm_volt *volt;
127
128 struct nvkm_engine *bsp;
129 struct nvkm_engine *ce[3];
130 struct nvkm_engine *cipher;
131 struct nvkm_disp *disp;
132 struct nvkm_dmaeng *dma;
133 struct nvkm_fifo *fifo;
134 struct nvkm_gr *gr;
135 struct nvkm_engine *ifb;
136 struct nvkm_engine *me;
137 struct nvkm_engine *mpeg;
138 struct nvkm_engine *msenc;
139 struct nvkm_engine *mspdec;
140 struct nvkm_engine *msppp;
141 struct nvkm_engine *msvld;
142 struct nvkm_pm *pm;
143 struct nvkm_engine *sec;
144 struct nvkm_sw *sw;
145 struct nvkm_engine *vic;
146 struct nvkm_engine *vp;
Ben Skeggs47b25052015-08-20 14:54:15 +1000147
148 struct nouveau_platform_gpu *gpu;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000149};
150
Ben Skeggs50254072015-01-14 14:11:21 +1000151struct nvkm_device *nvkm_device_find(u64 name);
152int nvkm_device_list(u64 *name, int size);
Ben Skeggs803c1782014-08-10 04:10:21 +1000153
Ben Skeggsdd646942015-08-20 14:54:08 +1000154/* privileged register interface accessor macros */
Ben Skeggs2ebfa1b2015-08-20 14:54:10 +1000155#define nvkm_rd08(d,a) ioread8((d)->pri + (a))
156#define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
157#define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
158#define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
159#define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
160#define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
Ben Skeggsdd646942015-08-20 14:54:08 +1000161#define nvkm_mask(d,a,m,v) ({ \
162 struct nvkm_device *_device = (d); \
163 u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
164 nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
165 _temp; \
166})
167
Ben Skeggs50254072015-01-14 14:11:21 +1000168struct nvkm_device *nv_device(void *obj);
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000169
170static inline bool
Ben Skeggsd351b852015-08-20 14:54:05 +1000171nv_device_match(struct nvkm_device *device, u16 dev, u16 ven, u16 sub)
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000172{
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000173 return device->pdev->device == dev &&
174 device->pdev->subsystem_vendor == ven &&
175 device->pdev->subsystem_device == sub;
176}
177
Alexandre Courbot420b9462014-02-17 15:17:26 +0900178static inline bool
Ben Skeggs50254072015-01-14 14:11:21 +1000179nv_device_is_pci(struct nvkm_device *device)
Alexandre Courbot420b9462014-02-17 15:17:26 +0900180{
181 return device->pdev != NULL;
182}
183
Alexandre Courbotc5d7ddf2014-10-27 18:49:16 +0900184static inline bool
Ben Skeggs50254072015-01-14 14:11:21 +1000185nv_device_is_cpu_coherent(struct nvkm_device *device)
Alexandre Courbotc5d7ddf2014-10-27 18:49:16 +0900186{
187 return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device));
188}
189
Alexandre Courbot420b9462014-02-17 15:17:26 +0900190static inline struct device *
Ben Skeggs50254072015-01-14 14:11:21 +1000191nv_device_base(struct nvkm_device *device)
Alexandre Courbot420b9462014-02-17 15:17:26 +0900192{
193 return nv_device_is_pci(device) ? &device->pdev->dev :
194 &device->platformdev->dev;
195}
196
197resource_size_t
Ben Skeggs50254072015-01-14 14:11:21 +1000198nv_device_resource_start(struct nvkm_device *device, unsigned int bar);
Alexandre Courbot420b9462014-02-17 15:17:26 +0900199
200resource_size_t
Ben Skeggs50254072015-01-14 14:11:21 +1000201nv_device_resource_len(struct nvkm_device *device, unsigned int bar);
Alexandre Courbot420b9462014-02-17 15:17:26 +0900202
Alexandre Courbot420b9462014-02-17 15:17:26 +0900203int
Ben Skeggs50254072015-01-14 14:11:21 +1000204nv_device_get_irq(struct nvkm_device *device, bool stall);
Ben Skeggs97190472015-01-14 15:35:00 +1000205
206struct platform_device;
207
208enum nv_bus_type {
209 NVKM_BUS_PCI,
210 NVKM_BUS_PLATFORM,
211};
212
213#define nvkm_device_create(p,t,n,s,c,d,u) \
214 nvkm_device_create_((void *)(p), (t), (n), (s), (c), (d), \
215 sizeof(**u), (void **)u)
216int nvkm_device_create_(void *, enum nv_bus_type type, u64 name,
217 const char *sname, const char *cfg, const char *dbg,
218 int, void **);
Ben Skeggs65943632015-08-20 14:54:11 +1000219
220/* device logging */
221#define nvdev_printk_(d,l,p,f,a...) do { \
222 struct nvkm_device *_device = (d); \
223 if (_device->engine.subdev.debug >= (l)) \
224 dev_##p(_device->dev, f, ##a); \
225} while(0)
226#define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
227#define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL, crit, f, ##a)
228#define nvdev_error(d,f,a...) nvdev_printk((d), ERROR, err, f, ##a)
229#define nvdev_warn(d,f,a...) nvdev_printk((d), WARN, notice, f, ##a)
230#define nvdev_info(d,f,a...) nvdev_printk((d), INFO, info, f, ##a)
231#define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG, info, f, ##a)
232#define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE, info, f, ##a)
233#define nvdev_spam(d,f,a...) nvdev_printk((d), SPAM, dbg, f, ##a)
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000234#endif