Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/cacheflush.h |
| 3 | * Based on: include/asm-m68knommu/cacheflush.h |
| 4 | * Author: LG Soft India |
| 5 | * Copyright (C) 2004 Analog Devices Inc. |
| 6 | * Created: Tue Sep 21 2004 |
| 7 | * Description: Blackfin low-level cache routines adapted from the i386 |
| 8 | * and PPC versions by Greg Ungerer (gerg@snapgear.com) |
| 9 | * |
| 10 | * Modified: |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2, or (at your option) |
| 17 | * any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; see the file COPYING. |
| 26 | * If not, write to the Free Software Foundation, |
| 27 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 28 | */ |
| 29 | |
| 30 | #ifndef _BLACKFIN_CACHEFLUSH_H |
| 31 | #define _BLACKFIN_CACHEFLUSH_H |
| 32 | |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 33 | #include <asm/blackfin.h> /* for SSYNC() */ |
| 34 | |
Mike Frysinger | 8fb4f8f | 2008-10-16 23:39:12 +0800 | [diff] [blame] | 35 | extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); |
| 36 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); |
| 37 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); |
| 38 | extern void blackfin_dflush_page(void *page); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 39 | extern void blackfin_invalidate_entire_dcache(void); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 40 | |
| 41 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 42 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
| 43 | #define flush_cache_mm(mm) do { } while (0) |
| 44 | #define flush_cache_range(vma, start, end) do { } while (0) |
| 45 | #define flush_cache_page(vma, vmaddr) do { } while (0) |
| 46 | #define flush_cache_vmap(start, end) do { } while (0) |
| 47 | #define flush_cache_vunmap(start, end) do { } while (0) |
| 48 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 49 | #ifdef CONFIG_SMP |
| 50 | #define flush_icache_range_others(start, end) \ |
| 51 | smp_icache_flush_range_others((start), (end)) |
| 52 | #else |
| 53 | #define flush_icache_range_others(start, end) do { } while (0) |
| 54 | #endif |
| 55 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 56 | static inline void flush_icache_range(unsigned start, unsigned end) |
| 57 | { |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 58 | #if defined(CONFIG_BFIN_WB) |
| 59 | blackfin_dcache_flush_range(start, end); |
| 60 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 61 | |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 62 | /* Make sure all write buffers in the data side of the core |
| 63 | * are flushed before trying to invalidate the icache. This |
| 64 | * needs to be after the data flush and before the icache |
| 65 | * flush so that the SSYNC does the right thing in preventing |
| 66 | * the instruction prefetcher from hitting things in cached |
| 67 | * memory at the wrong time -- it runs much further ahead than |
| 68 | * the pipeline. |
| 69 | */ |
| 70 | SSYNC(); |
| 71 | #if defined(CONFIG_BFIN_ICACHE) |
| 72 | blackfin_icache_flush_range(start, end); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 73 | flush_icache_range_others(start, end); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 74 | #endif |
| 75 | } |
| 76 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 77 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 78 | do { memcpy(dst, src, len); \ |
| 79 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 80 | } while (0) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 81 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 82 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) |
| 83 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 84 | #if defined(CONFIG_BFIN_DCACHE) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 85 | # define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) |
| 86 | #else |
| 87 | # define invalidate_dcache_range(start,end) do { } while (0) |
| 88 | #endif |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 89 | #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 90 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) |
| 91 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) |
| 92 | #else |
| 93 | # define flush_dcache_range(start,end) do { } while (0) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 94 | # define flush_dcache_page(page) do { } while (0) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 95 | #endif |
| 96 | |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 97 | extern unsigned long reserved_mem_dcache_on; |
| 98 | extern unsigned long reserved_mem_icache_on; |
| 99 | |
Jie Zhang | 67834fa | 2009-06-10 06:26:26 +0000 | [diff] [blame] | 100 | static inline int bfin_addr_dcacheable(unsigned long addr) |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 101 | { |
| 102 | #ifdef CONFIG_BFIN_DCACHE |
| 103 | if (addr < (_ramend - DMA_UNCACHED_REGION)) |
| 104 | return 1; |
| 105 | #endif |
| 106 | |
| 107 | if (reserved_mem_dcache_on && |
| 108 | addr >= _ramend && addr < physical_mem_end) |
| 109 | return 1; |
| 110 | |
Mike Frysinger | f339f46 | 2009-05-19 12:58:13 +0000 | [diff] [blame] | 111 | #ifndef CONFIG_BFIN_L2_NOT_CACHED |
| 112 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) |
| 113 | return 1; |
| 114 | #endif |
| 115 | |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 116 | return 0; |
| 117 | } |
| 118 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 119 | #endif /* _BLACKFIN_ICACHEFLUSH_H */ |