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gerrit-public.fairphone.software / kernel / msm-4.9 / 481fbe13528d2a9dfe8fee881cb3f0c895f0c3b6 / . / arch / arm / boot / dts / imx53.dtsi
blob: cec6cdd2f1963749aa71b2a522451c0c473fc1be [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 gpio5 = &gpio6;
24 gpio6 = &gpio7;
Philipp Zabelc60dc1d2013-04-09 19:18:47 +0200[diff] [blame]25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
Sascha Hauercf4e5772013-06-25 15:51:56 +0200[diff] [blame]28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 spi0 = &ecspi1;
34 spi1 = &ecspi2;
35 spi2 = &cspi;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]36 };
37
38 tzic: tz-interrupt-controller@0fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
40 interrupt-controller;
41 #interrupt-cells = <1>;
42 reg = <0x0fffc000 0x4000>;
43 };
44
45 clocks {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 ckil {
50 compatible = "fsl,imx-ckil", "fixed-clock";
51 clock-frequency = <32768>;
52 };
53
54 ckih1 {
55 compatible = "fsl,imx-ckih1", "fixed-clock";
56 clock-frequency = <22579200>;
57 };
58
59 ckih2 {
60 compatible = "fsl,imx-ckih2", "fixed-clock";
61 clock-frequency = <0>;
62 };
63
64 osc {
65 compatible = "fsl,imx-osc", "fixed-clock";
66 clock-frequency = <24000000>;
67 };
68 };
69
70 soc {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "simple-bus";
74 interrupt-parent = <&tzic>;
75 ranges;
76
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]77 ipu: ipu@18000000 {
78 #crtc-cells = <1>;
79 compatible = "fsl,imx53-ipu";
80 reg = <0x18000000 0x080000000>;
81 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]82 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
83 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]84 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]85 };
86
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]87 aips@50000000 { /* AIPS1 */
88 compatible = "fsl,aips-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x50000000 0x10000000>;
92 ranges;
93
94 spba@50000000 {
95 compatible = "fsl,spba-bus", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x50000000 0x40000>;
99 ranges;
100
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]101 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]102 compatible = "fsl,imx53-esdhc";
103 reg = <0x50004000 0x4000>;
104 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]105 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
106 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]107 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]108 status = "disabled";
109 };
110
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]111 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]112 compatible = "fsl,imx53-esdhc";
113 reg = <0x50008000 0x4000>;
114 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]115 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
116 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]117 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]118 status = "disabled";
119 };
120
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]121 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]122 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
123 reg = <0x5000c000 0x4000>;
124 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]125 clocks = <&clks 32>, <&clks 33>;
126 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]127 status = "disabled";
128 };
129
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]130 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
134 reg = <0x50010000 0x4000>;
135 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]136 clocks = <&clks 51>, <&clks 52>;
137 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]138 status = "disabled";
139 };
140
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]141 ssi2: ssi@50014000 {
142 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
143 reg = <0x50014000 0x4000>;
144 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]145 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]146 fsl,fifo-depth = <15>;
147 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
148 status = "disabled";
149 };
150
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]151 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]152 compatible = "fsl,imx53-esdhc";
153 reg = <0x50020000 0x4000>;
154 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]155 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
156 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]157 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]158 status = "disabled";
159 };
160
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]161 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]162 compatible = "fsl,imx53-esdhc";
163 reg = <0x50024000 0x4000>;
164 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]165 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
166 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]167 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]168 status = "disabled";
169 };
170 };
171
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]172 usbphy0: usbphy@0 {
173 compatible = "usb-nop-xceiv";
174 clocks = <&clks 124>;
175 clock-names = "main_clk";
176 status = "okay";
177 };
178
179 usbphy1: usbphy@1 {
180 compatible = "usb-nop-xceiv";
181 clocks = <&clks 125>;
182 clock-names = "main_clk";
183 status = "okay";
184 };
185
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]186 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]187 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
188 reg = <0x53f80000 0x0200>;
189 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]190 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]191 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]192 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]193 status = "disabled";
194 };
195
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]196 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]197 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
198 reg = <0x53f80200 0x0200>;
199 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]200 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]201 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]202 fsl,usbphy = <&usbphy1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]203 status = "disabled";
204 };
205
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]206 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]207 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
208 reg = <0x53f80400 0x0200>;
209 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]210 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]211 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]212 status = "disabled";
213 };
214
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]215 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]216 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
217 reg = <0x53f80600 0x0200>;
218 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]219 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]220 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]221 status = "disabled";
222 };
223
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]224 usbmisc: usbmisc@53f80800 {
225 #index-cells = <1>;
226 compatible = "fsl,imx53-usbmisc";
227 reg = <0x53f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]228 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]229 };
230
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]231 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]232 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]233 reg = <0x53f84000 0x4000>;
234 interrupts = <50 51>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]238 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]239 };
240
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]241 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]242 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]243 reg = <0x53f88000 0x4000>;
244 interrupts = <52 53>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]248 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]249 };
250
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]251 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]252 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]253 reg = <0x53f8c000 0x4000>;
254 interrupts = <54 55>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]258 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]259 };
260
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]261 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]262 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]263 reg = <0x53f90000 0x4000>;
264 interrupts = <56 57>;
265 gpio-controller;
266 #gpio-cells = <2>;
267 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]268 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]269 };
270
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]271 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]272 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
273 reg = <0x53f98000 0x4000>;
274 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]275 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]276 };
277
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]278 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]279 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
280 reg = <0x53f9c000 0x4000>;
281 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]282 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]283 status = "disabled";
284 };
285
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]286 gpt: timer@53fa0000 {
287 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
288 reg = <0x53fa0000 0x4000>;
289 interrupts = <39>;
290 clocks = <&clks 36>, <&clks 41>;
291 clock-names = "ipg", "per";
292 };
293
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]294 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]295 compatible = "fsl,imx53-iomuxc";
296 reg = <0x53fa8000 0x4000>;
297
298 audmux {
299 pinctrl_audmux_1: audmuxgrp-1 {
300 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]301 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
302 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
303 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
304 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]305 >;
306 };
Marek Vasutdd04c172013-04-21 23:30:01 +0200[diff] [blame]307
308 pinctrl_audmux_2: audmuxgrp-2 {
309 fsl,pins = <
310 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
311 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
312 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
313 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
314 >;
315 };
Steffen Trumtrarbb6e2fa2013-04-24 11:41:20 +0200[diff] [blame]316
317 pinctrl_audmux_3: audmuxgrp-3 {
318 fsl,pins = <
319 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
320 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
321 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
322 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
323 >;
324 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]325 };
326
327 fec {
328 pinctrl_fec_1: fecgrp-1 {
329 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]330 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
331 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
332 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
333 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
334 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
335 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
336 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
337 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
338 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
339 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]340 >;
341 };
Jonas Anderssonfad1ea02013-05-27 10:52:54 +0200[diff] [blame]342
343 pinctrl_fec_2: fecgrp-2 {
344 fsl,pins = <
345 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
346 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
347 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
348 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
349 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
350 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
351 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
352 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
353 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
354 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
355 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
356 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
357 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
358 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
359 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
360 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
361 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
362 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
363 >;
364 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]365 };
366
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]367 csi {
368 pinctrl_csi_1: csigrp-1 {
369 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]370 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
371 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
372 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
373 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
374 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
375 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
376 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
377 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
378 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
379 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
380 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
381 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
382 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
383 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
384 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
385 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
386 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
387 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
388 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
389 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
390 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]391 >;
392 };
Steffen Trumtrard0cae682013-04-24 11:41:21 +0200[diff] [blame]393
394 pinctrl_csi_2: csigrp-2 {
395 fsl,pins = <
396 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
397 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
398 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
399 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
400 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
401 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
402 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
403 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
404 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
405 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
406 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
407 >;
408 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]409 };
410
411 cspi {
412 pinctrl_cspi_1: cspigrp-1 {
413 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]414 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
415 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
416 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]417 >;
418 };
Jonas Andersson4017f792013-05-27 10:52:21 +0200[diff] [blame]419
420 pinctrl_cspi_2: cspigrp-2 {
421 fsl,pins = <
422 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
423 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
424 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
425 >;
426 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]427 };
428
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]429 ecspi1 {
430 pinctrl_ecspi1_1: ecspi1grp-1 {
431 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]432 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
433 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
434 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]435 >;
436 };
Steffen Trumtrar6a079e62013-04-24 11:41:22 +0200[diff] [blame]437
438 pinctrl_ecspi1_2: ecspi1grp-2 {
439 fsl,pins = <
440 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
441 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
442 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
443 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
444 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
445 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
446 >;
447 };
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]448 };
449
Jonas Andersson1a6c5602013-05-27 10:52:45 +0200[diff] [blame]450 ecspi2 {
451 pinctrl_ecspi2_1: ecspi2grp-1 {
452 fsl,pins = <
453 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
454 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
455 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
456 >;
457 };
458 };
459
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]460 esdhc1 {
461 pinctrl_esdhc1_1: esdhc1grp-1 {
462 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]463 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
464 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
465 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
466 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
467 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
468 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]469 >;
470 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]471
472 pinctrl_esdhc1_2: esdhc1grp-2 {
473 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]474 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
475 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
476 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
477 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
478 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
479 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
480 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
481 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
482 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
483 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]484 >;
485 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]486 };
487
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]488 esdhc2 {
489 pinctrl_esdhc2_1: esdhc2grp-1 {
490 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]491 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
492 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
493 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
494 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
495 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
496 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]497 >;
498 };
499 };
500
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]501 esdhc3 {
502 pinctrl_esdhc3_1: esdhc3grp-1 {
503 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]504 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
505 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
506 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
507 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
508 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
509 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
510 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
511 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
512 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
513 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]514 >;
515 };
516 };
517
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]518 can1 {
519 pinctrl_can1_1: can1grp-1 {
520 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]521 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
522 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]523 >;
524 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]525
526 pinctrl_can1_2: can1grp-2 {
527 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]528 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
529 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]530 >;
531 };
Marek Vasut0f14ac42013-04-21 23:30:02 +0200[diff] [blame]532
533 pinctrl_can1_3: can1grp-3 {
534 fsl,pins = <
535 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
536 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
537 >;
538 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]539 };
540
541 can2 {
542 pinctrl_can2_1: can2grp-1 {
543 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]544 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
545 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]546 >;
547 };
548 };
549
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]550 i2c1 {
551 pinctrl_i2c1_1: i2c1grp-1 {
552 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]553 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
554 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]555 >;
556 };
Marek Vasutd7974712013-04-21 23:30:03 +0200[diff] [blame]557
558 pinctrl_i2c1_2: i2c1grp-2 {
559 fsl,pins = <
560 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
561 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
562 >;
563 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]564 };
565
566 i2c2 {
567 pinctrl_i2c2_1: i2c2grp-1 {
568 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]569 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
570 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]571 >;
572 };
Marek Vasuted5be462013-04-21 23:30:04 +0200[diff] [blame]573
574 pinctrl_i2c2_2: i2c2grp-2 {
575 fsl,pins = <
576 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
577 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
578 >;
579 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]580 };
581
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]582 i2c3 {
583 pinctrl_i2c3_1: i2c3grp-1 {
584 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]585 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
586 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]587 >;
588 };
589 };
590
Rogerio Pimentelc2689472013-05-24 11:09:30 -0300[diff] [blame]591 ipu_disp0 {
592 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
593 fsl,pins = <
594 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
595 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
596 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
597 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
598 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
599 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
600 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
601 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
602 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
603 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
604 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
605 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
606 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
607 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
608 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
609 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
610 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
611 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
612 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
613 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
614 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
615 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
616 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
617 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
618 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
619 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
620 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
621 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
622 >;
623 };
624 };
625
Marek Vasut9f7fbb12013-04-21 23:30:06 +0200[diff] [blame]626 ipu_disp1 {
627 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
628 fsl,pins = <
629 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
630 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
631 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
632 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
633 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
634 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
635 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
636 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
637 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
638 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
639 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
640 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
641 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
642 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
643 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
644 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
645 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
646 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
647 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
648 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
649 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
650 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
651 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
652 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
653 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
654 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
655 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
656 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
657 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
658 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
659 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
660 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
661 >;
662 };
663 };
664
665 ipu_disp2 {
666 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
667 fsl,pins = <
668 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
669 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
670 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
671 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
672 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
673 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
674 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
675 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
676 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
677 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
678 >;
679 };
680 };
681
Marek Vasutefee5e12013-04-21 23:30:05 +0200[diff] [blame]682 nand {
683 pinctrl_nand_1: nandgrp-1 {
684 fsl,pins = <
685 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
686 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
687 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
688 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
689 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
690 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
691 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
692 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
693 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
694 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
695 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
696 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
697 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
698 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
699 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
700 >;
701 };
702 };
703
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]704 owire {
705 pinctrl_owire_1: owiregrp-1 {
706 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]707 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]708 >;
709 };
710 };
711
Marek Vasut95050492013-04-21 23:30:07 +0200[diff] [blame]712 pwm1 {
713 pinctrl_pwm1_1: pwm1grp-1 {
714 fsl,pins = <
715 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
716 >;
717 };
718 };
719
Steffen Trumtrar20e081c2013-04-24 11:41:23 +0200[diff] [blame]720 pwm2 {
721 pinctrl_pwm2_1: pwm2grp-1 {
722 fsl,pins = <
723 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
724 >;
725 };
726 };
727
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]728 uart1 {
729 pinctrl_uart1_1: uart1grp-1 {
730 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]731 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
732 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]733 >;
734 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]735
736 pinctrl_uart1_2: uart1grp-2 {
737 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]738 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
739 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]740 >;
741 };
Steffen Trumtrar47d63392013-04-24 11:41:24 +0200[diff] [blame]742
743 pinctrl_uart1_3: uart1grp-3 {
744 fsl,pins = <
745 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
746 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
747 >;
748 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]749 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]750
751 uart2 {
752 pinctrl_uart2_1: uart2grp-1 {
753 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]754 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
755 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]756 >;
757 };
Steffen Trumtrarc3fcca22013-04-24 11:41:25 +0200[diff] [blame]758
759 pinctrl_uart2_2: uart2grp-2 {
760 fsl,pins = <
761 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
762 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
763 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
764 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
765 >;
766 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]767 };
768
769 uart3 {
770 pinctrl_uart3_1: uart3grp-1 {
771 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]772 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
773 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
774 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
775 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]776 >;
777 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]778
779 pinctrl_uart3_2: uart3grp-2 {
780 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]781 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
782 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]783 >;
784 };
785
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]786 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]787
788 uart4 {
789 pinctrl_uart4_1: uart4grp-1 {
790 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]791 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
792 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]793 >;
794 };
795 };
796
797 uart5 {
798 pinctrl_uart5_1: uart5grp-1 {
799 fsl,pins = <
Philipp Zabelf5786b82013-06-21 15:36:11 +0200[diff] [blame]800 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
801 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]802 >;
803 };
804 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]805 };
806
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]807 gpr: iomuxc-gpr@53fa8000 {
808 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
809 reg = <0x53fa8000 0xc>;
810 };
811
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]812 ldb: ldb@53fa8008 {
813 #address-cells = <1>;
814 #size-cells = <0>;
815 compatible = "fsl,imx53-ldb";
816 reg = <0x53fa8008 0x4>;
817 gpr = <&gpr>;
818 clocks = <&clks 122>, <&clks 120>,
819 <&clks 115>, <&clks 116>,
820 <&clks 123>, <&clks 85>;
821 clock-names = "di0_pll", "di1_pll",
822 "di0_sel", "di1_sel",
823 "di0", "di1";
824 status = "disabled";
825
826 lvds-channel@0 {
827 reg = <0>;
828 crtcs = <&ipu 0>;
829 status = "disabled";
830 };
831
832 lvds-channel@1 {
833 reg = <1>;
834 crtcs = <&ipu 1>;
835 status = "disabled";
836 };
837 };
838
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]839 pwm1: pwm@53fb4000 {
840 #pwm-cells = <2>;
841 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
842 reg = <0x53fb4000 0x4000>;
843 clocks = <&clks 37>, <&clks 38>;
844 clock-names = "ipg", "per";
845 interrupts = <61>;
846 };
847
848 pwm2: pwm@53fb8000 {
849 #pwm-cells = <2>;
850 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
851 reg = <0x53fb8000 0x4000>;
852 clocks = <&clks 39>, <&clks 40>;
853 clock-names = "ipg", "per";
854 interrupts = <94>;
855 };
856
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]857 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]858 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
859 reg = <0x53fbc000 0x4000>;
860 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]861 clocks = <&clks 28>, <&clks 29>;
862 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]863 status = "disabled";
864 };
865
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]866 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]867 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
868 reg = <0x53fc0000 0x4000>;
869 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]870 clocks = <&clks 30>, <&clks 31>;
871 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]872 status = "disabled";
873 };
874
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]875 can1: can@53fc8000 {
876 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
877 reg = <0x53fc8000 0x4000>;
878 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]879 clocks = <&clks 158>, <&clks 157>;
880 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]881 status = "disabled";
882 };
883
884 can2: can@53fcc000 {
885 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
886 reg = <0x53fcc000 0x4000>;
887 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]888 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]889 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]890 status = "disabled";
891 };
892
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]893 src: src@53fd0000 {
894 compatible = "fsl,imx53-src", "fsl,imx51-src";
895 reg = <0x53fd0000 0x4000>;
896 #reset-cells = <1>;
897 };
898
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]899 clks: ccm@53fd4000{
900 compatible = "fsl,imx53-ccm";
901 reg = <0x53fd4000 0x4000>;
902 interrupts = <0 71 0x04 0 72 0x04>;
903 #clock-cells = <1>;
904 };
905
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]906 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]907 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]908 reg = <0x53fdc000 0x4000>;
909 interrupts = <103 104>;
910 gpio-controller;
911 #gpio-cells = <2>;
912 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]913 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]914 };
915
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]916 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]917 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]918 reg = <0x53fe0000 0x4000>;
919 interrupts = <105 106>;
920 gpio-controller;
921 #gpio-cells = <2>;
922 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]923 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]924 };
925
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]926 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]927 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]928 reg = <0x53fe4000 0x4000>;
929 interrupts = <107 108>;
930 gpio-controller;
931 #gpio-cells = <2>;
932 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]933 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]934 };
935
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]936 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]937 #address-cells = <1>;
938 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]939 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]940 reg = <0x53fec000 0x4000>;
941 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]942 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]943 status = "disabled";
944 };
945
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]946 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]947 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
948 reg = <0x53ff0000 0x4000>;
949 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]950 clocks = <&clks 65>, <&clks 66>;
951 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]952 status = "disabled";
953 };
954 };
955
956 aips@60000000 { /* AIPS2 */
957 compatible = "fsl,aips-bus", "simple-bus";
958 #address-cells = <1>;
959 #size-cells = <1>;
960 reg = <0x60000000 0x10000000>;
961 ranges;
962
Sascha Hauer4f3b2a42013-06-25 15:51:52 +0200[diff] [blame]963 iim: iim@63f98000 {
964 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
965 reg = <0x63f98000 0x4000>;
966 interrupts = <69>;
967 clocks = <&clks 107>;
968 };
969
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]970 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]971 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
972 reg = <0x63f90000 0x4000>;
973 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]974 clocks = <&clks 67>, <&clks 68>;
975 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]976 status = "disabled";
977 };
978
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]979 owire: owire@63fa4000 {
980 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
981 reg = <0x63fa4000 0x4000>;
982 clocks = <&clks 159>;
983 status = "disabled";
984 };
985
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]986 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]987 #address-cells = <1>;
988 #size-cells = <0>;
989 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
990 reg = <0x63fac000 0x4000>;
991 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]992 clocks = <&clks 53>, <&clks 54>;
993 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]994 status = "disabled";
995 };
996
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]997 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]998 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
999 reg = <0x63fb0000 0x4000>;
1000 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1001 clocks = <&clks 56>, <&clks 56>;
1002 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]1003 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1004 };
1005
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1006 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1010 reg = <0x63fc0000 0x4000>;
1011 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]1012 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1013 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1014 status = "disabled";
1015 };
1016
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1017 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1018 #address-cells = <1>;
1019 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1020 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1021 reg = <0x63fc4000 0x4000>;
1022 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1023 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1024 status = "disabled";
1025 };
1026
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1027 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1028 #address-cells = <1>;
1029 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1030 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1031 reg = <0x63fc8000 0x4000>;
1032 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1033 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1034 status = "disabled";
1035 };
1036
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1037 ssi1: ssi@63fcc000 {
1038 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1039 reg = <0x63fcc000 0x4000>;
1040 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1041 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1042 fsl,fifo-depth = <15>;
1043 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1044 status = "disabled";
1045 };
1046
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1047 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1048 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1049 reg = <0x63fd0000 0x4000>;
1050 status = "disabled";
1051 };
1052
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1053 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]1054 compatible = "fsl,imx53-nand";
1055 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1056 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1057 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]1058 status = "disabled";
1059 };
1060
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1061 ssi3: ssi@63fe8000 {
1062 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1063 reg = <0x63fe8000 0x4000>;
1064 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1065 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]1066 fsl,fifo-depth = <15>;
1067 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1068 status = "disabled";
1069 };
1070
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1071 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1072 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1073 reg = <0x63fec000 0x4000>;
1074 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]1075 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1076 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1077 status = "disabled";
1078 };
Philipp Zabel19194c22013-06-04 12:12:22 +0200[diff] [blame]1079
1080 tve: tve@63ff0000 {
1081 compatible = "fsl,imx53-tve";
1082 reg = <0x63ff0000 0x1000>;
1083 interrupts = <92>;
1084 clocks = <&clks 69>, <&clks 116>;
1085 clock-names = "tve", "di_sel";
1086 crtcs = <&ipu 1>;
1087 status = "disabled";
1088 };
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1089 };
Philipp Zabel481fbe12013-07-01 11:06:09 +0200[diff] [blame^]1090
1091 ocram: sram@f8000000 {
1092 compatible = "mmio-sram";
1093 reg = <0xf8000000 0x20000>;
1094 };
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1095 };
1096};