Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 1 | /* |
| 2 | * HD audio interface patch for Creative CA0132 chip |
| 3 | * |
| 4 | * Copyright (c) 2011, Creative Technology Ltd. |
| 5 | * |
| 6 | * Based on patch_ca0110.c |
| 7 | * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> |
| 8 | * |
| 9 | * This driver is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This driver is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/mutex.h> |
Paul Gortmaker | da155d5 | 2011-07-15 12:38:28 -0400 | [diff] [blame] | 29 | #include <linux/module.h> |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 30 | #include <linux/firmware.h> |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 31 | #include <sound/core.h> |
| 32 | #include "hda_codec.h" |
| 33 | #include "hda_local.h" |
Takashi Iwai | 128bc4b | 2012-05-07 17:42:31 +0200 | [diff] [blame] | 34 | #include "hda_auto_parser.h" |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 35 | |
Ian Minett | bcd109c | 2012-09-20 20:29:14 -0700 | [diff] [blame] | 36 | #include "ca0132_regs.h" |
| 37 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 38 | #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) |
| 39 | #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) |
| 40 | |
| 41 | #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 |
| 42 | #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 |
| 43 | #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 |
| 44 | |
| 45 | #define MASTERCONTROL 0x80 |
| 46 | #define MASTERCONTROL_ALLOC_DMA_CHAN 9 |
| 47 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 48 | #define WIDGET_CHIP_CTRL 0x15 |
| 49 | #define WIDGET_DSP_CTRL 0x16 |
| 50 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 51 | #define MEM_CONNID_MICIN1 3 |
| 52 | #define MEM_CONNID_MICIN2 5 |
| 53 | #define MEM_CONNID_MICOUT1 12 |
| 54 | #define MEM_CONNID_MICOUT2 14 |
| 55 | #define MEM_CONNID_WUH 10 |
| 56 | #define MEM_CONNID_DSP 16 |
| 57 | #define MEM_CONNID_DMIC 100 |
| 58 | |
| 59 | #define SCP_SET 0 |
| 60 | #define SCP_GET 1 |
| 61 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 62 | #define EFX_FILE "ctefx.bin" |
| 63 | |
| 64 | MODULE_FIRMWARE(EFX_FILE); |
| 65 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 66 | enum hda_cmd_vendor_io { |
| 67 | /* for DspIO node */ |
| 68 | VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, |
| 69 | VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, |
| 70 | |
| 71 | VENDOR_DSPIO_STATUS = 0xF01, |
| 72 | VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, |
| 73 | VENDOR_DSPIO_SCP_READ_DATA = 0xF02, |
| 74 | VENDOR_DSPIO_DSP_INIT = 0x703, |
| 75 | VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, |
| 76 | VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, |
| 77 | |
| 78 | /* for ChipIO node */ |
| 79 | VENDOR_CHIPIO_ADDRESS_LOW = 0x000, |
| 80 | VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, |
| 81 | VENDOR_CHIPIO_STREAM_FORMAT = 0x200, |
| 82 | VENDOR_CHIPIO_DATA_LOW = 0x300, |
| 83 | VENDOR_CHIPIO_DATA_HIGH = 0x400, |
| 84 | |
| 85 | VENDOR_CHIPIO_GET_PARAMETER = 0xF00, |
| 86 | VENDOR_CHIPIO_STATUS = 0xF01, |
| 87 | VENDOR_CHIPIO_HIC_POST_READ = 0x702, |
| 88 | VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, |
| 89 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 90 | VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, |
| 91 | VENDOR_CHIPIO_8051_DATA_READ = 0xF07, |
| 92 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 93 | VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 94 | VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 95 | |
| 96 | VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, |
| 97 | VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, |
| 98 | VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, |
| 99 | VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, |
| 100 | VENDOR_CHIPIO_FLAG_SET = 0x70F, |
| 101 | VENDOR_CHIPIO_FLAGS_GET = 0xF0F, |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 102 | VENDOR_CHIPIO_PARAM_SET = 0x710, |
| 103 | VENDOR_CHIPIO_PARAM_GET = 0xF10, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 104 | |
| 105 | VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, |
| 106 | VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, |
| 107 | VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, |
| 108 | VENDOR_CHIPIO_PORT_FREE_SET = 0x713, |
| 109 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 110 | VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, |
| 111 | VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, |
| 112 | VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, |
| 113 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, |
| 114 | |
| 115 | VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, |
| 116 | VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, |
| 117 | VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, |
| 118 | VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, |
| 119 | VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, |
| 120 | VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, |
| 121 | |
| 122 | VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | /* |
| 126 | * Control flag IDs |
| 127 | */ |
| 128 | enum control_flag_id { |
| 129 | /* Connection manager stream setup is bypassed/enabled */ |
| 130 | CONTROL_FLAG_C_MGR = 0, |
| 131 | /* DSP DMA is bypassed/enabled */ |
| 132 | CONTROL_FLAG_DMA = 1, |
| 133 | /* 8051 'idle' mode is disabled/enabled */ |
| 134 | CONTROL_FLAG_IDLE_ENABLE = 2, |
| 135 | /* Tracker for the SPDIF-in path is bypassed/enabled */ |
| 136 | CONTROL_FLAG_TRACKER = 3, |
| 137 | /* DigitalOut to Spdif2Out connection is disabled/enabled */ |
| 138 | CONTROL_FLAG_SPDIF2OUT = 4, |
| 139 | /* Digital Microphone is disabled/enabled */ |
| 140 | CONTROL_FLAG_DMIC = 5, |
| 141 | /* ADC_B rate is 48 kHz/96 kHz */ |
| 142 | CONTROL_FLAG_ADC_B_96KHZ = 6, |
| 143 | /* ADC_C rate is 48 kHz/96 kHz */ |
| 144 | CONTROL_FLAG_ADC_C_96KHZ = 7, |
| 145 | /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ |
| 146 | CONTROL_FLAG_DAC_96KHZ = 8, |
| 147 | /* DSP rate is 48 kHz/96 kHz */ |
| 148 | CONTROL_FLAG_DSP_96KHZ = 9, |
| 149 | /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ |
| 150 | CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, |
| 151 | /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ |
| 152 | CONTROL_FLAG_SRC_RATE_96KHZ = 11, |
| 153 | /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ |
| 154 | CONTROL_FLAG_DECODE_LOOP = 12, |
| 155 | /* De-emphasis filter on DAC-1 disabled/enabled */ |
| 156 | CONTROL_FLAG_DAC1_DEEMPHASIS = 13, |
| 157 | /* De-emphasis filter on DAC-2 disabled/enabled */ |
| 158 | CONTROL_FLAG_DAC2_DEEMPHASIS = 14, |
| 159 | /* De-emphasis filter on DAC-3 disabled/enabled */ |
| 160 | CONTROL_FLAG_DAC3_DEEMPHASIS = 15, |
| 161 | /* High-pass filter on ADC_B disabled/enabled */ |
| 162 | CONTROL_FLAG_ADC_B_HIGH_PASS = 16, |
| 163 | /* High-pass filter on ADC_C disabled/enabled */ |
| 164 | CONTROL_FLAG_ADC_C_HIGH_PASS = 17, |
| 165 | /* Common mode on Port_A disabled/enabled */ |
| 166 | CONTROL_FLAG_PORT_A_COMMON_MODE = 18, |
| 167 | /* Common mode on Port_D disabled/enabled */ |
| 168 | CONTROL_FLAG_PORT_D_COMMON_MODE = 19, |
| 169 | /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ |
| 170 | CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, |
| 171 | /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 172 | CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 173 | /* ASI rate is 48kHz/96kHz */ |
| 174 | CONTROL_FLAG_ASI_96KHZ = 22, |
| 175 | /* DAC power settings able to control attached ports no/yes */ |
| 176 | CONTROL_FLAG_DACS_CONTROL_PORTS = 23, |
| 177 | /* Clock Stop OK reporting is disabled/enabled */ |
| 178 | CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, |
| 179 | /* Number of control flags */ |
| 180 | CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) |
| 181 | }; |
| 182 | |
| 183 | /* |
| 184 | * Control parameter IDs |
| 185 | */ |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 186 | enum control_param_id { |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 187 | /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ |
| 188 | CONTROL_PARAM_SPDIF1_SOURCE = 2, |
| 189 | |
| 190 | /* Stream Control */ |
| 191 | |
| 192 | /* Select stream with the given ID */ |
| 193 | CONTROL_PARAM_STREAM_ID = 24, |
| 194 | /* Source connection point for the selected stream */ |
| 195 | CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, |
| 196 | /* Destination connection point for the selected stream */ |
| 197 | CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, |
| 198 | /* Number of audio channels in the selected stream */ |
| 199 | CONTROL_PARAM_STREAMS_CHANNELS = 27, |
| 200 | /*Enable control for the selected stream */ |
| 201 | CONTROL_PARAM_STREAM_CONTROL = 28, |
| 202 | |
| 203 | /* Connection Point Control */ |
| 204 | |
| 205 | /* Select connection point with the given ID */ |
| 206 | CONTROL_PARAM_CONN_POINT_ID = 29, |
| 207 | /* Connection point sample rate */ |
| 208 | CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, |
| 209 | |
| 210 | /* Node Control */ |
| 211 | |
| 212 | /* Select HDA node with the given ID */ |
| 213 | CONTROL_PARAM_NODE_ID = 31 |
| 214 | }; |
| 215 | |
| 216 | /* |
| 217 | * Dsp Io Status codes |
| 218 | */ |
| 219 | enum hda_vendor_status_dspio { |
| 220 | /* Success */ |
| 221 | VENDOR_STATUS_DSPIO_OK = 0x00, |
| 222 | /* Busy, unable to accept new command, the host must retry */ |
| 223 | VENDOR_STATUS_DSPIO_BUSY = 0x01, |
| 224 | /* SCP command queue is full */ |
| 225 | VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, |
| 226 | /* SCP response queue is empty */ |
| 227 | VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 |
| 228 | }; |
| 229 | |
| 230 | /* |
| 231 | * Chip Io Status codes |
| 232 | */ |
| 233 | enum hda_vendor_status_chipio { |
| 234 | /* Success */ |
| 235 | VENDOR_STATUS_CHIPIO_OK = 0x00, |
| 236 | /* Busy, unable to accept new command, the host must retry */ |
| 237 | VENDOR_STATUS_CHIPIO_BUSY = 0x01 |
| 238 | }; |
| 239 | |
| 240 | /* |
| 241 | * CA0132 sample rate |
| 242 | */ |
| 243 | enum ca0132_sample_rate { |
| 244 | SR_6_000 = 0x00, |
| 245 | SR_8_000 = 0x01, |
| 246 | SR_9_600 = 0x02, |
| 247 | SR_11_025 = 0x03, |
| 248 | SR_16_000 = 0x04, |
| 249 | SR_22_050 = 0x05, |
| 250 | SR_24_000 = 0x06, |
| 251 | SR_32_000 = 0x07, |
| 252 | SR_44_100 = 0x08, |
| 253 | SR_48_000 = 0x09, |
| 254 | SR_88_200 = 0x0A, |
| 255 | SR_96_000 = 0x0B, |
| 256 | SR_144_000 = 0x0C, |
| 257 | SR_176_400 = 0x0D, |
| 258 | SR_192_000 = 0x0E, |
| 259 | SR_384_000 = 0x0F, |
| 260 | |
| 261 | SR_COUNT = 0x10, |
| 262 | |
| 263 | SR_RATE_UNKNOWN = 0x1F |
| 264 | }; |
| 265 | |
| 266 | /* |
| 267 | * Scp Helper function |
| 268 | */ |
| 269 | enum get_set { |
| 270 | IS_SET = 0, |
| 271 | IS_GET = 1, |
| 272 | }; |
| 273 | |
| 274 | /* |
| 275 | * Duplicated from ca0110 codec |
| 276 | */ |
| 277 | |
| 278 | static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) |
| 279 | { |
| 280 | if (pin) { |
Takashi Iwai | cdd03ce | 2012-04-20 12:34:50 +0200 | [diff] [blame] | 281 | snd_hda_set_pin_ctl(codec, pin, PIN_HP); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 282 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) |
| 283 | snd_hda_codec_write(codec, pin, 0, |
| 284 | AC_VERB_SET_AMP_GAIN_MUTE, |
| 285 | AMP_OUT_UNMUTE); |
| 286 | } |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 287 | if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 288 | snd_hda_codec_write(codec, dac, 0, |
| 289 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); |
| 290 | } |
| 291 | |
| 292 | static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) |
| 293 | { |
| 294 | if (pin) { |
Takashi Iwai | 4740860 | 2012-04-20 13:06:53 +0200 | [diff] [blame] | 295 | snd_hda_set_pin_ctl(codec, pin, PIN_IN | |
| 296 | snd_hda_get_default_vref(codec, pin)); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 297 | if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) |
| 298 | snd_hda_codec_write(codec, pin, 0, |
| 299 | AC_VERB_SET_AMP_GAIN_MUTE, |
| 300 | AMP_IN_UNMUTE(0)); |
| 301 | } |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 302 | if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 303 | snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, |
| 304 | AMP_IN_UNMUTE(0)); |
| 305 | } |
| 306 | |
| 307 | static char *dirstr[2] = { "Playback", "Capture" }; |
| 308 | |
| 309 | static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx, |
| 310 | int chan, int dir) |
| 311 | { |
| 312 | char namestr[44]; |
| 313 | int type = dir ? HDA_INPUT : HDA_OUTPUT; |
| 314 | struct snd_kcontrol_new knew = |
| 315 | HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type); |
David Henningsson | c41999a | 2012-08-20 11:17:00 +0200 | [diff] [blame] | 316 | if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_MUTE) == 0) { |
| 317 | snd_printdd("Skipping '%s %s Switch' (no mute on node 0x%x)\n", pfx, dirstr[dir], nid); |
| 318 | return 0; |
| 319 | } |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 320 | sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); |
| 321 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 322 | } |
| 323 | |
| 324 | static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx, |
| 325 | int chan, int dir) |
| 326 | { |
| 327 | char namestr[44]; |
| 328 | int type = dir ? HDA_INPUT : HDA_OUTPUT; |
| 329 | struct snd_kcontrol_new knew = |
| 330 | HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type); |
David Henningsson | c41999a | 2012-08-20 11:17:00 +0200 | [diff] [blame] | 331 | if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_NUM_STEPS) == 0) { |
| 332 | snd_printdd("Skipping '%s %s Volume' (no amp on node 0x%x)\n", pfx, dirstr[dir], nid); |
| 333 | return 0; |
| 334 | } |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 335 | sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]); |
| 336 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 337 | } |
| 338 | |
| 339 | #define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0) |
| 340 | #define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0) |
| 341 | #define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1) |
| 342 | #define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1) |
| 343 | #define add_mono_switch(codec, nid, pfx, chan) \ |
| 344 | _add_switch(codec, nid, pfx, chan, 0) |
| 345 | #define add_mono_volume(codec, nid, pfx, chan) \ |
| 346 | _add_volume(codec, nid, pfx, chan, 0) |
| 347 | #define add_in_mono_switch(codec, nid, pfx, chan) \ |
| 348 | _add_switch(codec, nid, pfx, chan, 1) |
| 349 | #define add_in_mono_volume(codec, nid, pfx, chan) \ |
| 350 | _add_volume(codec, nid, pfx, chan, 1) |
| 351 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 352 | enum dsp_download_state { |
| 353 | DSP_DOWNLOAD_FAILED = -1, |
| 354 | DSP_DOWNLOAD_INIT = 0, |
| 355 | DSP_DOWNLOADING = 1, |
| 356 | DSP_DOWNLOADED = 2 |
| 357 | }; |
| 358 | |
| 359 | struct hda_stream_format { |
| 360 | unsigned int sample_rate; |
| 361 | unsigned short valid_bits_per_sample; |
| 362 | unsigned short container_size; |
| 363 | unsigned short number_channels; |
| 364 | }; |
| 365 | |
| 366 | /* retrieve parameters from hda format */ |
| 367 | #define get_hdafmt_chs(fmt) (fmt & 0xf) |
| 368 | #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) |
| 369 | #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) |
| 370 | #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 371 | |
| 372 | /* |
| 373 | * CA0132 specific |
| 374 | */ |
| 375 | |
| 376 | struct ca0132_spec { |
| 377 | struct auto_pin_cfg autocfg; |
| 378 | struct hda_multi_out multiout; |
| 379 | hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; |
| 380 | hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; |
| 381 | hda_nid_t hp_dac; |
| 382 | hda_nid_t input_pins[AUTO_PIN_LAST]; |
| 383 | hda_nid_t adcs[AUTO_PIN_LAST]; |
| 384 | hda_nid_t dig_out; |
| 385 | hda_nid_t dig_in; |
| 386 | unsigned int num_inputs; |
| 387 | long curr_hp_switch; |
| 388 | long curr_hp_volume[2]; |
| 389 | long curr_speaker_switch; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 390 | const char *input_labels[AUTO_PIN_LAST]; |
| 391 | struct hda_pcm pcm_rec[2]; /* PCM information */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 392 | |
| 393 | /* chip access */ |
| 394 | struct mutex chipio_mutex; /* chip access mutex */ |
| 395 | u32 curr_chip_addx; |
| 396 | |
| 397 | /* DSP download related */ |
| 398 | enum dsp_download_state dsp_state; |
| 399 | unsigned int dsp_stream_id; |
| 400 | unsigned int wait_scp; |
| 401 | unsigned int wait_scp_header; |
| 402 | unsigned int wait_num_data; |
| 403 | unsigned int scp_resp_header; |
| 404 | unsigned int scp_resp_data[4]; |
| 405 | unsigned int scp_resp_count; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 406 | }; |
| 407 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 408 | /* |
| 409 | * CA0132 codec access |
| 410 | */ |
| 411 | unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, |
| 412 | unsigned int verb, unsigned int parm, unsigned int *res) |
| 413 | { |
| 414 | unsigned int response; |
| 415 | response = snd_hda_codec_read(codec, nid, 0, verb, parm); |
| 416 | *res = response; |
| 417 | |
| 418 | return ((response == -1) ? -1 : 0); |
| 419 | } |
| 420 | |
| 421 | static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, |
| 422 | unsigned short converter_format, unsigned int *res) |
| 423 | { |
| 424 | return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, |
| 425 | converter_format & 0xffff, res); |
| 426 | } |
| 427 | |
| 428 | static int codec_set_converter_stream_channel(struct hda_codec *codec, |
| 429 | hda_nid_t nid, unsigned char stream, |
| 430 | unsigned char channel, unsigned int *res) |
| 431 | { |
| 432 | unsigned char converter_stream_channel = 0; |
| 433 | |
| 434 | converter_stream_channel = (stream << 4) | (channel & 0x0f); |
| 435 | return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, |
| 436 | converter_stream_channel, res); |
| 437 | } |
| 438 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 439 | /* Chip access helper function */ |
| 440 | static int chipio_send(struct hda_codec *codec, |
| 441 | unsigned int reg, |
| 442 | unsigned int data) |
| 443 | { |
| 444 | unsigned int res; |
| 445 | int retry = 50; |
| 446 | |
| 447 | /* send bits of data specified by reg */ |
| 448 | do { |
| 449 | res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, |
| 450 | reg, data); |
| 451 | if (res == VENDOR_STATUS_CHIPIO_OK) |
| 452 | return 0; |
| 453 | } while (--retry); |
| 454 | return -EIO; |
| 455 | } |
| 456 | |
| 457 | /* |
| 458 | * Write chip address through the vendor widget -- NOT protected by the Mutex! |
| 459 | */ |
| 460 | static int chipio_write_address(struct hda_codec *codec, |
| 461 | unsigned int chip_addx) |
| 462 | { |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame^] | 463 | struct ca0132_spec *spec = codec->spec; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 464 | int res; |
| 465 | |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame^] | 466 | if (spec->curr_chip_addx == chip_addx) |
| 467 | return 0; |
| 468 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 469 | /* send low 16 bits of the address */ |
| 470 | res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, |
| 471 | chip_addx & 0xffff); |
| 472 | |
| 473 | if (res != -EIO) { |
| 474 | /* send high 16 bits of the address */ |
| 475 | res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, |
| 476 | chip_addx >> 16); |
| 477 | } |
| 478 | |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame^] | 479 | spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx; |
| 480 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 481 | return res; |
| 482 | } |
| 483 | |
| 484 | /* |
| 485 | * Write data through the vendor widget -- NOT protected by the Mutex! |
| 486 | */ |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 487 | static int chipio_write_data(struct hda_codec *codec, unsigned int data) |
| 488 | { |
| 489 | int res; |
| 490 | |
| 491 | /* send low 16 bits of the data */ |
| 492 | res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); |
| 493 | |
| 494 | if (res != -EIO) { |
| 495 | /* send high 16 bits of the data */ |
| 496 | res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, |
| 497 | data >> 16); |
| 498 | } |
| 499 | |
| 500 | return res; |
| 501 | } |
| 502 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 503 | /* |
| 504 | * Write multiple data through the vendor widget -- NOT protected by the Mutex! |
| 505 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 506 | static int chipio_write_data_multiple(struct hda_codec *codec, |
| 507 | const u32 *data, |
| 508 | unsigned int count) |
| 509 | { |
| 510 | int status = 0; |
| 511 | |
| 512 | if (data == NULL) { |
| 513 | snd_printdd(KERN_ERR "chipio_write_data null ptr"); |
| 514 | return -EINVAL; |
| 515 | } |
| 516 | |
| 517 | while ((count-- != 0) && (status == 0)) |
| 518 | status = chipio_write_data(codec, *data++); |
| 519 | |
| 520 | return status; |
| 521 | } |
| 522 | |
| 523 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 524 | /* |
| 525 | * Read data through the vendor widget -- NOT protected by the Mutex! |
| 526 | */ |
| 527 | static int chipio_read_data(struct hda_codec *codec, unsigned int *data) |
| 528 | { |
| 529 | int res; |
| 530 | |
| 531 | /* post read */ |
| 532 | res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); |
| 533 | |
| 534 | if (res != -EIO) { |
| 535 | /* read status */ |
| 536 | res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 537 | } |
| 538 | |
| 539 | if (res != -EIO) { |
| 540 | /* read data */ |
| 541 | *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, |
| 542 | VENDOR_CHIPIO_HIC_READ_DATA, |
| 543 | 0); |
| 544 | } |
| 545 | |
| 546 | return res; |
| 547 | } |
| 548 | |
| 549 | /* |
| 550 | * Write given value to the given address through the chip I/O widget. |
| 551 | * protected by the Mutex |
| 552 | */ |
| 553 | static int chipio_write(struct hda_codec *codec, |
| 554 | unsigned int chip_addx, const unsigned int data) |
| 555 | { |
| 556 | struct ca0132_spec *spec = codec->spec; |
| 557 | int err; |
| 558 | |
| 559 | mutex_lock(&spec->chipio_mutex); |
| 560 | |
| 561 | /* write the address, and if successful proceed to write data */ |
| 562 | err = chipio_write_address(codec, chip_addx); |
| 563 | if (err < 0) |
| 564 | goto exit; |
| 565 | |
| 566 | err = chipio_write_data(codec, data); |
| 567 | if (err < 0) |
| 568 | goto exit; |
| 569 | |
| 570 | exit: |
| 571 | mutex_unlock(&spec->chipio_mutex); |
| 572 | return err; |
| 573 | } |
| 574 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 575 | /* |
| 576 | * Write multiple values to the given address through the chip I/O widget. |
| 577 | * protected by the Mutex |
| 578 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 579 | static int chipio_write_multiple(struct hda_codec *codec, |
| 580 | u32 chip_addx, |
| 581 | const u32 *data, |
| 582 | unsigned int count) |
| 583 | { |
| 584 | struct ca0132_spec *spec = codec->spec; |
| 585 | int status; |
| 586 | |
| 587 | mutex_lock(&spec->chipio_mutex); |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame^] | 588 | status = chipio_write_address(codec, chip_addx); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 589 | if (status < 0) |
| 590 | goto error; |
| 591 | |
| 592 | status = chipio_write_data_multiple(codec, data, count); |
| 593 | error: |
| 594 | mutex_unlock(&spec->chipio_mutex); |
| 595 | |
| 596 | return status; |
| 597 | } |
| 598 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 599 | /* |
| 600 | * Read the given address through the chip I/O widget |
| 601 | * protected by the Mutex |
| 602 | */ |
| 603 | static int chipio_read(struct hda_codec *codec, |
| 604 | unsigned int chip_addx, unsigned int *data) |
| 605 | { |
| 606 | struct ca0132_spec *spec = codec->spec; |
| 607 | int err; |
| 608 | |
| 609 | mutex_lock(&spec->chipio_mutex); |
| 610 | |
| 611 | /* write the address, and if successful proceed to write data */ |
| 612 | err = chipio_write_address(codec, chip_addx); |
| 613 | if (err < 0) |
| 614 | goto exit; |
| 615 | |
| 616 | err = chipio_read_data(codec, data); |
| 617 | if (err < 0) |
| 618 | goto exit; |
| 619 | |
| 620 | exit: |
| 621 | mutex_unlock(&spec->chipio_mutex); |
| 622 | return err; |
| 623 | } |
| 624 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 625 | /* |
| 626 | * Set chip control flags through the chip I/O widget. |
| 627 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 628 | static void chipio_set_control_flag(struct hda_codec *codec, |
| 629 | enum control_flag_id flag_id, |
| 630 | bool flag_state) |
| 631 | { |
| 632 | unsigned int val; |
| 633 | unsigned int flag_bit; |
| 634 | |
| 635 | flag_bit = (flag_state ? 1 : 0); |
| 636 | val = (flag_bit << 7) | (flag_id); |
| 637 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 638 | VENDOR_CHIPIO_FLAG_SET, val); |
| 639 | } |
| 640 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 641 | /* |
| 642 | * Set chip parameters through the chip I/O widget. |
| 643 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 644 | static void chipio_set_control_param(struct hda_codec *codec, |
| 645 | enum control_param_id param_id, int param_val) |
| 646 | { |
| 647 | struct ca0132_spec *spec = codec->spec; |
| 648 | int val; |
| 649 | |
| 650 | if ((param_id < 32) && (param_val < 8)) { |
| 651 | val = (param_val << 5) | (param_id); |
| 652 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 653 | VENDOR_CHIPIO_PARAM_SET, val); |
| 654 | } else { |
| 655 | mutex_lock(&spec->chipio_mutex); |
| 656 | if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { |
| 657 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 658 | VENDOR_CHIPIO_PARAM_EX_ID_SET, |
| 659 | param_id); |
| 660 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 661 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET, |
| 662 | param_val); |
| 663 | } |
| 664 | mutex_unlock(&spec->chipio_mutex); |
| 665 | } |
| 666 | } |
| 667 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 668 | /* |
| 669 | * Set sampling rate of the connection point. |
| 670 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 671 | static void chipio_set_conn_rate(struct hda_codec *codec, |
| 672 | int connid, enum ca0132_sample_rate rate) |
| 673 | { |
| 674 | chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); |
| 675 | chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, |
| 676 | rate); |
| 677 | } |
| 678 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 679 | /* |
| 680 | * Enable clocks. |
| 681 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 682 | static void chipio_enable_clocks(struct hda_codec *codec) |
| 683 | { |
| 684 | struct ca0132_spec *spec = codec->spec; |
| 685 | |
| 686 | mutex_lock(&spec->chipio_mutex); |
| 687 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 688 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); |
| 689 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 690 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); |
| 691 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 692 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); |
| 693 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 694 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); |
| 695 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 696 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); |
| 697 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 698 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); |
| 699 | mutex_unlock(&spec->chipio_mutex); |
| 700 | } |
| 701 | |
| 702 | /* |
| 703 | * CA0132 DSP IO stuffs |
| 704 | */ |
| 705 | static int dspio_send(struct hda_codec *codec, unsigned int reg, |
| 706 | unsigned int data) |
| 707 | { |
| 708 | unsigned int res; |
| 709 | int retry = 50; |
| 710 | |
| 711 | /* send bits of data specified by reg to dsp */ |
| 712 | do { |
| 713 | res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); |
| 714 | if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) |
| 715 | return res; |
| 716 | } while (--retry); |
| 717 | |
| 718 | return -EIO; |
| 719 | } |
| 720 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 721 | /* |
| 722 | * Wait for DSP to be ready for commands |
| 723 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 724 | static void dspio_write_wait(struct hda_codec *codec) |
| 725 | { |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame^] | 726 | int status; |
| 727 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 728 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 729 | do { |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame^] | 730 | status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, |
| 731 | VENDOR_DSPIO_STATUS, 0); |
| 732 | if ((status == VENDOR_STATUS_DSPIO_OK) || |
| 733 | (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) |
| 734 | break; |
| 735 | msleep(1); |
| 736 | } while (time_before(jiffies, timeout)); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 737 | } |
| 738 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 739 | /* |
| 740 | * Write SCP data to DSP |
| 741 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 742 | static int dspio_write(struct hda_codec *codec, unsigned int scp_data) |
| 743 | { |
| 744 | struct ca0132_spec *spec = codec->spec; |
| 745 | int status; |
| 746 | |
| 747 | dspio_write_wait(codec); |
| 748 | |
| 749 | mutex_lock(&spec->chipio_mutex); |
| 750 | status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, |
| 751 | scp_data & 0xffff); |
| 752 | if (status < 0) |
| 753 | goto error; |
| 754 | |
| 755 | status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, |
| 756 | scp_data >> 16); |
| 757 | if (status < 0) |
| 758 | goto error; |
| 759 | |
| 760 | /* OK, now check if the write itself has executed*/ |
| 761 | status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, |
| 762 | VENDOR_DSPIO_STATUS, 0); |
| 763 | error: |
| 764 | mutex_unlock(&spec->chipio_mutex); |
| 765 | |
| 766 | return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? |
| 767 | -EIO : 0; |
| 768 | } |
| 769 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 770 | /* |
| 771 | * Write multiple SCP data to DSP |
| 772 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 773 | static int dspio_write_multiple(struct hda_codec *codec, |
| 774 | unsigned int *buffer, unsigned int size) |
| 775 | { |
| 776 | int status = 0; |
| 777 | unsigned int count; |
| 778 | |
| 779 | if ((buffer == NULL)) |
| 780 | return -EINVAL; |
| 781 | |
| 782 | count = 0; |
| 783 | while (count < size) { |
| 784 | status = dspio_write(codec, *buffer++); |
| 785 | if (status != 0) |
| 786 | break; |
| 787 | count++; |
| 788 | } |
| 789 | |
| 790 | return status; |
| 791 | } |
| 792 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 793 | /* |
| 794 | * Construct the SCP header using corresponding fields |
| 795 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 796 | static inline unsigned int |
| 797 | make_scp_header(unsigned int target_id, unsigned int source_id, |
| 798 | unsigned int get_flag, unsigned int req, |
| 799 | unsigned int device_flag, unsigned int resp_flag, |
| 800 | unsigned int error_flag, unsigned int data_size) |
| 801 | { |
| 802 | unsigned int header = 0; |
| 803 | |
| 804 | header = (data_size & 0x1f) << 27; |
| 805 | header |= (error_flag & 0x01) << 26; |
| 806 | header |= (resp_flag & 0x01) << 25; |
| 807 | header |= (device_flag & 0x01) << 24; |
| 808 | header |= (req & 0x7f) << 17; |
| 809 | header |= (get_flag & 0x01) << 16; |
| 810 | header |= (source_id & 0xff) << 8; |
| 811 | header |= target_id & 0xff; |
| 812 | |
| 813 | return header; |
| 814 | } |
| 815 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 816 | /* |
| 817 | * Extract corresponding fields from SCP header |
| 818 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 819 | static inline void |
| 820 | extract_scp_header(unsigned int header, |
| 821 | unsigned int *target_id, unsigned int *source_id, |
| 822 | unsigned int *get_flag, unsigned int *req, |
| 823 | unsigned int *device_flag, unsigned int *resp_flag, |
| 824 | unsigned int *error_flag, unsigned int *data_size) |
| 825 | { |
| 826 | if (data_size) |
| 827 | *data_size = (header >> 27) & 0x1f; |
| 828 | if (error_flag) |
| 829 | *error_flag = (header >> 26) & 0x01; |
| 830 | if (resp_flag) |
| 831 | *resp_flag = (header >> 25) & 0x01; |
| 832 | if (device_flag) |
| 833 | *device_flag = (header >> 24) & 0x01; |
| 834 | if (req) |
| 835 | *req = (header >> 17) & 0x7f; |
| 836 | if (get_flag) |
| 837 | *get_flag = (header >> 16) & 0x01; |
| 838 | if (source_id) |
| 839 | *source_id = (header >> 8) & 0xff; |
| 840 | if (target_id) |
| 841 | *target_id = header & 0xff; |
| 842 | } |
| 843 | |
| 844 | #define SCP_MAX_DATA_WORDS (16) |
| 845 | |
| 846 | /* Structure to contain any SCP message */ |
| 847 | struct scp_msg { |
| 848 | unsigned int hdr; |
| 849 | unsigned int data[SCP_MAX_DATA_WORDS]; |
| 850 | }; |
| 851 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 852 | /* |
| 853 | * Send SCP message to DSP |
| 854 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 855 | static int dspio_send_scp_message(struct hda_codec *codec, |
| 856 | unsigned char *send_buf, |
| 857 | unsigned int send_buf_size, |
| 858 | unsigned char *return_buf, |
| 859 | unsigned int return_buf_size, |
| 860 | unsigned int *bytes_returned) |
| 861 | { |
| 862 | struct ca0132_spec *spec = codec->spec; |
| 863 | int retry; |
| 864 | int status = -1; |
| 865 | unsigned int scp_send_size = 0; |
| 866 | unsigned int total_size; |
| 867 | bool waiting_for_resp = false; |
| 868 | unsigned int header; |
| 869 | struct scp_msg *ret_msg; |
| 870 | unsigned int resp_src_id, resp_target_id; |
| 871 | unsigned int data_size, src_id, target_id, get_flag, device_flag; |
| 872 | |
| 873 | if (bytes_returned) |
| 874 | *bytes_returned = 0; |
| 875 | |
| 876 | /* get scp header from buffer */ |
| 877 | header = *((unsigned int *)send_buf); |
| 878 | extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, |
| 879 | &device_flag, NULL, NULL, &data_size); |
| 880 | scp_send_size = data_size + 1; |
| 881 | total_size = (scp_send_size * 4); |
| 882 | |
| 883 | if (send_buf_size < total_size) |
| 884 | return -EINVAL; |
| 885 | |
| 886 | if (get_flag || device_flag) { |
| 887 | if (!return_buf || return_buf_size < 4 || !bytes_returned) |
| 888 | return -EINVAL; |
| 889 | |
| 890 | spec->wait_scp_header = *((unsigned int *)send_buf); |
| 891 | |
| 892 | /* swap source id with target id */ |
| 893 | resp_target_id = src_id; |
| 894 | resp_src_id = target_id; |
| 895 | spec->wait_scp_header &= 0xffff0000; |
| 896 | spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); |
| 897 | spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; |
| 898 | spec->wait_scp = 1; |
| 899 | waiting_for_resp = true; |
| 900 | } |
| 901 | |
| 902 | status = dspio_write_multiple(codec, (unsigned int *)send_buf, |
| 903 | scp_send_size); |
| 904 | if (status < 0) { |
| 905 | spec->wait_scp = 0; |
| 906 | return status; |
| 907 | } |
| 908 | |
| 909 | if (waiting_for_resp) { |
| 910 | memset(return_buf, 0, return_buf_size); |
| 911 | retry = 50; |
| 912 | do { |
| 913 | msleep(20); |
| 914 | } while (spec->wait_scp && (--retry != 0)); |
| 915 | waiting_for_resp = false; |
| 916 | if (retry != 0) { |
| 917 | ret_msg = (struct scp_msg *)return_buf; |
| 918 | memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); |
| 919 | memcpy(&ret_msg->data, spec->scp_resp_data, |
| 920 | spec->wait_num_data); |
| 921 | *bytes_returned = (spec->scp_resp_count + 1) * 4; |
| 922 | status = 0; |
| 923 | } else { |
| 924 | status = -EIO; |
| 925 | } |
| 926 | spec->wait_scp = 0; |
| 927 | } |
| 928 | |
| 929 | return status; |
| 930 | } |
| 931 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 932 | /** |
| 933 | * Prepare and send the SCP message to DSP |
| 934 | * @codec: the HDA codec |
| 935 | * @mod_id: ID of the DSP module to send the command |
| 936 | * @req: ID of request to send to the DSP module |
| 937 | * @dir: SET or GET |
| 938 | * @data: pointer to the data to send with the request, request specific |
| 939 | * @len: length of the data, in bytes |
| 940 | * @reply: point to the buffer to hold data returned for a reply |
| 941 | * @reply_len: length of the reply buffer returned from GET |
| 942 | * |
| 943 | * Returns zero or a negative error code. |
| 944 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 945 | static int dspio_scp(struct hda_codec *codec, |
| 946 | int mod_id, int req, int dir, void *data, unsigned int len, |
| 947 | void *reply, unsigned int *reply_len) |
| 948 | { |
| 949 | int status = 0; |
| 950 | struct scp_msg scp_send, scp_reply; |
| 951 | unsigned int ret_bytes, send_size, ret_size; |
| 952 | unsigned int send_get_flag, reply_resp_flag, reply_error_flag; |
| 953 | unsigned int reply_data_size; |
| 954 | |
| 955 | memset(&scp_send, 0, sizeof(scp_send)); |
| 956 | memset(&scp_reply, 0, sizeof(scp_reply)); |
| 957 | |
| 958 | if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) |
| 959 | return -EINVAL; |
| 960 | |
| 961 | if (dir == SCP_GET && reply == NULL) { |
| 962 | snd_printdd(KERN_ERR "dspio_scp get but has no buffer"); |
| 963 | return -EINVAL; |
| 964 | } |
| 965 | |
| 966 | if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { |
| 967 | snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms"); |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | |
| 971 | scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req, |
| 972 | 0, 0, 0, len/sizeof(unsigned int)); |
| 973 | if (data != NULL && len > 0) { |
| 974 | len = min((unsigned int)(sizeof(scp_send.data)), len); |
| 975 | memcpy(scp_send.data, data, len); |
| 976 | } |
| 977 | |
| 978 | ret_bytes = 0; |
| 979 | send_size = sizeof(unsigned int) + len; |
| 980 | status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, |
| 981 | send_size, (unsigned char *)&scp_reply, |
| 982 | sizeof(scp_reply), &ret_bytes); |
| 983 | |
| 984 | if (status < 0) { |
| 985 | snd_printdd(KERN_ERR "dspio_scp: send scp msg failed"); |
| 986 | return status; |
| 987 | } |
| 988 | |
| 989 | /* extract send and reply headers members */ |
| 990 | extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, |
| 991 | NULL, NULL, NULL, NULL, NULL); |
| 992 | extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, |
| 993 | &reply_resp_flag, &reply_error_flag, |
| 994 | &reply_data_size); |
| 995 | |
| 996 | if (!send_get_flag) |
| 997 | return 0; |
| 998 | |
| 999 | if (reply_resp_flag && !reply_error_flag) { |
| 1000 | ret_size = (ret_bytes - sizeof(scp_reply.hdr)) |
| 1001 | / sizeof(unsigned int); |
| 1002 | |
| 1003 | if (*reply_len < ret_size*sizeof(unsigned int)) { |
| 1004 | snd_printdd(KERN_ERR "reply too long for buf"); |
| 1005 | return -EINVAL; |
| 1006 | } else if (ret_size != reply_data_size) { |
| 1007 | snd_printdd(KERN_ERR "RetLen and HdrLen .NE."); |
| 1008 | return -EINVAL; |
| 1009 | } else { |
| 1010 | *reply_len = ret_size*sizeof(unsigned int); |
| 1011 | memcpy(reply, scp_reply.data, *reply_len); |
| 1012 | } |
| 1013 | } else { |
| 1014 | snd_printdd(KERN_ERR "reply ill-formed or errflag set"); |
| 1015 | return -EIO; |
| 1016 | } |
| 1017 | |
| 1018 | return status; |
| 1019 | } |
| 1020 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1021 | /* |
| 1022 | * Allocate a DSP DMA channel via an SCP message |
| 1023 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1024 | static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) |
| 1025 | { |
| 1026 | int status = 0; |
| 1027 | unsigned int size = sizeof(dma_chan); |
| 1028 | |
| 1029 | snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin"); |
| 1030 | status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, |
| 1031 | SCP_GET, NULL, 0, dma_chan, &size); |
| 1032 | |
| 1033 | if (status < 0) { |
| 1034 | snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed"); |
| 1035 | return status; |
| 1036 | } |
| 1037 | |
| 1038 | if ((*dma_chan + 1) == 0) { |
| 1039 | snd_printdd(KERN_INFO "no free dma channels to allocate"); |
| 1040 | return -EBUSY; |
| 1041 | } |
| 1042 | |
| 1043 | snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan); |
| 1044 | snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete"); |
| 1045 | |
| 1046 | return status; |
| 1047 | } |
| 1048 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1049 | /* |
| 1050 | * Free a DSP DMA via an SCP message |
| 1051 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1052 | static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) |
| 1053 | { |
| 1054 | int status = 0; |
| 1055 | unsigned int dummy = 0; |
| 1056 | |
| 1057 | snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin"); |
| 1058 | snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan); |
| 1059 | |
| 1060 | status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, |
| 1061 | SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy); |
| 1062 | |
| 1063 | if (status < 0) { |
| 1064 | snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed"); |
| 1065 | return status; |
| 1066 | } |
| 1067 | |
| 1068 | snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete"); |
| 1069 | |
| 1070 | return status; |
| 1071 | } |
| 1072 | |
| 1073 | /* |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1074 | * (Re)start the DSP |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1075 | */ |
| 1076 | static int dsp_set_run_state(struct hda_codec *codec) |
| 1077 | { |
| 1078 | unsigned int dbg_ctrl_reg; |
| 1079 | unsigned int halt_state; |
| 1080 | int err; |
| 1081 | |
| 1082 | err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); |
| 1083 | if (err < 0) |
| 1084 | return err; |
| 1085 | |
| 1086 | halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> |
| 1087 | DSP_DBGCNTL_STATE_LOBIT; |
| 1088 | |
| 1089 | if (halt_state != 0) { |
| 1090 | dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & |
| 1091 | DSP_DBGCNTL_SS_MASK); |
| 1092 | err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, |
| 1093 | dbg_ctrl_reg); |
| 1094 | if (err < 0) |
| 1095 | return err; |
| 1096 | |
| 1097 | dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & |
| 1098 | DSP_DBGCNTL_EXEC_MASK; |
| 1099 | err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, |
| 1100 | dbg_ctrl_reg); |
| 1101 | if (err < 0) |
| 1102 | return err; |
| 1103 | } |
| 1104 | |
| 1105 | return 0; |
| 1106 | } |
| 1107 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1108 | /* |
| 1109 | * Reset the DSP |
| 1110 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1111 | static int dsp_reset(struct hda_codec *codec) |
| 1112 | { |
| 1113 | unsigned int res; |
| 1114 | int retry = 20; |
| 1115 | |
| 1116 | snd_printdd("dsp_reset\n"); |
| 1117 | do { |
| 1118 | res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); |
| 1119 | retry--; |
| 1120 | } while (res == -EIO && retry); |
| 1121 | |
| 1122 | if (!retry) { |
| 1123 | snd_printdd("dsp_reset timeout\n"); |
| 1124 | return -EIO; |
| 1125 | } |
| 1126 | |
| 1127 | return 0; |
| 1128 | } |
| 1129 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1130 | /* |
| 1131 | * Convert chip address to DSP address |
| 1132 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1133 | static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, |
| 1134 | bool *code, bool *yram) |
| 1135 | { |
| 1136 | *code = *yram = false; |
| 1137 | |
| 1138 | if (UC_RANGE(chip_addx, 1)) { |
| 1139 | *code = true; |
| 1140 | return UC_OFF(chip_addx); |
| 1141 | } else if (X_RANGE_ALL(chip_addx, 1)) { |
| 1142 | return X_OFF(chip_addx); |
| 1143 | } else if (Y_RANGE_ALL(chip_addx, 1)) { |
| 1144 | *yram = true; |
| 1145 | return Y_OFF(chip_addx); |
| 1146 | } |
| 1147 | |
| 1148 | return (unsigned int)INVALID_CHIP_ADDRESS; |
| 1149 | } |
| 1150 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1151 | /* |
| 1152 | * Check if the DSP DMA is active |
| 1153 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1154 | static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) |
| 1155 | { |
| 1156 | unsigned int dma_chnlstart_reg; |
| 1157 | |
| 1158 | chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); |
| 1159 | |
| 1160 | return ((dma_chnlstart_reg & (1 << |
| 1161 | (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); |
| 1162 | } |
| 1163 | |
| 1164 | static int dsp_dma_setup_common(struct hda_codec *codec, |
| 1165 | unsigned int chip_addx, |
| 1166 | unsigned int dma_chan, |
| 1167 | unsigned int port_map_mask, |
| 1168 | bool ovly) |
| 1169 | { |
| 1170 | int status = 0; |
| 1171 | unsigned int chnl_prop; |
| 1172 | unsigned int dsp_addx; |
| 1173 | unsigned int active; |
| 1174 | bool code, yram; |
| 1175 | |
| 1176 | snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------"); |
| 1177 | |
| 1178 | if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { |
| 1179 | snd_printdd(KERN_ERR "dma chan num invalid"); |
| 1180 | return -EINVAL; |
| 1181 | } |
| 1182 | |
| 1183 | if (dsp_is_dma_active(codec, dma_chan)) { |
| 1184 | snd_printdd(KERN_ERR "dma already active"); |
| 1185 | return -EBUSY; |
| 1186 | } |
| 1187 | |
| 1188 | dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); |
| 1189 | |
| 1190 | if (dsp_addx == INVALID_CHIP_ADDRESS) { |
| 1191 | snd_printdd(KERN_ERR "invalid chip addr"); |
| 1192 | return -ENXIO; |
| 1193 | } |
| 1194 | |
| 1195 | chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; |
| 1196 | active = 0; |
| 1197 | |
| 1198 | snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm"); |
| 1199 | |
| 1200 | if (ovly) { |
| 1201 | status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, |
| 1202 | &chnl_prop); |
| 1203 | |
| 1204 | if (status < 0) { |
| 1205 | snd_printdd(KERN_ERR "read CHNLPROP Reg fail"); |
| 1206 | return status; |
| 1207 | } |
| 1208 | snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP"); |
| 1209 | } |
| 1210 | |
| 1211 | if (!code) |
| 1212 | chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); |
| 1213 | else |
| 1214 | chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); |
| 1215 | |
| 1216 | chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); |
| 1217 | |
| 1218 | status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); |
| 1219 | if (status < 0) { |
| 1220 | snd_printdd(KERN_ERR "write CHNLPROP Reg fail"); |
| 1221 | return status; |
| 1222 | } |
| 1223 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP"); |
| 1224 | |
| 1225 | if (ovly) { |
| 1226 | status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, |
| 1227 | &active); |
| 1228 | |
| 1229 | if (status < 0) { |
| 1230 | snd_printdd(KERN_ERR "read ACTIVE Reg fail"); |
| 1231 | return status; |
| 1232 | } |
| 1233 | snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE"); |
| 1234 | } |
| 1235 | |
| 1236 | active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & |
| 1237 | DSPDMAC_ACTIVE_AAR_MASK; |
| 1238 | |
| 1239 | status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); |
| 1240 | if (status < 0) { |
| 1241 | snd_printdd(KERN_ERR "write ACTIVE Reg fail"); |
| 1242 | return status; |
| 1243 | } |
| 1244 | |
| 1245 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE"); |
| 1246 | |
| 1247 | status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), |
| 1248 | port_map_mask); |
| 1249 | if (status < 0) { |
| 1250 | snd_printdd(KERN_ERR "write AUDCHSEL Reg fail"); |
| 1251 | return status; |
| 1252 | } |
| 1253 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL"); |
| 1254 | |
| 1255 | status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), |
| 1256 | DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); |
| 1257 | if (status < 0) { |
| 1258 | snd_printdd(KERN_ERR "write IRQCNT Reg fail"); |
| 1259 | return status; |
| 1260 | } |
| 1261 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT"); |
| 1262 | |
| 1263 | snd_printdd( |
| 1264 | "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " |
| 1265 | "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", |
| 1266 | chip_addx, dsp_addx, dma_chan, |
| 1267 | port_map_mask, chnl_prop, active); |
| 1268 | |
| 1269 | snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------"); |
| 1270 | |
| 1271 | return 0; |
| 1272 | } |
| 1273 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1274 | /* |
| 1275 | * Setup the DSP DMA per-transfer-specific registers |
| 1276 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1277 | static int dsp_dma_setup(struct hda_codec *codec, |
| 1278 | unsigned int chip_addx, |
| 1279 | unsigned int count, |
| 1280 | unsigned int dma_chan) |
| 1281 | { |
| 1282 | int status = 0; |
| 1283 | bool code, yram; |
| 1284 | unsigned int dsp_addx; |
| 1285 | unsigned int addr_field; |
| 1286 | unsigned int incr_field; |
| 1287 | unsigned int base_cnt; |
| 1288 | unsigned int cur_cnt; |
| 1289 | unsigned int dma_cfg = 0; |
| 1290 | unsigned int adr_ofs = 0; |
| 1291 | unsigned int xfr_cnt = 0; |
| 1292 | const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - |
| 1293 | DSPDMAC_XFRCNT_BCNT_LOBIT + 1); |
| 1294 | |
| 1295 | snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------"); |
| 1296 | |
| 1297 | if (count > max_dma_count) { |
| 1298 | snd_printdd(KERN_ERR "count too big"); |
| 1299 | return -EINVAL; |
| 1300 | } |
| 1301 | |
| 1302 | dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); |
| 1303 | if (dsp_addx == INVALID_CHIP_ADDRESS) { |
| 1304 | snd_printdd(KERN_ERR "invalid chip addr"); |
| 1305 | return -ENXIO; |
| 1306 | } |
| 1307 | |
| 1308 | snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm"); |
| 1309 | |
| 1310 | addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; |
| 1311 | incr_field = 0; |
| 1312 | |
| 1313 | if (!code) { |
| 1314 | addr_field <<= 1; |
| 1315 | if (yram) |
| 1316 | addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); |
| 1317 | |
| 1318 | incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); |
| 1319 | } |
| 1320 | |
| 1321 | dma_cfg = addr_field + incr_field; |
| 1322 | status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), |
| 1323 | dma_cfg); |
| 1324 | if (status < 0) { |
| 1325 | snd_printdd(KERN_ERR "write DMACFG Reg fail"); |
| 1326 | return status; |
| 1327 | } |
| 1328 | snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG"); |
| 1329 | |
| 1330 | adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + |
| 1331 | (code ? 0 : 1)); |
| 1332 | |
| 1333 | status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), |
| 1334 | adr_ofs); |
| 1335 | if (status < 0) { |
| 1336 | snd_printdd(KERN_ERR "write DSPADROFS Reg fail"); |
| 1337 | return status; |
| 1338 | } |
| 1339 | snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS"); |
| 1340 | |
| 1341 | base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; |
| 1342 | |
| 1343 | cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; |
| 1344 | |
| 1345 | xfr_cnt = base_cnt | cur_cnt; |
| 1346 | |
| 1347 | status = chipio_write(codec, |
| 1348 | DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); |
| 1349 | if (status < 0) { |
| 1350 | snd_printdd(KERN_ERR "write XFRCNT Reg fail"); |
| 1351 | return status; |
| 1352 | } |
| 1353 | snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT"); |
| 1354 | |
| 1355 | snd_printdd( |
| 1356 | "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " |
| 1357 | "ADROFS=0x%x, XFRCNT=0x%x\n", |
| 1358 | chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); |
| 1359 | |
| 1360 | snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------"); |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1365 | /* |
| 1366 | * Start the DSP DMA |
| 1367 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1368 | static int dsp_dma_start(struct hda_codec *codec, |
| 1369 | unsigned int dma_chan, bool ovly) |
| 1370 | { |
| 1371 | unsigned int reg = 0; |
| 1372 | int status = 0; |
| 1373 | |
| 1374 | snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------"); |
| 1375 | |
| 1376 | if (ovly) { |
| 1377 | status = chipio_read(codec, |
| 1378 | DSPDMAC_CHNLSTART_INST_OFFSET, ®); |
| 1379 | |
| 1380 | if (status < 0) { |
| 1381 | snd_printdd(KERN_ERR "read CHNLSTART reg fail"); |
| 1382 | return status; |
| 1383 | } |
| 1384 | snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART"); |
| 1385 | |
| 1386 | reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | |
| 1387 | DSPDMAC_CHNLSTART_DIS_MASK); |
| 1388 | } |
| 1389 | |
| 1390 | status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, |
| 1391 | reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); |
| 1392 | if (status < 0) { |
| 1393 | snd_printdd(KERN_ERR "write CHNLSTART reg fail"); |
| 1394 | return status; |
| 1395 | } |
| 1396 | snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------"); |
| 1397 | |
| 1398 | return status; |
| 1399 | } |
| 1400 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1401 | /* |
| 1402 | * Stop the DSP DMA |
| 1403 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1404 | static int dsp_dma_stop(struct hda_codec *codec, |
| 1405 | unsigned int dma_chan, bool ovly) |
| 1406 | { |
| 1407 | unsigned int reg = 0; |
| 1408 | int status = 0; |
| 1409 | |
| 1410 | snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------"); |
| 1411 | |
| 1412 | if (ovly) { |
| 1413 | status = chipio_read(codec, |
| 1414 | DSPDMAC_CHNLSTART_INST_OFFSET, ®); |
| 1415 | |
| 1416 | if (status < 0) { |
| 1417 | snd_printdd(KERN_ERR "read CHNLSTART reg fail"); |
| 1418 | return status; |
| 1419 | } |
| 1420 | snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART"); |
| 1421 | reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | |
| 1422 | DSPDMAC_CHNLSTART_DIS_MASK); |
| 1423 | } |
| 1424 | |
| 1425 | status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, |
| 1426 | reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); |
| 1427 | if (status < 0) { |
| 1428 | snd_printdd(KERN_ERR "write CHNLSTART reg fail"); |
| 1429 | return status; |
| 1430 | } |
| 1431 | snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------"); |
| 1432 | |
| 1433 | return status; |
| 1434 | } |
| 1435 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1436 | /** |
| 1437 | * Allocate router ports |
| 1438 | * |
| 1439 | * @codec: the HDA codec |
| 1440 | * @num_chans: number of channels in the stream |
| 1441 | * @ports_per_channel: number of ports per channel |
| 1442 | * @start_device: start device |
| 1443 | * @port_map: pointer to the port list to hold the allocated ports |
| 1444 | * |
| 1445 | * Returns zero or a negative error code. |
| 1446 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1447 | static int dsp_allocate_router_ports(struct hda_codec *codec, |
| 1448 | unsigned int num_chans, |
| 1449 | unsigned int ports_per_channel, |
| 1450 | unsigned int start_device, |
| 1451 | unsigned int *port_map) |
| 1452 | { |
| 1453 | int status = 0; |
| 1454 | int res; |
| 1455 | u8 val; |
| 1456 | |
| 1457 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1458 | if (status < 0) |
| 1459 | return status; |
| 1460 | |
| 1461 | val = start_device << 6; |
| 1462 | val |= (ports_per_channel - 1) << 4; |
| 1463 | val |= num_chans - 1; |
| 1464 | |
| 1465 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1466 | VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, |
| 1467 | val); |
| 1468 | |
| 1469 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1470 | VENDOR_CHIPIO_PORT_ALLOC_SET, |
| 1471 | MEM_CONNID_DSP); |
| 1472 | |
| 1473 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1474 | if (status < 0) |
| 1475 | return status; |
| 1476 | |
| 1477 | res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, |
| 1478 | VENDOR_CHIPIO_PORT_ALLOC_GET, 0); |
| 1479 | |
| 1480 | *port_map = res; |
| 1481 | |
| 1482 | return (res < 0) ? res : 0; |
| 1483 | } |
| 1484 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1485 | /* |
| 1486 | * Free router ports |
| 1487 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1488 | static int dsp_free_router_ports(struct hda_codec *codec) |
| 1489 | { |
| 1490 | int status = 0; |
| 1491 | |
| 1492 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1493 | if (status < 0) |
| 1494 | return status; |
| 1495 | |
| 1496 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1497 | VENDOR_CHIPIO_PORT_FREE_SET, |
| 1498 | MEM_CONNID_DSP); |
| 1499 | |
| 1500 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1501 | |
| 1502 | return status; |
| 1503 | } |
| 1504 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1505 | /* |
| 1506 | * Allocate DSP ports for the download stream |
| 1507 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1508 | static int dsp_allocate_ports(struct hda_codec *codec, |
| 1509 | unsigned int num_chans, |
| 1510 | unsigned int rate_multi, unsigned int *port_map) |
| 1511 | { |
| 1512 | int status; |
| 1513 | |
| 1514 | snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin"); |
| 1515 | |
| 1516 | if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { |
| 1517 | snd_printdd(KERN_ERR "bad rate multiple"); |
| 1518 | return -EINVAL; |
| 1519 | } |
| 1520 | |
| 1521 | status = dsp_allocate_router_ports(codec, num_chans, |
| 1522 | rate_multi, 0, port_map); |
| 1523 | |
| 1524 | snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete"); |
| 1525 | |
| 1526 | return status; |
| 1527 | } |
| 1528 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1529 | static int dsp_allocate_ports_format(struct hda_codec *codec, |
| 1530 | const unsigned short fmt, |
| 1531 | unsigned int *port_map) |
| 1532 | { |
| 1533 | int status; |
| 1534 | unsigned int num_chans; |
| 1535 | |
| 1536 | unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; |
| 1537 | unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; |
| 1538 | unsigned int rate_multi = sample_rate_mul / sample_rate_div; |
| 1539 | |
| 1540 | if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { |
| 1541 | snd_printdd(KERN_ERR "bad rate multiple"); |
| 1542 | return -EINVAL; |
| 1543 | } |
| 1544 | |
| 1545 | num_chans = get_hdafmt_chs(fmt) + 1; |
| 1546 | |
| 1547 | status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); |
| 1548 | |
| 1549 | return status; |
| 1550 | } |
| 1551 | |
| 1552 | /* |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1553 | * free DSP ports |
| 1554 | */ |
| 1555 | static int dsp_free_ports(struct hda_codec *codec) |
| 1556 | { |
| 1557 | int status; |
| 1558 | |
| 1559 | snd_printdd(KERN_INFO " dsp_free_ports() -- begin"); |
| 1560 | |
| 1561 | status = dsp_free_router_ports(codec); |
| 1562 | if (status < 0) { |
| 1563 | snd_printdd(KERN_ERR "free router ports fail"); |
| 1564 | return status; |
| 1565 | } |
| 1566 | snd_printdd(KERN_INFO " dsp_free_ports() -- complete"); |
| 1567 | |
| 1568 | return status; |
| 1569 | } |
| 1570 | |
| 1571 | /* |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1572 | * HDA DMA engine stuffs for DSP code download |
| 1573 | */ |
| 1574 | struct dma_engine { |
| 1575 | struct hda_codec *codec; |
| 1576 | unsigned short m_converter_format; |
| 1577 | struct snd_dma_buffer *dmab; |
| 1578 | unsigned int buf_size; |
| 1579 | }; |
| 1580 | |
| 1581 | |
| 1582 | enum dma_state { |
| 1583 | DMA_STATE_STOP = 0, |
| 1584 | DMA_STATE_RUN = 1 |
| 1585 | }; |
| 1586 | |
| 1587 | static int dma_convert_to_hda_format( |
| 1588 | struct hda_stream_format *stream_format, |
| 1589 | unsigned short *hda_format) |
| 1590 | { |
| 1591 | unsigned int format_val; |
| 1592 | |
| 1593 | format_val = snd_hda_calc_stream_format( |
| 1594 | stream_format->sample_rate, |
| 1595 | stream_format->number_channels, |
| 1596 | SNDRV_PCM_FORMAT_S32_LE, |
| 1597 | stream_format->container_size, 0); |
| 1598 | |
| 1599 | if (hda_format) |
| 1600 | *hda_format = (unsigned short)format_val; |
| 1601 | |
| 1602 | return 0; |
| 1603 | } |
| 1604 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1605 | /* |
| 1606 | * Reset DMA for DSP download |
| 1607 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1608 | static int dma_reset(struct dma_engine *dma) |
| 1609 | { |
| 1610 | struct hda_codec *codec = dma->codec; |
| 1611 | struct ca0132_spec *spec = codec->spec; |
| 1612 | int status; |
| 1613 | |
| 1614 | if (dma->dmab) |
| 1615 | snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); |
| 1616 | |
| 1617 | status = snd_hda_codec_load_dsp_prepare(codec, |
| 1618 | dma->m_converter_format, |
| 1619 | dma->buf_size, |
| 1620 | dma->dmab); |
| 1621 | if (status < 0) |
| 1622 | return status; |
| 1623 | spec->dsp_stream_id = status; |
| 1624 | return 0; |
| 1625 | } |
| 1626 | |
| 1627 | static int dma_set_state(struct dma_engine *dma, enum dma_state state) |
| 1628 | { |
| 1629 | bool cmd; |
| 1630 | |
| 1631 | snd_printdd("dma_set_state state=%d\n", state); |
| 1632 | |
| 1633 | switch (state) { |
| 1634 | case DMA_STATE_STOP: |
| 1635 | cmd = false; |
| 1636 | break; |
| 1637 | case DMA_STATE_RUN: |
| 1638 | cmd = true; |
| 1639 | break; |
| 1640 | default: |
| 1641 | return 0; |
| 1642 | } |
| 1643 | |
| 1644 | snd_hda_codec_load_dsp_trigger(dma->codec, cmd); |
| 1645 | return 0; |
| 1646 | } |
| 1647 | |
| 1648 | static unsigned int dma_get_buffer_size(struct dma_engine *dma) |
| 1649 | { |
| 1650 | return dma->dmab->bytes; |
| 1651 | } |
| 1652 | |
| 1653 | static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) |
| 1654 | { |
| 1655 | return dma->dmab->area; |
| 1656 | } |
| 1657 | |
| 1658 | static int dma_xfer(struct dma_engine *dma, |
| 1659 | const unsigned int *data, |
| 1660 | unsigned int count) |
| 1661 | { |
| 1662 | memcpy(dma->dmab->area, data, count); |
| 1663 | return 0; |
| 1664 | } |
| 1665 | |
| 1666 | static void dma_get_converter_format( |
| 1667 | struct dma_engine *dma, |
| 1668 | unsigned short *format) |
| 1669 | { |
| 1670 | if (format) |
| 1671 | *format = dma->m_converter_format; |
| 1672 | } |
| 1673 | |
| 1674 | static unsigned int dma_get_stream_id(struct dma_engine *dma) |
| 1675 | { |
| 1676 | struct ca0132_spec *spec = dma->codec->spec; |
| 1677 | |
| 1678 | return spec->dsp_stream_id; |
| 1679 | } |
| 1680 | |
| 1681 | struct dsp_image_seg { |
| 1682 | u32 magic; |
| 1683 | u32 chip_addr; |
| 1684 | u32 count; |
| 1685 | u32 data[0]; |
| 1686 | }; |
| 1687 | |
| 1688 | static const u32 g_magic_value = 0x4c46584d; |
| 1689 | static const u32 g_chip_addr_magic_value = 0xFFFFFF01; |
| 1690 | |
| 1691 | static bool is_valid(const struct dsp_image_seg *p) |
| 1692 | { |
| 1693 | return p->magic == g_magic_value; |
| 1694 | } |
| 1695 | |
| 1696 | static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) |
| 1697 | { |
| 1698 | return g_chip_addr_magic_value == p->chip_addr; |
| 1699 | } |
| 1700 | |
| 1701 | static bool is_last(const struct dsp_image_seg *p) |
| 1702 | { |
| 1703 | return p->count == 0; |
| 1704 | } |
| 1705 | |
| 1706 | static size_t dsp_sizeof(const struct dsp_image_seg *p) |
| 1707 | { |
| 1708 | return sizeof(*p) + p->count*sizeof(u32); |
| 1709 | } |
| 1710 | |
| 1711 | static const struct dsp_image_seg *get_next_seg_ptr( |
| 1712 | const struct dsp_image_seg *p) |
| 1713 | { |
| 1714 | return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); |
| 1715 | } |
| 1716 | |
| 1717 | /* |
| 1718 | * CA0132 chip DSP transfer stuffs. For DSP download. |
| 1719 | */ |
| 1720 | #define INVALID_DMA_CHANNEL (~0UL) |
| 1721 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1722 | /* |
| 1723 | * Program a list of address/data pairs via the ChipIO widget. |
| 1724 | * The segment data is in the format of successive pairs of words. |
| 1725 | * These are repeated as indicated by the segment's count field. |
| 1726 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1727 | static int dspxfr_hci_write(struct hda_codec *codec, |
| 1728 | const struct dsp_image_seg *fls) |
| 1729 | { |
| 1730 | int status; |
| 1731 | const u32 *data; |
| 1732 | unsigned int count; |
| 1733 | |
| 1734 | if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { |
| 1735 | snd_printdd(KERN_ERR "hci_write invalid params"); |
| 1736 | return -EINVAL; |
| 1737 | } |
| 1738 | |
| 1739 | count = fls->count; |
| 1740 | data = (u32 *)(fls->data); |
| 1741 | while (count >= 2) { |
| 1742 | status = chipio_write(codec, data[0], data[1]); |
| 1743 | if (status < 0) { |
| 1744 | snd_printdd(KERN_ERR "hci_write chipio failed"); |
| 1745 | return status; |
| 1746 | } |
| 1747 | count -= 2; |
| 1748 | data += 2; |
| 1749 | } |
| 1750 | return 0; |
| 1751 | } |
| 1752 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1753 | /** |
| 1754 | * Write a block of data into DSP code or data RAM using pre-allocated |
| 1755 | * DMA engine. |
| 1756 | * |
| 1757 | * @codec: the HDA codec |
| 1758 | * @fls: pointer to a fast load image |
| 1759 | * @reloc: Relocation address for loading single-segment overlays, or 0 for |
| 1760 | * no relocation |
| 1761 | * @dma_engine: pointer to DMA engine to be used for DSP download |
| 1762 | * @dma_chan: The number of DMA channels used for DSP download |
| 1763 | * @port_map_mask: port mapping |
| 1764 | * @ovly: TRUE if overlay format is required |
| 1765 | * |
| 1766 | * Returns zero or a negative error code. |
| 1767 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1768 | static int dspxfr_one_seg(struct hda_codec *codec, |
| 1769 | const struct dsp_image_seg *fls, |
| 1770 | unsigned int reloc, |
| 1771 | struct dma_engine *dma_engine, |
| 1772 | unsigned int dma_chan, |
| 1773 | unsigned int port_map_mask, |
| 1774 | bool ovly) |
| 1775 | { |
| 1776 | int status; |
| 1777 | bool comm_dma_setup_done = false; |
| 1778 | const unsigned int *data; |
| 1779 | unsigned int chip_addx; |
| 1780 | unsigned int words_to_write; |
| 1781 | unsigned int buffer_size_words; |
| 1782 | unsigned char *buffer_addx; |
| 1783 | unsigned short hda_format; |
| 1784 | unsigned int sample_rate_div; |
| 1785 | unsigned int sample_rate_mul; |
| 1786 | unsigned int num_chans; |
| 1787 | unsigned int hda_frame_size_words; |
| 1788 | unsigned int remainder_words; |
| 1789 | const u32 *data_remainder; |
| 1790 | u32 chip_addx_remainder; |
| 1791 | unsigned int run_size_words; |
| 1792 | const struct dsp_image_seg *hci_write = NULL; |
| 1793 | int retry; |
| 1794 | |
| 1795 | if (fls == NULL) |
| 1796 | return -EINVAL; |
| 1797 | if (is_hci_prog_list_seg(fls)) { |
| 1798 | hci_write = fls; |
| 1799 | fls = get_next_seg_ptr(fls); |
| 1800 | } |
| 1801 | |
| 1802 | if (hci_write && (!fls || is_last(fls))) { |
| 1803 | snd_printdd("hci_write\n"); |
| 1804 | return dspxfr_hci_write(codec, hci_write); |
| 1805 | } |
| 1806 | |
| 1807 | if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { |
| 1808 | snd_printdd("Invalid Params\n"); |
| 1809 | return -EINVAL; |
| 1810 | } |
| 1811 | |
| 1812 | data = fls->data; |
| 1813 | chip_addx = fls->chip_addr, |
| 1814 | words_to_write = fls->count; |
| 1815 | |
| 1816 | if (!words_to_write) |
| 1817 | return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; |
| 1818 | if (reloc) |
| 1819 | chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); |
| 1820 | |
| 1821 | if (!UC_RANGE(chip_addx, words_to_write) && |
| 1822 | !X_RANGE_ALL(chip_addx, words_to_write) && |
| 1823 | !Y_RANGE_ALL(chip_addx, words_to_write)) { |
| 1824 | snd_printdd("Invalid chip_addx Params\n"); |
| 1825 | return -EINVAL; |
| 1826 | } |
| 1827 | |
| 1828 | buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / |
| 1829 | sizeof(u32); |
| 1830 | |
| 1831 | buffer_addx = dma_get_buffer_addr(dma_engine); |
| 1832 | |
| 1833 | if (buffer_addx == NULL) { |
| 1834 | snd_printdd(KERN_ERR "dma_engine buffer NULL\n"); |
| 1835 | return -EINVAL; |
| 1836 | } |
| 1837 | |
| 1838 | dma_get_converter_format(dma_engine, &hda_format); |
| 1839 | sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; |
| 1840 | sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; |
| 1841 | num_chans = get_hdafmt_chs(hda_format) + 1; |
| 1842 | |
| 1843 | hda_frame_size_words = ((sample_rate_div == 0) ? 0 : |
| 1844 | (num_chans * sample_rate_mul / sample_rate_div)); |
| 1845 | |
| 1846 | buffer_size_words = min(buffer_size_words, |
| 1847 | (unsigned int)(UC_RANGE(chip_addx, 1) ? |
| 1848 | 65536 : 32768)); |
| 1849 | buffer_size_words -= buffer_size_words % hda_frame_size_words; |
| 1850 | snd_printdd( |
| 1851 | "chpadr=0x%08x frmsz=%u nchan=%u " |
| 1852 | "rate_mul=%u div=%u bufsz=%u\n", |
| 1853 | chip_addx, hda_frame_size_words, num_chans, |
| 1854 | sample_rate_mul, sample_rate_div, buffer_size_words); |
| 1855 | |
| 1856 | if ((buffer_addx == NULL) || (hda_frame_size_words == 0) || |
| 1857 | (buffer_size_words < hda_frame_size_words)) { |
| 1858 | snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n"); |
| 1859 | return -EINVAL; |
| 1860 | } |
| 1861 | |
| 1862 | remainder_words = words_to_write % hda_frame_size_words; |
| 1863 | data_remainder = data; |
| 1864 | chip_addx_remainder = chip_addx; |
| 1865 | |
| 1866 | data += remainder_words; |
| 1867 | chip_addx += remainder_words*sizeof(u32); |
| 1868 | words_to_write -= remainder_words; |
| 1869 | |
| 1870 | while (words_to_write != 0) { |
| 1871 | run_size_words = min(buffer_size_words, words_to_write); |
| 1872 | snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", |
| 1873 | words_to_write, run_size_words, remainder_words); |
| 1874 | dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); |
| 1875 | if (!comm_dma_setup_done) { |
| 1876 | status = dsp_dma_stop(codec, dma_chan, ovly); |
| 1877 | if (status < 0) |
| 1878 | return -EIO; |
| 1879 | status = dsp_dma_setup_common(codec, chip_addx, |
| 1880 | dma_chan, port_map_mask, ovly); |
| 1881 | if (status < 0) |
| 1882 | return status; |
| 1883 | comm_dma_setup_done = true; |
| 1884 | } |
| 1885 | |
| 1886 | status = dsp_dma_setup(codec, chip_addx, |
| 1887 | run_size_words, dma_chan); |
| 1888 | if (status < 0) |
| 1889 | return status; |
| 1890 | status = dsp_dma_start(codec, dma_chan, ovly); |
| 1891 | if (status < 0) |
| 1892 | return status; |
| 1893 | if (!dsp_is_dma_active(codec, dma_chan)) { |
| 1894 | snd_printdd(KERN_ERR "dspxfr:DMA did not start"); |
| 1895 | return -EIO; |
| 1896 | } |
| 1897 | status = dma_set_state(dma_engine, DMA_STATE_RUN); |
| 1898 | if (status < 0) |
| 1899 | return status; |
| 1900 | if (remainder_words != 0) { |
| 1901 | status = chipio_write_multiple(codec, |
| 1902 | chip_addx_remainder, |
| 1903 | data_remainder, |
| 1904 | remainder_words); |
| 1905 | remainder_words = 0; |
| 1906 | } |
| 1907 | if (hci_write) { |
| 1908 | status = dspxfr_hci_write(codec, hci_write); |
| 1909 | hci_write = NULL; |
| 1910 | } |
| 1911 | retry = 5000; |
| 1912 | while (dsp_is_dma_active(codec, dma_chan)) { |
| 1913 | if (--retry <= 0) |
| 1914 | break; |
| 1915 | } |
| 1916 | snd_printdd(KERN_INFO "+++++ DMA complete"); |
| 1917 | dma_set_state(dma_engine, DMA_STATE_STOP); |
| 1918 | dma_reset(dma_engine); |
| 1919 | |
| 1920 | if (status < 0) |
| 1921 | return status; |
| 1922 | |
| 1923 | data += run_size_words; |
| 1924 | chip_addx += run_size_words*sizeof(u32); |
| 1925 | words_to_write -= run_size_words; |
| 1926 | } |
| 1927 | |
| 1928 | if (remainder_words != 0) { |
| 1929 | status = chipio_write_multiple(codec, chip_addx_remainder, |
| 1930 | data_remainder, remainder_words); |
| 1931 | } |
| 1932 | |
| 1933 | return status; |
| 1934 | } |
| 1935 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1936 | /** |
| 1937 | * Write the entire DSP image of a DSP code/data overlay to DSP memories |
| 1938 | * |
| 1939 | * @codec: the HDA codec |
| 1940 | * @fls_data: pointer to a fast load image |
| 1941 | * @reloc: Relocation address for loading single-segment overlays, or 0 for |
| 1942 | * no relocation |
| 1943 | * @format: format of the stream used for DSP download |
| 1944 | * @ovly: TRUE if overlay format is required |
| 1945 | * |
| 1946 | * Returns zero or a negative error code. |
| 1947 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1948 | static int dspxfr_image(struct hda_codec *codec, |
| 1949 | const struct dsp_image_seg *fls_data, |
| 1950 | unsigned int reloc, struct hda_stream_format *format, |
| 1951 | bool ovly) |
| 1952 | { |
| 1953 | struct ca0132_spec *spec = codec->spec; |
| 1954 | int status; |
| 1955 | unsigned short hda_format = 0; |
| 1956 | unsigned int response; |
| 1957 | unsigned char stream_id = 0; |
| 1958 | struct dma_engine *dma_engine; |
| 1959 | unsigned int dma_chan; |
| 1960 | unsigned int port_map_mask; |
| 1961 | |
| 1962 | if (fls_data == NULL) |
| 1963 | return -EINVAL; |
| 1964 | |
| 1965 | dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); |
| 1966 | if (!dma_engine) { |
| 1967 | status = -ENOMEM; |
| 1968 | goto exit; |
| 1969 | } |
| 1970 | memset((void *)dma_engine, 0, sizeof(*dma_engine)); |
| 1971 | |
| 1972 | dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); |
| 1973 | if (!dma_engine->dmab) { |
| 1974 | status = -ENOMEM; |
| 1975 | goto exit; |
| 1976 | } |
| 1977 | |
| 1978 | dma_engine->codec = codec; |
| 1979 | dma_convert_to_hda_format(format, &hda_format); |
| 1980 | dma_engine->m_converter_format = hda_format; |
| 1981 | dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : |
| 1982 | DSP_DMA_WRITE_BUFLEN_INIT) * 2; |
| 1983 | |
| 1984 | dma_chan = 0; |
| 1985 | |
| 1986 | status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, |
| 1987 | hda_format, &response); |
| 1988 | |
| 1989 | if (status < 0) { |
| 1990 | snd_printdd(KERN_ERR "set converter format fail"); |
| 1991 | goto exit; |
| 1992 | } |
| 1993 | |
| 1994 | status = snd_hda_codec_load_dsp_prepare(codec, |
| 1995 | dma_engine->m_converter_format, |
| 1996 | dma_engine->buf_size, |
| 1997 | dma_engine->dmab); |
| 1998 | if (status < 0) |
| 1999 | goto exit; |
| 2000 | spec->dsp_stream_id = status; |
| 2001 | |
| 2002 | if (ovly) { |
| 2003 | status = dspio_alloc_dma_chan(codec, &dma_chan); |
| 2004 | if (status < 0) { |
| 2005 | snd_printdd(KERN_ERR "alloc dmachan fail"); |
| 2006 | dma_chan = (unsigned int)INVALID_DMA_CHANNEL; |
| 2007 | goto exit; |
| 2008 | } |
| 2009 | } |
| 2010 | |
| 2011 | port_map_mask = 0; |
| 2012 | status = dsp_allocate_ports_format(codec, hda_format, |
| 2013 | &port_map_mask); |
| 2014 | if (status < 0) { |
| 2015 | snd_printdd(KERN_ERR "alloc ports fail"); |
| 2016 | goto exit; |
| 2017 | } |
| 2018 | |
| 2019 | stream_id = dma_get_stream_id(dma_engine); |
| 2020 | status = codec_set_converter_stream_channel(codec, |
| 2021 | WIDGET_CHIP_CTRL, stream_id, 0, &response); |
| 2022 | if (status < 0) { |
| 2023 | snd_printdd(KERN_ERR "set stream chan fail"); |
| 2024 | goto exit; |
| 2025 | } |
| 2026 | |
| 2027 | while ((fls_data != NULL) && !is_last(fls_data)) { |
| 2028 | if (!is_valid(fls_data)) { |
| 2029 | snd_printdd(KERN_ERR "FLS check fail"); |
| 2030 | status = -EINVAL; |
| 2031 | goto exit; |
| 2032 | } |
| 2033 | status = dspxfr_one_seg(codec, fls_data, reloc, |
| 2034 | dma_engine, dma_chan, |
| 2035 | port_map_mask, ovly); |
| 2036 | if (status < 0) |
| 2037 | break; |
| 2038 | |
| 2039 | if (is_hci_prog_list_seg(fls_data)) |
| 2040 | fls_data = get_next_seg_ptr(fls_data); |
| 2041 | |
| 2042 | if ((fls_data != NULL) && !is_last(fls_data)) |
| 2043 | fls_data = get_next_seg_ptr(fls_data); |
| 2044 | } |
| 2045 | |
| 2046 | if (port_map_mask != 0) |
| 2047 | status = dsp_free_ports(codec); |
| 2048 | |
| 2049 | if (status < 0) |
| 2050 | goto exit; |
| 2051 | |
| 2052 | status = codec_set_converter_stream_channel(codec, |
| 2053 | WIDGET_CHIP_CTRL, 0, 0, &response); |
| 2054 | |
| 2055 | exit: |
| 2056 | if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) |
| 2057 | dspio_free_dma_chan(codec, dma_chan); |
| 2058 | |
| 2059 | if (dma_engine->dmab) |
| 2060 | snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); |
| 2061 | kfree(dma_engine->dmab); |
| 2062 | kfree(dma_engine); |
| 2063 | |
| 2064 | return status; |
| 2065 | } |
| 2066 | |
| 2067 | /* |
| 2068 | * CA0132 DSP download stuffs. |
| 2069 | */ |
| 2070 | static void dspload_post_setup(struct hda_codec *codec) |
| 2071 | { |
| 2072 | snd_printdd(KERN_INFO "---- dspload_post_setup ------"); |
| 2073 | |
| 2074 | /*set DSP speaker to 2.0 configuration*/ |
| 2075 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); |
| 2076 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); |
| 2077 | |
| 2078 | /*update write pointer*/ |
| 2079 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); |
| 2080 | } |
| 2081 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2082 | /** |
| 2083 | * Download DSP from a DSP Image Fast Load structure. This structure is a |
| 2084 | * linear, non-constant sized element array of structures, each of which |
| 2085 | * contain the count of the data to be loaded, the data itself, and the |
| 2086 | * corresponding starting chip address of the starting data location. |
| 2087 | * |
| 2088 | * @codec: the HDA codec |
| 2089 | * @fls: pointer to a fast load image |
| 2090 | * @ovly: TRUE if overlay format is required |
| 2091 | * @reloc: Relocation address for loading single-segment overlays, or 0 for |
| 2092 | * no relocation |
| 2093 | * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE |
| 2094 | * @router_chans: number of audio router channels to be allocated (0 means use |
| 2095 | * internal defaults; max is 32) |
| 2096 | * |
| 2097 | * Returns zero or a negative error code. |
| 2098 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2099 | static int dspload_image(struct hda_codec *codec, |
| 2100 | const struct dsp_image_seg *fls, |
| 2101 | bool ovly, |
| 2102 | unsigned int reloc, |
| 2103 | bool autostart, |
| 2104 | int router_chans) |
| 2105 | { |
| 2106 | int status = 0; |
| 2107 | struct hda_stream_format stream_format; |
| 2108 | |
| 2109 | snd_printdd(KERN_INFO "---- dspload_image begin ------"); |
| 2110 | if (router_chans == 0) { |
| 2111 | if (!ovly) |
| 2112 | router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; |
| 2113 | else |
| 2114 | router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; |
| 2115 | } |
| 2116 | |
| 2117 | stream_format.sample_rate = 48000; |
| 2118 | stream_format.number_channels = (unsigned short)router_chans; |
| 2119 | |
| 2120 | while (stream_format.number_channels > 16) { |
| 2121 | stream_format.sample_rate *= 2; |
| 2122 | stream_format.number_channels /= 2; |
| 2123 | } |
| 2124 | |
| 2125 | stream_format.container_size = 32; |
| 2126 | stream_format.valid_bits_per_sample = 32; |
| 2127 | |
| 2128 | do { |
| 2129 | snd_printdd(KERN_INFO "Ready to program DMA"); |
| 2130 | if (!ovly) |
| 2131 | status = dsp_reset(codec); |
| 2132 | |
| 2133 | if (status < 0) |
| 2134 | break; |
| 2135 | |
| 2136 | snd_printdd(KERN_INFO "dsp_reset() complete"); |
| 2137 | status = dspxfr_image(codec, fls, reloc, &stream_format, ovly); |
| 2138 | |
| 2139 | if (status < 0) |
| 2140 | break; |
| 2141 | |
| 2142 | snd_printdd(KERN_INFO "dspxfr_image() complete"); |
| 2143 | if (autostart && !ovly) { |
| 2144 | dspload_post_setup(codec); |
| 2145 | status = dsp_set_run_state(codec); |
| 2146 | } |
| 2147 | |
| 2148 | snd_printdd(KERN_INFO "LOAD FINISHED"); |
| 2149 | } while (0); |
| 2150 | |
| 2151 | return status; |
| 2152 | } |
| 2153 | |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 2154 | static const struct firmware *fw_efx; |
| 2155 | |
| 2156 | static int request_firmware_cached(const struct firmware **firmware_p, |
| 2157 | const char *name, struct device *device) |
| 2158 | { |
| 2159 | if (*firmware_p) |
| 2160 | return 0; /* already loaded */ |
| 2161 | return request_firmware(firmware_p, name, device); |
| 2162 | } |
| 2163 | |
| 2164 | static void release_cached_firmware(void) |
| 2165 | { |
| 2166 | if (fw_efx) { |
| 2167 | release_firmware(fw_efx); |
| 2168 | fw_efx = NULL; |
| 2169 | } |
| 2170 | } |
| 2171 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2172 | static bool dspload_is_loaded(struct hda_codec *codec) |
| 2173 | { |
| 2174 | unsigned int data = 0; |
| 2175 | int status = 0; |
| 2176 | |
| 2177 | status = chipio_read(codec, 0x40004, &data); |
| 2178 | if ((status < 0) || (data != 1)) |
| 2179 | return false; |
| 2180 | |
| 2181 | return true; |
| 2182 | } |
| 2183 | |
| 2184 | static bool dspload_wait_loaded(struct hda_codec *codec) |
| 2185 | { |
| 2186 | int retry = 100; |
| 2187 | |
| 2188 | do { |
| 2189 | msleep(20); |
| 2190 | if (dspload_is_loaded(codec)) { |
| 2191 | pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n"); |
| 2192 | return true; |
| 2193 | } |
| 2194 | } while (--retry); |
| 2195 | |
| 2196 | pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n"); |
| 2197 | return false; |
| 2198 | } |
| 2199 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2200 | /* |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2201 | * PCM callbacks |
| 2202 | */ |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2203 | static int ca0132_playback_pcm_open(struct hda_pcm_stream *hinfo, |
| 2204 | struct hda_codec *codec, |
| 2205 | struct snd_pcm_substream *substream) |
| 2206 | { |
| 2207 | struct ca0132_spec *spec = codec->spec; |
| 2208 | return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream, |
| 2209 | hinfo); |
| 2210 | } |
| 2211 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2212 | static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, |
| 2213 | struct hda_codec *codec, |
| 2214 | unsigned int stream_tag, |
| 2215 | unsigned int format, |
| 2216 | struct snd_pcm_substream *substream) |
| 2217 | { |
| 2218 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2219 | return snd_hda_multi_out_analog_prepare(codec, &spec->multiout, |
| 2220 | stream_tag, format, substream); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2221 | } |
| 2222 | |
| 2223 | static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
| 2224 | struct hda_codec *codec, |
| 2225 | struct snd_pcm_substream *substream) |
| 2226 | { |
| 2227 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2228 | return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | /* |
| 2232 | * Digital out |
| 2233 | */ |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2234 | static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, |
| 2235 | struct hda_codec *codec, |
| 2236 | struct snd_pcm_substream *substream) |
| 2237 | { |
| 2238 | struct ca0132_spec *spec = codec->spec; |
| 2239 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
| 2240 | } |
| 2241 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2242 | static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, |
| 2243 | struct hda_codec *codec, |
| 2244 | unsigned int stream_tag, |
| 2245 | unsigned int format, |
| 2246 | struct snd_pcm_substream *substream) |
| 2247 | { |
| 2248 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2249 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, |
| 2250 | stream_tag, format, substream); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2251 | } |
| 2252 | |
| 2253 | static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
| 2254 | struct hda_codec *codec, |
| 2255 | struct snd_pcm_substream *substream) |
| 2256 | { |
| 2257 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2258 | return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2259 | } |
| 2260 | |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2261 | static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, |
| 2262 | struct hda_codec *codec, |
| 2263 | struct snd_pcm_substream *substream) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2264 | { |
| 2265 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2266 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2267 | } |
| 2268 | |
| 2269 | /* |
| 2270 | */ |
| 2271 | static struct hda_pcm_stream ca0132_pcm_analog_playback = { |
| 2272 | .substreams = 1, |
| 2273 | .channels_min = 2, |
| 2274 | .channels_max = 2, |
| 2275 | .ops = { |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2276 | .open = ca0132_playback_pcm_open, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2277 | .prepare = ca0132_playback_pcm_prepare, |
| 2278 | .cleanup = ca0132_playback_pcm_cleanup |
| 2279 | }, |
| 2280 | }; |
| 2281 | |
| 2282 | static struct hda_pcm_stream ca0132_pcm_analog_capture = { |
| 2283 | .substreams = 1, |
| 2284 | .channels_min = 2, |
| 2285 | .channels_max = 2, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2286 | }; |
| 2287 | |
| 2288 | static struct hda_pcm_stream ca0132_pcm_digital_playback = { |
| 2289 | .substreams = 1, |
| 2290 | .channels_min = 2, |
| 2291 | .channels_max = 2, |
| 2292 | .ops = { |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2293 | .open = ca0132_dig_playback_pcm_open, |
| 2294 | .close = ca0132_dig_playback_pcm_close, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2295 | .prepare = ca0132_dig_playback_pcm_prepare, |
| 2296 | .cleanup = ca0132_dig_playback_pcm_cleanup |
| 2297 | }, |
| 2298 | }; |
| 2299 | |
| 2300 | static struct hda_pcm_stream ca0132_pcm_digital_capture = { |
| 2301 | .substreams = 1, |
| 2302 | .channels_min = 2, |
| 2303 | .channels_max = 2, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2304 | }; |
| 2305 | |
| 2306 | static int ca0132_build_pcms(struct hda_codec *codec) |
| 2307 | { |
| 2308 | struct ca0132_spec *spec = codec->spec; |
| 2309 | struct hda_pcm *info = spec->pcm_rec; |
| 2310 | |
| 2311 | codec->pcm_info = info; |
| 2312 | codec->num_pcms = 0; |
| 2313 | |
| 2314 | info->name = "CA0132 Analog"; |
| 2315 | info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; |
| 2316 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; |
| 2317 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = |
| 2318 | spec->multiout.max_channels; |
| 2319 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; |
| 2320 | info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs; |
| 2321 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; |
| 2322 | codec->num_pcms++; |
| 2323 | |
| 2324 | if (!spec->dig_out && !spec->dig_in) |
| 2325 | return 0; |
| 2326 | |
| 2327 | info++; |
| 2328 | info->name = "CA0132 Digital"; |
| 2329 | info->pcm_type = HDA_PCM_TYPE_SPDIF; |
| 2330 | if (spec->dig_out) { |
| 2331 | info->stream[SNDRV_PCM_STREAM_PLAYBACK] = |
| 2332 | ca0132_pcm_digital_playback; |
| 2333 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; |
| 2334 | } |
| 2335 | if (spec->dig_in) { |
| 2336 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = |
| 2337 | ca0132_pcm_digital_capture; |
| 2338 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; |
| 2339 | } |
| 2340 | codec->num_pcms++; |
| 2341 | |
| 2342 | return 0; |
| 2343 | } |
| 2344 | |
| 2345 | #define REG_CODEC_MUTE 0x18b014 |
| 2346 | #define REG_CODEC_HP_VOL_L 0x18b070 |
| 2347 | #define REG_CODEC_HP_VOL_R 0x18b074 |
| 2348 | |
| 2349 | static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol, |
| 2350 | struct snd_ctl_elem_value *ucontrol) |
| 2351 | { |
| 2352 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2353 | struct ca0132_spec *spec = codec->spec; |
| 2354 | long *valp = ucontrol->value.integer.value; |
| 2355 | |
| 2356 | *valp = spec->curr_hp_switch; |
| 2357 | return 0; |
| 2358 | } |
| 2359 | |
| 2360 | static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol, |
| 2361 | struct snd_ctl_elem_value *ucontrol) |
| 2362 | { |
| 2363 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2364 | struct ca0132_spec *spec = codec->spec; |
| 2365 | long *valp = ucontrol->value.integer.value; |
| 2366 | unsigned int data; |
| 2367 | int err; |
| 2368 | |
| 2369 | /* any change? */ |
| 2370 | if (spec->curr_hp_switch == *valp) |
| 2371 | return 0; |
| 2372 | |
| 2373 | snd_hda_power_up(codec); |
| 2374 | |
| 2375 | err = chipio_read(codec, REG_CODEC_MUTE, &data); |
| 2376 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2377 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2378 | |
| 2379 | /* *valp 0 is mute, 1 is unmute */ |
| 2380 | data = (data & 0x7f) | (*valp ? 0 : 0x80); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2381 | err = chipio_write(codec, REG_CODEC_MUTE, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2382 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2383 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2384 | |
| 2385 | spec->curr_hp_switch = *valp; |
| 2386 | |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2387 | exit: |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2388 | snd_hda_power_down(codec); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2389 | return err < 0 ? err : 1; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2390 | } |
| 2391 | |
| 2392 | static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol, |
| 2393 | struct snd_ctl_elem_value *ucontrol) |
| 2394 | { |
| 2395 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2396 | struct ca0132_spec *spec = codec->spec; |
| 2397 | long *valp = ucontrol->value.integer.value; |
| 2398 | |
| 2399 | *valp = spec->curr_speaker_switch; |
| 2400 | return 0; |
| 2401 | } |
| 2402 | |
| 2403 | static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol, |
| 2404 | struct snd_ctl_elem_value *ucontrol) |
| 2405 | { |
| 2406 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2407 | struct ca0132_spec *spec = codec->spec; |
| 2408 | long *valp = ucontrol->value.integer.value; |
| 2409 | unsigned int data; |
| 2410 | int err; |
| 2411 | |
| 2412 | /* any change? */ |
| 2413 | if (spec->curr_speaker_switch == *valp) |
| 2414 | return 0; |
| 2415 | |
| 2416 | snd_hda_power_up(codec); |
| 2417 | |
| 2418 | err = chipio_read(codec, REG_CODEC_MUTE, &data); |
| 2419 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2420 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2421 | |
| 2422 | /* *valp 0 is mute, 1 is unmute */ |
| 2423 | data = (data & 0xef) | (*valp ? 0 : 0x10); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2424 | err = chipio_write(codec, REG_CODEC_MUTE, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2425 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2426 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2427 | |
| 2428 | spec->curr_speaker_switch = *valp; |
| 2429 | |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2430 | exit: |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2431 | snd_hda_power_down(codec); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2432 | return err < 0 ? err : 1; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2433 | } |
| 2434 | |
| 2435 | static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol, |
| 2436 | struct snd_ctl_elem_value *ucontrol) |
| 2437 | { |
| 2438 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2439 | struct ca0132_spec *spec = codec->spec; |
| 2440 | long *valp = ucontrol->value.integer.value; |
| 2441 | |
| 2442 | *valp++ = spec->curr_hp_volume[0]; |
| 2443 | *valp = spec->curr_hp_volume[1]; |
| 2444 | return 0; |
| 2445 | } |
| 2446 | |
| 2447 | static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol, |
| 2448 | struct snd_ctl_elem_value *ucontrol) |
| 2449 | { |
| 2450 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 2451 | struct ca0132_spec *spec = codec->spec; |
| 2452 | long *valp = ucontrol->value.integer.value; |
| 2453 | long left_vol, right_vol; |
| 2454 | unsigned int data; |
| 2455 | int val; |
| 2456 | int err; |
| 2457 | |
| 2458 | left_vol = *valp++; |
| 2459 | right_vol = *valp; |
| 2460 | |
| 2461 | /* any change? */ |
| 2462 | if ((spec->curr_hp_volume[0] == left_vol) && |
| 2463 | (spec->curr_hp_volume[1] == right_vol)) |
| 2464 | return 0; |
| 2465 | |
| 2466 | snd_hda_power_up(codec); |
| 2467 | |
| 2468 | err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data); |
| 2469 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2470 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2471 | |
| 2472 | val = 31 - left_vol; |
| 2473 | data = (data & 0xe0) | val; |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2474 | err = chipio_write(codec, REG_CODEC_HP_VOL_L, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2475 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2476 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2477 | |
| 2478 | val = 31 - right_vol; |
| 2479 | data = (data & 0xe0) | val; |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2480 | err = chipio_write(codec, REG_CODEC_HP_VOL_R, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2481 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2482 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2483 | |
| 2484 | spec->curr_hp_volume[0] = left_vol; |
| 2485 | spec->curr_hp_volume[1] = right_vol; |
| 2486 | |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2487 | exit: |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2488 | snd_hda_power_down(codec); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 2489 | return err < 0 ? err : 1; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2490 | } |
| 2491 | |
| 2492 | static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid) |
| 2493 | { |
| 2494 | struct snd_kcontrol_new knew = |
| 2495 | HDA_CODEC_MUTE_MONO("Headphone Playback Switch", |
| 2496 | nid, 1, 0, HDA_OUTPUT); |
| 2497 | knew.get = ca0132_hp_switch_get; |
| 2498 | knew.put = ca0132_hp_switch_put; |
| 2499 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 2500 | } |
| 2501 | |
| 2502 | static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid) |
| 2503 | { |
| 2504 | struct snd_kcontrol_new knew = |
| 2505 | HDA_CODEC_VOLUME_MONO("Headphone Playback Volume", |
| 2506 | nid, 3, 0, HDA_OUTPUT); |
| 2507 | knew.get = ca0132_hp_volume_get; |
| 2508 | knew.put = ca0132_hp_volume_put; |
| 2509 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 2510 | } |
| 2511 | |
| 2512 | static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid) |
| 2513 | { |
| 2514 | struct snd_kcontrol_new knew = |
| 2515 | HDA_CODEC_MUTE_MONO("Speaker Playback Switch", |
| 2516 | nid, 1, 0, HDA_OUTPUT); |
| 2517 | knew.get = ca0132_speaker_switch_get; |
| 2518 | knew.put = ca0132_speaker_switch_put; |
| 2519 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 2520 | } |
| 2521 | |
| 2522 | static void ca0132_fix_hp_caps(struct hda_codec *codec) |
| 2523 | { |
| 2524 | struct ca0132_spec *spec = codec->spec; |
| 2525 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 2526 | unsigned int caps; |
| 2527 | |
| 2528 | /* set mute-capable, 1db step, 32 steps, ofs 6 */ |
| 2529 | caps = 0x80031f06; |
| 2530 | snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps); |
| 2531 | } |
| 2532 | |
| 2533 | static int ca0132_build_controls(struct hda_codec *codec) |
| 2534 | { |
| 2535 | struct ca0132_spec *spec = codec->spec; |
| 2536 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 2537 | int i, err; |
| 2538 | |
| 2539 | if (spec->multiout.num_dacs) { |
| 2540 | err = add_speaker_switch(codec, spec->out_pins[0]); |
| 2541 | if (err < 0) |
| 2542 | return err; |
| 2543 | } |
| 2544 | |
| 2545 | if (cfg->hp_outs) { |
| 2546 | ca0132_fix_hp_caps(codec); |
| 2547 | err = add_hp_switch(codec, cfg->hp_pins[0]); |
| 2548 | if (err < 0) |
| 2549 | return err; |
| 2550 | err = add_hp_volume(codec, cfg->hp_pins[0]); |
| 2551 | if (err < 0) |
| 2552 | return err; |
| 2553 | } |
| 2554 | |
| 2555 | for (i = 0; i < spec->num_inputs; i++) { |
| 2556 | const char *label = spec->input_labels[i]; |
| 2557 | |
| 2558 | err = add_in_switch(codec, spec->adcs[i], label); |
| 2559 | if (err < 0) |
| 2560 | return err; |
| 2561 | err = add_in_volume(codec, spec->adcs[i], label); |
| 2562 | if (err < 0) |
| 2563 | return err; |
| 2564 | if (cfg->inputs[i].type == AUTO_PIN_MIC) { |
| 2565 | /* add Mic-Boost */ |
| 2566 | err = add_in_mono_volume(codec, spec->input_pins[i], |
| 2567 | "Mic Boost", 1); |
| 2568 | if (err < 0) |
| 2569 | return err; |
| 2570 | } |
| 2571 | } |
| 2572 | |
| 2573 | if (spec->dig_out) { |
Takashi Iwai | efb9f46 | 2011-06-21 07:44:51 +0200 | [diff] [blame] | 2574 | err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, |
| 2575 | spec->dig_out); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2576 | if (err < 0) |
| 2577 | return err; |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 2578 | err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2579 | if (err < 0) |
| 2580 | return err; |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 2581 | /* spec->multiout.share_spdif = 1; */ |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2582 | } |
| 2583 | |
| 2584 | if (spec->dig_in) { |
| 2585 | err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); |
| 2586 | if (err < 0) |
| 2587 | return err; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2588 | } |
| 2589 | return 0; |
| 2590 | } |
| 2591 | |
| 2592 | |
| 2593 | static void ca0132_set_ct_ext(struct hda_codec *codec, int enable) |
| 2594 | { |
| 2595 | /* Set Creative extension */ |
| 2596 | snd_printdd("SET CREATIVE EXTENSION\n"); |
| 2597 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 2598 | VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, |
| 2599 | enable); |
| 2600 | msleep(20); |
| 2601 | } |
| 2602 | |
| 2603 | |
| 2604 | static void ca0132_config(struct hda_codec *codec) |
| 2605 | { |
| 2606 | struct ca0132_spec *spec = codec->spec; |
| 2607 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 2608 | |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2609 | codec->pcm_format_first = 1; |
| 2610 | codec->no_sticky_stream = 1; |
| 2611 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2612 | /* line-outs */ |
| 2613 | cfg->line_outs = 1; |
| 2614 | cfg->line_out_pins[0] = 0x0b; /* front */ |
| 2615 | cfg->line_out_type = AUTO_PIN_LINE_OUT; |
| 2616 | |
| 2617 | spec->dacs[0] = 0x02; |
| 2618 | spec->out_pins[0] = 0x0b; |
| 2619 | spec->multiout.dac_nids = spec->dacs; |
| 2620 | spec->multiout.num_dacs = 1; |
| 2621 | spec->multiout.max_channels = 2; |
| 2622 | |
| 2623 | /* headphone */ |
| 2624 | cfg->hp_outs = 1; |
| 2625 | cfg->hp_pins[0] = 0x0f; |
| 2626 | |
| 2627 | spec->hp_dac = 0; |
| 2628 | spec->multiout.hp_nid = 0; |
| 2629 | |
| 2630 | /* inputs */ |
| 2631 | cfg->num_inputs = 2; /* Mic-in and line-in */ |
| 2632 | cfg->inputs[0].pin = 0x12; |
| 2633 | cfg->inputs[0].type = AUTO_PIN_MIC; |
| 2634 | cfg->inputs[1].pin = 0x11; |
| 2635 | cfg->inputs[1].type = AUTO_PIN_LINE_IN; |
| 2636 | |
| 2637 | /* Mic-in */ |
| 2638 | spec->input_pins[0] = 0x12; |
Takashi Iwai | 55cf87f | 2012-08-08 17:15:55 +0200 | [diff] [blame] | 2639 | spec->input_labels[0] = "Mic"; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2640 | spec->adcs[0] = 0x07; |
| 2641 | |
| 2642 | /* Line-In */ |
| 2643 | spec->input_pins[1] = 0x11; |
Takashi Iwai | 55cf87f | 2012-08-08 17:15:55 +0200 | [diff] [blame] | 2644 | spec->input_labels[1] = "Line"; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2645 | spec->adcs[1] = 0x08; |
| 2646 | spec->num_inputs = 2; |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 2647 | |
| 2648 | /* SPDIF I/O */ |
| 2649 | spec->dig_out = 0x05; |
| 2650 | spec->multiout.dig_out_nid = spec->dig_out; |
| 2651 | cfg->dig_out_pins[0] = 0x0c; |
| 2652 | cfg->dig_outs = 1; |
| 2653 | cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; |
| 2654 | spec->dig_in = 0x09; |
| 2655 | cfg->dig_in_pin = 0x0e; |
| 2656 | cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2657 | } |
| 2658 | |
| 2659 | static void ca0132_init_chip(struct hda_codec *codec) |
| 2660 | { |
| 2661 | struct ca0132_spec *spec = codec->spec; |
| 2662 | |
| 2663 | mutex_init(&spec->chipio_mutex); |
| 2664 | } |
| 2665 | |
| 2666 | static void ca0132_exit_chip(struct hda_codec *codec) |
| 2667 | { |
| 2668 | /* put any chip cleanup stuffs here. */ |
| 2669 | } |
| 2670 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2671 | static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) |
| 2672 | { |
| 2673 | chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); |
| 2674 | chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); |
| 2675 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); |
| 2676 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); |
| 2677 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); |
| 2678 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); |
| 2679 | |
| 2680 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); |
| 2681 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); |
| 2682 | chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); |
| 2683 | } |
| 2684 | |
| 2685 | static bool ca0132_download_dsp_images(struct hda_codec *codec) |
| 2686 | { |
| 2687 | bool dsp_loaded = false; |
| 2688 | const struct dsp_image_seg *dsp_os_image; |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2689 | |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 2690 | if (request_firmware_cached(&fw_efx, EFX_FILE, |
| 2691 | codec->bus->card->dev) != 0) |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2692 | return false; |
| 2693 | |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 2694 | dsp_os_image = (struct dsp_image_seg *)(fw_efx->data); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2695 | dspload_image(codec, dsp_os_image, 0, 0, true, 0); |
| 2696 | dsp_loaded = dspload_wait_loaded(codec); |
| 2697 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2698 | return dsp_loaded; |
| 2699 | } |
| 2700 | |
| 2701 | static void ca0132_download_dsp(struct hda_codec *codec) |
| 2702 | { |
| 2703 | struct ca0132_spec *spec = codec->spec; |
| 2704 | |
| 2705 | spec->dsp_state = DSP_DOWNLOAD_INIT; |
| 2706 | |
| 2707 | if (spec->dsp_state == DSP_DOWNLOAD_INIT) { |
| 2708 | chipio_enable_clocks(codec); |
| 2709 | spec->dsp_state = DSP_DOWNLOADING; |
| 2710 | if (!ca0132_download_dsp_images(codec)) |
| 2711 | spec->dsp_state = DSP_DOWNLOAD_FAILED; |
| 2712 | else |
| 2713 | spec->dsp_state = DSP_DOWNLOADED; |
| 2714 | } |
| 2715 | |
| 2716 | if (spec->dsp_state == DSP_DOWNLOADED) |
| 2717 | ca0132_set_dsp_msr(codec, true); |
| 2718 | } |
| 2719 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2720 | static int ca0132_init(struct hda_codec *codec) |
| 2721 | { |
| 2722 | struct ca0132_spec *spec = codec->spec; |
| 2723 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 2724 | int i; |
| 2725 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2726 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
| 2727 | ca0132_download_dsp(codec); |
| 2728 | #endif |
| 2729 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2730 | for (i = 0; i < spec->multiout.num_dacs; i++) { |
| 2731 | init_output(codec, spec->out_pins[i], |
| 2732 | spec->multiout.dac_nids[i]); |
| 2733 | } |
| 2734 | init_output(codec, cfg->hp_pins[0], spec->hp_dac); |
| 2735 | init_output(codec, cfg->dig_out_pins[0], spec->dig_out); |
| 2736 | |
| 2737 | for (i = 0; i < spec->num_inputs; i++) |
| 2738 | init_input(codec, spec->input_pins[i], spec->adcs[i]); |
| 2739 | |
| 2740 | init_input(codec, cfg->dig_in_pin, spec->dig_in); |
| 2741 | |
| 2742 | ca0132_set_ct_ext(codec, 1); |
| 2743 | |
| 2744 | return 0; |
| 2745 | } |
| 2746 | |
| 2747 | |
| 2748 | static void ca0132_free(struct hda_codec *codec) |
| 2749 | { |
| 2750 | ca0132_set_ct_ext(codec, 0); |
| 2751 | ca0132_exit_chip(codec); |
| 2752 | kfree(codec->spec); |
| 2753 | } |
| 2754 | |
| 2755 | static struct hda_codec_ops ca0132_patch_ops = { |
| 2756 | .build_controls = ca0132_build_controls, |
| 2757 | .build_pcms = ca0132_build_pcms, |
| 2758 | .init = ca0132_init, |
| 2759 | .free = ca0132_free, |
| 2760 | }; |
| 2761 | |
| 2762 | |
| 2763 | |
| 2764 | static int patch_ca0132(struct hda_codec *codec) |
| 2765 | { |
| 2766 | struct ca0132_spec *spec; |
| 2767 | |
| 2768 | snd_printdd("patch_ca0132\n"); |
| 2769 | |
| 2770 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); |
| 2771 | if (!spec) |
| 2772 | return -ENOMEM; |
| 2773 | codec->spec = spec; |
| 2774 | |
| 2775 | ca0132_init_chip(codec); |
| 2776 | |
| 2777 | ca0132_config(codec); |
| 2778 | |
| 2779 | codec->patch_ops = ca0132_patch_ops; |
| 2780 | |
| 2781 | return 0; |
| 2782 | } |
| 2783 | |
| 2784 | /* |
| 2785 | * patch entries |
| 2786 | */ |
| 2787 | static struct hda_codec_preset snd_hda_preset_ca0132[] = { |
| 2788 | { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 }, |
| 2789 | {} /* terminator */ |
| 2790 | }; |
| 2791 | |
| 2792 | MODULE_ALIAS("snd-hda-codec-id:11020011"); |
| 2793 | |
| 2794 | MODULE_LICENSE("GPL"); |
| 2795 | MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec"); |
| 2796 | |
| 2797 | static struct hda_codec_preset_list ca0132_list = { |
| 2798 | .preset = snd_hda_preset_ca0132, |
| 2799 | .owner = THIS_MODULE, |
| 2800 | }; |
| 2801 | |
| 2802 | static int __init patch_ca0132_init(void) |
| 2803 | { |
| 2804 | return snd_hda_add_codec_preset(&ca0132_list); |
| 2805 | } |
| 2806 | |
| 2807 | static void __exit patch_ca0132_exit(void) |
| 2808 | { |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 2809 | release_cached_firmware(); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2810 | snd_hda_delete_codec_preset(&ca0132_list); |
| 2811 | } |
| 2812 | |
| 2813 | module_init(patch_ca0132_init) |
| 2814 | module_exit(patch_ca0132_exit) |