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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * include/asm-s390/system.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 *
8 * Derived from "include/asm-i386/system.h"
9 */
10
11#ifndef __ASM_SYSTEM_H
12#define __ASM_SYSTEM_H
13
14#include <linux/config.h>
15#include <linux/kernel.h>
16#include <asm/types.h>
17#include <asm/ptrace.h>
18#include <asm/setup.h>
Heiko Carstens77fa2242005-06-25 14:55:30 -070019#include <asm/processor.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21#ifdef __KERNEL__
22
23struct task_struct;
24
25extern struct task_struct *__switch_to(void *, void *);
26
27#ifdef __s390x__
28#define __FLAG_SHIFT 56
29#else /* ! __s390x__ */
30#define __FLAG_SHIFT 24
31#endif /* ! __s390x__ */
32
33static inline void save_fp_regs(s390_fp_regs *fpregs)
34{
35 asm volatile (
36 " std 0,8(%1)\n"
37 " std 2,24(%1)\n"
38 " std 4,40(%1)\n"
39 " std 6,56(%1)"
40 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
41 if (!MACHINE_HAS_IEEE)
42 return;
43 asm volatile(
44 " stfpc 0(%1)\n"
45 " std 1,16(%1)\n"
46 " std 3,32(%1)\n"
47 " std 5,48(%1)\n"
48 " std 7,64(%1)\n"
49 " std 8,72(%1)\n"
50 " std 9,80(%1)\n"
51 " std 10,88(%1)\n"
52 " std 11,96(%1)\n"
53 " std 12,104(%1)\n"
54 " std 13,112(%1)\n"
55 " std 14,120(%1)\n"
56 " std 15,128(%1)\n"
57 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
58}
59
60static inline void restore_fp_regs(s390_fp_regs *fpregs)
61{
62 asm volatile (
63 " ld 0,8(%0)\n"
64 " ld 2,24(%0)\n"
65 " ld 4,40(%0)\n"
66 " ld 6,56(%0)"
67 : : "a" (fpregs), "m" (*fpregs) );
68 if (!MACHINE_HAS_IEEE)
69 return;
70 asm volatile(
71 " lfpc 0(%0)\n"
72 " ld 1,16(%0)\n"
73 " ld 3,32(%0)\n"
74 " ld 5,48(%0)\n"
75 " ld 7,64(%0)\n"
76 " ld 8,72(%0)\n"
77 " ld 9,80(%0)\n"
78 " ld 10,88(%0)\n"
79 " ld 11,96(%0)\n"
80 " ld 12,104(%0)\n"
81 " ld 13,112(%0)\n"
82 " ld 14,120(%0)\n"
83 " ld 15,128(%0)\n"
84 : : "a" (fpregs), "m" (*fpregs) );
85}
86
87static inline void save_access_regs(unsigned int *acrs)
88{
89 asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
90}
91
92static inline void restore_access_regs(unsigned int *acrs)
93{
94 asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
95}
96
97#define switch_to(prev,next,last) do { \
98 if (prev == next) \
99 break; \
100 save_fp_regs(&prev->thread.fp_regs); \
101 restore_fp_regs(&next->thread.fp_regs); \
102 save_access_regs(&prev->thread.acrs[0]); \
103 restore_access_regs(&next->thread.acrs[0]); \
104 prev = __switch_to(prev,next); \
105} while (0)
106
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107#ifdef CONFIG_VIRT_CPU_ACCOUNTING
108extern void account_user_vtime(struct task_struct *);
109extern void account_system_vtime(struct task_struct *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110#else
Nick Piggin4866cde2005-06-25 14:57:23 -0700111#define account_system_vtime(prev) do { } while (0)
112#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
114#define finish_arch_switch(rq, prev) do { \
115 set_fs(current->thread.mm_segment); \
Nick Piggin4866cde2005-06-25 14:57:23 -0700116 account_system_vtime(prev); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117} while (0)
118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119#define nop() __asm__ __volatile__ ("nop")
120
121#define xchg(ptr,x) \
122 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
123
124static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
125{
126 unsigned long addr, old;
127 int shift;
128
129 switch (size) {
130 case 1:
131 addr = (unsigned long) ptr;
132 shift = (3 ^ (addr & 3)) << 3;
133 addr ^= addr & 3;
134 asm volatile(
135 " l %0,0(%4)\n"
136 "0: lr 0,%0\n"
137 " nr 0,%3\n"
138 " or 0,%2\n"
139 " cs %0,0,0(%4)\n"
140 " jl 0b\n"
141 : "=&d" (old), "=m" (*(int *) addr)
142 : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
143 "m" (*(int *) addr) : "memory", "cc", "0" );
144 x = old >> shift;
145 break;
146 case 2:
147 addr = (unsigned long) ptr;
148 shift = (2 ^ (addr & 2)) << 3;
149 addr ^= addr & 2;
150 asm volatile(
151 " l %0,0(%4)\n"
152 "0: lr 0,%0\n"
153 " nr 0,%3\n"
154 " or 0,%2\n"
155 " cs %0,0,0(%4)\n"
156 " jl 0b\n"
157 : "=&d" (old), "=m" (*(int *) addr)
158 : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
159 "m" (*(int *) addr) : "memory", "cc", "0" );
160 x = old >> shift;
161 break;
162 case 4:
163 asm volatile (
164 " l %0,0(%3)\n"
165 "0: cs %0,%2,0(%3)\n"
166 " jl 0b\n"
167 : "=&d" (old), "=m" (*(int *) ptr)
168 : "d" (x), "a" (ptr), "m" (*(int *) ptr)
169 : "memory", "cc" );
170 x = old;
171 break;
172#ifdef __s390x__
173 case 8:
174 asm volatile (
175 " lg %0,0(%3)\n"
176 "0: csg %0,%2,0(%3)\n"
177 " jl 0b\n"
178 : "=&d" (old), "=m" (*(long *) ptr)
179 : "d" (x), "a" (ptr), "m" (*(long *) ptr)
180 : "memory", "cc" );
181 x = old;
182 break;
183#endif /* __s390x__ */
184 }
185 return x;
186}
187
188/*
189 * Atomic compare and exchange. Compare OLD with MEM, if identical,
190 * store NEW in MEM. Return the initial value in MEM. Success is
191 * indicated by comparing RETURN with OLD.
192 */
193
194#define __HAVE_ARCH_CMPXCHG 1
195
196#define cmpxchg(ptr,o,n)\
197 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
198 (unsigned long)(n),sizeof(*(ptr))))
199
200static inline unsigned long
201__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
202{
203 unsigned long addr, prev, tmp;
204 int shift;
205
206 switch (size) {
207 case 1:
208 addr = (unsigned long) ptr;
209 shift = (3 ^ (addr & 3)) << 3;
210 addr ^= addr & 3;
211 asm volatile(
212 " l %0,0(%4)\n"
213 "0: nr %0,%5\n"
214 " lr %1,%0\n"
215 " or %0,%2\n"
216 " or %1,%3\n"
217 " cs %0,%1,0(%4)\n"
218 " jnl 1f\n"
219 " xr %1,%0\n"
220 " nr %1,%5\n"
221 " jnz 0b\n"
222 "1:"
223 : "=&d" (prev), "=&d" (tmp)
224 : "d" (old << shift), "d" (new << shift), "a" (ptr),
225 "d" (~(255 << shift))
226 : "memory", "cc" );
227 return prev >> shift;
228 case 2:
229 addr = (unsigned long) ptr;
230 shift = (2 ^ (addr & 2)) << 3;
231 addr ^= addr & 2;
232 asm volatile(
233 " l %0,0(%4)\n"
234 "0: nr %0,%5\n"
235 " lr %1,%0\n"
236 " or %0,%2\n"
237 " or %1,%3\n"
238 " cs %0,%1,0(%4)\n"
239 " jnl 1f\n"
240 " xr %1,%0\n"
241 " nr %1,%5\n"
242 " jnz 0b\n"
243 "1:"
244 : "=&d" (prev), "=&d" (tmp)
245 : "d" (old << shift), "d" (new << shift), "a" (ptr),
246 "d" (~(65535 << shift))
247 : "memory", "cc" );
248 return prev >> shift;
249 case 4:
250 asm volatile (
251 " cs %0,%2,0(%3)\n"
252 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
253 : "memory", "cc" );
254 return prev;
255#ifdef __s390x__
256 case 8:
257 asm volatile (
258 " csg %0,%2,0(%3)\n"
259 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
260 : "memory", "cc" );
261 return prev;
262#endif /* __s390x__ */
263 }
264 return old;
265}
266
267/*
268 * Force strict CPU ordering.
269 * And yes, this is required on UP too when we're talking
270 * to devices.
271 *
272 * This is very similar to the ppc eieio/sync instruction in that is
273 * does a checkpoint syncronisation & makes sure that
274 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
275 */
276
277#define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
278# define SYNC_OTHER_CORES(x) eieio()
279#define mb() eieio()
280#define rmb() eieio()
281#define wmb() eieio()
282#define read_barrier_depends() do { } while(0)
283#define smp_mb() mb()
284#define smp_rmb() rmb()
285#define smp_wmb() wmb()
286#define smp_read_barrier_depends() read_barrier_depends()
287#define smp_mb__before_clear_bit() smp_mb()
288#define smp_mb__after_clear_bit() smp_mb()
289
290
291#define set_mb(var, value) do { var = value; mb(); } while (0)
292#define set_wmb(var, value) do { var = value; wmb(); } while (0)
293
294/* interrupt control.. */
295#define local_irq_enable() ({ \
296 unsigned long __dummy; \
297 __asm__ __volatile__ ( \
298 "stosm 0(%1),0x03" \
299 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
300 })
301
302#define local_irq_disable() ({ \
303 unsigned long __flags; \
304 __asm__ __volatile__ ( \
305 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
306 __flags; \
307 })
308
309#define local_save_flags(x) \
310 __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
311
312#define local_irq_restore(x) \
313 __asm__ __volatile__("ssm 0(%0)" : : "a" (&x), "m" (x) : "memory")
314
315#define irqs_disabled() \
316({ \
317 unsigned long flags; \
318 local_save_flags(flags); \
319 !((flags >> __FLAG_SHIFT) & 3); \
320})
321
322#ifdef __s390x__
323
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324#define __ctl_load(array, low, high) ({ \
325 typedef struct { char _[sizeof(array)]; } addrtype; \
326 __asm__ __volatile__ ( \
327 " bras 1,0f\n" \
328 " lctlg 0,0,0(%0)\n" \
329 "0: ex %1,0(1)" \
330 : : "a" (&array), "a" (((low)<<4)+(high)), \
331 "m" (*(addrtype *)(array)) : "1" ); \
332 })
333
334#define __ctl_store(array, low, high) ({ \
335 typedef struct { char _[sizeof(array)]; } addrtype; \
336 __asm__ __volatile__ ( \
337 " bras 1,0f\n" \
338 " stctg 0,0,0(%1)\n" \
339 "0: ex %2,0(1)" \
340 : "=m" (*(addrtype *)(array)) \
341 : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
342 })
343
344#define __ctl_set_bit(cr, bit) ({ \
345 __u8 __dummy[24]; \
346 __asm__ __volatile__ ( \
347 " bras 1,0f\n" /* skip indirect insns */ \
348 " stctg 0,0,0(%1)\n" \
349 " lctlg 0,0,0(%1)\n" \
350 "0: ex %2,0(1)\n" /* execute stctl */ \
351 " lg 0,0(%1)\n" \
352 " ogr 0,%3\n" /* set the bit */ \
353 " stg 0,0(%1)\n" \
354 "1: ex %2,6(1)" /* execute lctl */ \
355 : "=m" (__dummy) \
356 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
357 "a" (cr*17), "a" (1L<<(bit)) \
358 : "cc", "0", "1" ); \
359 })
360
361#define __ctl_clear_bit(cr, bit) ({ \
362 __u8 __dummy[16]; \
363 __asm__ __volatile__ ( \
364 " bras 1,0f\n" /* skip indirect insns */ \
365 " stctg 0,0,0(%1)\n" \
366 " lctlg 0,0,0(%1)\n" \
367 "0: ex %2,0(1)\n" /* execute stctl */ \
368 " lg 0,0(%1)\n" \
369 " ngr 0,%3\n" /* set the bit */ \
370 " stg 0,0(%1)\n" \
371 "1: ex %2,6(1)" /* execute lctl */ \
372 : "=m" (__dummy) \
373 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
374 "a" (cr*17), "a" (~(1L<<(bit))) \
375 : "cc", "0", "1" ); \
376 })
377
378#else /* __s390x__ */
379
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380#define __ctl_load(array, low, high) ({ \
381 typedef struct { char _[sizeof(array)]; } addrtype; \
382 __asm__ __volatile__ ( \
383 " bras 1,0f\n" \
384 " lctl 0,0,0(%0)\n" \
385 "0: ex %1,0(1)" \
386 : : "a" (&array), "a" (((low)<<4)+(high)), \
387 "m" (*(addrtype *)(array)) : "1" ); \
388 })
389
390#define __ctl_store(array, low, high) ({ \
391 typedef struct { char _[sizeof(array)]; } addrtype; \
392 __asm__ __volatile__ ( \
393 " bras 1,0f\n" \
394 " stctl 0,0,0(%1)\n" \
395 "0: ex %2,0(1)" \
396 : "=m" (*(addrtype *)(array)) \
397 : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
398 })
399
400#define __ctl_set_bit(cr, bit) ({ \
401 __u8 __dummy[16]; \
402 __asm__ __volatile__ ( \
403 " bras 1,0f\n" /* skip indirect insns */ \
404 " stctl 0,0,0(%1)\n" \
405 " lctl 0,0,0(%1)\n" \
406 "0: ex %2,0(1)\n" /* execute stctl */ \
407 " l 0,0(%1)\n" \
408 " or 0,%3\n" /* set the bit */ \
409 " st 0,0(%1)\n" \
410 "1: ex %2,4(1)" /* execute lctl */ \
411 : "=m" (__dummy) \
412 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
413 "a" (cr*17), "a" (1<<(bit)) \
414 : "cc", "0", "1" ); \
415 })
416
417#define __ctl_clear_bit(cr, bit) ({ \
418 __u8 __dummy[16]; \
419 __asm__ __volatile__ ( \
420 " bras 1,0f\n" /* skip indirect insns */ \
421 " stctl 0,0,0(%1)\n" \
422 " lctl 0,0,0(%1)\n" \
423 "0: ex %2,0(1)\n" /* execute stctl */ \
424 " l 0,0(%1)\n" \
425 " nr 0,%3\n" /* set the bit */ \
426 " st 0,0(%1)\n" \
427 "1: ex %2,4(1)" /* execute lctl */ \
428 : "=m" (__dummy) \
429 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
430 "a" (cr*17), "a" (~(1<<(bit))) \
431 : "cc", "0", "1" ); \
432 })
433#endif /* __s390x__ */
434
435/* For spinlocks etc */
436#define local_irq_save(x) ((x) = local_irq_disable())
437
Heiko Carstens77fa2242005-06-25 14:55:30 -0700438/*
439 * Use to set psw mask except for the first byte which
440 * won't be changed by this function.
441 */
442static inline void
443__set_psw_mask(unsigned long mask)
444{
445 local_save_flags(mask);
446 __load_psw_mask(mask);
447}
448
449#define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
450#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
451
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452#ifdef CONFIG_SMP
453
454extern void smp_ctl_set_bit(int cr, int bit);
455extern void smp_ctl_clear_bit(int cr, int bit);
456#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
457#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
458
459#else
460
461#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
462#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
463
464#endif /* CONFIG_SMP */
465
466extern void (*_machine_restart)(char *command);
467extern void (*_machine_halt)(void);
468extern void (*_machine_power_off)(void);
469
470#define arch_align_stack(x) (x)
471
472#endif /* __KERNEL__ */
473
474#endif
475