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Yusuke Godafdc50a92010-05-26 14:41:59 -07001/*
2 * include/linux/mmc/sh_mmcif.h
3 *
4 * platform data for eMMC driver
5 *
6 * Copyright (C) 2010 Renesas Solutions Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 */
13
14#ifndef __SH_MMCIF_H__
15#define __SH_MMCIF_H__
16
Magnus Damm487d9fc2010-05-18 14:42:51 +000017#include <linux/platform_device.h>
18#include <linux/io.h>
19
Yusuke Godafdc50a92010-05-26 14:41:59 -070020/*
21 * MMCIF : CE_CLK_CTRL [19:16]
22 * 1000 : Peripheral clock / 512
23 * 0111 : Peripheral clock / 256
24 * 0110 : Peripheral clock / 128
25 * 0101 : Peripheral clock / 64
26 * 0100 : Peripheral clock / 32
27 * 0011 : Peripheral clock / 16
28 * 0010 : Peripheral clock / 8
29 * 0001 : Peripheral clock / 4
30 * 0000 : Peripheral clock / 2
31 * 1111 : Peripheral clock (sup_pclk set '1')
32 */
33
34struct sh_mmcif_plat_data {
35 void (*set_pwr)(struct platform_device *pdev, int state);
36 void (*down_pwr)(struct platform_device *pdev);
37 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
38 unsigned long caps;
39 u32 ocr;
40};
41
Magnus Damm487d9fc2010-05-18 14:42:51 +000042#define MMCIF_CE_CMD_SET 0x00000000
43#define MMCIF_CE_ARG 0x00000008
44#define MMCIF_CE_ARG_CMD12 0x0000000C
45#define MMCIF_CE_CMD_CTRL 0x00000010
46#define MMCIF_CE_BLOCK_SET 0x00000014
47#define MMCIF_CE_CLK_CTRL 0x00000018
48#define MMCIF_CE_BUF_ACC 0x0000001C
49#define MMCIF_CE_RESP3 0x00000020
50#define MMCIF_CE_RESP2 0x00000024
51#define MMCIF_CE_RESP1 0x00000028
52#define MMCIF_CE_RESP0 0x0000002C
53#define MMCIF_CE_RESP_CMD12 0x00000030
54#define MMCIF_CE_DATA 0x00000034
55#define MMCIF_CE_INT 0x00000040
56#define MMCIF_CE_INT_MASK 0x00000044
57#define MMCIF_CE_HOST_STS1 0x00000048
58#define MMCIF_CE_HOST_STS2 0x0000004C
59#define MMCIF_CE_VERSION 0x0000007C
60
61extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
62{
63 return readl(addr + reg);
64}
65
66extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
67{
68 writel(val, addr + reg);
69}
70
Yusuke Godafdc50a92010-05-26 14:41:59 -070071#endif /* __SH_MMCIF_H__ */