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Ben Dooks7162ba02010-01-06 10:14:51 +09001/* arch/arm/plat-samsung/irq-vic-timer.c
2 * originally part of arch/arm/plat-s3c64xx/irq.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * S3C64XX - Interrupt handling
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22#include <plat/irq-vic-timer.h>
23#include <plat/regs-timer.h>
24
25static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
26{
Lennert Buytenhek04ea1cc2010-12-14 22:55:57 +010027 generic_handle_irq((int)desc->irq_data.handler_data);
Ben Dooks7162ba02010-01-06 10:14:51 +090028}
29
30/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
31
Mark Browndf3d0292010-12-03 20:28:21 +090032static void s3c_irq_timer_mask(struct irq_data *data)
Ben Dooks7162ba02010-01-06 10:14:51 +090033{
34 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
Mark Browndf3d0292010-12-03 20:28:21 +090035 u32 mask = (u32)data->chip_data;
Ben Dooks7162ba02010-01-06 10:14:51 +090036
37 reg &= 0x1f; /* mask out pending interrupts */
Mark Browndf3d0292010-12-03 20:28:21 +090038 reg &= ~mask;
Ben Dooks7162ba02010-01-06 10:14:51 +090039 __raw_writel(reg, S3C64XX_TINT_CSTAT);
40}
41
Mark Browndf3d0292010-12-03 20:28:21 +090042static void s3c_irq_timer_unmask(struct irq_data *data)
Ben Dooks7162ba02010-01-06 10:14:51 +090043{
44 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
Mark Browndf3d0292010-12-03 20:28:21 +090045 u32 mask = (u32)data->chip_data;
Ben Dooks7162ba02010-01-06 10:14:51 +090046
47 reg &= 0x1f; /* mask out pending interrupts */
Mark Browndf3d0292010-12-03 20:28:21 +090048 reg |= mask;
Ben Dooks7162ba02010-01-06 10:14:51 +090049 __raw_writel(reg, S3C64XX_TINT_CSTAT);
50}
51
Mark Browndf3d0292010-12-03 20:28:21 +090052static void s3c_irq_timer_ack(struct irq_data *data)
Ben Dooks7162ba02010-01-06 10:14:51 +090053{
54 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
Mark Browndf3d0292010-12-03 20:28:21 +090055 u32 mask = (u32)data->chip_data;
Ben Dooks7162ba02010-01-06 10:14:51 +090056
57 reg &= 0x1f;
Mark Browndf3d0292010-12-03 20:28:21 +090058 reg |= mask << 5;
Ben Dooks7162ba02010-01-06 10:14:51 +090059 __raw_writel(reg, S3C64XX_TINT_CSTAT);
60}
61
62static struct irq_chip s3c_irq_timer = {
63 .name = "s3c-timer",
Mark Browndf3d0292010-12-03 20:28:21 +090064 .irq_mask = s3c_irq_timer_mask,
65 .irq_unmask = s3c_irq_timer_unmask,
66 .irq_ack = s3c_irq_timer_ack,
Ben Dooks7162ba02010-01-06 10:14:51 +090067};
68
69/**
70 * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
71 * @parent_irq: The parent IRQ on the VIC for the timer.
72 * @timer_irq: The IRQ to be used for the timer.
73 *
74 * Register the necessary IRQ chaining and support for the timer IRQs
75 * chained of the VIC.
76 */
77void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
78 unsigned int timer_irq)
79{
80 struct irq_desc *desc = irq_to_desc(parent_irq);
81
82 set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
83
84 set_irq_chip(timer_irq, &s3c_irq_timer);
Mark Browndf3d0292010-12-03 20:28:21 +090085 set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
Ben Dooks7162ba02010-01-06 10:14:51 +090086 set_irq_handler(timer_irq, handle_level_irq);
87 set_irq_flags(timer_irq, IRQF_VALID);
88
Lennert Buytenhek04ea1cc2010-12-14 22:55:57 +010089 desc->irq_data.handler_data = (void *)timer_irq;
Ben Dooks7162ba02010-01-06 10:14:51 +090090}