| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* clear_page.S: UltraSparc optimized clear page. |
| 2 | * |
| 3 | * Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com) |
| 4 | * Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com) |
| 5 | */ |
| 6 | |
| 7 | #include <asm/visasm.h> |
| 8 | #include <asm/thread_info.h> |
| 9 | #include <asm/page.h> |
| 10 | #include <asm/pgtable.h> |
| 11 | #include <asm/spitfire.h> |
| David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 12 | #include <asm/head.h> |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | |
| 14 | /* What we used to do was lock a TLB entry into a specific |
| 15 | * TLB slot, clear the page with interrupts disabled, then |
| 16 | * restore the original TLB entry. This was great for |
| 17 | * disturbing the TLB as little as possible, but it meant |
| 18 | * we had to keep interrupts disabled for a long time. |
| 19 | * |
| 20 | * Now, we simply use the normal TLB loading mechanism, |
| 21 | * and this makes the cpu choose a slot all by itself. |
| 22 | * Then we do a normal TLB flush on exit. We need only |
| 23 | * disable preemption during the clear. |
| 24 | */ |
| 25 | |
| 26 | #define TTE_BITS_TOP (_PAGE_VALID | _PAGE_SZBITS) |
| 27 | #define TTE_BITS_BOTTOM (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W) |
| 28 | |
| 29 | .text |
| 30 | |
| 31 | .globl _clear_page |
| 32 | _clear_page: /* %o0=dest */ |
| 33 | ba,pt %xcc, clear_page_common |
| 34 | clr %o4 |
| 35 | |
| 36 | /* This thing is pretty important, it shows up |
| 37 | * on the profiles via do_anonymous_page(). |
| 38 | */ |
| 39 | .align 32 |
| 40 | .globl clear_user_page |
| 41 | clear_user_page: /* %o0=dest, %o1=vaddr */ |
| 42 | lduw [%g6 + TI_PRE_COUNT], %o2 |
| 43 | sethi %uhi(PAGE_OFFSET), %g2 |
| 44 | sethi %hi(PAGE_SIZE), %o4 |
| 45 | |
| 46 | sllx %g2, 32, %g2 |
| 47 | sethi %uhi(TTE_BITS_TOP), %g3 |
| 48 | |
| 49 | sllx %g3, 32, %g3 |
| 50 | sub %o0, %g2, %g1 ! paddr |
| 51 | |
| 52 | or %g3, TTE_BITS_BOTTOM, %g3 |
| 53 | and %o1, %o4, %o0 ! vaddr D-cache alias bit |
| 54 | |
| 55 | or %g1, %g3, %g1 ! TTE data |
| 56 | sethi %hi(TLBTEMP_BASE), %o3 |
| 57 | |
| 58 | add %o2, 1, %o4 |
| 59 | add %o0, %o3, %o0 ! TTE vaddr |
| 60 | |
| 61 | /* Disable preemption. */ |
| 62 | mov TLB_TAG_ACCESS, %g3 |
| 63 | stw %o4, [%g6 + TI_PRE_COUNT] |
| 64 | |
| 65 | /* Load TLB entry. */ |
| 66 | rdpr %pstate, %o4 |
| 67 | wrpr %o4, PSTATE_IE, %pstate |
| 68 | stxa %o0, [%g3] ASI_DMMU |
| 69 | stxa %g1, [%g0] ASI_DTLB_DATA_IN |
| David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 70 | sethi %hi(KERNBASE), %g1 |
| 71 | flush %g1 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | wrpr %o4, 0x0, %pstate |
| 73 | |
| 74 | mov 1, %o4 |
| 75 | |
| 76 | clear_page_common: |
| 77 | VISEntryHalf |
| 78 | membar #StoreLoad | #StoreStore | #LoadStore |
| 79 | fzero %f0 |
| 80 | sethi %hi(PAGE_SIZE/64), %o1 |
| 81 | mov %o0, %g1 ! remember vaddr for tlbflush |
| 82 | fzero %f2 |
| 83 | or %o1, %lo(PAGE_SIZE/64), %o1 |
| 84 | faddd %f0, %f2, %f4 |
| 85 | fmuld %f0, %f2, %f6 |
| 86 | faddd %f0, %f2, %f8 |
| 87 | fmuld %f0, %f2, %f10 |
| 88 | |
| 89 | faddd %f0, %f2, %f12 |
| 90 | fmuld %f0, %f2, %f14 |
| 91 | 1: stda %f0, [%o0 + %g0] ASI_BLK_P |
| 92 | subcc %o1, 1, %o1 |
| 93 | bne,pt %icc, 1b |
| 94 | add %o0, 0x40, %o0 |
| 95 | membar #Sync |
| 96 | VISExitHalf |
| 97 | |
| 98 | brz,pn %o4, out |
| 99 | nop |
| 100 | |
| 101 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
| 102 | membar #Sync |
| 103 | stw %o2, [%g6 + TI_PRE_COUNT] |
| 104 | |
| 105 | out: retl |
| 106 | nop |
| 107 | |