blob: 3417dd3a7c37341ac08af33175428348f1d0467b [file] [log] [blame]
Vaibhav Hiremathddd04b92012-06-18 00:47:26 -06001/*
2 * AM33XX PRM functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/io.h>
21
22#include <plat/common.h>
23
24#include "common.h"
Paul Walmsley49815392012-10-21 01:01:10 -060025#include "powerdomain.h"
Vaibhav Hiremathddd04b92012-06-18 00:47:26 -060026#include "prm33xx.h"
27#include "prm-regbits-33xx.h"
28
29/* Read a register in a PRM instance */
30u32 am33xx_prm_read_reg(s16 inst, u16 idx)
31{
32 return __raw_readl(prm_base + inst + idx);
33}
34
35/* Write into a register in a PRM instance */
36void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
37{
38 __raw_writel(val, prm_base + inst + idx);
39}
40
41/* Read-modify-write a register in PRM. Caller must lock */
42u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
43{
44 u32 v;
45
46 v = am33xx_prm_read_reg(inst, idx);
47 v &= ~mask;
48 v |= bits;
49 am33xx_prm_write_reg(v, inst, idx);
50
51 return v;
52}
53
54/**
55 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
56 * submodules contained in the hwmod module
57 * @shift: register bit shift corresponding to the reset line to check
58 * @inst: CM instance register offset (*_INST macro)
59 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
60 *
61 * Returns 1 if the (sub)module hardreset line is currently asserted,
62 * 0 if the (sub)module hardreset line is not currently asserted, or
63 * -EINVAL upon parameter error.
64 */
65int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
66{
67 u32 v;
68
69 v = am33xx_prm_read_reg(inst, rstctrl_offs);
70 v &= 1 << shift;
71 v >>= shift;
72
73 return v;
74}
75
76/**
77 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
78 * @shift: register bit shift corresponding to the reset line to assert
79 * @inst: CM instance register offset (*_INST macro)
80 * @rstctrl_reg: RM_RSTCTRL register address for this module
81 *
82 * Some IPs like dsp, ipu or iva contain processors that require an HW
83 * reset line to be asserted / deasserted in order to fully enable the
84 * IP. These modules may have multiple hard-reset lines that reset
85 * different 'submodules' inside the IP block. This function will
86 * place the submodule into reset. Returns 0 upon success or -EINVAL
87 * upon an argument error.
88 */
89int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
90{
91 u32 mask = 1 << shift;
92
93 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
94
95 return 0;
96}
97
98/**
99 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
100 * wait
101 * @shift: register bit shift corresponding to the reset line to deassert
102 * @inst: CM instance register offset (*_INST macro)
103 * @rstctrl_reg: RM_RSTCTRL register address for this module
104 * @rstst_reg: RM_RSTST register address for this module
105 *
106 * Some IPs like dsp, ipu or iva contain processors that require an HW
107 * reset line to be asserted / deasserted in order to fully enable the
108 * IP. These modules may have multiple hard-reset lines that reset
109 * different 'submodules' inside the IP block. This function will
110 * take the submodule out of reset and wait until the PRCM indicates
111 * that the reset has completed before returning. Returns 0 upon success or
112 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
113 * of reset, or -EBUSY if the submodule did not exit reset promptly.
114 */
115int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
116 u16 rstctrl_offs, u16 rstst_offs)
117{
118 int c;
119 u32 mask = 1 << shift;
120
121 /* Check the current status to avoid de-asserting the line twice */
122 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
123 return -EEXIST;
124
125 /* Clear the reset status by writing 1 to the status bit */
126 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
127 /* de-assert the reset control line */
128 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
129 /* wait the status to be set */
130
131 omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
132 rstst_offs),
133 MAX_MODULE_HARDRESET_WAIT, c);
134
135 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
136}
Paul Walmsley49815392012-10-21 01:01:10 -0600137
138static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
139{
140 am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
141 (pwrst << OMAP_POWERSTATE_SHIFT),
142 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
143 return 0;
144}
145
146static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
147{
148 u32 v;
149
150 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
151 v &= OMAP_POWERSTATE_MASK;
152 v >>= OMAP_POWERSTATE_SHIFT;
153
154 return v;
155}
156
157static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
158{
159 u32 v;
160
161 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
162 v &= OMAP_POWERSTATEST_MASK;
163 v >>= OMAP_POWERSTATEST_SHIFT;
164
165 return v;
166}
167
168static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
169{
170 u32 v;
171
172 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
173 v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
174 v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
175
176 return v;
177}
178
179static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
180{
181 am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
182 (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
183 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
184 return 0;
185}
186
187static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
188{
189 am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
190 AM33XX_LASTPOWERSTATEENTERED_MASK,
191 pwrdm->prcm_offs, pwrdm->pwrstst_offs);
192 return 0;
193}
194
195static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
196{
197 u32 m;
198
199 m = pwrdm->logicretstate_mask;
200 if (!m)
201 return -EINVAL;
202
203 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
204 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
205
206 return 0;
207}
208
209static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
210{
211 u32 v;
212
213 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
214 v &= AM33XX_LOGICSTATEST_MASK;
215 v >>= AM33XX_LOGICSTATEST_SHIFT;
216
217 return v;
218}
219
220static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
221{
222 u32 v, m;
223
224 m = pwrdm->logicretstate_mask;
225 if (!m)
226 return -EINVAL;
227
228 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
229 v &= m;
230 v >>= __ffs(m);
231
232 return v;
233}
234
235static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
236 u8 pwrst)
237{
238 u32 m;
239
240 m = pwrdm->mem_on_mask[bank];
241 if (!m)
242 return -EINVAL;
243
244 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
245 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
246
247 return 0;
248}
249
250static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
251 u8 pwrst)
252{
253 u32 m;
254
255 m = pwrdm->mem_ret_mask[bank];
256 if (!m)
257 return -EINVAL;
258
259 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
260 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
261
262 return 0;
263}
264
265static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
266{
267 u32 m, v;
268
269 m = pwrdm->mem_pwrst_mask[bank];
270 if (!m)
271 return -EINVAL;
272
273 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
274 v &= m;
275 v >>= __ffs(m);
276
277 return v;
278}
279
280static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
281{
282 u32 m, v;
283
284 m = pwrdm->mem_retst_mask[bank];
285 if (!m)
286 return -EINVAL;
287
288 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
289 v &= m;
290 v >>= __ffs(m);
291
292 return v;
293}
294
295static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
296{
297 u32 c = 0;
298
299 /*
300 * REVISIT: pwrdm_wait_transition() may be better implemented
301 * via a callback and a periodic timer check -- how long do we expect
302 * powerdomain transitions to take?
303 */
304
305 /* XXX Is this udelay() value meaningful? */
306 while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
307 & OMAP_INTRANSITION_MASK) &&
308 (c++ < PWRDM_TRANSITION_BAILOUT))
309 udelay(1);
310
311 if (c > PWRDM_TRANSITION_BAILOUT) {
312 pr_err("powerdomain: %s: waited too long to complete transition\n",
313 pwrdm->name);
314 return -EAGAIN;
315 }
316
317 pr_debug("powerdomain: completed transition in %d loops\n", c);
318
319 return 0;
320}
321
322struct pwrdm_ops am33xx_pwrdm_operations = {
323 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
324 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
325 .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
326 .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
327 .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
328 .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
329 .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
330 .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
331 .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
332 .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
333 .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
334 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
335 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
336 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
337};