Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2012 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 13 | #include <linux/clk-provider.h> |
Shawn Guo | 322503a | 2013-10-30 15:12:55 +0800 | [diff] [blame] | 14 | #include <linux/delay.h> |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 15 | #include <linux/io.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/jiffies.h> |
| 18 | #include <linux/err.h> |
| 19 | #include "clk.h" |
| 20 | |
| 21 | #define PLL_NUM_OFFSET 0x10 |
| 22 | #define PLL_DENOM_OFFSET 0x20 |
| 23 | |
| 24 | #define BM_PLL_POWER (0x1 << 12) |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 25 | #define BM_PLL_LOCK (0x1 << 31) |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 26 | #define IMX7_ENET_PLL_POWER (0x1 << 5) |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 27 | |
| 28 | /** |
| 29 | * struct clk_pllv3 - IMX PLL clock version 3 |
| 30 | * @clk_hw: clock source |
| 31 | * @base: base address of PLL registers |
| 32 | * @powerup_set: set POWER bit to power up the PLL |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 33 | * @powerdown: pll powerdown offset bit |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 34 | * @div_mask: mask of divider bits |
Stefan Agner | 60ad846 | 2014-12-02 17:59:42 +0100 | [diff] [blame] | 35 | * @div_shift: shift of divider bits |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 36 | * |
| 37 | * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 |
| 38 | * is actually a multiplier, and always sits at bit 0. |
| 39 | */ |
| 40 | struct clk_pllv3 { |
| 41 | struct clk_hw hw; |
| 42 | void __iomem *base; |
| 43 | bool powerup_set; |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 44 | u32 powerdown; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 45 | u32 div_mask; |
Stefan Agner | 60ad846 | 2014-12-02 17:59:42 +0100 | [diff] [blame] | 46 | u32 div_shift; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 47 | }; |
| 48 | |
| 49 | #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) |
| 50 | |
Shawn Guo | bc3b84d | 2013-10-30 15:56:22 +0800 | [diff] [blame] | 51 | static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) |
| 52 | { |
| 53 | unsigned long timeout = jiffies + msecs_to_jiffies(10); |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 54 | u32 val = readl_relaxed(pll->base) & pll->powerdown; |
Shawn Guo | bc3b84d | 2013-10-30 15:56:22 +0800 | [diff] [blame] | 55 | |
| 56 | /* No need to wait for lock when pll is not powered up */ |
| 57 | if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) |
| 58 | return 0; |
| 59 | |
| 60 | /* Wait for PLL to lock */ |
| 61 | do { |
| 62 | if (readl_relaxed(pll->base) & BM_PLL_LOCK) |
| 63 | break; |
| 64 | if (time_after(jiffies, timeout)) |
| 65 | break; |
| 66 | usleep_range(50, 500); |
| 67 | } while (1); |
| 68 | |
| 69 | return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; |
| 70 | } |
| 71 | |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 72 | static int clk_pllv3_prepare(struct clk_hw *hw) |
| 73 | { |
| 74 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 75 | u32 val; |
| 76 | |
| 77 | val = readl_relaxed(pll->base); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 78 | if (pll->powerup_set) |
| 79 | val |= BM_PLL_POWER; |
| 80 | else |
| 81 | val &= ~BM_PLL_POWER; |
| 82 | writel_relaxed(val, pll->base); |
| 83 | |
Dmitry Voytik | c400f7a | 2014-11-06 22:49:32 +0400 | [diff] [blame] | 84 | return clk_pllv3_wait_lock(pll); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static void clk_pllv3_unprepare(struct clk_hw *hw) |
| 88 | { |
| 89 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 90 | u32 val; |
| 91 | |
| 92 | val = readl_relaxed(pll->base); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 93 | if (pll->powerup_set) |
| 94 | val &= ~BM_PLL_POWER; |
| 95 | else |
| 96 | val |= BM_PLL_POWER; |
| 97 | writel_relaxed(val, pll->base); |
| 98 | } |
| 99 | |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 100 | static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, |
| 101 | unsigned long parent_rate) |
| 102 | { |
| 103 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
Stefan Agner | 60ad846 | 2014-12-02 17:59:42 +0100 | [diff] [blame] | 104 | u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 105 | |
| 106 | return (div == 1) ? parent_rate * 22 : parent_rate * 20; |
| 107 | } |
| 108 | |
| 109 | static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, |
| 110 | unsigned long *prate) |
| 111 | { |
| 112 | unsigned long parent_rate = *prate; |
| 113 | |
| 114 | return (rate >= parent_rate * 22) ? parent_rate * 22 : |
| 115 | parent_rate * 20; |
| 116 | } |
| 117 | |
| 118 | static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, |
| 119 | unsigned long parent_rate) |
| 120 | { |
| 121 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 122 | u32 val, div; |
| 123 | |
| 124 | if (rate == parent_rate * 22) |
| 125 | div = 1; |
| 126 | else if (rate == parent_rate * 20) |
| 127 | div = 0; |
| 128 | else |
| 129 | return -EINVAL; |
| 130 | |
| 131 | val = readl_relaxed(pll->base); |
Stefan Agner | 60ad846 | 2014-12-02 17:59:42 +0100 | [diff] [blame] | 132 | val &= ~(pll->div_mask << pll->div_shift); |
| 133 | val |= (div << pll->div_shift); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 134 | writel_relaxed(val, pll->base); |
| 135 | |
Shawn Guo | bc3b84d | 2013-10-30 15:56:22 +0800 | [diff] [blame] | 136 | return clk_pllv3_wait_lock(pll); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | static const struct clk_ops clk_pllv3_ops = { |
| 140 | .prepare = clk_pllv3_prepare, |
| 141 | .unprepare = clk_pllv3_unprepare, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 142 | .recalc_rate = clk_pllv3_recalc_rate, |
| 143 | .round_rate = clk_pllv3_round_rate, |
| 144 | .set_rate = clk_pllv3_set_rate, |
| 145 | }; |
| 146 | |
| 147 | static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, |
| 148 | unsigned long parent_rate) |
| 149 | { |
| 150 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 151 | u32 div = readl_relaxed(pll->base) & pll->div_mask; |
| 152 | |
| 153 | return parent_rate * div / 2; |
| 154 | } |
| 155 | |
| 156 | static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, |
| 157 | unsigned long *prate) |
| 158 | { |
| 159 | unsigned long parent_rate = *prate; |
| 160 | unsigned long min_rate = parent_rate * 54 / 2; |
| 161 | unsigned long max_rate = parent_rate * 108 / 2; |
| 162 | u32 div; |
| 163 | |
| 164 | if (rate > max_rate) |
| 165 | rate = max_rate; |
| 166 | else if (rate < min_rate) |
| 167 | rate = min_rate; |
| 168 | div = rate * 2 / parent_rate; |
| 169 | |
| 170 | return parent_rate * div / 2; |
| 171 | } |
| 172 | |
| 173 | static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, |
| 174 | unsigned long parent_rate) |
| 175 | { |
| 176 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 177 | unsigned long min_rate = parent_rate * 54 / 2; |
| 178 | unsigned long max_rate = parent_rate * 108 / 2; |
| 179 | u32 val, div; |
| 180 | |
| 181 | if (rate < min_rate || rate > max_rate) |
| 182 | return -EINVAL; |
| 183 | |
| 184 | div = rate * 2 / parent_rate; |
| 185 | val = readl_relaxed(pll->base); |
| 186 | val &= ~pll->div_mask; |
| 187 | val |= div; |
| 188 | writel_relaxed(val, pll->base); |
| 189 | |
Shawn Guo | bc3b84d | 2013-10-30 15:56:22 +0800 | [diff] [blame] | 190 | return clk_pllv3_wait_lock(pll); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | static const struct clk_ops clk_pllv3_sys_ops = { |
| 194 | .prepare = clk_pllv3_prepare, |
| 195 | .unprepare = clk_pllv3_unprepare, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 196 | .recalc_rate = clk_pllv3_sys_recalc_rate, |
| 197 | .round_rate = clk_pllv3_sys_round_rate, |
| 198 | .set_rate = clk_pllv3_sys_set_rate, |
| 199 | }; |
| 200 | |
| 201 | static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, |
| 202 | unsigned long parent_rate) |
| 203 | { |
| 204 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 205 | u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); |
| 206 | u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); |
| 207 | u32 div = readl_relaxed(pll->base) & pll->div_mask; |
| 208 | |
| 209 | return (parent_rate * div) + ((parent_rate / mfd) * mfn); |
| 210 | } |
| 211 | |
| 212 | static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, |
| 213 | unsigned long *prate) |
| 214 | { |
| 215 | unsigned long parent_rate = *prate; |
| 216 | unsigned long min_rate = parent_rate * 27; |
| 217 | unsigned long max_rate = parent_rate * 54; |
| 218 | u32 div; |
| 219 | u32 mfn, mfd = 1000000; |
Anson Huang | 7a5568c | 2015-05-08 00:16:51 +0800 | [diff] [blame] | 220 | u64 temp64; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 221 | |
| 222 | if (rate > max_rate) |
| 223 | rate = max_rate; |
| 224 | else if (rate < min_rate) |
| 225 | rate = min_rate; |
| 226 | |
| 227 | div = rate / parent_rate; |
| 228 | temp64 = (u64) (rate - div * parent_rate); |
| 229 | temp64 *= mfd; |
| 230 | do_div(temp64, parent_rate); |
| 231 | mfn = temp64; |
| 232 | |
| 233 | return parent_rate * div + parent_rate / mfd * mfn; |
| 234 | } |
| 235 | |
| 236 | static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, |
| 237 | unsigned long parent_rate) |
| 238 | { |
| 239 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 240 | unsigned long min_rate = parent_rate * 27; |
| 241 | unsigned long max_rate = parent_rate * 54; |
| 242 | u32 val, div; |
| 243 | u32 mfn, mfd = 1000000; |
Anson Huang | 7a5568c | 2015-05-08 00:16:51 +0800 | [diff] [blame] | 244 | u64 temp64; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 245 | |
| 246 | if (rate < min_rate || rate > max_rate) |
| 247 | return -EINVAL; |
| 248 | |
| 249 | div = rate / parent_rate; |
| 250 | temp64 = (u64) (rate - div * parent_rate); |
| 251 | temp64 *= mfd; |
| 252 | do_div(temp64, parent_rate); |
| 253 | mfn = temp64; |
| 254 | |
| 255 | val = readl_relaxed(pll->base); |
| 256 | val &= ~pll->div_mask; |
| 257 | val |= div; |
| 258 | writel_relaxed(val, pll->base); |
| 259 | writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); |
| 260 | writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); |
| 261 | |
Shawn Guo | bc3b84d | 2013-10-30 15:56:22 +0800 | [diff] [blame] | 262 | return clk_pllv3_wait_lock(pll); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | static const struct clk_ops clk_pllv3_av_ops = { |
| 266 | .prepare = clk_pllv3_prepare, |
| 267 | .unprepare = clk_pllv3_unprepare, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 268 | .recalc_rate = clk_pllv3_av_recalc_rate, |
| 269 | .round_rate = clk_pllv3_av_round_rate, |
| 270 | .set_rate = clk_pllv3_av_set_rate, |
| 271 | }; |
| 272 | |
| 273 | static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, |
| 274 | unsigned long parent_rate) |
| 275 | { |
Sascha Hauer | 7a04092 | 2012-11-21 14:42:31 +0100 | [diff] [blame] | 276 | return 500000000; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | static const struct clk_ops clk_pllv3_enet_ops = { |
| 280 | .prepare = clk_pllv3_prepare, |
| 281 | .unprepare = clk_pllv3_unprepare, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 282 | .recalc_rate = clk_pllv3_enet_recalc_rate, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 283 | }; |
| 284 | |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 285 | struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, |
| 286 | const char *parent_name, void __iomem *base, |
Sascha Hauer | 2b25469 | 2012-11-22 10:18:41 +0100 | [diff] [blame] | 287 | u32 div_mask) |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 288 | { |
| 289 | struct clk_pllv3 *pll; |
| 290 | const struct clk_ops *ops; |
| 291 | struct clk *clk; |
| 292 | struct clk_init_data init; |
| 293 | |
| 294 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
| 295 | if (!pll) |
| 296 | return ERR_PTR(-ENOMEM); |
| 297 | |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 298 | pll->powerdown = BM_PLL_POWER; |
| 299 | |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 300 | switch (type) { |
| 301 | case IMX_PLLV3_SYS: |
| 302 | ops = &clk_pllv3_sys_ops; |
| 303 | break; |
Stefan Agner | 60ad846 | 2014-12-02 17:59:42 +0100 | [diff] [blame] | 304 | case IMX_PLLV3_USB_VF610: |
| 305 | pll->div_shift = 1; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 306 | case IMX_PLLV3_USB: |
| 307 | ops = &clk_pllv3_ops; |
| 308 | pll->powerup_set = true; |
| 309 | break; |
| 310 | case IMX_PLLV3_AV: |
| 311 | ops = &clk_pllv3_av_ops; |
| 312 | break; |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 313 | case IMX_PLLV3_ENET_IMX7: |
| 314 | pll->powerdown = IMX7_ENET_PLL_POWER; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 315 | case IMX_PLLV3_ENET: |
| 316 | ops = &clk_pllv3_enet_ops; |
| 317 | break; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 318 | default: |
| 319 | ops = &clk_pllv3_ops; |
| 320 | } |
| 321 | pll->base = base; |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 322 | pll->div_mask = div_mask; |
| 323 | |
| 324 | init.name = name; |
| 325 | init.ops = ops; |
| 326 | init.flags = 0; |
| 327 | init.parent_names = &parent_name; |
| 328 | init.num_parents = 1; |
| 329 | |
| 330 | pll->hw.init = &init; |
| 331 | |
| 332 | clk = clk_register(NULL, &pll->hw); |
| 333 | if (IS_ERR(clk)) |
| 334 | kfree(pll); |
| 335 | |
| 336 | return clk; |
| 337 | } |