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Russell Kingf32f4ce2009-05-16 12:14:21 +01001#ifndef __ASMARM_SMP_TWD_H
2#define __ASMARM_SMP_TWD_H
3
Srinidhi Kasagarf4a27ae2010-05-12 05:52:18 +01004#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C
8
9#define TWD_WDOG_LOAD 0x20
10#define TWD_WDOG_COUNTER 0x24
11#define TWD_WDOG_CONTROL 0x28
12#define TWD_WDOG_INTSTAT 0x2C
13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34
15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
Russell Kingf32f4ce2009-05-16 12:14:21 +010021struct clock_event_device;
22
23extern void __iomem *twd_base;
24
Russell Kingf32f4ce2009-05-16 12:14:21 +010025void twd_timer_setup(struct clock_event_device *);
Marc Zyngier28af6902011-07-22 12:52:37 +010026void twd_timer_stop(struct clock_event_device *);
Russell Kingf32f4ce2009-05-16 12:14:21 +010027
28#endif