blob: 609ea2ded7e388a22ed9c9d59ba888672ebb13ab [file] [log] [blame]
Hiroshi DOYU340a6142006-12-07 15:43:59 -08001/*
Hiroshi DOYU733ecc52009-03-23 18:07:23 -07002 * Mailbox reservation modules for OMAP2/3
Hiroshi DOYU340a6142006-12-07 15:43:59 -08003 *
Hiroshi DOYU733ecc52009-03-23 18:07:23 -07004 * Copyright (C) 2006-2009 Nokia Corporation
Hiroshi DOYU340a6142006-12-07 15:43:59 -08005 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Hiroshi DOYU733ecc52009-03-23 18:07:23 -07006 * and Paul Mundt
Hiroshi DOYU340a6142006-12-07 15:43:59 -08007 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
Tony Lindgrena1bcc1d2011-11-07 12:27:10 -080013#include <linux/module.h>
Hiroshi DOYU340a6142006-12-07 15:43:59 -080014#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
Russell Kingfced80c2008-09-06 12:10:45 +010017#include <linux/io.h>
Omar Ramirez Luna82d2a5d2011-02-24 12:51:33 -080018#include <linux/pm_runtime.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070019#include <plat/mailbox.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/irqs.h>
Hiroshi DOYU340a6142006-12-07 15:43:59 -080021
Hiroshi DOYU733ecc52009-03-23 18:07:23 -070022#define MAILBOX_REVISION 0x000
Hiroshi DOYU733ecc52009-03-23 18:07:23 -070023#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
24#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
25#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
26#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
27#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
28
C A Subramaniam5f00ec62009-11-22 10:11:22 -080029#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
30#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
31#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
32
33#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
34#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
Hiroshi DOYU340a6142006-12-07 15:43:59 -080035
Hiroshi DOYUc75ee752009-03-23 18:07:26 -070036#define MBOX_REG_SIZE 0x120
C A Subramaniam5f00ec62009-11-22 10:11:22 -080037
38#define OMAP4_MBOX_REG_SIZE 0x130
39
Hiroshi DOYUc75ee752009-03-23 18:07:26 -070040#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
C A Subramaniam5f00ec62009-11-22 10:11:22 -080041#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
Hiroshi DOYUc75ee752009-03-23 18:07:26 -070042
Hiroshi DOYU6c20a682009-03-23 18:07:23 -070043static void __iomem *mbox_base;
Hiroshi DOYU340a6142006-12-07 15:43:59 -080044
Hiroshi DOYU340a6142006-12-07 15:43:59 -080045struct omap_mbox2_fifo {
46 unsigned long msg;
47 unsigned long fifo_stat;
48 unsigned long msg_stat;
49};
50
51struct omap_mbox2_priv {
52 struct omap_mbox2_fifo tx_fifo;
53 struct omap_mbox2_fifo rx_fifo;
54 unsigned long irqenable;
55 unsigned long irqstatus;
56 u32 newmsg_bit;
57 u32 notfull_bit;
C A Subramaniam5f00ec62009-11-22 10:11:22 -080058 u32 ctx[OMAP4_MBOX_NR_REGS];
59 unsigned long irqdisable;
Hiroshi DOYU340a6142006-12-07 15:43:59 -080060};
61
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +030062static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
63 omap_mbox_type_t irq);
64
Hiroshi DOYU6c20a682009-03-23 18:07:23 -070065static inline unsigned int mbox_read_reg(size_t ofs)
Hiroshi DOYU340a6142006-12-07 15:43:59 -080066{
Hiroshi DOYU6c20a682009-03-23 18:07:23 -070067 return __raw_readl(mbox_base + ofs);
Hiroshi DOYU340a6142006-12-07 15:43:59 -080068}
69
Hiroshi DOYU6c20a682009-03-23 18:07:23 -070070static inline void mbox_write_reg(u32 val, size_t ofs)
Hiroshi DOYU340a6142006-12-07 15:43:59 -080071{
Hiroshi DOYU6c20a682009-03-23 18:07:23 -070072 __raw_writel(val, mbox_base + ofs);
Hiroshi DOYU340a6142006-12-07 15:43:59 -080073}
74
75/* Mailbox H/W preparations */
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +030076static int omap2_mbox_startup(struct omap_mbox *mbox)
Hiroshi DOYU340a6142006-12-07 15:43:59 -080077{
Hiroshi DOYU1ffe6272009-09-24 16:23:09 -070078 u32 l;
Hiroshi DOYU340a6142006-12-07 15:43:59 -080079
Omar Ramirez Luna82d2a5d2011-02-24 12:51:33 -080080 pm_runtime_enable(mbox->dev->parent);
81 pm_runtime_get_sync(mbox->dev->parent);
Hiroshi DOYU1ffe6272009-09-24 16:23:09 -070082
Hiroshi DOYU94fc58c2009-03-23 18:07:24 -070083 l = mbox_read_reg(MAILBOX_REVISION);
Felipe Contreras909f9dc2010-06-11 15:51:37 +000084 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
Hiroshi DOYU94fc58c2009-03-23 18:07:24 -070085
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +030086 omap2_mbox_enable_irq(mbox, IRQ_RX);
87
Hiroshi DOYU340a6142006-12-07 15:43:59 -080088 return 0;
89}
90
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +030091static void omap2_mbox_shutdown(struct omap_mbox *mbox)
Hiroshi DOYU340a6142006-12-07 15:43:59 -080092{
Omar Ramirez Luna82d2a5d2011-02-24 12:51:33 -080093 pm_runtime_put_sync(mbox->dev->parent);
94 pm_runtime_disable(mbox->dev->parent);
Hiroshi DOYU340a6142006-12-07 15:43:59 -080095}
96
97/* Mailbox FIFO handle functions */
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +030098static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
Hiroshi DOYU340a6142006-12-07 15:43:59 -080099{
100 struct omap_mbox2_fifo *fifo =
101 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
102 return (mbox_msg_t) mbox_read_reg(fifo->msg);
103}
104
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300105static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800106{
107 struct omap_mbox2_fifo *fifo =
108 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
109 mbox_write_reg(msg, fifo->msg);
110}
111
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300112static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800113{
114 struct omap_mbox2_fifo *fifo =
115 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
116 return (mbox_read_reg(fifo->msg_stat) == 0);
117}
118
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300119static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800120{
121 struct omap_mbox2_fifo *fifo =
122 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800123 return mbox_read_reg(fifo->fifo_stat);
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800124}
125
126/* Mailbox IRQ handle functions */
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300127static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800128 omap_mbox_type_t irq)
129{
matt mooneyb45b5012010-09-27 19:04:32 -0700130 struct omap_mbox2_priv *p = mbox->priv;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800131 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
132
133 l = mbox_read_reg(p->irqenable);
134 l |= bit;
135 mbox_write_reg(l, p->irqenable);
136}
137
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300138static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800139 omap_mbox_type_t irq)
140{
matt mooneyb45b5012010-09-27 19:04:32 -0700141 struct omap_mbox2_priv *p = mbox->priv;
Hari Kanigeri525a1132011-03-02 22:14:18 +0000142 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
143
144 if (!cpu_is_omap44xx())
145 bit = mbox_read_reg(p->irqdisable) & ~bit;
146
147 mbox_write_reg(bit, p->irqdisable);
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800148}
149
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300150static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800151 omap_mbox_type_t irq)
152{
matt mooneyb45b5012010-09-27 19:04:32 -0700153 struct omap_mbox2_priv *p = mbox->priv;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800154 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
155
156 mbox_write_reg(bit, p->irqstatus);
Hiroshi DOYU88288802009-09-24 16:23:10 -0700157
158 /* Flush posted write for irq status to avoid spurious interrupts */
159 mbox_read_reg(p->irqstatus);
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800160}
161
Hiroshi DOYUbfbdcf82007-07-30 14:04:04 +0300162static int omap2_mbox_is_irq(struct omap_mbox *mbox,
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800163 omap_mbox_type_t irq)
164{
matt mooneyb45b5012010-09-27 19:04:32 -0700165 struct omap_mbox2_priv *p = mbox->priv;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800166 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
167 u32 enable = mbox_read_reg(p->irqenable);
168 u32 status = mbox_read_reg(p->irqstatus);
169
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800170 return (int)(enable & status & bit);
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800171}
172
Hiroshi DOYUc75ee752009-03-23 18:07:26 -0700173static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
174{
175 int i;
176 struct omap_mbox2_priv *p = mbox->priv;
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800177 int nr_regs;
178 if (cpu_is_omap44xx())
179 nr_regs = OMAP4_MBOX_NR_REGS;
180 else
181 nr_regs = MBOX_NR_REGS;
182 for (i = 0; i < nr_regs; i++) {
Hiroshi DOYUc75ee752009-03-23 18:07:26 -0700183 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
184
185 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
186 i, p->ctx[i]);
187 }
188}
189
190static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
191{
192 int i;
193 struct omap_mbox2_priv *p = mbox->priv;
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800194 int nr_regs;
195 if (cpu_is_omap44xx())
196 nr_regs = OMAP4_MBOX_NR_REGS;
197 else
198 nr_regs = MBOX_NR_REGS;
199 for (i = 0; i < nr_regs; i++) {
Hiroshi DOYUc75ee752009-03-23 18:07:26 -0700200 mbox_write_reg(p->ctx[i], i * sizeof(u32));
201
202 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
203 i, p->ctx[i]);
204 }
205}
206
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800207static struct omap_mbox_ops omap2_mbox_ops = {
208 .type = OMAP_MBOX_TYPE2,
209 .startup = omap2_mbox_startup,
210 .shutdown = omap2_mbox_shutdown,
211 .fifo_read = omap2_mbox_fifo_read,
212 .fifo_write = omap2_mbox_fifo_write,
213 .fifo_empty = omap2_mbox_fifo_empty,
214 .fifo_full = omap2_mbox_fifo_full,
215 .enable_irq = omap2_mbox_enable_irq,
216 .disable_irq = omap2_mbox_disable_irq,
217 .ack_irq = omap2_mbox_ack_irq,
218 .is_irq = omap2_mbox_is_irq,
Hiroshi DOYUc75ee752009-03-23 18:07:26 -0700219 .save_ctx = omap2_mbox_save_ctx,
220 .restore_ctx = omap2_mbox_restore_ctx,
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800221};
222
223/*
224 * MAILBOX 0: ARM -> DSP,
225 * MAILBOX 1: ARM <- DSP.
226 * MAILBOX 2: ARM -> IVA,
227 * MAILBOX 3: ARM <- IVA.
228 */
229
230/* FIXME: the following structs should be filled automatically by the user id */
Felipe Contreras07d65d82010-06-11 15:51:38 +0000231
Omar Ramirez Lunaff0fba02010-10-22 20:10:58 -0500232#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800233/* DSP */
234static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
235 .tx_fifo = {
Hiroshi DOYU733ecc52009-03-23 18:07:23 -0700236 .msg = MAILBOX_MESSAGE(0),
237 .fifo_stat = MAILBOX_FIFOSTATUS(0),
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800238 },
239 .rx_fifo = {
Hiroshi DOYU733ecc52009-03-23 18:07:23 -0700240 .msg = MAILBOX_MESSAGE(1),
241 .msg_stat = MAILBOX_MSGSTATUS(1),
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800242 },
Hiroshi DOYU733ecc52009-03-23 18:07:23 -0700243 .irqenable = MAILBOX_IRQENABLE(0),
244 .irqstatus = MAILBOX_IRQSTATUS(0),
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800245 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
246 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800247 .irqdisable = MAILBOX_IRQENABLE(0),
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800248};
249
Felipe Contreras07d65d82010-06-11 15:51:38 +0000250struct omap_mbox mbox_dsp_info = {
251 .name = "dsp",
252 .ops = &omap2_mbox_ops,
253 .priv = &omap2_mbox_dsp_priv,
254};
Felipe Contreras14476bd2010-06-11 15:51:47 +0000255#endif
Felipe Contreras07d65d82010-06-11 15:51:38 +0000256
Omar Ramirez Lunaff0fba02010-10-22 20:10:58 -0500257#if defined(CONFIG_ARCH_OMAP3)
Felipe Contreras898ee752010-06-11 15:51:45 +0000258struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
Felipe Contreras14476bd2010-06-11 15:51:47 +0000259#endif
Felipe Contreras898ee752010-06-11 15:51:45 +0000260
Tony Lindgren59b479e2011-01-27 16:39:40 -0800261#if defined(CONFIG_SOC_OMAP2420)
Felipe Contreras07d65d82010-06-11 15:51:38 +0000262/* IVA */
263static struct omap_mbox2_priv omap2_mbox_iva_priv = {
264 .tx_fifo = {
265 .msg = MAILBOX_MESSAGE(2),
266 .fifo_stat = MAILBOX_FIFOSTATUS(2),
267 },
268 .rx_fifo = {
269 .msg = MAILBOX_MESSAGE(3),
270 .msg_stat = MAILBOX_MSGSTATUS(3),
271 },
272 .irqenable = MAILBOX_IRQENABLE(3),
273 .irqstatus = MAILBOX_IRQSTATUS(3),
274 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
275 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
276 .irqdisable = MAILBOX_IRQENABLE(3),
277};
278
279static struct omap_mbox mbox_iva_info = {
280 .name = "iva",
281 .ops = &omap2_mbox_ops,
282 .priv = &omap2_mbox_iva_priv,
283};
Felipe Contreras898ee752010-06-11 15:51:45 +0000284
Kevin Hilmaneca83252011-02-11 19:56:42 +0000285struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
Felipe Contreras07d65d82010-06-11 15:51:38 +0000286#endif
287
Felipe Contreras14476bd2010-06-11 15:51:47 +0000288#if defined(CONFIG_ARCH_OMAP4)
Felipe Contreras07d65d82010-06-11 15:51:38 +0000289/* OMAP4 */
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800290static struct omap_mbox2_priv omap2_mbox_1_priv = {
291 .tx_fifo = {
292 .msg = MAILBOX_MESSAGE(0),
293 .fifo_stat = MAILBOX_FIFOSTATUS(0),
294 },
295 .rx_fifo = {
296 .msg = MAILBOX_MESSAGE(1),
297 .msg_stat = MAILBOX_MSGSTATUS(1),
298 },
299 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
300 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
301 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
302 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
303 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
304};
305
306struct omap_mbox mbox_1_info = {
307 .name = "mailbox-1",
308 .ops = &omap2_mbox_ops,
309 .priv = &omap2_mbox_1_priv,
310};
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800311
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800312static struct omap_mbox2_priv omap2_mbox_2_priv = {
313 .tx_fifo = {
314 .msg = MAILBOX_MESSAGE(3),
315 .fifo_stat = MAILBOX_FIFOSTATUS(3),
316 },
317 .rx_fifo = {
318 .msg = MAILBOX_MESSAGE(2),
319 .msg_stat = MAILBOX_MSGSTATUS(2),
320 },
321 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
322 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
323 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
324 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
325 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
326};
327
328struct omap_mbox mbox_2_info = {
329 .name = "mailbox-2",
330 .ops = &omap2_mbox_ops,
331 .priv = &omap2_mbox_2_priv,
332};
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800333
Felipe Contreras898ee752010-06-11 15:51:45 +0000334struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
Felipe Contreras14476bd2010-06-11 15:51:47 +0000335#endif
Felipe Contreras898ee752010-06-11 15:51:45 +0000336
Hiroshi DOYUda8cfe02009-03-23 18:07:25 -0700337static int __devinit omap2_mbox_probe(struct platform_device *pdev)
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800338{
Felipe Contreras898ee752010-06-11 15:51:45 +0000339 struct resource *mem;
Hiroshi DOYU6c20a682009-03-23 18:07:23 -0700340 int ret;
Felipe Contreras9c80c8c2010-06-11 15:51:46 +0000341 struct omap_mbox **list;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800342
Felipe Contreras14476bd2010-06-11 15:51:47 +0000343 if (false)
344 ;
Omar Ramirez Lunaff0fba02010-10-22 20:10:58 -0500345#if defined(CONFIG_ARCH_OMAP3)
346 else if (cpu_is_omap34xx()) {
Felipe Contreras898ee752010-06-11 15:51:45 +0000347 list = omap3_mboxes;
348
Felipe Contreras69dbf852011-02-24 12:51:33 -0800349 list[0]->irq = platform_get_irq(pdev, 0);
Felipe Contreras898ee752010-06-11 15:51:45 +0000350 }
Felipe Contreras14476bd2010-06-11 15:51:47 +0000351#endif
Omar Ramirez Lunaff0fba02010-10-22 20:10:58 -0500352#if defined(CONFIG_ARCH_OMAP2)
353 else if (cpu_is_omap2430()) {
354 list = omap2_mboxes;
355
Felipe Contreras69dbf852011-02-24 12:51:33 -0800356 list[0]->irq = platform_get_irq(pdev, 0);
Omar Ramirez Lunaff0fba02010-10-22 20:10:58 -0500357 } else if (cpu_is_omap2420()) {
Felipe Contreras898ee752010-06-11 15:51:45 +0000358 list = omap2_mboxes;
359
360 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
361 list[1]->irq = platform_get_irq_byname(pdev, "iva");
362 }
363#endif
Felipe Contreras14476bd2010-06-11 15:51:47 +0000364#if defined(CONFIG_ARCH_OMAP4)
Felipe Contreras898ee752010-06-11 15:51:45 +0000365 else if (cpu_is_omap44xx()) {
366 list = omap4_mboxes;
367
Felipe Contreras69dbf852011-02-24 12:51:33 -0800368 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
Felipe Contreras898ee752010-06-11 15:51:45 +0000369 }
Felipe Contreras14476bd2010-06-11 15:51:47 +0000370#endif
Felipe Contreras898ee752010-06-11 15:51:45 +0000371 else {
372 pr_err("%s: platform not supported\n", __func__);
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800373 return -ENODEV;
374 }
Felipe Contreras898ee752010-06-11 15:51:45 +0000375
376 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
377 mbox_base = ioremap(mem->start, resource_size(mem));
Hiroshi DOYU6c20a682009-03-23 18:07:23 -0700378 if (!mbox_base)
379 return -ENOMEM;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800380
Felipe Contreras9c80c8c2010-06-11 15:51:46 +0000381 ret = omap_mbox_register(&pdev->dev, list);
382 if (ret) {
383 iounmap(mbox_base);
384 return ret;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800385 }
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800386
Omar Ramirez Luna5d783732010-12-01 14:15:08 -0600387 return 0;
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800388}
389
Hiroshi DOYUda8cfe02009-03-23 18:07:25 -0700390static int __devexit omap2_mbox_remove(struct platform_device *pdev)
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800391{
Felipe Contreras9c80c8c2010-06-11 15:51:46 +0000392 omap_mbox_unregister();
Hiroshi DOYU6c20a682009-03-23 18:07:23 -0700393 iounmap(mbox_base);
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800394 return 0;
395}
396
397static struct platform_driver omap2_mbox_driver = {
398 .probe = omap2_mbox_probe,
Hiroshi DOYUda8cfe02009-03-23 18:07:25 -0700399 .remove = __devexit_p(omap2_mbox_remove),
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800400 .driver = {
Felipe Contrerasd7427092010-06-11 15:51:48 +0000401 .name = "omap-mailbox",
Hiroshi DOYU340a6142006-12-07 15:43:59 -0800402 },
403};
404
405static int __init omap2_mbox_init(void)
406{
407 return platform_driver_register(&omap2_mbox_driver);
408}
409
410static void __exit omap2_mbox_exit(void)
411{
412 platform_driver_unregister(&omap2_mbox_driver);
413}
414
415module_init(omap2_mbox_init);
416module_exit(omap2_mbox_exit);
417
Hiroshi DOYU733ecc52009-03-23 18:07:23 -0700418MODULE_LICENSE("GPL v2");
C A Subramaniam5f00ec62009-11-22 10:11:22 -0800419MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
Ohad Ben-Cohenf3753252010-05-05 15:33:07 +0000420MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
421MODULE_AUTHOR("Paul Mundt");
Felipe Contrerasd7427092010-06-11 15:51:48 +0000422MODULE_ALIAS("platform:omap2-mailbox");