Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Allwinner SoCs hstimer driver. |
| 3 | * |
| 4 | * Copyright (C) 2013 Maxime Ripard |
| 5 | * |
| 6 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/clk.h> |
| 14 | #include <linux/clockchips.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/irq.h> |
| 18 | #include <linux/irqreturn.h> |
Maxime Ripard | e50a00b | 2014-04-17 11:06:45 +0200 | [diff] [blame] | 19 | #include <linux/reset.h> |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 20 | #include <linux/slab.h> |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 21 | #include <linux/of.h> |
| 22 | #include <linux/of_address.h> |
| 23 | #include <linux/of_irq.h> |
| 24 | |
| 25 | #define TIMER_IRQ_EN_REG 0x00 |
| 26 | #define TIMER_IRQ_EN(val) BIT(val) |
| 27 | #define TIMER_IRQ_ST_REG 0x04 |
| 28 | #define TIMER_CTL_REG(val) (0x20 * (val) + 0x10) |
| 29 | #define TIMER_CTL_ENABLE BIT(0) |
| 30 | #define TIMER_CTL_RELOAD BIT(1) |
| 31 | #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) |
| 32 | #define TIMER_CTL_ONESHOT BIT(7) |
| 33 | #define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14) |
| 34 | #define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18) |
| 35 | #define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c) |
| 36 | #define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20) |
| 37 | |
| 38 | #define TIMER_SYNC_TICKS 3 |
| 39 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 40 | struct sun5i_timer { |
| 41 | void __iomem *base; |
| 42 | struct clk *clk; |
| 43 | u32 ticks_per_jiffy; |
| 44 | }; |
| 45 | |
| 46 | struct sun5i_timer_clksrc { |
| 47 | struct sun5i_timer timer; |
| 48 | struct clocksource clksrc; |
| 49 | }; |
| 50 | |
| 51 | #define to_sun5i_timer_clksrc(x) \ |
| 52 | container_of(x, struct sun5i_timer_clksrc, clksrc) |
| 53 | |
| 54 | struct sun5i_timer_clkevt { |
| 55 | struct sun5i_timer timer; |
| 56 | struct clock_event_device clkevt; |
| 57 | }; |
| 58 | |
| 59 | #define to_sun5i_timer_clkevt(x) \ |
| 60 | container_of(x, struct sun5i_timer_clkevt, clkevt) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 61 | |
| 62 | /* |
| 63 | * When we disable a timer, we need to wait at least for 2 cycles of |
| 64 | * the timer source clock. We will use for that the clocksource timer |
| 65 | * that is already setup and runs at the same frequency than the other |
| 66 | * timers, and we never will be disabled. |
| 67 | */ |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 68 | static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 69 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 70 | u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 71 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 72 | while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 73 | cpu_relax(); |
| 74 | } |
| 75 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 76 | static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 77 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 78 | u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); |
| 79 | writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 80 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 81 | sun5i_clkevt_sync(ce); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 82 | } |
| 83 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 84 | static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 85 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 86 | writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 87 | } |
| 88 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 89 | static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 90 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 91 | u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 92 | |
| 93 | if (periodic) |
| 94 | val &= ~TIMER_CTL_ONESHOT; |
| 95 | else |
| 96 | val |= TIMER_CTL_ONESHOT; |
| 97 | |
| 98 | writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 99 | ce->timer.base + TIMER_CTL_REG(timer)); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | static void sun5i_clkevt_mode(enum clock_event_mode mode, |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 103 | struct clock_event_device *clkevt) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 104 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 105 | struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt); |
| 106 | |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 107 | switch (mode) { |
| 108 | case CLOCK_EVT_MODE_PERIODIC: |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 109 | sun5i_clkevt_time_stop(ce, 0); |
| 110 | sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy); |
| 111 | sun5i_clkevt_time_start(ce, 0, true); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 112 | break; |
| 113 | case CLOCK_EVT_MODE_ONESHOT: |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 114 | sun5i_clkevt_time_stop(ce, 0); |
| 115 | sun5i_clkevt_time_start(ce, 0, false); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 116 | break; |
| 117 | case CLOCK_EVT_MODE_UNUSED: |
| 118 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 119 | default: |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 120 | sun5i_clkevt_time_stop(ce, 0); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 121 | break; |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | static int sun5i_clkevt_next_event(unsigned long evt, |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 126 | struct clock_event_device *clkevt) |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 127 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 128 | struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt); |
| 129 | |
| 130 | sun5i_clkevt_time_stop(ce, 0); |
| 131 | sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS); |
| 132 | sun5i_clkevt_time_start(ce, 0, false); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 137 | static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id) |
| 138 | { |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 139 | struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id; |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 140 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 141 | writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG); |
| 142 | ce->clkevt.event_handler(&ce->clkevt); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 143 | |
| 144 | return IRQ_HANDLED; |
| 145 | } |
| 146 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 147 | static cycle_t sun5i_clksrc_read(struct clocksource *clksrc) |
| 148 | { |
| 149 | struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc); |
| 150 | |
| 151 | return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1)); |
| 152 | } |
| 153 | |
| 154 | static int __init sun5i_setup_clocksource(struct device_node *node, |
| 155 | void __iomem *base, |
| 156 | struct clk *clk, int irq) |
| 157 | { |
| 158 | struct sun5i_timer_clksrc *cs; |
| 159 | unsigned long rate; |
| 160 | int ret; |
| 161 | |
| 162 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
| 163 | if (!cs) |
| 164 | return -ENOMEM; |
| 165 | |
| 166 | ret = clk_prepare_enable(clk); |
| 167 | if (ret) { |
| 168 | pr_err("Couldn't enable parent clock\n"); |
| 169 | goto err_free; |
| 170 | } |
| 171 | |
| 172 | rate = clk_get_rate(clk); |
| 173 | |
| 174 | cs->timer.base = base; |
| 175 | cs->timer.clk = clk; |
| 176 | |
| 177 | writel(~0, base + TIMER_INTVAL_LO_REG(1)); |
| 178 | writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, |
| 179 | base + TIMER_CTL_REG(1)); |
| 180 | |
| 181 | cs->clksrc.name = node->name; |
| 182 | cs->clksrc.rating = 340; |
| 183 | cs->clksrc.read = sun5i_clksrc_read; |
| 184 | cs->clksrc.mask = CLOCKSOURCE_MASK(32); |
| 185 | cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
| 186 | |
| 187 | ret = clocksource_register_hz(&cs->clksrc, rate); |
| 188 | if (ret) { |
| 189 | pr_err("Couldn't register clock source.\n"); |
| 190 | goto err_disable_clk; |
| 191 | } |
| 192 | |
| 193 | return 0; |
| 194 | |
| 195 | err_disable_clk: |
| 196 | clk_disable_unprepare(clk); |
| 197 | err_free: |
| 198 | kfree(cs); |
| 199 | return ret; |
| 200 | } |
| 201 | |
| 202 | static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base, |
| 203 | struct clk *clk, int irq) |
| 204 | { |
| 205 | struct sun5i_timer_clkevt *ce; |
| 206 | unsigned long rate; |
| 207 | int ret; |
| 208 | u32 val; |
| 209 | |
| 210 | ce = kzalloc(sizeof(*ce), GFP_KERNEL); |
| 211 | if (!ce) |
| 212 | return -ENOMEM; |
| 213 | |
| 214 | ret = clk_prepare_enable(clk); |
| 215 | if (ret) { |
| 216 | pr_err("Couldn't enable parent clock\n"); |
| 217 | goto err_free; |
| 218 | } |
| 219 | |
| 220 | rate = clk_get_rate(clk); |
| 221 | |
| 222 | ce->timer.base = base; |
| 223 | ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); |
| 224 | ce->timer.clk = clk; |
| 225 | |
| 226 | ce->clkevt.name = node->name; |
| 227 | ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
| 228 | ce->clkevt.set_next_event = sun5i_clkevt_next_event; |
| 229 | ce->clkevt.set_mode = sun5i_clkevt_mode; |
| 230 | ce->clkevt.rating = 340; |
| 231 | ce->clkevt.irq = irq; |
| 232 | ce->clkevt.cpumask = cpu_possible_mask; |
| 233 | |
| 234 | /* Enable timer0 interrupt */ |
| 235 | val = readl(base + TIMER_IRQ_EN_REG); |
| 236 | writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG); |
| 237 | |
| 238 | clockevents_config_and_register(&ce->clkevt, rate, |
| 239 | TIMER_SYNC_TICKS, 0xffffffff); |
| 240 | |
| 241 | ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, |
| 242 | "sun5i_timer0", ce); |
| 243 | if (ret) { |
| 244 | pr_err("Unable to register interrupt\n"); |
| 245 | goto err_disable_clk; |
| 246 | } |
| 247 | |
| 248 | return 0; |
| 249 | |
| 250 | err_disable_clk: |
| 251 | clk_disable_unprepare(clk); |
| 252 | err_free: |
| 253 | kfree(ce); |
| 254 | return ret; |
| 255 | } |
| 256 | |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 257 | static void __init sun5i_timer_init(struct device_node *node) |
| 258 | { |
Maxime Ripard | e50a00b | 2014-04-17 11:06:45 +0200 | [diff] [blame] | 259 | struct reset_control *rstc; |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 260 | void __iomem *timer_base; |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 261 | struct clk *clk; |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 262 | int irq; |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 263 | |
Maxime Ripard | a45860d | 2015-03-31 12:12:24 +0200 | [diff] [blame] | 264 | timer_base = of_io_request_and_map(node, 0, of_node_full_name(node)); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 265 | if (!timer_base) |
| 266 | panic("Can't map registers"); |
| 267 | |
| 268 | irq = irq_of_parse_and_map(node, 0); |
| 269 | if (irq <= 0) |
| 270 | panic("Can't parse IRQ"); |
| 271 | |
| 272 | clk = of_clk_get(node, 0); |
| 273 | if (IS_ERR(clk)) |
| 274 | panic("Can't get timer clock"); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 275 | |
Maxime Ripard | e50a00b | 2014-04-17 11:06:45 +0200 | [diff] [blame] | 276 | rstc = of_reset_control_get(node, NULL); |
| 277 | if (!IS_ERR(rstc)) |
| 278 | reset_control_deassert(rstc); |
| 279 | |
Maxime Ripard | 4a59058 | 2015-03-31 12:12:25 +0200 | [diff] [blame^] | 280 | sun5i_setup_clocksource(node, timer_base, clk, irq); |
| 281 | sun5i_setup_clockevent(node, timer_base, clk, irq); |
Maxime Ripard | 6790554 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 282 | } |
| 283 | CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer", |
| 284 | sun5i_timer_init); |
| 285 | CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer", |
| 286 | sun5i_timer_init); |