Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
Maxime Ripard | 394c56c | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 6 | * This file is dual-licensed: you can use it either under the terms |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual |
| 8 | * licensing only applies to this file, and not this project as a |
| 9 | * whole. |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 10 | * |
Maxime Ripard | 5186d83 | 2014-10-17 11:38:23 +0200 | [diff] [blame] | 11 | * a) This file is free software; you can redistribute it and/or |
Maxime Ripard | 394c56c | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of the |
| 14 | * License, or (at your option) any later version. |
| 15 | * |
Maxime Ripard | 5186d83 | 2014-10-17 11:38:23 +0200 | [diff] [blame] | 16 | * This file is distributed in the hope that it will be useful, |
Maxime Ripard | 394c56c | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public |
Maxime Ripard | 5186d83 | 2014-10-17 11:38:23 +0200 | [diff] [blame] | 22 | * License along with this file; if not, write to the Free |
Maxime Ripard | 394c56c | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 24 | * MA 02110-1301 USA |
| 25 | * |
| 26 | * Or, alternatively, |
| 27 | * |
| 28 | * b) Permission is hereby granted, free of charge, to any person |
| 29 | * obtaining a copy of this software and associated documentation |
| 30 | * files (the "Software"), to deal in the Software without |
| 31 | * restriction, including without limitation the rights to use, |
| 32 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 33 | * sell copies of the Software, and to permit persons to whom the |
| 34 | * Software is furnished to do so, subject to the following |
| 35 | * conditions: |
| 36 | * |
| 37 | * The above copyright notice and this permission notice shall be |
| 38 | * included in all copies or substantial portions of the Software. |
| 39 | * |
| 40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 47 | * OTHER DEALINGS IN THE SOFTWARE. |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 48 | */ |
| 49 | |
Maxime Ripard | 7145570 | 2014-12-16 22:59:54 +0100 | [diff] [blame] | 50 | #include "skeleton.dtsi" |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 51 | |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 52 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Chen-Yu Tsai | b6d3424 | 2015-01-12 12:34:03 +0800 | [diff] [blame] | 53 | #include <dt-bindings/thermal/thermal.h> |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 54 | |
Maxime Ripard | 1f9f6a7 | 2014-12-16 22:59:56 +0100 | [diff] [blame] | 55 | #include <dt-bindings/dma/sun4i-a10.h> |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 56 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 57 | |
| 58 | / { |
| 59 | interrupt-parent = <&gic>; |
| 60 | |
Emilio López | e751cce | 2013-11-16 15:17:29 -0300 | [diff] [blame] | 61 | aliases { |
Chen-Yu Tsai | 18428f7 | 2014-02-10 18:35:54 +0800 | [diff] [blame] | 62 | ethernet0 = &gmac; |
Emilio López | e751cce | 2013-11-16 15:17:29 -0300 | [diff] [blame] | 63 | }; |
| 64 | |
Hans de Goede | 8efc5c2 | 2014-11-14 16:34:37 +0100 | [diff] [blame] | 65 | chosen { |
| 66 | #address-cells = <1>; |
| 67 | #size-cells = <1>; |
| 68 | ranges; |
| 69 | |
Hans de Goede | a9f8cda | 2014-11-18 12:07:13 +0100 | [diff] [blame] | 70 | framebuffer@0 { |
| 71 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; |
| 72 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
Hans de Goede | 678e75d | 2014-11-16 17:09:32 +0100 | [diff] [blame] | 73 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
| 74 | <&ahb_gates 44>; |
Hans de Goede | 8efc5c2 | 2014-11-14 16:34:37 +0100 | [diff] [blame] | 75 | status = "disabled"; |
| 76 | }; |
Hans de Goede | fd18c7e | 2015-01-19 14:05:12 +0100 | [diff] [blame] | 77 | |
| 78 | framebuffer@1 { |
| 79 | compatible = "allwinner,simple-framebuffer", |
| 80 | "simple-framebuffer"; |
| 81 | allwinner,pipeline = "de_be0-lcd0"; |
| 82 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; |
| 83 | status = "disabled"; |
| 84 | }; |
| 85 | |
| 86 | framebuffer@2 { |
| 87 | compatible = "allwinner,simple-framebuffer", |
| 88 | "simple-framebuffer"; |
| 89 | allwinner,pipeline = "de_be0-lcd0-tve0"; |
| 90 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, |
| 91 | <&ahb_gates 44>; |
| 92 | status = "disabled"; |
| 93 | }; |
Hans de Goede | 8efc5c2 | 2014-11-14 16:34:37 +0100 | [diff] [blame] | 94 | }; |
| 95 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 96 | cpus { |
| 97 | #address-cells = <1>; |
| 98 | #size-cells = <0>; |
| 99 | |
Chen-Yu Tsai | d96b716 | 2015-01-06 10:35:16 +0800 | [diff] [blame] | 100 | cpu0: cpu@0 { |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 101 | compatible = "arm,cortex-a7"; |
| 102 | device_type = "cpu"; |
| 103 | reg = <0>; |
Chen-Yu Tsai | d96b716 | 2015-01-06 10:35:16 +0800 | [diff] [blame] | 104 | clocks = <&cpu>; |
| 105 | clock-latency = <244144>; /* 8 32k periods */ |
| 106 | operating-points = < |
| 107 | /* kHz uV */ |
| 108 | 1008000 1450000 |
| 109 | 960000 1400000 |
| 110 | 912000 1400000 |
| 111 | 864000 1300000 |
| 112 | 720000 1200000 |
| 113 | 528000 1100000 |
| 114 | 312000 1000000 |
| 115 | 144000 900000 |
| 116 | >; |
| 117 | #cooling-cells = <2>; |
| 118 | cooling-min-level = <0>; |
| 119 | cooling-max-level = <7>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 120 | }; |
| 121 | |
| 122 | cpu@1 { |
| 123 | compatible = "arm,cortex-a7"; |
| 124 | device_type = "cpu"; |
| 125 | reg = <1>; |
| 126 | }; |
| 127 | }; |
| 128 | |
Chen-Yu Tsai | b6d3424 | 2015-01-12 12:34:03 +0800 | [diff] [blame] | 129 | thermal-zones { |
| 130 | cpu_thermal { |
| 131 | /* milliseconds */ |
| 132 | polling-delay-passive = <250>; |
| 133 | polling-delay = <1000>; |
| 134 | thermal-sensors = <&rtp>; |
| 135 | |
| 136 | cooling-maps { |
| 137 | map0 { |
| 138 | trip = <&cpu_alert0>; |
| 139 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| 140 | }; |
| 141 | }; |
| 142 | |
| 143 | trips { |
| 144 | cpu_alert0: cpu_alert0 { |
| 145 | /* milliCelsius */ |
| 146 | temperature = <75000>; |
| 147 | hysteresis = <2000>; |
| 148 | type = "passive"; |
| 149 | }; |
| 150 | |
| 151 | cpu_crit: cpu_crit { |
| 152 | /* milliCelsius */ |
| 153 | temperature = <100000>; |
| 154 | hysteresis = <2000>; |
| 155 | type = "critical"; |
| 156 | }; |
| 157 | }; |
| 158 | }; |
| 159 | }; |
| 160 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 161 | memory { |
| 162 | reg = <0x40000000 0x80000000>; |
| 163 | }; |
| 164 | |
Marc Zyngier | 7902763 | 2014-02-18 14:04:44 +0000 | [diff] [blame] | 165 | timer { |
| 166 | compatible = "arm,armv7-timer"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 167 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 168 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 169 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 170 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 7902763 | 2014-02-18 14:04:44 +0000 | [diff] [blame] | 171 | }; |
| 172 | |
Maxime Ripard | e29ea4d | 2014-04-17 21:54:41 +0200 | [diff] [blame] | 173 | pmu { |
| 174 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 175 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 176 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | e29ea4d | 2014-04-17 21:54:41 +0200 | [diff] [blame] | 177 | }; |
| 178 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 179 | clocks { |
| 180 | #address-cells = <1>; |
| 181 | #size-cells = <1>; |
| 182 | ranges; |
| 183 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 184 | osc24M: clk@01c20050 { |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 185 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 186 | compatible = "allwinner,sun4i-a10-osc-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 187 | reg = <0x01c20050 0x4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 188 | clock-frequency = <24000000>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 189 | clock-output-names = "osc24M"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 190 | }; |
| 191 | |
Chen-Yu Tsai | 673fac7 | 2014-01-01 10:30:47 +0800 | [diff] [blame] | 192 | osc32k: clk@0 { |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 193 | #clock-cells = <0>; |
| 194 | compatible = "fixed-clock"; |
| 195 | clock-frequency = <32768>; |
Chen-Yu Tsai | 673fac7 | 2014-01-01 10:30:47 +0800 | [diff] [blame] | 196 | clock-output-names = "osc32k"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 197 | }; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 198 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 199 | pll1: clk@01c20000 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 200 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 201 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 202 | reg = <0x01c20000 0x4>; |
| 203 | clocks = <&osc24M>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 204 | clock-output-names = "pll1"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 205 | }; |
| 206 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 207 | pll4: clk@01c20018 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 208 | #clock-cells = <0>; |
Emilio López | 04ebcb5 | 2014-03-19 15:19:31 -0300 | [diff] [blame] | 209 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 210 | reg = <0x01c20018 0x4>; |
| 211 | clocks = <&osc24M>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 212 | clock-output-names = "pll4"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 213 | }; |
| 214 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 215 | pll5: clk@01c20020 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 216 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 217 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 218 | reg = <0x01c20020 0x4>; |
| 219 | clocks = <&osc24M>; |
| 220 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 221 | }; |
| 222 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 223 | pll6: clk@01c20028 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 224 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 225 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 226 | reg = <0x01c20028 0x4>; |
| 227 | clocks = <&osc24M>; |
| 228 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 229 | }; |
| 230 | |
Emilio López | 04ebcb5 | 2014-03-19 15:19:31 -0300 | [diff] [blame] | 231 | pll8: clk@01c20040 { |
| 232 | #clock-cells = <0>; |
| 233 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
| 234 | reg = <0x01c20040 0x4>; |
| 235 | clocks = <&osc24M>; |
| 236 | clock-output-names = "pll8"; |
| 237 | }; |
| 238 | |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 239 | cpu: cpu@01c20054 { |
| 240 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 241 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 242 | reg = <0x01c20054 0x4>; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 243 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 244 | clock-output-names = "cpu"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | axi: axi@01c20054 { |
| 248 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 249 | compatible = "allwinner,sun4i-a10-axi-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 250 | reg = <0x01c20054 0x4>; |
| 251 | clocks = <&cpu>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 252 | clock-output-names = "axi"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | ahb: ahb@01c20054 { |
| 256 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 257 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 258 | reg = <0x01c20054 0x4>; |
| 259 | clocks = <&axi>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 260 | clock-output-names = "ahb"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 261 | }; |
| 262 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 263 | ahb_gates: clk@01c20060 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 264 | #clock-cells = <1>; |
| 265 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; |
| 266 | reg = <0x01c20060 0x8>; |
| 267 | clocks = <&ahb>; |
| 268 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
| 269 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", |
| 270 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| 271 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", |
| 272 | "ahb_nand", "ahb_sdram", "ahb_ace", |
| 273 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", |
| 274 | "ahb_spi2", "ahb_spi3", "ahb_sata", |
| 275 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", |
| 276 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", |
| 277 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", |
| 278 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", |
| 279 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", |
| 280 | "ahb_mali"; |
| 281 | }; |
| 282 | |
| 283 | apb0: apb0@01c20054 { |
| 284 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 285 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 286 | reg = <0x01c20054 0x4>; |
| 287 | clocks = <&ahb>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 288 | clock-output-names = "apb0"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 289 | }; |
| 290 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 291 | apb0_gates: clk@01c20068 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 292 | #clock-cells = <1>; |
| 293 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; |
| 294 | reg = <0x01c20068 0x4>; |
| 295 | clocks = <&apb0>; |
| 296 | clock-output-names = "apb0_codec", "apb0_spdif", |
| 297 | "apb0_ac97", "apb0_iis0", "apb0_iis1", |
| 298 | "apb0_pio", "apb0_ir0", "apb0_ir1", |
| 299 | "apb0_iis2", "apb0_keypad"; |
| 300 | }; |
| 301 | |
Emilio López | acbcc0f | 2014-11-06 11:40:30 +0800 | [diff] [blame] | 302 | apb1: clk@01c20058 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 303 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 304 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 305 | reg = <0x01c20058 0x4>; |
Emilio López | acbcc0f | 2014-11-06 11:40:30 +0800 | [diff] [blame] | 306 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 307 | clock-output-names = "apb1"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 308 | }; |
| 309 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 310 | apb1_gates: clk@01c2006c { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 311 | #clock-cells = <1>; |
| 312 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; |
| 313 | reg = <0x01c2006c 0x4>; |
| 314 | clocks = <&apb1>; |
| 315 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| 316 | "apb1_i2c2", "apb1_i2c3", "apb1_can", |
| 317 | "apb1_scr", "apb1_ps20", "apb1_ps21", |
| 318 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", |
| 319 | "apb1_uart2", "apb1_uart3", "apb1_uart4", |
| 320 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; |
| 321 | }; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 322 | |
| 323 | nand_clk: clk@01c20080 { |
| 324 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 325 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 326 | reg = <0x01c20080 0x4>; |
| 327 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 328 | clock-output-names = "nand"; |
| 329 | }; |
| 330 | |
| 331 | ms_clk: clk@01c20084 { |
| 332 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 333 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 334 | reg = <0x01c20084 0x4>; |
| 335 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 336 | clock-output-names = "ms"; |
| 337 | }; |
| 338 | |
| 339 | mmc0_clk: clk@01c20088 { |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 340 | #clock-cells = <1>; |
| 341 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 342 | reg = <0x01c20088 0x4>; |
| 343 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 344 | clock-output-names = "mmc0", |
| 345 | "mmc0_output", |
| 346 | "mmc0_sample"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 347 | }; |
| 348 | |
| 349 | mmc1_clk: clk@01c2008c { |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 350 | #clock-cells = <1>; |
| 351 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 352 | reg = <0x01c2008c 0x4>; |
| 353 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 354 | clock-output-names = "mmc1", |
| 355 | "mmc1_output", |
| 356 | "mmc1_sample"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | mmc2_clk: clk@01c20090 { |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 360 | #clock-cells = <1>; |
| 361 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 362 | reg = <0x01c20090 0x4>; |
| 363 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 364 | clock-output-names = "mmc2", |
| 365 | "mmc2_output", |
| 366 | "mmc2_sample"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 367 | }; |
| 368 | |
| 369 | mmc3_clk: clk@01c20094 { |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 370 | #clock-cells = <1>; |
| 371 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 372 | reg = <0x01c20094 0x4>; |
| 373 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 374 | clock-output-names = "mmc3", |
| 375 | "mmc3_output", |
| 376 | "mmc3_sample"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 377 | }; |
| 378 | |
| 379 | ts_clk: clk@01c20098 { |
| 380 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 381 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 382 | reg = <0x01c20098 0x4>; |
| 383 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 384 | clock-output-names = "ts"; |
| 385 | }; |
| 386 | |
| 387 | ss_clk: clk@01c2009c { |
| 388 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 389 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 390 | reg = <0x01c2009c 0x4>; |
| 391 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 392 | clock-output-names = "ss"; |
| 393 | }; |
| 394 | |
| 395 | spi0_clk: clk@01c200a0 { |
| 396 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 397 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 398 | reg = <0x01c200a0 0x4>; |
| 399 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 400 | clock-output-names = "spi0"; |
| 401 | }; |
| 402 | |
| 403 | spi1_clk: clk@01c200a4 { |
| 404 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 405 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 406 | reg = <0x01c200a4 0x4>; |
| 407 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 408 | clock-output-names = "spi1"; |
| 409 | }; |
| 410 | |
| 411 | spi2_clk: clk@01c200a8 { |
| 412 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 413 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 414 | reg = <0x01c200a8 0x4>; |
| 415 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 416 | clock-output-names = "spi2"; |
| 417 | }; |
| 418 | |
| 419 | pata_clk: clk@01c200ac { |
| 420 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 421 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 422 | reg = <0x01c200ac 0x4>; |
| 423 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 424 | clock-output-names = "pata"; |
| 425 | }; |
| 426 | |
| 427 | ir0_clk: clk@01c200b0 { |
| 428 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 429 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 430 | reg = <0x01c200b0 0x4>; |
| 431 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 432 | clock-output-names = "ir0"; |
| 433 | }; |
| 434 | |
| 435 | ir1_clk: clk@01c200b4 { |
| 436 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 437 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 438 | reg = <0x01c200b4 0x4>; |
| 439 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 440 | clock-output-names = "ir1"; |
| 441 | }; |
| 442 | |
Roman Byshko | 434e41b | 2014-02-07 16:21:53 +0100 | [diff] [blame] | 443 | usb_clk: clk@01c200cc { |
| 444 | #clock-cells = <1>; |
| 445 | #reset-cells = <1>; |
| 446 | compatible = "allwinner,sun4i-a10-usb-clk"; |
| 447 | reg = <0x01c200cc 0x4>; |
| 448 | clocks = <&pll6 1>; |
| 449 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; |
| 450 | }; |
| 451 | |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 452 | spi3_clk: clk@01c200d4 { |
| 453 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 454 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 455 | reg = <0x01c200d4 0x4>; |
| 456 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 457 | clock-output-names = "spi3"; |
| 458 | }; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 459 | |
| 460 | mbus_clk: clk@01c2015c { |
| 461 | #clock-cells = <0>; |
Maxime Ripard | 7868c5e | 2014-07-16 23:45:48 +0200 | [diff] [blame] | 462 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 463 | reg = <0x01c2015c 0x4>; |
| 464 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; |
| 465 | clock-output-names = "mbus"; |
| 466 | }; |
Chen-Yu Tsai | 0aff037 | 2014-01-01 10:30:48 +0800 | [diff] [blame] | 467 | |
| 468 | /* |
Chen-Yu Tsai | daed5a8 | 2014-02-10 18:35:48 +0800 | [diff] [blame] | 469 | * The following two are dummy clocks, placeholders used in the gmac_tx |
| 470 | * clock. The gmac driver will choose one parent depending on the PHY |
| 471 | * interface mode, using clk_set_rate auto-reparenting. |
| 472 | * The actual TX clock rate is not controlled by the gmac_tx clock. |
| 473 | */ |
| 474 | mii_phy_tx_clk: clk@2 { |
| 475 | #clock-cells = <0>; |
| 476 | compatible = "fixed-clock"; |
| 477 | clock-frequency = <25000000>; |
| 478 | clock-output-names = "mii_phy_tx"; |
| 479 | }; |
| 480 | |
| 481 | gmac_int_tx_clk: clk@3 { |
| 482 | #clock-cells = <0>; |
| 483 | compatible = "fixed-clock"; |
| 484 | clock-frequency = <125000000>; |
| 485 | clock-output-names = "gmac_int_tx"; |
| 486 | }; |
| 487 | |
| 488 | gmac_tx_clk: clk@01c20164 { |
| 489 | #clock-cells = <0>; |
| 490 | compatible = "allwinner,sun7i-a20-gmac-clk"; |
| 491 | reg = <0x01c20164 0x4>; |
| 492 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; |
| 493 | clock-output-names = "gmac_tx"; |
| 494 | }; |
| 495 | |
| 496 | /* |
Chen-Yu Tsai | 0aff037 | 2014-01-01 10:30:48 +0800 | [diff] [blame] | 497 | * Dummy clock used by output clocks |
| 498 | */ |
| 499 | osc24M_32k: clk@1 { |
| 500 | #clock-cells = <0>; |
| 501 | compatible = "fixed-factor-clock"; |
| 502 | clock-div = <750>; |
| 503 | clock-mult = <1>; |
| 504 | clocks = <&osc24M>; |
| 505 | clock-output-names = "osc24M_32k"; |
| 506 | }; |
| 507 | |
| 508 | clk_out_a: clk@01c201f0 { |
| 509 | #clock-cells = <0>; |
| 510 | compatible = "allwinner,sun7i-a20-out-clk"; |
| 511 | reg = <0x01c201f0 0x4>; |
| 512 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; |
| 513 | clock-output-names = "clk_out_a"; |
| 514 | }; |
| 515 | |
| 516 | clk_out_b: clk@01c201f4 { |
| 517 | #clock-cells = <0>; |
| 518 | compatible = "allwinner,sun7i-a20-out-clk"; |
| 519 | reg = <0x01c201f4 0x4>; |
| 520 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; |
| 521 | clock-output-names = "clk_out_b"; |
| 522 | }; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 523 | }; |
| 524 | |
| 525 | soc@01c00000 { |
| 526 | compatible = "simple-bus"; |
| 527 | #address-cells = <1>; |
| 528 | #size-cells = <1>; |
| 529 | ranges; |
| 530 | |
Carlo Caione | 8ff973a | 2014-03-19 20:21:18 +0100 | [diff] [blame] | 531 | nmi_intc: interrupt-controller@01c00030 { |
| 532 | compatible = "allwinner,sun7i-a20-sc-nmi"; |
| 533 | interrupt-controller; |
| 534 | #interrupt-cells = <2>; |
| 535 | reg = <0x01c00030 0x0c>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 536 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
Carlo Caione | 8ff973a | 2014-03-19 20:21:18 +0100 | [diff] [blame] | 537 | }; |
| 538 | |
Emilio López | 316e0b0 | 2014-08-04 17:09:59 -0300 | [diff] [blame] | 539 | dma: dma-controller@01c02000 { |
| 540 | compatible = "allwinner,sun4i-a10-dma"; |
| 541 | reg = <0x01c02000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 542 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
Emilio López | 316e0b0 | 2014-08-04 17:09:59 -0300 | [diff] [blame] | 543 | clocks = <&ahb_gates 6>; |
| 544 | #dma-cells = <2>; |
| 545 | }; |
| 546 | |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 547 | spi0: spi@01c05000 { |
| 548 | compatible = "allwinner,sun4i-a10-spi"; |
| 549 | reg = <0x01c05000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 550 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 551 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
| 552 | clock-names = "ahb", "mod"; |
Maxime Ripard | 1f9f6a7 | 2014-12-16 22:59:56 +0100 | [diff] [blame] | 553 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
| 554 | <&dma SUN4I_DMA_DEDICATED 26>; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 555 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 556 | status = "disabled"; |
| 557 | #address-cells = <1>; |
| 558 | #size-cells = <0>; |
| 559 | }; |
| 560 | |
| 561 | spi1: spi@01c06000 { |
| 562 | compatible = "allwinner,sun4i-a10-spi"; |
| 563 | reg = <0x01c06000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 564 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 565 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
| 566 | clock-names = "ahb", "mod"; |
Maxime Ripard | 1f9f6a7 | 2014-12-16 22:59:56 +0100 | [diff] [blame] | 567 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
| 568 | <&dma SUN4I_DMA_DEDICATED 8>; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 569 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 570 | status = "disabled"; |
| 571 | #address-cells = <1>; |
| 572 | #size-cells = <0>; |
| 573 | }; |
| 574 | |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 575 | emac: ethernet@01c0b000 { |
Maxime Ripard | 1c70e09 | 2014-02-02 14:49:13 +0100 | [diff] [blame] | 576 | compatible = "allwinner,sun4i-a10-emac"; |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 577 | reg = <0x01c0b000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 578 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 579 | clocks = <&ahb_gates 17>; |
| 580 | status = "disabled"; |
| 581 | }; |
| 582 | |
Aleksei Mamlin | 92395f5 | 2015-01-19 22:35:22 +0300 | [diff] [blame] | 583 | mdio: mdio@01c0b080 { |
Maxime Ripard | 1c70e09 | 2014-02-02 14:49:13 +0100 | [diff] [blame] | 584 | compatible = "allwinner,sun4i-a10-mdio"; |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 585 | reg = <0x01c0b080 0x14>; |
| 586 | status = "disabled"; |
| 587 | #address-cells = <1>; |
| 588 | #size-cells = <0>; |
| 589 | }; |
| 590 | |
Hans de Goede | dd29ce5 | 2014-05-02 17:57:26 +0200 | [diff] [blame] | 591 | mmc0: mmc@01c0f000 { |
| 592 | compatible = "allwinner,sun5i-a13-mmc"; |
| 593 | reg = <0x01c0f000 0x1000>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 594 | clocks = <&ahb_gates 8>, |
| 595 | <&mmc0_clk 0>, |
| 596 | <&mmc0_clk 1>, |
| 597 | <&mmc0_clk 2>; |
| 598 | clock-names = "ahb", |
| 599 | "mmc", |
| 600 | "output", |
| 601 | "sample"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 602 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | dd29ce5 | 2014-05-02 17:57:26 +0200 | [diff] [blame] | 603 | status = "disabled"; |
| 604 | }; |
| 605 | |
| 606 | mmc1: mmc@01c10000 { |
| 607 | compatible = "allwinner,sun5i-a13-mmc"; |
| 608 | reg = <0x01c10000 0x1000>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 609 | clocks = <&ahb_gates 9>, |
| 610 | <&mmc1_clk 0>, |
| 611 | <&mmc1_clk 1>, |
| 612 | <&mmc1_clk 2>; |
| 613 | clock-names = "ahb", |
| 614 | "mmc", |
| 615 | "output", |
| 616 | "sample"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 617 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | dd29ce5 | 2014-05-02 17:57:26 +0200 | [diff] [blame] | 618 | status = "disabled"; |
| 619 | }; |
| 620 | |
| 621 | mmc2: mmc@01c11000 { |
| 622 | compatible = "allwinner,sun5i-a13-mmc"; |
| 623 | reg = <0x01c11000 0x1000>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 624 | clocks = <&ahb_gates 10>, |
| 625 | <&mmc2_clk 0>, |
| 626 | <&mmc2_clk 1>, |
| 627 | <&mmc2_clk 2>; |
| 628 | clock-names = "ahb", |
| 629 | "mmc", |
| 630 | "output", |
| 631 | "sample"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 632 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | dd29ce5 | 2014-05-02 17:57:26 +0200 | [diff] [blame] | 633 | status = "disabled"; |
| 634 | }; |
| 635 | |
| 636 | mmc3: mmc@01c12000 { |
| 637 | compatible = "allwinner,sun5i-a13-mmc"; |
| 638 | reg = <0x01c12000 0x1000>; |
Maxime Ripard | d8c3a39 | 2014-07-11 19:39:06 +0200 | [diff] [blame] | 639 | clocks = <&ahb_gates 11>, |
| 640 | <&mmc3_clk 0>, |
| 641 | <&mmc3_clk 1>, |
| 642 | <&mmc3_clk 2>; |
| 643 | clock-names = "ahb", |
| 644 | "mmc", |
| 645 | "output", |
| 646 | "sample"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 647 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | dd29ce5 | 2014-05-02 17:57:26 +0200 | [diff] [blame] | 648 | status = "disabled"; |
| 649 | }; |
| 650 | |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 651 | usbphy: phy@01c13400 { |
| 652 | #phy-cells = <1>; |
| 653 | compatible = "allwinner,sun7i-a20-usb-phy"; |
| 654 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; |
| 655 | reg-names = "phy_ctrl", "pmu1", "pmu2"; |
| 656 | clocks = <&usb_clk 8>; |
| 657 | clock-names = "usb_phy"; |
Roman Byshko | 134c60a | 2014-11-10 19:55:08 +0100 | [diff] [blame] | 658 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
| 659 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 660 | status = "disabled"; |
| 661 | }; |
| 662 | |
| 663 | ehci0: usb@01c14000 { |
| 664 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; |
| 665 | reg = <0x01c14000 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 666 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 667 | clocks = <&ahb_gates 1>; |
| 668 | phys = <&usbphy 1>; |
| 669 | phy-names = "usb"; |
| 670 | status = "disabled"; |
| 671 | }; |
| 672 | |
| 673 | ohci0: usb@01c14400 { |
| 674 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; |
| 675 | reg = <0x01c14400 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 676 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 677 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
| 678 | phys = <&usbphy 1>; |
| 679 | phy-names = "usb"; |
| 680 | status = "disabled"; |
| 681 | }; |
| 682 | |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 683 | spi2: spi@01c17000 { |
| 684 | compatible = "allwinner,sun4i-a10-spi"; |
| 685 | reg = <0x01c17000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 686 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 687 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
| 688 | clock-names = "ahb", "mod"; |
Maxime Ripard | 1f9f6a7 | 2014-12-16 22:59:56 +0100 | [diff] [blame] | 689 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
| 690 | <&dma SUN4I_DMA_DEDICATED 28>; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 691 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 692 | status = "disabled"; |
| 693 | #address-cells = <1>; |
| 694 | #size-cells = <0>; |
| 695 | }; |
| 696 | |
Hans de Goede | 902febf | 2014-03-01 20:26:22 +0100 | [diff] [blame] | 697 | ahci: sata@01c18000 { |
| 698 | compatible = "allwinner,sun4i-a10-ahci"; |
| 699 | reg = <0x01c18000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 700 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | 902febf | 2014-03-01 20:26:22 +0100 | [diff] [blame] | 701 | clocks = <&pll6 0>, <&ahb_gates 25>; |
| 702 | status = "disabled"; |
| 703 | }; |
| 704 | |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 705 | ehci1: usb@01c1c000 { |
| 706 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; |
| 707 | reg = <0x01c1c000 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 708 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 709 | clocks = <&ahb_gates 3>; |
| 710 | phys = <&usbphy 2>; |
| 711 | phy-names = "usb"; |
| 712 | status = "disabled"; |
| 713 | }; |
| 714 | |
| 715 | ohci1: usb@01c1c400 { |
| 716 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; |
| 717 | reg = <0x01c1c400 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 718 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 719 | clocks = <&usb_clk 7>, <&ahb_gates 4>; |
| 720 | phys = <&usbphy 2>; |
| 721 | phy-names = "usb"; |
| 722 | status = "disabled"; |
| 723 | }; |
| 724 | |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 725 | spi3: spi@01c1f000 { |
| 726 | compatible = "allwinner,sun4i-a10-spi"; |
| 727 | reg = <0x01c1f000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 728 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 729 | clocks = <&ahb_gates 23>, <&spi3_clk>; |
| 730 | clock-names = "ahb", "mod"; |
Maxime Ripard | 1f9f6a7 | 2014-12-16 22:59:56 +0100 | [diff] [blame] | 731 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
| 732 | <&dma SUN4I_DMA_DEDICATED 30>; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 733 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 734 | status = "disabled"; |
| 735 | #address-cells = <1>; |
| 736 | #size-cells = <0>; |
| 737 | }; |
| 738 | |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 739 | pio: pinctrl@01c20800 { |
| 740 | compatible = "allwinner,sun7i-a20-pinctrl"; |
| 741 | reg = <0x01c20800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 742 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 743 | clocks = <&apb0_gates 5>; |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 744 | gpio-controller; |
| 745 | interrupt-controller; |
Chen-Yu Tsai | 7d4ff96 | 2014-06-30 23:57:51 +0200 | [diff] [blame] | 746 | #interrupt-cells = <2>; |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 747 | #size-cells = <0>; |
| 748 | #gpio-cells = <3>; |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 749 | |
Alexandre Belloni | fd7898a | 2014-04-28 18:17:12 +0200 | [diff] [blame] | 750 | pwm0_pins_a: pwm0@0 { |
| 751 | allwinner,pins = "PB2"; |
| 752 | allwinner,function = "pwm"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 753 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 754 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Alexandre Belloni | fd7898a | 2014-04-28 18:17:12 +0200 | [diff] [blame] | 755 | }; |
| 756 | |
| 757 | pwm1_pins_a: pwm1@0 { |
| 758 | allwinner,pins = "PI3"; |
| 759 | allwinner,function = "pwm"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 760 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 761 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Alexandre Belloni | fd7898a | 2014-04-28 18:17:12 +0200 | [diff] [blame] | 762 | }; |
| 763 | |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 764 | uart0_pins_a: uart0@0 { |
| 765 | allwinner,pins = "PB22", "PB23"; |
| 766 | allwinner,function = "uart0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 767 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 768 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 769 | }; |
| 770 | |
Chen-Yu Tsai | 4261ec4 | 2014-01-14 22:49:50 +0800 | [diff] [blame] | 771 | uart2_pins_a: uart2@0 { |
| 772 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; |
| 773 | allwinner,function = "uart2"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 774 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 775 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | 4261ec4 | 2014-01-14 22:49:50 +0800 | [diff] [blame] | 776 | }; |
| 777 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 778 | uart3_pins_a: uart3@0 { |
| 779 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; |
| 780 | allwinner,function = "uart3"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 781 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 782 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 783 | }; |
| 784 | |
Hans de Goede | 0510e4b | 2014-10-01 09:26:05 +0200 | [diff] [blame] | 785 | uart3_pins_b: uart3@1 { |
| 786 | allwinner,pins = "PH0", "PH1"; |
| 787 | allwinner,function = "uart3"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 788 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 789 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Hans de Goede | 0510e4b | 2014-10-01 09:26:05 +0200 | [diff] [blame] | 790 | }; |
| 791 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 792 | uart4_pins_a: uart4@0 { |
| 793 | allwinner,pins = "PG10", "PG11"; |
| 794 | allwinner,function = "uart4"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 795 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 796 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 797 | }; |
| 798 | |
| 799 | uart5_pins_a: uart5@0 { |
| 800 | allwinner,pins = "PI10", "PI11"; |
| 801 | allwinner,function = "uart5"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 802 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 803 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 804 | }; |
| 805 | |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 806 | uart6_pins_a: uart6@0 { |
| 807 | allwinner,pins = "PI12", "PI13"; |
| 808 | allwinner,function = "uart6"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 809 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 810 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 811 | }; |
| 812 | |
| 813 | uart7_pins_a: uart7@0 { |
| 814 | allwinner,pins = "PI20", "PI21"; |
| 815 | allwinner,function = "uart7"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 816 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 817 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 818 | }; |
Maxime Ripard | 756084c | 2013-09-11 11:10:07 +0200 | [diff] [blame] | 819 | |
Maxime Ripard | e5496a3 | 2013-08-31 23:08:49 +0200 | [diff] [blame] | 820 | i2c0_pins_a: i2c0@0 { |
| 821 | allwinner,pins = "PB0", "PB1"; |
| 822 | allwinner,function = "i2c0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 823 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 824 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | e5496a3 | 2013-08-31 23:08:49 +0200 | [diff] [blame] | 825 | }; |
| 826 | |
| 827 | i2c1_pins_a: i2c1@0 { |
| 828 | allwinner,pins = "PB18", "PB19"; |
| 829 | allwinner,function = "i2c1"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 830 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 831 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | e5496a3 | 2013-08-31 23:08:49 +0200 | [diff] [blame] | 832 | }; |
| 833 | |
| 834 | i2c2_pins_a: i2c2@0 { |
| 835 | allwinner,pins = "PB20", "PB21"; |
| 836 | allwinner,function = "i2c2"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 837 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 838 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | e5496a3 | 2013-08-31 23:08:49 +0200 | [diff] [blame] | 839 | }; |
| 840 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 841 | i2c3_pins_a: i2c3@0 { |
| 842 | allwinner,pins = "PI0", "PI1"; |
| 843 | allwinner,function = "i2c3"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 844 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 845 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 846 | }; |
| 847 | |
Maxime Ripard | 756084c | 2013-09-11 11:10:07 +0200 | [diff] [blame] | 848 | emac_pins_a: emac0@0 { |
| 849 | allwinner,pins = "PA0", "PA1", "PA2", |
| 850 | "PA3", "PA4", "PA5", "PA6", |
| 851 | "PA7", "PA8", "PA9", "PA10", |
| 852 | "PA11", "PA12", "PA13", "PA14", |
| 853 | "PA15", "PA16"; |
| 854 | allwinner,function = "emac"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 855 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 856 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 756084c | 2013-09-11 11:10:07 +0200 | [diff] [blame] | 857 | }; |
Chen-Yu Tsai | f2e0759 | 2014-01-01 10:30:50 +0800 | [diff] [blame] | 858 | |
| 859 | clk_out_a_pins_a: clk_out_a@0 { |
| 860 | allwinner,pins = "PI12"; |
| 861 | allwinner,function = "clk_out_a"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 862 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 863 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | f2e0759 | 2014-01-01 10:30:50 +0800 | [diff] [blame] | 864 | }; |
| 865 | |
| 866 | clk_out_b_pins_a: clk_out_b@0 { |
| 867 | allwinner,pins = "PI13"; |
| 868 | allwinner,function = "clk_out_b"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 869 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 870 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | f2e0759 | 2014-01-01 10:30:50 +0800 | [diff] [blame] | 871 | }; |
Chen-Yu Tsai | 129ccbc | 2014-02-10 18:35:50 +0800 | [diff] [blame] | 872 | |
| 873 | gmac_pins_mii_a: gmac_mii@0 { |
| 874 | allwinner,pins = "PA0", "PA1", "PA2", |
| 875 | "PA3", "PA4", "PA5", "PA6", |
| 876 | "PA7", "PA8", "PA9", "PA10", |
| 877 | "PA11", "PA12", "PA13", "PA14", |
| 878 | "PA15", "PA16"; |
| 879 | allwinner,function = "gmac"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 880 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 881 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | 129ccbc | 2014-02-10 18:35:50 +0800 | [diff] [blame] | 882 | }; |
| 883 | |
| 884 | gmac_pins_rgmii_a: gmac_rgmii@0 { |
| 885 | allwinner,pins = "PA0", "PA1", "PA2", |
| 886 | "PA3", "PA4", "PA5", "PA6", |
| 887 | "PA7", "PA8", "PA10", |
| 888 | "PA11", "PA12", "PA13", |
| 889 | "PA15", "PA16"; |
| 890 | allwinner,function = "gmac"; |
| 891 | /* |
| 892 | * data lines in RGMII mode use DDR mode |
| 893 | * and need a higher signal drive strength |
| 894 | */ |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 895 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; |
| 896 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Chen-Yu Tsai | 129ccbc | 2014-02-10 18:35:50 +0800 | [diff] [blame] | 897 | }; |
Maxime Ripard | 412f2c6 | 2014-02-22 22:35:58 +0100 | [diff] [blame] | 898 | |
Hans de Goede | 2dad53b | 2014-10-01 09:26:04 +0200 | [diff] [blame] | 899 | spi0_pins_a: spi0@0 { |
| 900 | allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; |
| 901 | allwinner,function = "spi0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 902 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 903 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Hans de Goede | 2dad53b | 2014-10-01 09:26:04 +0200 | [diff] [blame] | 904 | }; |
| 905 | |
Maxime Ripard | 412f2c6 | 2014-02-22 22:35:58 +0100 | [diff] [blame] | 906 | spi1_pins_a: spi1@0 { |
| 907 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; |
| 908 | allwinner,function = "spi1"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 909 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 910 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 412f2c6 | 2014-02-22 22:35:58 +0100 | [diff] [blame] | 911 | }; |
| 912 | |
| 913 | spi2_pins_a: spi2@0 { |
| 914 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; |
| 915 | allwinner,function = "spi2"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 916 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 917 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 412f2c6 | 2014-02-22 22:35:58 +0100 | [diff] [blame] | 918 | }; |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 919 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 920 | spi2_pins_b: spi2@1 { |
| 921 | allwinner,pins = "PB14", "PB15", "PB16", "PB17"; |
| 922 | allwinner,function = "spi2"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 923 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 924 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 925 | }; |
| 926 | |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 927 | mmc0_pins_a: mmc0@0 { |
| 928 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; |
| 929 | allwinner,function = "mmc0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 930 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 931 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 932 | }; |
| 933 | |
| 934 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { |
| 935 | allwinner,pins = "PH1"; |
| 936 | allwinner,function = "gpio_in"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 937 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 938 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 939 | }; |
| 940 | |
Hans de Goede | 8fa8232 | 2014-10-01 16:25:36 +0200 | [diff] [blame] | 941 | mmc2_pins_a: mmc2@0 { |
| 942 | allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; |
| 943 | allwinner,function = "mmc2"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 944 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 945 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
Hans de Goede | 8fa8232 | 2014-10-01 16:25:36 +0200 | [diff] [blame] | 946 | }; |
| 947 | |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 948 | mmc3_pins_a: mmc3@0 { |
| 949 | allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; |
| 950 | allwinner,function = "mmc3"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 951 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 952 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 953 | }; |
Alexander Bersenev | 0fc2b7a | 2014-06-09 00:08:11 +0600 | [diff] [blame] | 954 | |
| 955 | ir0_pins_a: ir0@0 { |
| 956 | allwinner,pins = "PB3","PB4"; |
| 957 | allwinner,function = "ir0"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 958 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 959 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Alexander Bersenev | 0fc2b7a | 2014-06-09 00:08:11 +0600 | [diff] [blame] | 960 | }; |
| 961 | |
| 962 | ir1_pins_a: ir1@0 { |
| 963 | allwinner,pins = "PB22","PB23"; |
| 964 | allwinner,function = "ir1"; |
Maxime Ripard | 092a0c3 | 2014-12-16 22:59:57 +0100 | [diff] [blame] | 965 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 966 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Alexander Bersenev | 0fc2b7a | 2014-06-09 00:08:11 +0600 | [diff] [blame] | 967 | }; |
Vishnu Patekar | 1e8d156 | 2015-01-25 19:10:09 +0530 | [diff] [blame] | 968 | |
| 969 | ps20_pins_a: ps20@0 { |
| 970 | allwinner,pins = "PI20", "PI21"; |
| 971 | allwinner,function = "ps2"; |
| 972 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 973 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 974 | }; |
| 975 | |
| 976 | ps21_pins_a: ps21@0 { |
| 977 | allwinner,pins = "PH12", "PH13"; |
| 978 | allwinner,function = "ps2"; |
| 979 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 980 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 981 | }; |
| 982 | }; |
Maxime Ripard | ca5d04d | 2014-02-07 22:29:26 +0100 | [diff] [blame] | 983 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 984 | timer@01c20c00 { |
| 985 | compatible = "allwinner,sun4i-a10-timer"; |
| 986 | reg = <0x01c20c00 0x90>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 987 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| 988 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, |
| 989 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
| 990 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, |
| 991 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 992 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 993 | clocks = <&osc24M>; |
| 994 | }; |
| 995 | |
| 996 | wdt: watchdog@01c20c90 { |
| 997 | compatible = "allwinner,sun4i-a10-wdt"; |
| 998 | reg = <0x01c20c90 0x10>; |
| 999 | }; |
| 1000 | |
Carlo Caione | b5d905c | 2013-10-16 20:30:26 +0200 | [diff] [blame] | 1001 | rtc: rtc@01c20d00 { |
| 1002 | compatible = "allwinner,sun7i-a20-rtc"; |
| 1003 | reg = <0x01c20d00 0x20>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1004 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
Carlo Caione | b5d905c | 2013-10-16 20:30:26 +0200 | [diff] [blame] | 1005 | }; |
| 1006 | |
Alexandre Belloni | 8ec40c2 | 2014-04-28 18:17:13 +0200 | [diff] [blame] | 1007 | pwm: pwm@01c20e00 { |
| 1008 | compatible = "allwinner,sun7i-a20-pwm"; |
| 1009 | reg = <0x01c20e00 0xc>; |
| 1010 | clocks = <&osc24M>; |
| 1011 | #pwm-cells = <3>; |
| 1012 | status = "disabled"; |
| 1013 | }; |
| 1014 | |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 1015 | ir0: ir@01c21800 { |
Hans de Goede | 1715a38 | 2014-06-30 23:57:54 +0200 | [diff] [blame] | 1016 | compatible = "allwinner,sun4i-a10-ir"; |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 1017 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
| 1018 | clock-names = "apb", "ir"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1019 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 1020 | reg = <0x01c21800 0x40>; |
| 1021 | status = "disabled"; |
| 1022 | }; |
| 1023 | |
| 1024 | ir1: ir@01c21c00 { |
Hans de Goede | 1715a38 | 2014-06-30 23:57:54 +0200 | [diff] [blame] | 1025 | compatible = "allwinner,sun4i-a10-ir"; |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 1026 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
| 1027 | clock-names = "apb", "ir"; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1028 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 1029 | reg = <0x01c21c00 0x40>; |
| 1030 | status = "disabled"; |
| 1031 | }; |
| 1032 | |
Hans de Goede | a6a2d64 | 2014-12-23 11:13:22 +0100 | [diff] [blame] | 1033 | lradc: lradc@01c22800 { |
| 1034 | compatible = "allwinner,sun4i-a10-lradc-keys"; |
| 1035 | reg = <0x01c22800 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1036 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hans de Goede | a6a2d64 | 2014-12-23 11:13:22 +0100 | [diff] [blame] | 1037 | status = "disabled"; |
| 1038 | }; |
| 1039 | |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 1040 | sid: eeprom@01c23800 { |
| 1041 | compatible = "allwinner,sun7i-a20-sid"; |
| 1042 | reg = <0x01c23800 0x200>; |
| 1043 | }; |
| 1044 | |
Hans de Goede | 00f7ed8 | 2013-12-31 17:20:52 +0100 | [diff] [blame] | 1045 | rtp: rtp@01c25000 { |
Maxime Ripard | 40dd8f3 | 2014-02-02 14:52:40 +0100 | [diff] [blame] | 1046 | compatible = "allwinner,sun4i-a10-ts"; |
Hans de Goede | 00f7ed8 | 2013-12-31 17:20:52 +0100 | [diff] [blame] | 1047 | reg = <0x01c25000 0x100>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1048 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
Chen-Yu Tsai | 41e7afb | 2015-01-06 10:35:15 +0800 | [diff] [blame] | 1049 | #thermal-sensor-cells = <0>; |
Hans de Goede | 00f7ed8 | 2013-12-31 17:20:52 +0100 | [diff] [blame] | 1050 | }; |
| 1051 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1052 | uart0: serial@01c28000 { |
| 1053 | compatible = "snps,dw-apb-uart"; |
| 1054 | reg = <0x01c28000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1055 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1056 | reg-shift = <2>; |
| 1057 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1058 | clocks = <&apb1_gates 16>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1059 | status = "disabled"; |
| 1060 | }; |
| 1061 | |
| 1062 | uart1: serial@01c28400 { |
| 1063 | compatible = "snps,dw-apb-uart"; |
| 1064 | reg = <0x01c28400 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1065 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1066 | reg-shift = <2>; |
| 1067 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1068 | clocks = <&apb1_gates 17>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1069 | status = "disabled"; |
| 1070 | }; |
| 1071 | |
| 1072 | uart2: serial@01c28800 { |
| 1073 | compatible = "snps,dw-apb-uart"; |
| 1074 | reg = <0x01c28800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1075 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1076 | reg-shift = <2>; |
| 1077 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1078 | clocks = <&apb1_gates 18>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1079 | status = "disabled"; |
| 1080 | }; |
| 1081 | |
| 1082 | uart3: serial@01c28c00 { |
| 1083 | compatible = "snps,dw-apb-uart"; |
| 1084 | reg = <0x01c28c00 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1085 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1086 | reg-shift = <2>; |
| 1087 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1088 | clocks = <&apb1_gates 19>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1089 | status = "disabled"; |
| 1090 | }; |
| 1091 | |
| 1092 | uart4: serial@01c29000 { |
| 1093 | compatible = "snps,dw-apb-uart"; |
| 1094 | reg = <0x01c29000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1095 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1096 | reg-shift = <2>; |
| 1097 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1098 | clocks = <&apb1_gates 20>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1099 | status = "disabled"; |
| 1100 | }; |
| 1101 | |
| 1102 | uart5: serial@01c29400 { |
| 1103 | compatible = "snps,dw-apb-uart"; |
| 1104 | reg = <0x01c29400 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1105 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1106 | reg-shift = <2>; |
| 1107 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1108 | clocks = <&apb1_gates 21>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1109 | status = "disabled"; |
| 1110 | }; |
| 1111 | |
| 1112 | uart6: serial@01c29800 { |
| 1113 | compatible = "snps,dw-apb-uart"; |
| 1114 | reg = <0x01c29800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1115 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1116 | reg-shift = <2>; |
| 1117 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1118 | clocks = <&apb1_gates 22>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1119 | status = "disabled"; |
| 1120 | }; |
| 1121 | |
| 1122 | uart7: serial@01c29c00 { |
| 1123 | compatible = "snps,dw-apb-uart"; |
| 1124 | reg = <0x01c29c00 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1125 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1126 | reg-shift = <2>; |
| 1127 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 1128 | clocks = <&apb1_gates 23>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1129 | status = "disabled"; |
| 1130 | }; |
| 1131 | |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1132 | i2c0: i2c@01c2ac00 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1133 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1134 | reg = <0x01c2ac00 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1135 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1136 | clocks = <&apb1_gates 0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1137 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1138 | #address-cells = <1>; |
| 1139 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1140 | }; |
| 1141 | |
| 1142 | i2c1: i2c@01c2b000 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1143 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1144 | reg = <0x01c2b000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1145 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1146 | clocks = <&apb1_gates 1>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1147 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1148 | #address-cells = <1>; |
| 1149 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1150 | }; |
| 1151 | |
| 1152 | i2c2: i2c@01c2b400 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1153 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1154 | reg = <0x01c2b400 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1155 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1156 | clocks = <&apb1_gates 2>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1157 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1158 | #address-cells = <1>; |
| 1159 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1160 | }; |
| 1161 | |
| 1162 | i2c3: i2c@01c2b800 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1163 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1164 | reg = <0x01c2b800 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1165 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1166 | clocks = <&apb1_gates 3>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1167 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1168 | #address-cells = <1>; |
| 1169 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1170 | }; |
| 1171 | |
Maxime Ripard | a386704 | 2014-04-18 21:13:08 +0200 | [diff] [blame] | 1172 | i2c4: i2c@01c2c000 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1173 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | a386704 | 2014-04-18 21:13:08 +0200 | [diff] [blame] | 1174 | reg = <0x01c2c000 0x400>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1175 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1176 | clocks = <&apb1_gates 15>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1177 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1178 | #address-cells = <1>; |
| 1179 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1180 | }; |
| 1181 | |
Chen-Yu Tsai | c40b8d5 | 2014-02-10 18:35:49 +0800 | [diff] [blame] | 1182 | gmac: ethernet@01c50000 { |
| 1183 | compatible = "allwinner,sun7i-a20-gmac"; |
| 1184 | reg = <0x01c50000 0x10000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1185 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Chen-Yu Tsai | c40b8d5 | 2014-02-10 18:35:49 +0800 | [diff] [blame] | 1186 | interrupt-names = "macirq"; |
| 1187 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; |
| 1188 | clock-names = "stmmaceth", "allwinner_gmac_tx"; |
| 1189 | snps,pbl = <2>; |
| 1190 | snps,fixed-burst; |
| 1191 | snps,force_sf_dma_mode; |
| 1192 | status = "disabled"; |
| 1193 | #address-cells = <1>; |
| 1194 | #size-cells = <0>; |
| 1195 | }; |
| 1196 | |
Maxime Ripard | 31f8ad3 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 1197 | hstimer@01c60000 { |
| 1198 | compatible = "allwinner,sun7i-a20-hstimer"; |
| 1199 | reg = <0x01c60000 0x1000>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1200 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, |
| 1201 | <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, |
| 1202 | <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, |
| 1203 | <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 31f8ad3 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 1204 | clocks = <&ahb_gates 28>; |
| 1205 | }; |
| 1206 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1207 | gic: interrupt-controller@01c81000 { |
| 1208 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 1209 | reg = <0x01c81000 0x1000>, |
| 1210 | <0x01c82000 0x1000>, |
| 1211 | <0x01c84000 0x2000>, |
| 1212 | <0x01c86000 0x2000>; |
| 1213 | interrupt-controller; |
| 1214 | #interrupt-cells = <3>; |
Maxime Ripard | 19882b8 | 2014-12-16 22:59:58 +0100 | [diff] [blame] | 1215 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1216 | }; |
Vishnu Patekar | 196654a | 2015-01-25 19:10:08 +0530 | [diff] [blame] | 1217 | |
| 1218 | ps20: ps2@01c2a000 { |
| 1219 | compatible = "allwinner,sun4i-a10-ps2"; |
| 1220 | reg = <0x01c2a000 0x400>; |
| 1221 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 1222 | clocks = <&apb1_gates 6>; |
| 1223 | status = "disabled"; |
| 1224 | }; |
| 1225 | |
| 1226 | ps21: ps2@01c2a400 { |
| 1227 | compatible = "allwinner,sun4i-a10-ps2"; |
| 1228 | reg = <0x01c2a400 0x400>; |
| 1229 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| 1230 | clocks = <&apb1_gates 7>; |
| 1231 | status = "disabled"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1232 | }; |
| 1233 | }; |
| 1234 | }; |