Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-clps711x/core.c |
| 3 | * |
| 4 | * Core support for the CLPS711x-based machines. |
| 5 | * |
| 6 | * Copyright (C) 2001,2011 Deep Blue Solutions Ltd |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 22 | #include <linux/io.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 23 | #include <linux/init.h> |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 24 | #include <linux/sizes.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 25 | #include <linux/interrupt.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 26 | #include <linux/irq.h> |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 27 | #include <linux/clk.h> |
| 28 | #include <linux/clkdev.h> |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 29 | #include <linux/clockchips.h> |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 30 | #include <linux/clk-provider.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 31 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 32 | #include <asm/mach/map.h> |
| 33 | #include <asm/mach/time.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 34 | #include <asm/system_misc.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 35 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 36 | #include <mach/hardware.h> |
| 37 | |
| 38 | static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh, |
| 39 | *clk_tint, *clk_spi; |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 40 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 41 | /* |
| 42 | * This maps the generic CLPS711x registers |
| 43 | */ |
| 44 | static struct map_desc clps711x_io_desc[] __initdata = { |
| 45 | { |
Alexander Shiyan | 304b2c6 | 2012-05-06 09:21:57 +0400 | [diff] [blame] | 46 | .virtual = (unsigned long)CLPS711X_VIRT_BASE, |
| 47 | .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE), |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 48 | .length = SZ_1M, |
| 49 | .type = MT_DEVICE |
| 50 | } |
| 51 | }; |
| 52 | |
| 53 | void __init clps711x_map_io(void) |
| 54 | { |
| 55 | iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc)); |
| 56 | } |
| 57 | |
| 58 | static void int1_mask(struct irq_data *d) |
| 59 | { |
| 60 | u32 intmr1; |
| 61 | |
| 62 | intmr1 = clps_readl(INTMR1); |
| 63 | intmr1 &= ~(1 << d->irq); |
| 64 | clps_writel(intmr1, INTMR1); |
| 65 | } |
| 66 | |
| 67 | static void int1_ack(struct irq_data *d) |
| 68 | { |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 69 | switch (d->irq) { |
| 70 | case IRQ_CSINT: clps_writel(0, COEOI); break; |
| 71 | case IRQ_TC1OI: clps_writel(0, TC1EOI); break; |
| 72 | case IRQ_TC2OI: clps_writel(0, TC2EOI); break; |
| 73 | case IRQ_RTCMI: clps_writel(0, RTCEOI); break; |
| 74 | case IRQ_TINT: clps_writel(0, TEOI); break; |
| 75 | case IRQ_UMSINT: clps_writel(0, UMSEOI); break; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | static void int1_unmask(struct irq_data *d) |
| 80 | { |
| 81 | u32 intmr1; |
| 82 | |
| 83 | intmr1 = clps_readl(INTMR1); |
| 84 | intmr1 |= 1 << d->irq; |
| 85 | clps_writel(intmr1, INTMR1); |
| 86 | } |
| 87 | |
| 88 | static struct irq_chip int1_chip = { |
| 89 | .irq_ack = int1_ack, |
| 90 | .irq_mask = int1_mask, |
| 91 | .irq_unmask = int1_unmask, |
| 92 | }; |
| 93 | |
| 94 | static void int2_mask(struct irq_data *d) |
| 95 | { |
| 96 | u32 intmr2; |
| 97 | |
| 98 | intmr2 = clps_readl(INTMR2); |
| 99 | intmr2 &= ~(1 << (d->irq - 16)); |
| 100 | clps_writel(intmr2, INTMR2); |
| 101 | } |
| 102 | |
| 103 | static void int2_ack(struct irq_data *d) |
| 104 | { |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 105 | switch (d->irq) { |
| 106 | case IRQ_KBDINT: clps_writel(0, KBDEOI); break; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | static void int2_unmask(struct irq_data *d) |
| 111 | { |
| 112 | u32 intmr2; |
| 113 | |
| 114 | intmr2 = clps_readl(INTMR2); |
| 115 | intmr2 |= 1 << (d->irq - 16); |
| 116 | clps_writel(intmr2, INTMR2); |
| 117 | } |
| 118 | |
| 119 | static struct irq_chip int2_chip = { |
| 120 | .irq_ack = int2_ack, |
| 121 | .irq_mask = int2_mask, |
| 122 | .irq_unmask = int2_unmask, |
| 123 | }; |
| 124 | |
| 125 | void __init clps711x_init_irq(void) |
| 126 | { |
| 127 | unsigned int i; |
| 128 | |
| 129 | for (i = 0; i < NR_IRQS; i++) { |
| 130 | if (INT1_IRQS & (1 << i)) { |
| 131 | irq_set_chip_and_handler(i, &int1_chip, |
| 132 | handle_level_irq); |
| 133 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 134 | } |
| 135 | if (INT2_IRQS & (1 << i)) { |
| 136 | irq_set_chip_and_handler(i, &int2_chip, |
| 137 | handle_level_irq); |
| 138 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | /* |
| 143 | * Disable interrupts |
| 144 | */ |
| 145 | clps_writel(0, INTMR1); |
| 146 | clps_writel(0, INTMR2); |
| 147 | |
| 148 | /* |
| 149 | * Clear down any pending interrupts |
| 150 | */ |
| 151 | clps_writel(0, COEOI); |
| 152 | clps_writel(0, TC1EOI); |
| 153 | clps_writel(0, TC2EOI); |
| 154 | clps_writel(0, RTCEOI); |
| 155 | clps_writel(0, TEOI); |
| 156 | clps_writel(0, UMSEOI); |
| 157 | clps_writel(0, SYNCIO); |
| 158 | clps_writel(0, KBDEOI); |
| 159 | } |
| 160 | |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 161 | static void clps711x_clockevent_set_mode(enum clock_event_mode mode, |
| 162 | struct clock_event_device *evt) |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 163 | { |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 164 | } |
| 165 | |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 166 | static struct clock_event_device clockevent_clps711x = { |
| 167 | .name = "CLPS711x Clockevents", |
| 168 | .rating = 300, |
| 169 | .features = CLOCK_EVT_FEAT_PERIODIC, |
| 170 | .set_mode = clps711x_clockevent_set_mode, |
| 171 | }; |
| 172 | |
| 173 | static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id) |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 174 | { |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 175 | clockevent_clps711x.event_handler(&clockevent_clps711x); |
| 176 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 177 | return IRQ_HANDLED; |
| 178 | } |
| 179 | |
| 180 | static struct irqaction clps711x_timer_irq = { |
| 181 | .name = "CLPS711x Timer Tick", |
| 182 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 183 | .handler = clps711x_timer_interrupt, |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 184 | }; |
| 185 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 186 | static void add_fixed_clk(struct clk *clk, const char *name, int rate) |
| 187 | { |
| 188 | clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); |
| 189 | clk_register_clkdev(clk, name, NULL); |
| 190 | } |
| 191 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 192 | static void __init clps711x_timer_init(void) |
| 193 | { |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 194 | int osc, ext, pll, cpu, bus, timl, timh, uart, spi; |
| 195 | u32 tmp; |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 196 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 197 | osc = 3686400; |
| 198 | ext = 13000000; |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 199 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 200 | tmp = clps_readl(PLLR) >> 24; |
| 201 | if (tmp) |
| 202 | pll = (osc * tmp) / 2; |
| 203 | else |
| 204 | pll = 73728000; /* Default value */ |
| 205 | |
| 206 | tmp = clps_readl(SYSFLG2); |
| 207 | if (tmp & SYSFLG2_CKMODE) { |
| 208 | cpu = ext; |
| 209 | bus = cpu; |
| 210 | spi = 135400; |
| 211 | } else { |
| 212 | cpu = pll; |
| 213 | if (cpu >= 36864000) |
| 214 | bus = cpu / 2; |
| 215 | else |
| 216 | bus = 36864000 / 2; |
| 217 | spi = cpu / 576; |
| 218 | } |
| 219 | |
| 220 | uart = bus / 10; |
| 221 | |
| 222 | if (tmp & SYSFLG2_CKMODE) { |
| 223 | tmp = clps_readl(SYSCON2); |
| 224 | if (tmp & SYSCON2_OSTB) |
| 225 | timh = ext / 26; |
| 226 | else |
| 227 | timh = 541440; |
| 228 | } else |
| 229 | timh = cpu / 144; |
| 230 | |
| 231 | timl = timh / 256; |
| 232 | |
| 233 | /* All clocks are fixed */ |
| 234 | add_fixed_clk(clk_pll, "pll", pll); |
| 235 | add_fixed_clk(clk_bus, "bus", bus); |
| 236 | add_fixed_clk(clk_uart, "uart", uart); |
| 237 | add_fixed_clk(clk_timerl, "timer_lf", timl); |
| 238 | add_fixed_clk(clk_timerh, "timer_hf", timh); |
| 239 | add_fixed_clk(clk_tint, "tint", 64); |
| 240 | add_fixed_clk(clk_spi, "spi", spi); |
| 241 | |
| 242 | pr_info("CPU frequency set at %i Hz.\n", cpu); |
| 243 | |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 244 | clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D); |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 245 | |
| 246 | tmp = clps_readl(SYSCON1); |
| 247 | tmp |= SYSCON1_TC2S | SYSCON1_TC2M; |
| 248 | clps_writel(tmp, SYSCON1); |
| 249 | |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame^] | 250 | clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 251 | |
| 252 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | struct sys_timer clps711x_timer = { |
| 256 | .init = clps711x_timer_init, |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 257 | }; |
Russell King | 6c00071 | 2011-11-05 17:41:52 +0000 | [diff] [blame] | 258 | |
| 259 | void clps711x_restart(char mode, const char *cmd) |
| 260 | { |
| 261 | soft_restart(0); |
| 262 | } |
Nicolas Pitre | 71e256c | 2011-08-02 12:22:48 -0400 | [diff] [blame] | 263 | |
| 264 | static void clps711x_idle(void) |
| 265 | { |
| 266 | clps_writel(1, HALT); |
| 267 | __asm__ __volatile__( |
| 268 | "mov r0, r0\n\ |
| 269 | mov r0, r0"); |
| 270 | } |
| 271 | |
| 272 | static int __init clps711x_idle_init(void) |
| 273 | { |
| 274 | arm_pm_idle = clps711x_idle; |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | arch_initcall(clps711x_idle_init); |