| Mark Salter | 041cadc | 2011-10-04 12:12:20 -0400 | [diff] [blame] | 1 | |
| 2 | / { |
| 3 | #address-cells = <1>; |
| 4 | #size-cells = <1>; |
| 5 | |
| 6 | cpus { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <0>; |
| 9 | |
| 10 | cpu@0 { |
| 11 | device_type = "cpu"; |
| 12 | model = "ti,c64x+"; |
| 13 | reg = <0>; |
| 14 | }; |
| 15 | }; |
| 16 | |
| 17 | soc { |
| 18 | compatible = "simple-bus"; |
| 19 | model = "tms320c6455"; |
| 20 | #address-cells = <1>; |
| 21 | #size-cells = <1>; |
| 22 | ranges; |
| 23 | |
| 24 | core_pic: interrupt-controller { |
| 25 | interrupt-controller; |
| 26 | #interrupt-cells = <1>; |
| 27 | compatible = "ti,c64x+core-pic"; |
| 28 | }; |
| 29 | |
| 30 | /* |
| 31 | * Megamodule interrupt controller |
| 32 | */ |
| 33 | megamod_pic: interrupt-controller@1800000 { |
| 34 | compatible = "ti,c64x+megamod-pic"; |
| 35 | interrupt-controller; |
| 36 | #interrupt-cells = <1>; |
| 37 | reg = <0x1800000 0x1000>; |
| 38 | interrupt-parent = <&core_pic>; |
| 39 | }; |
| 40 | |
| 41 | cache-controller@1840000 { |
| 42 | compatible = "ti,c64x+cache"; |
| 43 | reg = <0x01840000 0x8400>; |
| 44 | }; |
| 45 | |
| 46 | emifa@70000000 { |
| 47 | compatible = "ti,c64x+emifa", "simple-bus"; |
| 48 | #address-cells = <2>; |
| 49 | #size-cells = <1>; |
| 50 | reg = <0x70000000 0x100>; |
| 51 | ranges = <0x2 0x0 0xa0000000 0x00000008 |
| 52 | 0x3 0x0 0xb0000000 0x00400000 |
| 53 | 0x4 0x0 0xc0000000 0x10000000 |
| 54 | 0x5 0x0 0xD0000000 0x10000000>; |
| 55 | |
| 56 | ti,dscr-dev-enable = <13>; |
| 57 | ti,emifa-burst-priority = <255>; |
| 58 | ti,emifa-ce-config = <0x00240120 |
| 59 | 0x00240120 |
| 60 | 0x00240122 |
| 61 | 0x00240122>; |
| 62 | }; |
| 63 | |
| 64 | timer1: timer@2980000 { |
| 65 | compatible = "ti,c64x+timer64"; |
| 66 | reg = <0x2980000 0x40>; |
| 67 | ti,dscr-dev-enable = <4>; |
| 68 | }; |
| 69 | |
| 70 | clock-controller@029a0000 { |
| 71 | compatible = "ti,c6455-pll", "ti,c64x+pll"; |
| 72 | reg = <0x029a0000 0x200>; |
| 73 | ti,c64x+pll-bypass-delay = <1440>; |
| 74 | ti,c64x+pll-reset-delay = <15360>; |
| 75 | ti,c64x+pll-lock-delay = <24000>; |
| 76 | }; |
| 77 | |
| 78 | device-state-config-regs@2a80000 { |
| 79 | compatible = "ti,c64x+dscr"; |
| 80 | reg = <0x02a80000 0x41000>; |
| 81 | |
| 82 | ti,dscr-devstat = <0>; |
| 83 | ti,dscr-silicon-rev = <8 28 0xf>; |
| 84 | ti,dscr-rmii-resets = <0 0x40020 0x00040000>; |
| 85 | |
| 86 | ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; |
| 87 | ti,dscr-devstate-ctl-regs = |
| 88 | <0 12 0x40008 1 0 0 2 |
| 89 | 12 1 0x40008 3 0 30 2 |
| 90 | 13 2 0x4002c 1 0xffffffff 0 1>; |
| 91 | ti,dscr-devstate-stat-regs = |
| 92 | <0 10 0x40014 1 0 0 3 |
| 93 | 10 2 0x40018 1 0 0 3>; |
| 94 | }; |
| 95 | }; |
| 96 | }; |