| H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_XOR_64_H |
| 2 | #define _ASM_X86_XOR_64_H |
| Vegard Nossum | 0db125c | 2008-06-10 23:45:45 +0200 | [diff] [blame] | 3 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | static struct xor_block_template xor_block_sse = { |
| Joe Perches | 687c805 | 2008-03-23 01:04:03 -0700 | [diff] [blame] | 5 | .name = "generic_sse", |
| 6 | .do_2 = xor_sse_2, |
| 7 | .do_3 = xor_sse_3, |
| 8 | .do_4 = xor_sse_4, |
| 9 | .do_5 = xor_sse_5, |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | }; |
| 11 | |
| Jim Kukunas | ea4d26a | 2012-05-22 13:54:04 +1000 | [diff] [blame] | 12 | |
| 13 | /* Also try the AVX routines */ |
| David Howells | a1ce392 | 2012-10-02 18:01:25 +0100 | [diff] [blame] | 14 | #include <asm/xor_avx.h> |
| Jim Kukunas | ea4d26a | 2012-05-22 13:54:04 +1000 | [diff] [blame] | 15 | |
| Jan Beulich | f317820 | 2012-11-02 14:20:24 +0000 | [diff] [blame] | 16 | /* We force the use of the SSE xor block because it can write around L2. |
| 17 | We may also be able to load into the L1 only depending on how the cpu |
| 18 | deals with a load to a line that is being prefetched. */ |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #undef XOR_TRY_TEMPLATES |
| Joe Perches | 687c805 | 2008-03-23 01:04:03 -0700 | [diff] [blame] | 20 | #define XOR_TRY_TEMPLATES \ |
| 21 | do { \ |
| Jim Kukunas | ea4d26a | 2012-05-22 13:54:04 +1000 | [diff] [blame] | 22 | AVX_XOR_SPEED; \ |
| Jan Beulich | f317820 | 2012-11-02 14:20:24 +0000 | [diff] [blame] | 23 | xor_speed(&xor_block_sse_pf64); \ |
| Joe Perches | 687c805 | 2008-03-23 01:04:03 -0700 | [diff] [blame] | 24 | xor_speed(&xor_block_sse); \ |
| 25 | } while (0) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
| H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 27 | #endif /* _ASM_X86_XOR_64_H */ |