Kyle Yan | 3d6600c | 2017-01-06 14:04:26 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/regulator/consumer.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/of_gpio.h> |
| 23 | #include <linux/delay.h> |
| 24 | |
| 25 | #include <linux/msm-bus-board.h> |
| 26 | #include <linux/msm-bus.h> |
| 27 | #include <linux/dma-mapping.h> |
| 28 | |
| 29 | #include <soc/qcom/subsystem_restart.h> |
| 30 | #include <soc/qcom/ramdump.h> |
| 31 | #include <soc/qcom/scm.h> |
| 32 | |
| 33 | #include <soc/qcom/smem.h> |
| 34 | |
| 35 | #include "peripheral-loader.h" |
| 36 | |
| 37 | #define XO_FREQ 19200000 |
| 38 | #define PROXY_TIMEOUT_MS 10000 |
Kyle Yan | fe3813e | 2017-06-06 17:03:58 -0700 | [diff] [blame] | 39 | #define MAX_SSR_REASON_LEN 256U |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 40 | #define STOP_ACK_TIMEOUT_MS 1000 |
| 41 | #define CRASH_STOP_ACK_TO_MS 200 |
| 42 | |
| 43 | #define ERR_READY 0 |
| 44 | #define PBL_DONE 1 |
| 45 | |
| 46 | #define desc_to_data(d) container_of(d, struct pil_tz_data, desc) |
| 47 | #define subsys_to_data(d) container_of(d, struct pil_tz_data, subsys_desc) |
| 48 | |
| 49 | /** |
| 50 | * struct reg_info - regulator info |
| 51 | * @reg: regulator handle |
| 52 | * @uV: voltage in uV |
| 53 | * @uA: current in uA |
| 54 | */ |
| 55 | struct reg_info { |
| 56 | struct regulator *reg; |
| 57 | int uV; |
| 58 | int uA; |
| 59 | }; |
| 60 | |
| 61 | /** |
| 62 | * struct pil_tz_data |
| 63 | * @regs: regulators that should be always on when the subsystem is |
| 64 | * brought out of reset |
| 65 | * @proxy_regs: regulators that should be on during pil proxy voting |
| 66 | * @clks: clocks that should be always on when the subsystem is |
| 67 | * brought out of reset |
| 68 | * @proxy_clks: clocks that should be on during pil proxy voting |
| 69 | * @reg_count: the number of always on regulators |
| 70 | * @proxy_reg_count: the number of proxy voting regulators |
| 71 | * @clk_count: the number of always on clocks |
| 72 | * @proxy_clk_count: the number of proxy voting clocks |
| 73 | * @smem_id: the smem id used for read the subsystem crash reason |
| 74 | * @ramdump_dev: ramdump device pointer |
| 75 | * @pas_id: the PAS id for tz |
| 76 | * @bus_client: bus client id |
| 77 | * @enable_bus_scaling: set to true if PIL needs to vote for |
| 78 | * bus bandwidth |
| 79 | * @keep_proxy_regs_on: If set, during proxy unvoting, PIL removes the |
| 80 | * voltage/current vote for proxy regulators but leaves |
| 81 | * them enabled. |
| 82 | * @stop_ack: state of completion of stop ack |
| 83 | * @desc: PIL descriptor |
| 84 | * @subsys: subsystem device pointer |
| 85 | * @subsys_desc: subsystem descriptor |
| 86 | * @u32 bits_arr[2]: array of bit positions in SCSR registers |
| 87 | */ |
| 88 | struct pil_tz_data { |
| 89 | struct reg_info *regs; |
| 90 | struct reg_info *proxy_regs; |
| 91 | struct clk **clks; |
| 92 | struct clk **proxy_clks; |
| 93 | int reg_count; |
| 94 | int proxy_reg_count; |
| 95 | int clk_count; |
| 96 | int proxy_clk_count; |
| 97 | int smem_id; |
| 98 | void *ramdump_dev; |
| 99 | u32 pas_id; |
| 100 | u32 bus_client; |
| 101 | bool enable_bus_scaling; |
| 102 | bool keep_proxy_regs_on; |
| 103 | struct completion stop_ack; |
| 104 | struct pil_desc desc; |
| 105 | struct subsys_device *subsys; |
| 106 | struct subsys_desc subsys_desc; |
| 107 | void __iomem *irq_status; |
| 108 | void __iomem *irq_clear; |
| 109 | void __iomem *irq_mask; |
| 110 | void __iomem *err_status; |
| 111 | void __iomem *err_status_spare; |
| 112 | u32 bits_arr[2]; |
| 113 | }; |
| 114 | |
| 115 | enum scm_cmd { |
| 116 | PAS_INIT_IMAGE_CMD = 1, |
| 117 | PAS_MEM_SETUP_CMD, |
| 118 | PAS_AUTH_AND_RESET_CMD = 5, |
| 119 | PAS_SHUTDOWN_CMD, |
| 120 | }; |
| 121 | |
| 122 | enum pas_id { |
| 123 | PAS_MODEM, |
| 124 | PAS_Q6, |
| 125 | PAS_DSPS, |
| 126 | PAS_TZAPPS, |
| 127 | PAS_MODEM_SW, |
| 128 | PAS_MODEM_FW, |
| 129 | PAS_WCNSS, |
| 130 | PAS_SECAPP, |
| 131 | PAS_GSS, |
| 132 | PAS_VIDC, |
| 133 | PAS_VPU, |
| 134 | PAS_BCSS, |
| 135 | }; |
| 136 | |
| 137 | static struct msm_bus_paths scm_pas_bw_tbl[] = { |
| 138 | { |
| 139 | .vectors = (struct msm_bus_vectors[]){ |
| 140 | { |
| 141 | .src = MSM_BUS_MASTER_SPS, |
| 142 | .dst = MSM_BUS_SLAVE_EBI_CH0, |
| 143 | }, |
| 144 | }, |
| 145 | .num_paths = 1, |
| 146 | }, |
| 147 | { |
| 148 | .vectors = (struct msm_bus_vectors[]){ |
| 149 | { |
| 150 | .src = MSM_BUS_MASTER_SPS, |
| 151 | .dst = MSM_BUS_SLAVE_EBI_CH0, |
| 152 | .ib = 492 * 8 * 1000000UL, |
| 153 | .ab = 492 * 8 * 100000UL, |
| 154 | }, |
| 155 | }, |
| 156 | .num_paths = 1, |
| 157 | }, |
| 158 | }; |
| 159 | |
| 160 | static struct msm_bus_scale_pdata scm_pas_bus_pdata = { |
| 161 | .usecase = scm_pas_bw_tbl, |
| 162 | .num_usecases = ARRAY_SIZE(scm_pas_bw_tbl), |
| 163 | .name = "scm_pas", |
| 164 | }; |
| 165 | |
| 166 | static uint32_t scm_perf_client; |
| 167 | static int scm_pas_bw_count; |
| 168 | static DEFINE_MUTEX(scm_pas_bw_mutex); |
| 169 | |
| 170 | static int scm_pas_enable_bw(void) |
| 171 | { |
| 172 | int ret = 0; |
| 173 | |
| 174 | if (!scm_perf_client) |
| 175 | return -EINVAL; |
| 176 | |
| 177 | mutex_lock(&scm_pas_bw_mutex); |
| 178 | if (!scm_pas_bw_count) { |
| 179 | ret = msm_bus_scale_client_update_request(scm_perf_client, 1); |
| 180 | if (ret) |
| 181 | goto err_bus; |
| 182 | scm_pas_bw_count++; |
| 183 | } |
| 184 | |
| 185 | mutex_unlock(&scm_pas_bw_mutex); |
| 186 | return ret; |
| 187 | |
| 188 | err_bus: |
| 189 | pr_err("scm-pas; Bandwidth request failed (%d)\n", ret); |
| 190 | msm_bus_scale_client_update_request(scm_perf_client, 0); |
| 191 | |
| 192 | mutex_unlock(&scm_pas_bw_mutex); |
| 193 | return ret; |
| 194 | } |
| 195 | |
| 196 | static void scm_pas_disable_bw(void) |
| 197 | { |
| 198 | mutex_lock(&scm_pas_bw_mutex); |
| 199 | if (scm_pas_bw_count-- == 1) |
| 200 | msm_bus_scale_client_update_request(scm_perf_client, 0); |
| 201 | mutex_unlock(&scm_pas_bw_mutex); |
| 202 | } |
| 203 | |
| 204 | static void scm_pas_init(int id) |
| 205 | { |
| 206 | static int is_inited; |
| 207 | |
| 208 | if (is_inited) |
| 209 | return; |
| 210 | |
| 211 | scm_pas_bw_tbl[0].vectors[0].src = id; |
| 212 | scm_pas_bw_tbl[1].vectors[0].src = id; |
| 213 | |
| 214 | scm_perf_client = msm_bus_scale_register_client(&scm_pas_bus_pdata); |
| 215 | if (!scm_perf_client) |
| 216 | pr_warn("scm-pas: Unable to register bus client\n"); |
| 217 | |
| 218 | is_inited = 1; |
| 219 | } |
| 220 | |
| 221 | static int of_read_clocks(struct device *dev, struct clk ***clks_ref, |
| 222 | const char *propname) |
| 223 | { |
| 224 | long clk_count; |
| 225 | int i, len; |
| 226 | struct clk **clks; |
| 227 | |
| 228 | if (!of_find_property(dev->of_node, propname, &len)) |
| 229 | return 0; |
| 230 | |
| 231 | clk_count = of_property_count_strings(dev->of_node, propname); |
| 232 | if (IS_ERR_VALUE(clk_count)) { |
| 233 | dev_err(dev, "Failed to get clock names\n"); |
| 234 | return -EINVAL; |
| 235 | } |
| 236 | |
| 237 | clks = devm_kzalloc(dev, sizeof(struct clk *) * clk_count, |
| 238 | GFP_KERNEL); |
| 239 | if (!clks) |
| 240 | return -ENOMEM; |
| 241 | |
| 242 | for (i = 0; i < clk_count; i++) { |
| 243 | const char *clock_name; |
| 244 | char clock_freq_name[50]; |
| 245 | u32 clock_rate = XO_FREQ; |
| 246 | |
| 247 | of_property_read_string_index(dev->of_node, |
| 248 | propname, i, |
| 249 | &clock_name); |
| 250 | snprintf(clock_freq_name, ARRAY_SIZE(clock_freq_name), |
| 251 | "qcom,%s-freq", clock_name); |
| 252 | if (of_find_property(dev->of_node, clock_freq_name, &len)) |
| 253 | if (of_property_read_u32(dev->of_node, clock_freq_name, |
| 254 | &clock_rate)) { |
| 255 | dev_err(dev, "Failed to read %s clock's freq\n", |
| 256 | clock_freq_name); |
| 257 | return -EINVAL; |
| 258 | } |
| 259 | |
| 260 | clks[i] = devm_clk_get(dev, clock_name); |
| 261 | if (IS_ERR(clks[i])) { |
| 262 | int rc = PTR_ERR(clks[i]); |
| 263 | |
| 264 | if (rc != -EPROBE_DEFER) |
| 265 | dev_err(dev, "Failed to get %s clock\n", |
| 266 | clock_name); |
| 267 | return rc; |
| 268 | } |
| 269 | |
| 270 | /* Make sure rate-settable clocks' rates are set */ |
| 271 | if (clk_get_rate(clks[i]) == 0) |
| 272 | clk_set_rate(clks[i], clk_round_rate(clks[i], |
| 273 | clock_rate)); |
| 274 | } |
| 275 | |
| 276 | *clks_ref = clks; |
| 277 | return clk_count; |
| 278 | } |
| 279 | |
| 280 | static int of_read_regs(struct device *dev, struct reg_info **regs_ref, |
| 281 | const char *propname) |
| 282 | { |
| 283 | long reg_count; |
| 284 | int i, len, rc; |
| 285 | struct reg_info *regs; |
| 286 | |
| 287 | if (!of_find_property(dev->of_node, propname, &len)) |
| 288 | return 0; |
| 289 | |
| 290 | reg_count = of_property_count_strings(dev->of_node, propname); |
| 291 | if (IS_ERR_VALUE(reg_count)) { |
| 292 | dev_err(dev, "Failed to get regulator names\n"); |
| 293 | return -EINVAL; |
| 294 | } |
| 295 | |
| 296 | regs = devm_kzalloc(dev, sizeof(struct reg_info) * reg_count, |
| 297 | GFP_KERNEL); |
| 298 | if (!regs) |
| 299 | return -ENOMEM; |
| 300 | |
| 301 | for (i = 0; i < reg_count; i++) { |
| 302 | const char *reg_name; |
| 303 | char reg_uV_uA_name[50]; |
| 304 | u32 vdd_uV_uA[2]; |
| 305 | |
| 306 | of_property_read_string_index(dev->of_node, |
| 307 | propname, i, |
| 308 | ®_name); |
| 309 | |
| 310 | regs[i].reg = devm_regulator_get(dev, reg_name); |
| 311 | if (IS_ERR(regs[i].reg)) { |
| 312 | int rc = PTR_ERR(regs[i].reg); |
| 313 | |
| 314 | if (rc != -EPROBE_DEFER) |
| 315 | dev_err(dev, "Failed to get %s\n regulator", |
| 316 | reg_name); |
| 317 | return rc; |
| 318 | } |
| 319 | |
| 320 | /* |
| 321 | * Read the voltage and current values for the corresponding |
| 322 | * regulator. The device tree property name is "qcom," + |
| 323 | * "regulator_name" + "-uV-uA". |
| 324 | */ |
| 325 | rc = snprintf(reg_uV_uA_name, ARRAY_SIZE(reg_uV_uA_name), |
| 326 | "qcom,%s-uV-uA", reg_name); |
| 327 | if (rc < strlen(reg_name) + 6) { |
| 328 | dev_err(dev, "Failed to hold reg_uV_uA_name\n"); |
| 329 | return -EINVAL; |
| 330 | } |
| 331 | |
| 332 | if (!of_find_property(dev->of_node, reg_uV_uA_name, &len)) |
| 333 | continue; |
| 334 | |
| 335 | len /= sizeof(vdd_uV_uA[0]); |
| 336 | |
| 337 | /* There should be two entries: one for uV and one for uA */ |
| 338 | if (len != 2) { |
| 339 | dev_err(dev, "Missing uV/uA value\n"); |
| 340 | return -EINVAL; |
| 341 | } |
| 342 | |
| 343 | rc = of_property_read_u32_array(dev->of_node, reg_uV_uA_name, |
| 344 | vdd_uV_uA, len); |
| 345 | if (rc) { |
| 346 | dev_err(dev, "Failed to read uV/uA values(rc:%d)\n", |
| 347 | rc); |
| 348 | return rc; |
| 349 | } |
| 350 | |
| 351 | regs[i].uV = vdd_uV_uA[0]; |
| 352 | regs[i].uA = vdd_uV_uA[1]; |
| 353 | } |
| 354 | |
| 355 | *regs_ref = regs; |
| 356 | return reg_count; |
| 357 | } |
| 358 | |
| 359 | static int of_read_bus_pdata(struct platform_device *pdev, |
| 360 | struct pil_tz_data *d) |
| 361 | { |
| 362 | struct msm_bus_scale_pdata *pdata; |
| 363 | |
| 364 | pdata = msm_bus_cl_get_pdata(pdev); |
| 365 | |
| 366 | if (!pdata) |
| 367 | return -EINVAL; |
| 368 | |
| 369 | d->bus_client = msm_bus_scale_register_client(pdata); |
| 370 | if (!d->bus_client) |
| 371 | pr_warn("%s: Unable to register bus client\n", __func__); |
| 372 | |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static int piltz_resc_init(struct platform_device *pdev, struct pil_tz_data *d) |
| 377 | { |
| 378 | int len, count, rc; |
| 379 | struct device *dev = &pdev->dev; |
| 380 | |
| 381 | count = of_read_clocks(dev, &d->clks, "qcom,active-clock-names"); |
| 382 | if (count < 0) { |
| 383 | dev_err(dev, "Failed to setup clocks.\n"); |
| 384 | return count; |
| 385 | } |
| 386 | d->clk_count = count; |
| 387 | |
| 388 | count = of_read_clocks(dev, &d->proxy_clks, "qcom,proxy-clock-names"); |
| 389 | if (count < 0) { |
| 390 | dev_err(dev, "Failed to setup proxy clocks.\n"); |
| 391 | return count; |
| 392 | } |
| 393 | d->proxy_clk_count = count; |
| 394 | |
| 395 | count = of_read_regs(dev, &d->regs, "qcom,active-reg-names"); |
| 396 | if (count < 0) { |
| 397 | dev_err(dev, "Failed to setup regulators.\n"); |
| 398 | return count; |
| 399 | } |
| 400 | d->reg_count = count; |
| 401 | |
| 402 | count = of_read_regs(dev, &d->proxy_regs, "qcom,proxy-reg-names"); |
| 403 | if (count < 0) { |
| 404 | dev_err(dev, "Failed to setup proxy regulators.\n"); |
| 405 | return count; |
| 406 | } |
| 407 | d->proxy_reg_count = count; |
| 408 | |
| 409 | if (of_find_property(dev->of_node, "qcom,msm-bus,name", &len)) { |
| 410 | d->enable_bus_scaling = true; |
| 411 | rc = of_read_bus_pdata(pdev, d); |
| 412 | if (rc) { |
| 413 | dev_err(dev, "Failed to setup bus scaling client.\n"); |
| 414 | return rc; |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static int enable_regulators(struct pil_tz_data *d, struct device *dev, |
| 422 | struct reg_info *regs, int reg_count, |
| 423 | bool reg_no_enable) |
| 424 | { |
| 425 | int i, rc = 0; |
| 426 | |
| 427 | for (i = 0; i < reg_count; i++) { |
| 428 | if (regs[i].uV > 0) { |
| 429 | rc = regulator_set_voltage(regs[i].reg, |
| 430 | regs[i].uV, INT_MAX); |
| 431 | if (rc) { |
| 432 | dev_err(dev, "Failed to request voltage(rc:%d)\n", |
| 433 | rc); |
| 434 | goto err_voltage; |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | if (regs[i].uA > 0) { |
| 439 | rc = regulator_set_load(regs[i].reg, |
| 440 | regs[i].uA); |
| 441 | if (rc < 0) { |
| 442 | dev_err(dev, "Failed to set regulator mode(rc:%d)\n", |
| 443 | rc); |
| 444 | goto err_mode; |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | if (d->keep_proxy_regs_on && reg_no_enable) |
| 449 | continue; |
| 450 | |
| 451 | rc = regulator_enable(regs[i].reg); |
| 452 | if (rc) { |
| 453 | dev_err(dev, "Regulator enable failed(rc:%d)\n", rc); |
| 454 | goto err_enable; |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | return 0; |
| 459 | err_enable: |
| 460 | if (regs[i].uA > 0) { |
| 461 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); |
| 462 | regulator_set_load(regs[i].reg, 0); |
| 463 | } |
| 464 | err_mode: |
| 465 | if (regs[i].uV > 0) |
| 466 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); |
| 467 | err_voltage: |
| 468 | for (i--; i >= 0; i--) { |
| 469 | if (regs[i].uV > 0) |
| 470 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); |
| 471 | |
| 472 | if (regs[i].uA > 0) |
| 473 | regulator_set_load(regs[i].reg, 0); |
| 474 | |
| 475 | if (d->keep_proxy_regs_on && reg_no_enable) |
| 476 | continue; |
| 477 | regulator_disable(regs[i].reg); |
| 478 | } |
| 479 | |
| 480 | return rc; |
| 481 | } |
| 482 | |
| 483 | static void disable_regulators(struct pil_tz_data *d, struct reg_info *regs, |
| 484 | int reg_count, bool reg_no_disable) |
| 485 | { |
| 486 | int i; |
| 487 | |
| 488 | for (i = 0; i < reg_count; i++) { |
| 489 | if (regs[i].uV > 0) |
| 490 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); |
| 491 | |
| 492 | if (regs[i].uA > 0) |
| 493 | regulator_set_load(regs[i].reg, 0); |
| 494 | |
| 495 | if (d->keep_proxy_regs_on && reg_no_disable) |
| 496 | continue; |
| 497 | regulator_disable(regs[i].reg); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | static int prepare_enable_clocks(struct device *dev, struct clk **clks, |
| 502 | int clk_count) |
| 503 | { |
| 504 | int rc = 0; |
| 505 | int i; |
| 506 | |
| 507 | for (i = 0; i < clk_count; i++) { |
| 508 | rc = clk_prepare_enable(clks[i]); |
| 509 | if (rc) { |
| 510 | dev_err(dev, "Clock enable failed(rc:%d)\n", rc); |
| 511 | goto err; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | return 0; |
| 516 | err: |
| 517 | for (i--; i >= 0; i--) |
| 518 | clk_disable_unprepare(clks[i]); |
| 519 | |
| 520 | return rc; |
| 521 | } |
| 522 | |
| 523 | static void disable_unprepare_clocks(struct clk **clks, int clk_count) |
| 524 | { |
| 525 | int i; |
| 526 | |
| 527 | for (i = --clk_count; i >= 0; i--) |
| 528 | clk_disable_unprepare(clks[i]); |
| 529 | } |
| 530 | |
| 531 | static int pil_make_proxy_vote(struct pil_desc *pil) |
| 532 | { |
| 533 | struct pil_tz_data *d = desc_to_data(pil); |
| 534 | int rc; |
| 535 | |
| 536 | if (d->subsys_desc.no_auth) |
| 537 | return 0; |
| 538 | |
Kyle Yan | f995ef6 | 2017-04-13 19:13:39 -0700 | [diff] [blame] | 539 | if (d->bus_client) { |
| 540 | rc = msm_bus_scale_client_update_request(d->bus_client, 1); |
| 541 | if (rc) { |
| 542 | dev_err(pil->dev, "bandwidth request failed(rc:%d)\n", |
| 543 | rc); |
| 544 | return rc; |
| 545 | } |
| 546 | } else |
| 547 | WARN(d->enable_bus_scaling, "Bus scaling not set up for %s!\n", |
| 548 | d->subsys_desc.name); |
| 549 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 550 | rc = enable_regulators(d, pil->dev, d->proxy_regs, |
| 551 | d->proxy_reg_count, false); |
| 552 | if (rc) |
| 553 | return rc; |
| 554 | |
| 555 | rc = prepare_enable_clocks(pil->dev, d->proxy_clks, |
| 556 | d->proxy_clk_count); |
| 557 | if (rc) |
| 558 | goto err_clks; |
| 559 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 560 | return 0; |
Kyle Yan | f995ef6 | 2017-04-13 19:13:39 -0700 | [diff] [blame] | 561 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 562 | err_clks: |
| 563 | disable_regulators(d, d->proxy_regs, d->proxy_reg_count, false); |
| 564 | |
| 565 | return rc; |
| 566 | } |
| 567 | |
| 568 | static void pil_remove_proxy_vote(struct pil_desc *pil) |
| 569 | { |
| 570 | struct pil_tz_data *d = desc_to_data(pil); |
| 571 | |
| 572 | if (d->subsys_desc.no_auth) |
| 573 | return; |
| 574 | |
Kyle Yan | f995ef6 | 2017-04-13 19:13:39 -0700 | [diff] [blame] | 575 | disable_unprepare_clocks(d->proxy_clks, d->proxy_clk_count); |
| 576 | |
| 577 | disable_regulators(d, d->proxy_regs, d->proxy_reg_count, true); |
| 578 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 579 | if (d->bus_client) |
| 580 | msm_bus_scale_client_update_request(d->bus_client, 0); |
| 581 | else |
| 582 | WARN(d->enable_bus_scaling, "Bus scaling not set up for %s!\n", |
| 583 | d->subsys_desc.name); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | static int pil_init_image_trusted(struct pil_desc *pil, |
| 587 | const u8 *metadata, size_t size) |
| 588 | { |
| 589 | struct pil_tz_data *d = desc_to_data(pil); |
| 590 | struct pas_init_image_req { |
| 591 | u32 proc; |
| 592 | u32 image_addr; |
| 593 | } request; |
| 594 | u32 scm_ret = 0; |
| 595 | void *mdata_buf; |
| 596 | dma_addr_t mdata_phys; |
| 597 | int ret; |
| 598 | unsigned long attrs = 0; |
| 599 | struct device dev = {0}; |
| 600 | struct scm_desc desc = {0}; |
| 601 | |
| 602 | if (d->subsys_desc.no_auth) |
| 603 | return 0; |
| 604 | |
| 605 | ret = scm_pas_enable_bw(); |
| 606 | if (ret) |
| 607 | return ret; |
| 608 | arch_setup_dma_ops(&dev, 0, 0, NULL, 0); |
| 609 | |
| 610 | dev.coherent_dma_mask = |
| 611 | DMA_BIT_MASK(sizeof(dma_addr_t) * 8); |
| 612 | attrs |= DMA_ATTR_STRONGLY_ORDERED; |
| 613 | mdata_buf = dma_alloc_attrs(&dev, size, &mdata_phys, GFP_KERNEL, |
| 614 | attrs); |
| 615 | if (!mdata_buf) { |
| 616 | pr_err("scm-pas: Allocation for metadata failed.\n"); |
| 617 | scm_pas_disable_bw(); |
| 618 | return -ENOMEM; |
| 619 | } |
| 620 | |
| 621 | memcpy(mdata_buf, metadata, size); |
| 622 | |
| 623 | request.proc = d->pas_id; |
| 624 | request.image_addr = mdata_phys; |
| 625 | |
| 626 | if (!is_scm_armv8()) { |
| 627 | ret = scm_call(SCM_SVC_PIL, PAS_INIT_IMAGE_CMD, &request, |
| 628 | sizeof(request), &scm_ret, sizeof(scm_ret)); |
| 629 | } else { |
| 630 | desc.args[0] = d->pas_id; |
| 631 | desc.args[1] = mdata_phys; |
| 632 | desc.arginfo = SCM_ARGS(2, SCM_VAL, SCM_RW); |
| 633 | ret = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, PAS_INIT_IMAGE_CMD), |
| 634 | &desc); |
| 635 | scm_ret = desc.ret[0]; |
| 636 | } |
| 637 | |
| 638 | dma_free_attrs(&dev, size, mdata_buf, mdata_phys, attrs); |
| 639 | scm_pas_disable_bw(); |
| 640 | if (ret) |
| 641 | return ret; |
| 642 | return scm_ret; |
| 643 | } |
| 644 | |
| 645 | static int pil_mem_setup_trusted(struct pil_desc *pil, phys_addr_t addr, |
| 646 | size_t size) |
| 647 | { |
| 648 | struct pil_tz_data *d = desc_to_data(pil); |
| 649 | struct pas_init_image_req { |
| 650 | u32 proc; |
| 651 | u32 start_addr; |
| 652 | u32 len; |
| 653 | } request; |
| 654 | u32 scm_ret = 0; |
| 655 | int ret; |
| 656 | struct scm_desc desc = {0}; |
| 657 | |
| 658 | if (d->subsys_desc.no_auth) |
| 659 | return 0; |
| 660 | |
| 661 | request.proc = d->pas_id; |
| 662 | request.start_addr = addr; |
| 663 | request.len = size; |
| 664 | |
| 665 | if (!is_scm_armv8()) { |
| 666 | ret = scm_call(SCM_SVC_PIL, PAS_MEM_SETUP_CMD, &request, |
| 667 | sizeof(request), &scm_ret, sizeof(scm_ret)); |
| 668 | } else { |
| 669 | desc.args[0] = d->pas_id; |
| 670 | desc.args[1] = addr; |
| 671 | desc.args[2] = size; |
| 672 | desc.arginfo = SCM_ARGS(3); |
| 673 | ret = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, PAS_MEM_SETUP_CMD), |
| 674 | &desc); |
| 675 | scm_ret = desc.ret[0]; |
| 676 | } |
| 677 | if (ret) |
| 678 | return ret; |
| 679 | return scm_ret; |
| 680 | } |
| 681 | |
| 682 | static int pil_auth_and_reset(struct pil_desc *pil) |
| 683 | { |
| 684 | struct pil_tz_data *d = desc_to_data(pil); |
| 685 | int rc; |
| 686 | u32 proc, scm_ret = 0; |
| 687 | struct scm_desc desc = {0}; |
| 688 | |
| 689 | if (d->subsys_desc.no_auth) |
| 690 | return 0; |
| 691 | |
| 692 | desc.args[0] = proc = d->pas_id; |
| 693 | desc.arginfo = SCM_ARGS(1); |
| 694 | |
Kyle Yan | f995ef6 | 2017-04-13 19:13:39 -0700 | [diff] [blame] | 695 | rc = scm_pas_enable_bw(); |
| 696 | if (rc) |
| 697 | return rc; |
| 698 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 699 | rc = enable_regulators(d, pil->dev, d->regs, d->reg_count, false); |
| 700 | if (rc) |
| 701 | return rc; |
| 702 | |
| 703 | rc = prepare_enable_clocks(pil->dev, d->clks, d->clk_count); |
| 704 | if (rc) |
| 705 | goto err_clks; |
| 706 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 707 | if (!is_scm_armv8()) { |
| 708 | rc = scm_call(SCM_SVC_PIL, PAS_AUTH_AND_RESET_CMD, &proc, |
| 709 | sizeof(proc), &scm_ret, sizeof(scm_ret)); |
| 710 | } else { |
| 711 | rc = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, |
| 712 | PAS_AUTH_AND_RESET_CMD), &desc); |
| 713 | scm_ret = desc.ret[0]; |
| 714 | } |
| 715 | scm_pas_disable_bw(); |
| 716 | if (rc) |
| 717 | goto err_reset; |
| 718 | |
| 719 | return scm_ret; |
| 720 | err_reset: |
| 721 | disable_unprepare_clocks(d->clks, d->clk_count); |
| 722 | err_clks: |
| 723 | disable_regulators(d, d->regs, d->reg_count, false); |
| 724 | |
| 725 | return rc; |
| 726 | } |
| 727 | |
| 728 | static int pil_shutdown_trusted(struct pil_desc *pil) |
| 729 | { |
| 730 | struct pil_tz_data *d = desc_to_data(pil); |
| 731 | u32 proc, scm_ret = 0; |
| 732 | int rc; |
| 733 | struct scm_desc desc = {0}; |
| 734 | |
| 735 | if (d->subsys_desc.no_auth) |
| 736 | return 0; |
| 737 | |
| 738 | desc.args[0] = proc = d->pas_id; |
| 739 | desc.arginfo = SCM_ARGS(1); |
| 740 | |
Kyle Yan | 5cb0e08 | 2017-04-21 18:13:25 -0700 | [diff] [blame] | 741 | if (d->bus_client) { |
| 742 | rc = msm_bus_scale_client_update_request(d->bus_client, 1); |
| 743 | if (rc) { |
| 744 | dev_err(pil->dev, "bandwidth request failed(rc:%d)\n", |
| 745 | rc); |
| 746 | return rc; |
| 747 | } |
| 748 | } else |
| 749 | WARN(d->enable_bus_scaling, "Bus scaling not set up for %s!\n", |
| 750 | d->subsys_desc.name); |
| 751 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 752 | rc = enable_regulators(d, pil->dev, d->proxy_regs, |
| 753 | d->proxy_reg_count, true); |
| 754 | if (rc) |
Kyle Yan | 5cb0e08 | 2017-04-21 18:13:25 -0700 | [diff] [blame] | 755 | goto err_regulators; |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 756 | |
| 757 | rc = prepare_enable_clocks(pil->dev, d->proxy_clks, |
| 758 | d->proxy_clk_count); |
| 759 | if (rc) |
| 760 | goto err_clks; |
| 761 | |
| 762 | if (!is_scm_armv8()) { |
| 763 | rc = scm_call(SCM_SVC_PIL, PAS_SHUTDOWN_CMD, &proc, |
| 764 | sizeof(proc), &scm_ret, sizeof(scm_ret)); |
| 765 | } else { |
| 766 | rc = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, PAS_SHUTDOWN_CMD), |
| 767 | &desc); |
| 768 | scm_ret = desc.ret[0]; |
| 769 | } |
| 770 | |
| 771 | disable_unprepare_clocks(d->proxy_clks, d->proxy_clk_count); |
| 772 | disable_regulators(d, d->proxy_regs, d->proxy_reg_count, false); |
Kyle Yan | 5cb0e08 | 2017-04-21 18:13:25 -0700 | [diff] [blame] | 773 | if (d->bus_client) |
| 774 | msm_bus_scale_client_update_request(d->bus_client, 0); |
| 775 | else |
| 776 | WARN(d->enable_bus_scaling, "Bus scaling not set up for %s!\n", |
| 777 | d->subsys_desc.name); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 778 | |
| 779 | if (rc) |
| 780 | return rc; |
| 781 | |
| 782 | disable_unprepare_clocks(d->clks, d->clk_count); |
| 783 | disable_regulators(d, d->regs, d->reg_count, false); |
| 784 | |
| 785 | return scm_ret; |
Kyle Yan | 5cb0e08 | 2017-04-21 18:13:25 -0700 | [diff] [blame] | 786 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 787 | err_clks: |
| 788 | disable_regulators(d, d->proxy_regs, d->proxy_reg_count, false); |
Kyle Yan | 5cb0e08 | 2017-04-21 18:13:25 -0700 | [diff] [blame] | 789 | err_regulators: |
| 790 | if (d->bus_client) |
| 791 | msm_bus_scale_client_update_request(d->bus_client, 0); |
| 792 | else |
| 793 | WARN(d->enable_bus_scaling, "Bus scaling not set up for %s!\n", |
| 794 | d->subsys_desc.name); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 795 | return rc; |
| 796 | } |
| 797 | |
| 798 | static struct pil_reset_ops pil_ops_trusted = { |
| 799 | .init_image = pil_init_image_trusted, |
| 800 | .mem_setup = pil_mem_setup_trusted, |
| 801 | .auth_and_reset = pil_auth_and_reset, |
| 802 | .shutdown = pil_shutdown_trusted, |
| 803 | .proxy_vote = pil_make_proxy_vote, |
| 804 | .proxy_unvote = pil_remove_proxy_vote, |
| 805 | }; |
| 806 | |
| 807 | static void log_failure_reason(const struct pil_tz_data *d) |
| 808 | { |
| 809 | u32 size; |
| 810 | char *smem_reason, reason[MAX_SSR_REASON_LEN]; |
| 811 | const char *name = d->subsys_desc.name; |
| 812 | |
| 813 | if (d->smem_id == -1) |
| 814 | return; |
| 815 | |
| 816 | smem_reason = smem_get_entry_no_rlock(d->smem_id, &size, 0, |
| 817 | SMEM_ANY_HOST_FLAG); |
| 818 | if (!smem_reason || !size) { |
| 819 | pr_err("%s SFR: (unknown, smem_get_entry_no_rlock failed).\n", |
| 820 | name); |
| 821 | return; |
| 822 | } |
| 823 | if (!smem_reason[0]) { |
| 824 | pr_err("%s SFR: (unknown, empty string found).\n", name); |
| 825 | return; |
| 826 | } |
| 827 | |
| 828 | strlcpy(reason, smem_reason, min(size, MAX_SSR_REASON_LEN)); |
| 829 | pr_err("%s subsystem failure reason: %s.\n", name, reason); |
| 830 | |
| 831 | smem_reason[0] = '\0'; |
| 832 | wmb(); |
| 833 | } |
| 834 | |
| 835 | static int subsys_shutdown(const struct subsys_desc *subsys, bool force_stop) |
| 836 | { |
| 837 | struct pil_tz_data *d = subsys_to_data(subsys); |
| 838 | int ret; |
| 839 | |
| 840 | if (!subsys_get_crash_status(d->subsys) && force_stop && |
| 841 | subsys->force_stop_gpio) { |
| 842 | gpio_set_value(subsys->force_stop_gpio, 1); |
| 843 | ret = wait_for_completion_timeout(&d->stop_ack, |
| 844 | msecs_to_jiffies(STOP_ACK_TIMEOUT_MS)); |
| 845 | if (!ret) |
| 846 | pr_warn("Timed out on stop ack from %s.\n", |
| 847 | subsys->name); |
| 848 | gpio_set_value(subsys->force_stop_gpio, 0); |
| 849 | } |
| 850 | |
| 851 | pil_shutdown(&d->desc); |
| 852 | return 0; |
| 853 | } |
| 854 | |
| 855 | static int subsys_powerup(const struct subsys_desc *subsys) |
| 856 | { |
| 857 | struct pil_tz_data *d = subsys_to_data(subsys); |
| 858 | int ret = 0; |
| 859 | |
| 860 | if (subsys->stop_ack_irq) |
| 861 | reinit_completion(&d->stop_ack); |
| 862 | |
| 863 | d->desc.fw_name = subsys->fw_name; |
| 864 | ret = pil_boot(&d->desc); |
| 865 | |
| 866 | return ret; |
| 867 | } |
| 868 | |
| 869 | static int subsys_ramdump(int enable, const struct subsys_desc *subsys) |
| 870 | { |
| 871 | struct pil_tz_data *d = subsys_to_data(subsys); |
| 872 | |
| 873 | if (!enable) |
| 874 | return 0; |
| 875 | |
| 876 | return pil_do_ramdump(&d->desc, d->ramdump_dev); |
| 877 | } |
| 878 | |
| 879 | static void subsys_free_memory(const struct subsys_desc *subsys) |
| 880 | { |
| 881 | struct pil_tz_data *d = subsys_to_data(subsys); |
| 882 | |
| 883 | pil_free_memory(&d->desc); |
| 884 | } |
| 885 | |
| 886 | static void subsys_crash_shutdown(const struct subsys_desc *subsys) |
| 887 | { |
| 888 | struct pil_tz_data *d = subsys_to_data(subsys); |
| 889 | |
| 890 | if (subsys->force_stop_gpio > 0 && |
| 891 | !subsys_get_crash_status(d->subsys)) { |
| 892 | gpio_set_value(subsys->force_stop_gpio, 1); |
| 893 | mdelay(CRASH_STOP_ACK_TO_MS); |
| 894 | } |
| 895 | } |
| 896 | |
| 897 | static irqreturn_t subsys_err_fatal_intr_handler (int irq, void *dev_id) |
| 898 | { |
| 899 | struct pil_tz_data *d = subsys_to_data(dev_id); |
| 900 | |
| 901 | pr_err("Fatal error on %s!\n", d->subsys_desc.name); |
| 902 | if (subsys_get_crash_status(d->subsys)) { |
| 903 | pr_err("%s: Ignoring error fatal, restart in progress\n", |
| 904 | d->subsys_desc.name); |
| 905 | return IRQ_HANDLED; |
| 906 | } |
Satya Durga Srinivasu Prabhala | 30af7d0 | 2016-12-15 13:33:39 -0800 | [diff] [blame] | 907 | subsys_set_crash_status(d->subsys, CRASH_STATUS_ERR_FATAL); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 908 | log_failure_reason(d); |
| 909 | subsystem_restart_dev(d->subsys); |
| 910 | |
| 911 | return IRQ_HANDLED; |
| 912 | } |
| 913 | |
| 914 | static irqreturn_t subsys_wdog_bite_irq_handler(int irq, void *dev_id) |
| 915 | { |
| 916 | struct pil_tz_data *d = subsys_to_data(dev_id); |
| 917 | |
| 918 | if (subsys_get_crash_status(d->subsys)) |
| 919 | return IRQ_HANDLED; |
| 920 | pr_err("Watchdog bite received from %s!\n", d->subsys_desc.name); |
| 921 | |
| 922 | if (d->subsys_desc.system_debug && |
| 923 | !gpio_get_value(d->subsys_desc.err_fatal_gpio)) |
| 924 | panic("%s: System ramdump requested. Triggering device restart!\n", |
| 925 | __func__); |
Satya Durga Srinivasu Prabhala | 30af7d0 | 2016-12-15 13:33:39 -0800 | [diff] [blame] | 926 | subsys_set_crash_status(d->subsys, CRASH_STATUS_WDOG_BITE); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 927 | log_failure_reason(d); |
| 928 | subsystem_restart_dev(d->subsys); |
| 929 | |
| 930 | return IRQ_HANDLED; |
| 931 | } |
| 932 | |
| 933 | static irqreturn_t subsys_stop_ack_intr_handler(int irq, void *dev_id) |
| 934 | { |
| 935 | struct pil_tz_data *d = subsys_to_data(dev_id); |
| 936 | |
| 937 | pr_info("Received stop ack interrupt from %s\n", d->subsys_desc.name); |
| 938 | complete(&d->stop_ack); |
| 939 | return IRQ_HANDLED; |
| 940 | } |
| 941 | |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 942 | static void clear_pbl_done(struct pil_tz_data *d) |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 943 | { |
| 944 | uint32_t err_value; |
| 945 | |
| 946 | err_value = __raw_readl(d->err_status); |
| 947 | pr_debug("PBL_DONE received from %s!\n", d->subsys_desc.name); |
| 948 | if (err_value) { |
| 949 | uint32_t rmb_err_spare0; |
| 950 | uint32_t rmb_err_spare1; |
| 951 | uint32_t rmb_err_spare2; |
| 952 | |
| 953 | rmb_err_spare2 = __raw_readl(d->err_status_spare); |
| 954 | rmb_err_spare1 = __raw_readl(d->err_status_spare-4); |
| 955 | rmb_err_spare0 = __raw_readl(d->err_status_spare-8); |
| 956 | |
| 957 | pr_err("PBL error status register: 0x%08x\n", err_value); |
| 958 | |
| 959 | pr_err("PBL error status spare0 register: 0x%08x\n", |
| 960 | rmb_err_spare0); |
| 961 | pr_err("PBL error status spare1 register: 0x%08x\n", |
| 962 | rmb_err_spare1); |
| 963 | pr_err("PBL error status spare2 register: 0x%08x\n", |
| 964 | rmb_err_spare2); |
| 965 | } |
| 966 | __raw_writel(BIT(d->bits_arr[PBL_DONE]), d->irq_clear); |
| 967 | } |
| 968 | |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 969 | static void clear_err_ready(struct pil_tz_data *d) |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 970 | { |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 971 | pr_debug("Subsystem error services up received from %s\n", |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 972 | d->subsys_desc.name); |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 973 | __raw_writel(BIT(d->bits_arr[ERR_READY]), d->irq_clear); |
| 974 | complete_err_ready(d->subsys); |
| 975 | } |
| 976 | |
| 977 | static void clear_wdog(struct pil_tz_data *d) |
| 978 | { |
| 979 | /* Check crash status to know if device is restarting*/ |
| 980 | if (!subsys_get_crash_status(d->subsys)) { |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 981 | pr_err("wdog bite received from %s!\n", d->subsys_desc.name); |
| 982 | __raw_writel(BIT(d->bits_arr[ERR_READY]), d->irq_clear); |
Satya Durga Srinivasu Prabhala | 30af7d0 | 2016-12-15 13:33:39 -0800 | [diff] [blame] | 983 | subsys_set_crash_status(d->subsys, CRASH_STATUS_WDOG_BITE); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 984 | log_failure_reason(d); |
| 985 | subsystem_restart_dev(d->subsys); |
| 986 | } |
| 987 | } |
| 988 | |
| 989 | static irqreturn_t subsys_generic_handler(int irq, void *dev_id) |
| 990 | { |
| 991 | struct pil_tz_data *d = subsys_to_data(dev_id); |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 992 | uint32_t status_val, err_value; |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 993 | |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 994 | err_value = __raw_readl(d->err_status_spare); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 995 | status_val = __raw_readl(d->irq_status); |
| 996 | |
Puja Gupta | 557f529 | 2016-11-28 14:01:03 -0800 | [diff] [blame] | 997 | if ((status_val & BIT(d->bits_arr[ERR_READY])) && !err_value) |
| 998 | clear_err_ready(d); |
| 999 | |
| 1000 | if ((status_val & BIT(d->bits_arr[ERR_READY])) && |
| 1001 | err_value == 0x44554d50) |
| 1002 | clear_wdog(d); |
| 1003 | |
| 1004 | if (status_val & BIT(d->bits_arr[PBL_DONE])) |
| 1005 | clear_pbl_done(d); |
| 1006 | |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 1007 | return IRQ_HANDLED; |
| 1008 | } |
| 1009 | |
| 1010 | static void mask_scsr_irqs(struct pil_tz_data *d) |
| 1011 | { |
| 1012 | uint32_t mask_val; |
| 1013 | /* Masking all interrupts not handled by HLOS */ |
| 1014 | mask_val = ~0; |
| 1015 | __raw_writel(mask_val & ~BIT(d->bits_arr[ERR_READY]) & |
| 1016 | ~BIT(d->bits_arr[PBL_DONE]), d->irq_mask); |
| 1017 | } |
| 1018 | |
| 1019 | static int pil_tz_driver_probe(struct platform_device *pdev) |
| 1020 | { |
| 1021 | struct pil_tz_data *d; |
| 1022 | struct resource *res; |
| 1023 | u32 proxy_timeout; |
| 1024 | int len, rc; |
| 1025 | |
| 1026 | d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); |
| 1027 | if (!d) |
| 1028 | return -ENOMEM; |
| 1029 | platform_set_drvdata(pdev, d); |
| 1030 | |
| 1031 | if (of_property_read_bool(pdev->dev.of_node, "qcom,pil-no-auth")) |
| 1032 | d->subsys_desc.no_auth = true; |
| 1033 | |
| 1034 | d->keep_proxy_regs_on = of_property_read_bool(pdev->dev.of_node, |
| 1035 | "qcom,keep-proxy-regs-on"); |
| 1036 | |
| 1037 | rc = of_property_read_string(pdev->dev.of_node, "qcom,firmware-name", |
| 1038 | &d->desc.name); |
| 1039 | if (rc) |
| 1040 | return rc; |
| 1041 | |
| 1042 | /* Defaulting smem_id to be not present */ |
| 1043 | d->smem_id = -1; |
| 1044 | |
| 1045 | if (of_find_property(pdev->dev.of_node, "qcom,smem-id", &len)) { |
| 1046 | rc = of_property_read_u32(pdev->dev.of_node, "qcom,smem-id", |
| 1047 | &d->smem_id); |
| 1048 | if (rc) { |
| 1049 | dev_err(&pdev->dev, "Failed to get the smem_id(rc:%d)\n", |
| 1050 | rc); |
| 1051 | return rc; |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | d->desc.dev = &pdev->dev; |
| 1056 | d->desc.owner = THIS_MODULE; |
| 1057 | d->desc.ops = &pil_ops_trusted; |
| 1058 | |
| 1059 | d->desc.proxy_timeout = PROXY_TIMEOUT_MS; |
Avaneesh Kumar Dwivedi | 7b506d2 | 2017-03-17 16:41:13 +0530 | [diff] [blame] | 1060 | d->desc.clear_fw_region = true; |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 1061 | |
| 1062 | rc = of_property_read_u32(pdev->dev.of_node, "qcom,proxy-timeout-ms", |
| 1063 | &proxy_timeout); |
| 1064 | if (!rc) |
| 1065 | d->desc.proxy_timeout = proxy_timeout; |
| 1066 | |
| 1067 | if (!d->subsys_desc.no_auth) { |
| 1068 | rc = piltz_resc_init(pdev, d); |
| 1069 | if (rc) |
Kyle Yan | 3d6600c | 2017-01-06 14:04:26 -0800 | [diff] [blame] | 1070 | return rc; |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 1071 | |
| 1072 | rc = of_property_read_u32(pdev->dev.of_node, "qcom,pas-id", |
| 1073 | &d->pas_id); |
| 1074 | if (rc) { |
| 1075 | dev_err(&pdev->dev, "Failed to find the pas_id(rc:%d)\n", |
| 1076 | rc); |
| 1077 | return rc; |
| 1078 | } |
Kyle Yan | 9f57f57 | 2017-03-28 10:31:54 -0700 | [diff] [blame] | 1079 | scm_pas_init(MSM_BUS_MASTER_CRYPTO_CORE_0); |
Kyle Yan | e45fa02 | 2016-08-29 11:40:26 -0700 | [diff] [blame] | 1080 | } |
| 1081 | |
| 1082 | rc = pil_desc_init(&d->desc); |
| 1083 | if (rc) |
| 1084 | return rc; |
| 1085 | |
| 1086 | init_completion(&d->stop_ack); |
| 1087 | |
| 1088 | d->subsys_desc.name = d->desc.name; |
| 1089 | d->subsys_desc.owner = THIS_MODULE; |
| 1090 | d->subsys_desc.dev = &pdev->dev; |
| 1091 | d->subsys_desc.shutdown = subsys_shutdown; |
| 1092 | d->subsys_desc.powerup = subsys_powerup; |
| 1093 | d->subsys_desc.ramdump = subsys_ramdump; |
| 1094 | d->subsys_desc.free_memory = subsys_free_memory; |
| 1095 | d->subsys_desc.crash_shutdown = subsys_crash_shutdown; |
| 1096 | if (of_property_read_bool(pdev->dev.of_node, |
| 1097 | "qcom,pil-generic-irq-handler")) { |
| 1098 | d->subsys_desc.generic_handler = subsys_generic_handler; |
| 1099 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1100 | "sp2soc_irq_status"); |
| 1101 | d->irq_status = devm_ioremap_resource(&pdev->dev, res); |
| 1102 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1103 | "sp2soc_irq_clr"); |
| 1104 | d->irq_clear = devm_ioremap_resource(&pdev->dev, res); |
| 1105 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1106 | "sp2soc_irq_mask"); |
| 1107 | d->irq_mask = devm_ioremap_resource(&pdev->dev, res); |
| 1108 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1109 | "rmb_err"); |
| 1110 | d->err_status = devm_ioremap_resource(&pdev->dev, res); |
| 1111 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1112 | "rmb_err_spare2"); |
| 1113 | d->err_status_spare = devm_ioremap_resource(&pdev->dev, res); |
| 1114 | rc = of_property_read_u32_array(pdev->dev.of_node, |
| 1115 | "qcom,spss-scsr-bits", d->bits_arr, sizeof(d->bits_arr)/ |
| 1116 | sizeof(d->bits_arr[0])); |
| 1117 | if (rc) |
| 1118 | dev_err(&pdev->dev, "Failed to read qcom,spss-scsr-bits"); |
| 1119 | mask_scsr_irqs(d); |
| 1120 | |
| 1121 | } else { |
| 1122 | d->subsys_desc.err_fatal_handler = |
| 1123 | subsys_err_fatal_intr_handler; |
| 1124 | d->subsys_desc.wdog_bite_handler = subsys_wdog_bite_irq_handler; |
| 1125 | d->subsys_desc.stop_ack_handler = subsys_stop_ack_intr_handler; |
| 1126 | } |
| 1127 | d->ramdump_dev = create_ramdump_device(d->subsys_desc.name, |
| 1128 | &pdev->dev); |
| 1129 | if (!d->ramdump_dev) { |
| 1130 | rc = -ENOMEM; |
| 1131 | goto err_ramdump; |
| 1132 | } |
| 1133 | |
| 1134 | d->subsys = subsys_register(&d->subsys_desc); |
| 1135 | if (IS_ERR(d->subsys)) { |
| 1136 | rc = PTR_ERR(d->subsys); |
| 1137 | goto err_subsys; |
| 1138 | } |
| 1139 | |
| 1140 | return 0; |
| 1141 | err_subsys: |
| 1142 | destroy_ramdump_device(d->ramdump_dev); |
| 1143 | err_ramdump: |
| 1144 | pil_desc_release(&d->desc); |
| 1145 | |
| 1146 | return rc; |
| 1147 | } |
| 1148 | |
| 1149 | static int pil_tz_driver_exit(struct platform_device *pdev) |
| 1150 | { |
| 1151 | struct pil_tz_data *d = platform_get_drvdata(pdev); |
| 1152 | |
| 1153 | subsys_unregister(d->subsys); |
| 1154 | destroy_ramdump_device(d->ramdump_dev); |
| 1155 | pil_desc_release(&d->desc); |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
| 1160 | static const struct of_device_id pil_tz_match_table[] = { |
| 1161 | {.compatible = "qcom,pil-tz-generic"}, |
| 1162 | {} |
| 1163 | }; |
| 1164 | |
| 1165 | static struct platform_driver pil_tz_driver = { |
| 1166 | .probe = pil_tz_driver_probe, |
| 1167 | .remove = pil_tz_driver_exit, |
| 1168 | .driver = { |
| 1169 | .name = "subsys-pil-tz", |
| 1170 | .of_match_table = pil_tz_match_table, |
| 1171 | .owner = THIS_MODULE, |
| 1172 | }, |
| 1173 | }; |
| 1174 | |
| 1175 | static int __init pil_tz_init(void) |
| 1176 | { |
| 1177 | return platform_driver_register(&pil_tz_driver); |
| 1178 | } |
| 1179 | module_init(pil_tz_init); |
| 1180 | |
| 1181 | static void __exit pil_tz_exit(void) |
| 1182 | { |
| 1183 | platform_driver_unregister(&pil_tz_driver); |
| 1184 | } |
| 1185 | module_exit(pil_tz_exit); |
| 1186 | |
| 1187 | MODULE_DESCRIPTION("Support for booting subsystems"); |
| 1188 | MODULE_LICENSE("GPL v2"); |