yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/fb.h> |
| 26 | #include "linux/delay.h" |
| 27 | #include "pp_acpi.h" |
| 28 | #include "hwmgr.h" |
| 29 | #include <atombios.h> |
| 30 | #include "tonga_hwmgr.h" |
| 31 | #include "pptable.h" |
| 32 | #include "processpptables.h" |
| 33 | #include "tonga_processpptables.h" |
| 34 | #include "tonga_pptable.h" |
| 35 | #include "pp_debug.h" |
| 36 | #include "tonga_ppsmc.h" |
| 37 | #include "cgs_common.h" |
| 38 | #include "pppcielanes.h" |
| 39 | #include "tonga_dyn_defaults.h" |
| 40 | #include "smumgr.h" |
| 41 | #include "tonga_smumgr.h" |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 42 | #include "tonga_clockpowergating.h" |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 43 | #include "tonga_thermal.h" |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 44 | |
| 45 | #include "smu/smu_7_1_2_d.h" |
| 46 | #include "smu/smu_7_1_2_sh_mask.h" |
| 47 | |
| 48 | #include "gmc/gmc_8_1_d.h" |
| 49 | #include "gmc/gmc_8_1_sh_mask.h" |
| 50 | |
| 51 | #include "bif/bif_5_0_d.h" |
| 52 | #include "bif/bif_5_0_sh_mask.h" |
| 53 | |
Alex Deucher | 7e8d1fb | 2016-04-08 16:42:38 -0400 | [diff] [blame] | 54 | #include "dce/dce_10_0_d.h" |
| 55 | #include "dce/dce_10_0_sh_mask.h" |
| 56 | |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 57 | #include "cgs_linux.h" |
| 58 | #include "eventmgr.h" |
Alex Deucher | 16881da | 2015-11-11 20:18:52 -0500 | [diff] [blame] | 59 | #include "amd_pcie_helpers.h" |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 60 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 61 | #define MC_CG_ARB_FREQ_F0 0x0a |
| 62 | #define MC_CG_ARB_FREQ_F1 0x0b |
| 63 | #define MC_CG_ARB_FREQ_F2 0x0c |
| 64 | #define MC_CG_ARB_FREQ_F3 0x0d |
| 65 | |
| 66 | #define MC_CG_SEQ_DRAMCONF_S0 0x05 |
| 67 | #define MC_CG_SEQ_DRAMCONF_S1 0x06 |
| 68 | #define MC_CG_SEQ_YCLK_SUSPEND 0x04 |
| 69 | #define MC_CG_SEQ_YCLK_RESUME 0x0a |
| 70 | |
| 71 | #define PCIE_BUS_CLK 10000 |
| 72 | #define TCLK (PCIE_BUS_CLK / 10) |
| 73 | |
| 74 | #define SMC_RAM_END 0x40000 |
| 75 | #define SMC_CG_IND_START 0xc0030000 |
| 76 | #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/ |
| 77 | |
| 78 | #define VOLTAGE_SCALE 4 |
| 79 | #define VOLTAGE_VID_OFFSET_SCALE1 625 |
| 80 | #define VOLTAGE_VID_OFFSET_SCALE2 100 |
| 81 | |
| 82 | #define VDDC_VDDCI_DELTA 200 |
| 83 | #define VDDC_VDDGFX_DELTA 300 |
| 84 | |
| 85 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 |
| 86 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 |
| 87 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 |
| 88 | |
| 89 | typedef uint32_t PECI_RegistryValue; |
| 90 | |
| 91 | /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 92 | static const uint16_t PP_ClockStretcherLookupTable[2][4] = { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 93 | {600, 1050, 3, 0}, |
| 94 | {600, 1050, 6, 1} }; |
| 95 | |
| 96 | /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 97 | static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 98 | { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, |
| 99 | { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; |
| 100 | |
| 101 | /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 102 | static const uint8_t PP_ClockStretchAmountConversion[2][6] = { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 103 | {0, 1, 3, 2, 4, 5}, |
| 104 | {0, 2, 4, 5, 6, 5} }; |
| 105 | |
| 106 | /* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ |
| 107 | enum DPM_EVENT_SRC { |
| 108 | DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */ |
| 109 | DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */ |
| 110 | DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */ |
| 111 | DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */ |
| 112 | DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */ |
| 113 | }; |
| 114 | typedef enum DPM_EVENT_SRC DPM_EVENT_SRC; |
| 115 | |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 116 | static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 117 | |
| 118 | struct tonga_power_state *cast_phw_tonga_power_state( |
| 119 | struct pp_hw_power_state *hw_ps) |
| 120 | { |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 121 | if (hw_ps == NULL) |
| 122 | return NULL; |
| 123 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 124 | PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), |
| 125 | "Invalid Powerstate Type!", |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 126 | return NULL); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 127 | |
| 128 | return (struct tonga_power_state *)hw_ps; |
| 129 | } |
| 130 | |
| 131 | const struct tonga_power_state *cast_const_phw_tonga_power_state( |
| 132 | const struct pp_hw_power_state *hw_ps) |
| 133 | { |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 134 | if (hw_ps == NULL) |
| 135 | return NULL; |
| 136 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 137 | PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), |
| 138 | "Invalid Powerstate Type!", |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 139 | return NULL); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 140 | |
| 141 | return (const struct tonga_power_state *)hw_ps; |
| 142 | } |
| 143 | |
| 144 | int tonga_add_voltage(struct pp_hwmgr *hwmgr, |
| 145 | phm_ppt_v1_voltage_lookup_table *look_up_table, |
| 146 | phm_ppt_v1_voltage_lookup_record *record) |
| 147 | { |
| 148 | uint32_t i; |
| 149 | PP_ASSERT_WITH_CODE((NULL != look_up_table), |
| 150 | "Lookup Table empty.", return -1;); |
| 151 | PP_ASSERT_WITH_CODE((0 != look_up_table->count), |
| 152 | "Lookup Table empty.", return -1;); |
| 153 | PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count), |
| 154 | "Lookup Table is full.", return -1;); |
| 155 | |
| 156 | /* This is to avoid entering duplicate calculated records. */ |
| 157 | for (i = 0; i < look_up_table->count; i++) { |
| 158 | if (look_up_table->entries[i].us_vdd == record->us_vdd) { |
| 159 | if (look_up_table->entries[i].us_calculated == 1) |
| 160 | return 0; |
| 161 | else |
| 162 | break; |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | look_up_table->entries[i].us_calculated = 1; |
| 167 | look_up_table->entries[i].us_vdd = record->us_vdd; |
| 168 | look_up_table->entries[i].us_cac_low = record->us_cac_low; |
| 169 | look_up_table->entries[i].us_cac_mid = record->us_cac_mid; |
| 170 | look_up_table->entries[i].us_cac_high = record->us_cac_high; |
| 171 | /* Only increment the count when we're appending, not replacing duplicate entry. */ |
| 172 | if (i == look_up_table->count) |
| 173 | look_up_table->count++; |
| 174 | |
| 175 | return 0; |
| 176 | } |
| 177 | |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 178 | int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) |
| 179 | { |
| 180 | PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; |
| 181 | |
| 182 | return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; |
| 183 | } |
| 184 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 185 | uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, |
| 186 | uint32_t voltage) |
| 187 | { |
| 188 | uint8_t count = (uint8_t) (voltage_table->count); |
| 189 | uint8_t i = 0; |
| 190 | |
| 191 | PP_ASSERT_WITH_CODE((NULL != voltage_table), |
| 192 | "Voltage Table empty.", return 0;); |
| 193 | PP_ASSERT_WITH_CODE((0 != count), |
| 194 | "Voltage Table empty.", return 0;); |
| 195 | |
| 196 | for (i = 0; i < count; i++) { |
| 197 | /* find first voltage bigger than requested */ |
| 198 | if (voltage_table->entries[i].value >= voltage) |
| 199 | return i; |
| 200 | } |
| 201 | |
| 202 | /* voltage is bigger than max voltage in the table */ |
| 203 | return i - 1; |
| 204 | } |
| 205 | |
| 206 | /** |
| 207 | * @brief PhwTonga_GetVoltageOrder |
| 208 | * Returns index of requested voltage record in lookup(table) |
| 209 | * @param hwmgr - pointer to hardware manager |
| 210 | * @param lookupTable - lookup list to search in |
| 211 | * @param voltage - voltage to look for |
| 212 | * @return 0 on success |
| 213 | */ |
| 214 | uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table, |
| 215 | uint16_t voltage) |
| 216 | { |
| 217 | uint8_t count = (uint8_t) (look_up_table->count); |
| 218 | uint8_t i; |
| 219 | |
| 220 | PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;); |
| 221 | PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;); |
| 222 | |
| 223 | for (i = 0; i < count; i++) { |
| 224 | /* find first voltage equal or bigger than requested */ |
| 225 | if (look_up_table->entries[i].us_vdd >= voltage) |
| 226 | return i; |
| 227 | } |
| 228 | |
| 229 | /* voltage is bigger than max voltage in the table */ |
| 230 | return i-1; |
| 231 | } |
| 232 | |
| 233 | bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) |
| 234 | { |
| 235 | /* |
| 236 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM |
| 237 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, |
| 238 | * whereas voltage control is a fundemental change that will not be disabled |
| 239 | */ |
| 240 | |
| 241 | return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 242 | FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0); |
| 243 | } |
| 244 | |
| 245 | /** |
| 246 | * Re-generate the DPM level mask value |
| 247 | * @param hwmgr the address of the hardware manager |
| 248 | */ |
| 249 | static uint32_t tonga_get_dpm_level_enable_mask_value( |
| 250 | struct tonga_single_dpm_table * dpm_table) |
| 251 | { |
| 252 | uint32_t i; |
| 253 | uint32_t mask_value = 0; |
| 254 | |
| 255 | for (i = dpm_table->count; i > 0; i--) { |
| 256 | mask_value = mask_value << 1; |
| 257 | |
| 258 | if (dpm_table->dpm_levels[i-1].enabled) |
| 259 | mask_value |= 0x1; |
| 260 | else |
| 261 | mask_value &= 0xFFFFFFFE; |
| 262 | } |
| 263 | return mask_value; |
| 264 | } |
| 265 | |
| 266 | /** |
| 267 | * Retrieve DPM default values from registry (if available) |
| 268 | * |
| 269 | * @param hwmgr the address of the powerplay hardware manager. |
| 270 | */ |
| 271 | void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) |
| 272 | { |
| 273 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 274 | phw_tonga_ulv_parm *ulv = &(data->ulv); |
| 275 | uint32_t tmp; |
| 276 | |
| 277 | ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT; |
| 278 | data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0; |
| 279 | data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1; |
| 280 | data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2; |
| 281 | data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3; |
| 282 | data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4; |
| 283 | data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5; |
| 284 | data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6; |
| 285 | data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7; |
| 286 | |
| 287 | data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT; |
| 288 | data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT; |
| 289 | |
| 290 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 291 | PHM_PlatformCaps_ABM); |
| 292 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 293 | PHM_PlatformCaps_NonABMSupportInPPLib); |
| 294 | |
| 295 | tmp = 0; |
| 296 | if (tmp == 0) |
| 297 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 298 | PHM_PlatformCaps_DynamicACTiming); |
| 299 | |
| 300 | tmp = 0; |
| 301 | if (0 != tmp) |
| 302 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 303 | PHM_PlatformCaps_DisableMemoryTransition); |
| 304 | |
| 305 | data->mclk_strobe_mode_threshold = 40000; |
| 306 | data->mclk_stutter_mode_threshold = 30000; |
| 307 | data->mclk_edc_enable_threshold = 40000; |
| 308 | data->mclk_edc_wr_enable_threshold = 40000; |
| 309 | |
| 310 | tmp = 0; |
| 311 | if (tmp != 0) |
| 312 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 313 | PHM_PlatformCaps_DisableMCLS); |
| 314 | |
| 315 | data->pcie_gen_performance.max = PP_PCIEGen1; |
| 316 | data->pcie_gen_performance.min = PP_PCIEGen3; |
| 317 | data->pcie_gen_power_saving.max = PP_PCIEGen1; |
| 318 | data->pcie_gen_power_saving.min = PP_PCIEGen3; |
| 319 | |
| 320 | data->pcie_lane_performance.max = 0; |
| 321 | data->pcie_lane_performance.min = 16; |
| 322 | data->pcie_lane_power_saving.max = 0; |
| 323 | data->pcie_lane_power_saving.min = 16; |
| 324 | |
| 325 | tmp = 0; |
| 326 | |
| 327 | if (tmp) |
| 328 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 329 | PHM_PlatformCaps_SclkThrottleLowNotification); |
| 330 | |
| 331 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 332 | PHM_PlatformCaps_DynamicUVDState); |
| 333 | |
| 334 | } |
| 335 | |
| 336 | int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) |
| 337 | { |
| 338 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 339 | |
| 340 | int result = 0; |
| 341 | uint32_t low_sclk_interrupt_threshold = 0; |
| 342 | |
| 343 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 344 | PHM_PlatformCaps_SclkThrottleLowNotification) |
| 345 | && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) { |
| 346 | data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold; |
| 347 | low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold; |
| 348 | |
| 349 | CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); |
| 350 | |
| 351 | result = tonga_copy_bytes_to_smc( |
| 352 | hwmgr->smumgr, |
| 353 | data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, |
| 354 | LowSclkInterruptThreshold), |
| 355 | (uint8_t *)&low_sclk_interrupt_threshold, |
| 356 | sizeof(uint32_t), |
| 357 | data->sram_end |
| 358 | ); |
| 359 | } |
| 360 | |
| 361 | return result; |
| 362 | } |
| 363 | |
| 364 | /** |
| 365 | * Find SCLK value that is associated with specified virtual_voltage_Id. |
| 366 | * |
| 367 | * @param hwmgr the address of the powerplay hardware manager. |
| 368 | * @param virtual_voltage_Id voltageId to look for. |
| 369 | * @param sclk output value . |
| 370 | * @return always 0 if success and 2 if association not found |
| 371 | */ |
| 372 | static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, |
| 373 | phm_ppt_v1_voltage_lookup_table *lookup_table, |
| 374 | uint16_t virtual_voltage_id, uint32_t *sclk) |
| 375 | { |
| 376 | uint8_t entryId; |
| 377 | uint8_t voltageId; |
| 378 | struct phm_ppt_v1_information *pptable_info = |
| 379 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 380 | |
| 381 | PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1); |
| 382 | |
| 383 | /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ |
| 384 | for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) { |
| 385 | voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd; |
| 386 | if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id) |
| 387 | break; |
| 388 | } |
| 389 | |
| 390 | PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count, |
| 391 | "Can't find requested voltage id in vdd_dep_on_sclk table!", |
| 392 | return -1; |
| 393 | ); |
| 394 | |
| 395 | *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk; |
| 396 | |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | /** |
| 401 | * Get Leakage VDDC based on leakage ID. |
| 402 | * |
| 403 | * @param hwmgr the address of the powerplay hardware manager. |
| 404 | * @return 2 if vddgfx returned is greater than 2V or if BIOS |
| 405 | */ |
| 406 | int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) |
| 407 | { |
| 408 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 409 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 410 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; |
| 411 | uint16_t virtual_voltage_id; |
| 412 | uint16_t vddc = 0; |
| 413 | uint16_t vddgfx = 0; |
| 414 | uint16_t i, j; |
| 415 | uint32_t sclk = 0; |
| 416 | |
| 417 | /* retrieve voltage for leakage ID (0xff01 + i) */ |
| 418 | for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) { |
| 419 | virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; |
| 420 | |
| 421 | /* in split mode we should have only vddgfx EVV leakages */ |
| 422 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 423 | if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, |
| 424 | pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) { |
| 425 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 426 | PHM_PlatformCaps_ClockStretcher)) { |
| 427 | for (j = 1; j < sclk_table->count; j++) { |
| 428 | if (sclk_table->entries[j].clk == sclk && |
| 429 | sclk_table->entries[j].cks_enable == 0) { |
| 430 | sclk += 5000; |
| 431 | break; |
| 432 | } |
| 433 | } |
| 434 | } |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 435 | if (0 == atomctrl_get_voltage_evv_on_sclk |
| 436 | (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, |
| 437 | virtual_voltage_id, &vddgfx)) { |
| 438 | /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ |
| 439 | PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 440 | |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 441 | /* the voltage should not be zero nor equal to leakage ID */ |
| 442 | if (vddgfx != 0 && vddgfx != virtual_voltage_id) { |
| 443 | data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; |
| 444 | data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id; |
| 445 | data->vddcgfx_leakage.count++; |
| 446 | } |
| 447 | } else { |
| 448 | printk("Error retrieving EVV voltage value!\n"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 449 | } |
| 450 | } |
| 451 | } else { |
| 452 | /* in merged mode we have only vddc EVV leakages */ |
| 453 | if (0 == tonga_get_sclk_for_voltage_evv(hwmgr, |
| 454 | pptable_info->vddc_lookup_table, |
| 455 | virtual_voltage_id, &sclk)) { |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 456 | if (0 == atomctrl_get_voltage_evv_on_sclk |
| 457 | (hwmgr, VOLTAGE_TYPE_VDDC, sclk, |
| 458 | virtual_voltage_id, &vddc)) { |
| 459 | /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ |
| 460 | PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 461 | |
Moritz Kühner | ac0cc35 | 2016-04-17 16:15:24 +0200 | [diff] [blame] | 462 | /* the voltage should not be zero nor equal to leakage ID */ |
| 463 | if (vddc != 0 && vddc != virtual_voltage_id) { |
| 464 | data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; |
| 465 | data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; |
| 466 | data->vddc_leakage.count++; |
| 467 | } |
| 468 | } else { |
| 469 | printk("Error retrieving EVV voltage value!\n"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 470 | } |
| 471 | } |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 479 | { |
| 480 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 481 | |
| 482 | /* enable SCLK dpm */ |
| 483 | if (0 == data->sclk_dpm_key_disabled) { |
| 484 | PP_ASSERT_WITH_CODE( |
| 485 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 486 | PPSMC_MSG_DPM_Enable)), |
| 487 | "Failed to enable SCLK DPM during DPM Start Function!", |
| 488 | return -1); |
| 489 | } |
| 490 | |
| 491 | /* enable MCLK dpm */ |
| 492 | if (0 == data->mclk_dpm_key_disabled) { |
| 493 | PP_ASSERT_WITH_CODE( |
| 494 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 495 | PPSMC_MSG_MCLKDPM_Enable)), |
| 496 | "Failed to enable MCLK DPM during DPM Start Function!", |
| 497 | return -1); |
| 498 | |
| 499 | PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); |
| 500 | |
| 501 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 502 | ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */ |
| 503 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 504 | ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */ |
| 505 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 506 | ixLCAC_CPL_CNTL, 0x100005);/*Read */ |
| 507 | |
| 508 | udelay(10); |
| 509 | |
| 510 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 511 | ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */ |
| 512 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 513 | ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */ |
| 514 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 515 | ixLCAC_CPL_CNTL, 0x500005);/* write */ |
| 516 | |
| 517 | } |
| 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | int tonga_start_dpm(struct pp_hwmgr *hwmgr) |
| 523 | { |
| 524 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 525 | |
| 526 | /* enable general power management */ |
| 527 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1); |
| 528 | /* enable sclk deep sleep */ |
| 529 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1); |
| 530 | |
| 531 | /* prepare for PCIE DPM */ |
| 532 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + |
| 533 | offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000); |
| 534 | |
| 535 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); |
| 536 | |
| 537 | PP_ASSERT_WITH_CODE( |
| 538 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 539 | PPSMC_MSG_Voltage_Cntl_Enable)), |
| 540 | "Failed to enable voltage DPM during DPM Start Function!", |
| 541 | return -1); |
| 542 | |
| 543 | if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) { |
| 544 | PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1); |
| 545 | } |
| 546 | |
| 547 | /* enable PCIE dpm */ |
| 548 | if (0 == data->pcie_dpm_key_disabled) { |
| 549 | PP_ASSERT_WITH_CODE( |
| 550 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 551 | PPSMC_MSG_PCIeDPM_Enable)), |
| 552 | "Failed to enable pcie DPM during DPM Start Function!", |
| 553 | return -1 |
| 554 | ); |
| 555 | } |
| 556 | |
| 557 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 558 | PHM_PlatformCaps_Falcon_QuickTransition)) { |
| 559 | smum_send_msg_to_smc(hwmgr->smumgr, |
| 560 | PPSMC_MSG_EnableACDCGPIOInterrupt); |
| 561 | } |
| 562 | |
| 563 | return 0; |
| 564 | } |
| 565 | |
| 566 | int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 567 | { |
| 568 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 569 | |
| 570 | /* disable SCLK dpm */ |
| 571 | if (0 == data->sclk_dpm_key_disabled) { |
| 572 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
| 573 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 574 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 575 | "Trying to Disable SCLK DPM when DPM is disabled", |
| 576 | return -1 |
| 577 | ); |
| 578 | |
| 579 | PP_ASSERT_WITH_CODE( |
| 580 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 581 | PPSMC_MSG_DPM_Disable)), |
| 582 | "Failed to disable SCLK DPM during DPM stop Function!", |
| 583 | return -1); |
| 584 | } |
| 585 | |
| 586 | /* disable MCLK dpm */ |
| 587 | if (0 == data->mclk_dpm_key_disabled) { |
| 588 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ |
| 589 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 590 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 591 | "Trying to Disable MCLK DPM when DPM is disabled", |
| 592 | return -1 |
| 593 | ); |
| 594 | |
| 595 | PP_ASSERT_WITH_CODE( |
| 596 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 597 | PPSMC_MSG_MCLKDPM_Disable)), |
| 598 | "Failed to Disable MCLK DPM during DPM stop Function!", |
| 599 | return -1); |
| 600 | } |
| 601 | |
| 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | int tonga_stop_dpm(struct pp_hwmgr *hwmgr) |
| 606 | { |
| 607 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 608 | |
| 609 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0); |
| 610 | /* disable sclk deep sleep*/ |
| 611 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0); |
| 612 | |
| 613 | /* disable PCIE dpm */ |
| 614 | if (0 == data->pcie_dpm_key_disabled) { |
| 615 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
| 616 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 617 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 618 | "Trying to Disable PCIE DPM when DPM is disabled", |
| 619 | return -1 |
| 620 | ); |
| 621 | PP_ASSERT_WITH_CODE( |
| 622 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 623 | PPSMC_MSG_PCIeDPM_Disable)), |
| 624 | "Failed to disable pcie DPM during DPM stop Function!", |
| 625 | return -1); |
| 626 | } |
| 627 | |
| 628 | if (0 != tonga_disable_sclk_mclk_dpm(hwmgr)) |
| 629 | PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1); |
| 630 | |
| 631 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
| 632 | PP_ASSERT_WITH_CODE( |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 633 | !tonga_is_dpm_running(hwmgr), |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 634 | "Trying to Disable Voltage CNTL when DPM is disabled", |
| 635 | return -1 |
| 636 | ); |
| 637 | |
| 638 | PP_ASSERT_WITH_CODE( |
| 639 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 640 | PPSMC_MSG_Voltage_Cntl_Disable)), |
| 641 | "Failed to disable voltage DPM during DPM stop Function!", |
| 642 | return -1); |
| 643 | |
| 644 | return 0; |
| 645 | } |
| 646 | |
| 647 | int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr) |
| 648 | { |
| 649 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); |
| 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
| 654 | /** |
| 655 | * Send a message to the SMC and return a parameter |
| 656 | * |
| 657 | * @param hwmgr: the address of the powerplay hardware manager. |
| 658 | * @param msg: the message to send. |
| 659 | * @param parameter: pointer to the received parameter |
| 660 | * @return The response that came from the SMC. |
| 661 | */ |
| 662 | PPSMC_Result tonga_send_msg_to_smc_return_parameter( |
| 663 | struct pp_hwmgr *hwmgr, |
| 664 | PPSMC_Msg msg, |
| 665 | uint32_t *parameter) |
| 666 | { |
| 667 | int result; |
| 668 | |
| 669 | result = smum_send_msg_to_smc(hwmgr->smumgr, msg); |
| 670 | |
| 671 | if ((0 == result) && parameter) { |
| 672 | *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 673 | } |
| 674 | |
| 675 | return result; |
| 676 | } |
| 677 | |
| 678 | /** |
| 679 | * force DPM power State |
| 680 | * |
| 681 | * @param hwmgr: the address of the powerplay hardware manager. |
| 682 | * @param n : DPM level |
| 683 | * @return The response that came from the SMC. |
| 684 | */ |
| 685 | int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) |
| 686 | { |
| 687 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 688 | uint32_t level_mask = 1 << n; |
| 689 | |
| 690 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 691 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 692 | "Trying to force SCLK when DPM is disabled", |
| 693 | return -1;); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 694 | if (0 == data->sclk_dpm_key_disabled) |
| 695 | return (0 == smum_send_msg_to_smc_with_parameter( |
| 696 | hwmgr->smumgr, |
| 697 | (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask), |
| 698 | level_mask) ? 0 : 1); |
| 699 | |
| 700 | return 0; |
| 701 | } |
| 702 | |
| 703 | /** |
| 704 | * force DPM power State |
| 705 | * |
| 706 | * @param hwmgr: the address of the powerplay hardware manager. |
| 707 | * @param n : DPM level |
| 708 | * @return The response that came from the SMC. |
| 709 | */ |
| 710 | int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) |
| 711 | { |
| 712 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 713 | uint32_t level_mask = 1 << n; |
| 714 | |
| 715 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 716 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 717 | "Trying to Force MCLK when DPM is disabled", |
| 718 | return -1;); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 719 | if (0 == data->mclk_dpm_key_disabled) |
| 720 | return (0 == smum_send_msg_to_smc_with_parameter( |
| 721 | hwmgr->smumgr, |
| 722 | (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask), |
| 723 | level_mask) ? 0 : 1); |
| 724 | |
| 725 | return 0; |
| 726 | } |
| 727 | |
| 728 | /** |
| 729 | * force DPM power State |
| 730 | * |
| 731 | * @param hwmgr: the address of the powerplay hardware manager. |
| 732 | * @param n : DPM level |
| 733 | * @return The response that came from the SMC. |
| 734 | */ |
| 735 | int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) |
| 736 | { |
| 737 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 738 | |
| 739 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 740 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 741 | "Trying to Force PCIE level when DPM is disabled", |
| 742 | return -1;); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 743 | if (0 == data->pcie_dpm_key_disabled) |
| 744 | return (0 == smum_send_msg_to_smc_with_parameter( |
| 745 | hwmgr->smumgr, |
| 746 | (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel), |
| 747 | n) ? 0 : 1); |
| 748 | |
| 749 | return 0; |
| 750 | } |
| 751 | |
| 752 | /** |
| 753 | * Set the initial state by calling SMC to switch to this state directly |
| 754 | * |
| 755 | * @param hwmgr the address of the powerplay hardware manager. |
| 756 | * @return always 0 |
| 757 | */ |
| 758 | int tonga_set_boot_state(struct pp_hwmgr *hwmgr) |
| 759 | { |
| 760 | /* |
| 761 | * SMC only stores one state that SW will ask to switch too, |
| 762 | * so we switch the the just uploaded one |
| 763 | */ |
| 764 | return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1; |
| 765 | } |
| 766 | |
| 767 | /** |
| 768 | * Get the location of various tables inside the FW image. |
| 769 | * |
| 770 | * @param hwmgr the address of the powerplay hardware manager. |
| 771 | * @return always 0 |
| 772 | */ |
| 773 | int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) |
| 774 | { |
| 775 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 776 | struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend); |
| 777 | |
| 778 | uint32_t tmp; |
| 779 | int result; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 780 | bool error = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 781 | |
| 782 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 783 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 784 | offsetof(SMU72_Firmware_Header, DpmTable), |
| 785 | &tmp, data->sram_end); |
| 786 | |
| 787 | if (0 == result) { |
| 788 | data->dpm_table_start = tmp; |
| 789 | } |
| 790 | |
| 791 | error |= (0 != result); |
| 792 | |
| 793 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 794 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 795 | offsetof(SMU72_Firmware_Header, SoftRegisters), |
| 796 | &tmp, data->sram_end); |
| 797 | |
| 798 | if (0 == result) { |
| 799 | data->soft_regs_start = tmp; |
| 800 | tonga_smu->ulSoftRegsStart = tmp; |
| 801 | } |
| 802 | |
| 803 | error |= (0 != result); |
| 804 | |
| 805 | |
| 806 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 807 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 808 | offsetof(SMU72_Firmware_Header, mcRegisterTable), |
| 809 | &tmp, data->sram_end); |
| 810 | |
| 811 | if (0 == result) { |
| 812 | data->mc_reg_table_start = tmp; |
| 813 | } |
| 814 | |
| 815 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 816 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 817 | offsetof(SMU72_Firmware_Header, FanTable), |
| 818 | &tmp, data->sram_end); |
| 819 | |
| 820 | if (0 == result) { |
| 821 | data->fan_table_start = tmp; |
| 822 | } |
| 823 | |
| 824 | error |= (0 != result); |
| 825 | |
| 826 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 827 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 828 | offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), |
| 829 | &tmp, data->sram_end); |
| 830 | |
| 831 | if (0 == result) { |
| 832 | data->arb_table_start = tmp; |
| 833 | } |
| 834 | |
| 835 | error |= (0 != result); |
| 836 | |
| 837 | |
| 838 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 839 | SMU72_FIRMWARE_HEADER_LOCATION + |
| 840 | offsetof(SMU72_Firmware_Header, Version), |
| 841 | &tmp, data->sram_end); |
| 842 | |
| 843 | if (0 == result) { |
| 844 | hwmgr->microcode_version_info.SMC = tmp; |
| 845 | } |
| 846 | |
| 847 | error |= (0 != result); |
| 848 | |
| 849 | return error ? 1 : 0; |
| 850 | } |
| 851 | |
| 852 | /** |
| 853 | * Read clock related registers. |
| 854 | * |
| 855 | * @param hwmgr the address of the powerplay hardware manager. |
| 856 | * @return always 0 |
| 857 | */ |
| 858 | int tonga_read_clock_registers(struct pp_hwmgr *hwmgr) |
| 859 | { |
| 860 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 861 | |
| 862 | data->clock_registers.vCG_SPLL_FUNC_CNTL = |
| 863 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); |
| 864 | data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = |
| 865 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); |
| 866 | data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = |
| 867 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); |
| 868 | data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = |
| 869 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); |
| 870 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = |
| 871 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); |
| 872 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = |
| 873 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); |
| 874 | data->clock_registers.vDLL_CNTL = |
| 875 | cgs_read_register(hwmgr->device, mmDLL_CNTL); |
| 876 | data->clock_registers.vMCLK_PWRMGT_CNTL = |
| 877 | cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); |
| 878 | data->clock_registers.vMPLL_AD_FUNC_CNTL = |
| 879 | cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); |
| 880 | data->clock_registers.vMPLL_DQ_FUNC_CNTL = |
| 881 | cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); |
| 882 | data->clock_registers.vMPLL_FUNC_CNTL = |
| 883 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); |
| 884 | data->clock_registers.vMPLL_FUNC_CNTL_1 = |
| 885 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); |
| 886 | data->clock_registers.vMPLL_FUNC_CNTL_2 = |
| 887 | cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); |
| 888 | data->clock_registers.vMPLL_SS1 = |
| 889 | cgs_read_register(hwmgr->device, mmMPLL_SS1); |
| 890 | data->clock_registers.vMPLL_SS2 = |
| 891 | cgs_read_register(hwmgr->device, mmMPLL_SS2); |
| 892 | |
| 893 | return 0; |
| 894 | } |
| 895 | |
| 896 | /** |
| 897 | * Find out if memory is GDDR5. |
| 898 | * |
| 899 | * @param hwmgr the address of the powerplay hardware manager. |
| 900 | * @return always 0 |
| 901 | */ |
| 902 | int tonga_get_memory_type(struct pp_hwmgr *hwmgr) |
| 903 | { |
| 904 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 905 | uint32_t temp; |
| 906 | |
| 907 | temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); |
| 908 | |
| 909 | data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE == |
| 910 | ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> |
| 911 | MC_SEQ_MISC0_GDDR5_SHIFT)); |
| 912 | |
| 913 | return 0; |
| 914 | } |
| 915 | |
| 916 | /** |
| 917 | * Enables Dynamic Power Management by SMC |
| 918 | * |
| 919 | * @param hwmgr the address of the powerplay hardware manager. |
| 920 | * @return always 0 |
| 921 | */ |
| 922 | int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr) |
| 923 | { |
| 924 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); |
| 925 | |
| 926 | return 0; |
| 927 | } |
| 928 | |
| 929 | /** |
| 930 | * Initialize PowerGating States for different engines |
| 931 | * |
| 932 | * @param hwmgr the address of the powerplay hardware manager. |
| 933 | * @return always 0 |
| 934 | */ |
| 935 | int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr) |
| 936 | { |
| 937 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 938 | |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 939 | data->uvd_power_gated = false; |
| 940 | data->vce_power_gated = false; |
| 941 | data->samu_power_gated = false; |
| 942 | data->acp_power_gated = false; |
| 943 | data->pg_acp_init = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 944 | |
| 945 | return 0; |
| 946 | } |
| 947 | |
| 948 | /** |
| 949 | * Checks if DPM is enabled |
| 950 | * |
| 951 | * @param hwmgr the address of the powerplay hardware manager. |
| 952 | * @return always 0 |
| 953 | */ |
| 954 | int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr) |
| 955 | { |
| 956 | /* |
| 957 | * We return the status of Voltage Control instead of checking SCLK/MCLK DPM |
| 958 | * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, |
| 959 | * whereas voltage control is a fundemental change that will not be disabled |
| 960 | */ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 961 | return (!tonga_is_dpm_running(hwmgr) ? 0 : 1); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 962 | } |
| 963 | |
| 964 | /** |
| 965 | * Checks if DPM is stopped |
| 966 | * |
| 967 | * @param hwmgr the address of the powerplay hardware manager. |
| 968 | * @return always 0 |
| 969 | */ |
| 970 | int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr) |
| 971 | { |
| 972 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 973 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 974 | if (tonga_is_dpm_running(hwmgr)) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 975 | /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */ |
| 976 | if (!data->dpm_table_start) { |
| 977 | return 1; |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | return 0; |
| 982 | } |
| 983 | |
| 984 | /** |
| 985 | * Remove repeated voltage values and create table with unique values. |
| 986 | * |
| 987 | * @param hwmgr the address of the powerplay hardware manager. |
| 988 | * @param voltage_table the pointer to changing voltage table |
| 989 | * @return 1 in success |
| 990 | */ |
| 991 | |
| 992 | static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr, |
| 993 | pp_atomctrl_voltage_table *voltage_table) |
| 994 | { |
| 995 | uint32_t table_size, i, j; |
| 996 | uint16_t vvalue; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 997 | bool bVoltageFound = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 998 | pp_atomctrl_voltage_table *table; |
| 999 | |
| 1000 | PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;); |
| 1001 | table_size = sizeof(pp_atomctrl_voltage_table); |
| 1002 | table = kzalloc(table_size, GFP_KERNEL); |
| 1003 | |
| 1004 | if (NULL == table) |
| 1005 | return -ENOMEM; |
| 1006 | |
| 1007 | memset(table, 0x00, table_size); |
| 1008 | table->mask_low = voltage_table->mask_low; |
| 1009 | table->phase_delay = voltage_table->phase_delay; |
| 1010 | |
| 1011 | for (i = 0; i < voltage_table->count; i++) { |
| 1012 | vvalue = voltage_table->entries[i].value; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 1013 | bVoltageFound = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1014 | |
| 1015 | for (j = 0; j < table->count; j++) { |
| 1016 | if (vvalue == table->entries[j].value) { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 1017 | bVoltageFound = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1018 | break; |
| 1019 | } |
| 1020 | } |
| 1021 | |
| 1022 | if (!bVoltageFound) { |
| 1023 | table->entries[table->count].value = vvalue; |
| 1024 | table->entries[table->count].smio_low = |
| 1025 | voltage_table->entries[i].smio_low; |
| 1026 | table->count++; |
| 1027 | } |
| 1028 | } |
| 1029 | |
| 1030 | memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table)); |
| 1031 | |
| 1032 | kfree(table); |
| 1033 | |
| 1034 | return 0; |
| 1035 | } |
| 1036 | |
| 1037 | static int tonga_get_svi2_vdd_ci_voltage_table( |
| 1038 | struct pp_hwmgr *hwmgr, |
| 1039 | phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table) |
| 1040 | { |
| 1041 | uint32_t i; |
| 1042 | int result; |
| 1043 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1044 | pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table); |
| 1045 | |
| 1046 | PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count), |
| 1047 | "Voltage Dependency Table empty.", return -1;); |
| 1048 | |
| 1049 | vddci_voltage_table->mask_low = 0; |
| 1050 | vddci_voltage_table->phase_delay = 0; |
| 1051 | vddci_voltage_table->count = voltage_dependency_table->count; |
| 1052 | |
| 1053 | for (i = 0; i < voltage_dependency_table->count; i++) { |
| 1054 | vddci_voltage_table->entries[i].value = |
| 1055 | voltage_dependency_table->entries[i].vddci; |
| 1056 | vddci_voltage_table->entries[i].smio_low = 0; |
| 1057 | } |
| 1058 | |
| 1059 | result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table); |
| 1060 | PP_ASSERT_WITH_CODE((0 == result), |
| 1061 | "Failed to trim VDDCI table.", return result;); |
| 1062 | |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | static int tonga_get_svi2_vdd_voltage_table( |
| 1069 | struct pp_hwmgr *hwmgr, |
| 1070 | phm_ppt_v1_voltage_lookup_table *look_up_table, |
| 1071 | pp_atomctrl_voltage_table *voltage_table) |
| 1072 | { |
| 1073 | uint8_t i = 0; |
| 1074 | |
| 1075 | PP_ASSERT_WITH_CODE((0 != look_up_table->count), |
| 1076 | "Voltage Lookup Table empty.", return -1;); |
| 1077 | |
| 1078 | voltage_table->mask_low = 0; |
| 1079 | voltage_table->phase_delay = 0; |
| 1080 | |
| 1081 | voltage_table->count = look_up_table->count; |
| 1082 | |
| 1083 | for (i = 0; i < voltage_table->count; i++) { |
| 1084 | voltage_table->entries[i].value = look_up_table->entries[i].us_vdd; |
| 1085 | voltage_table->entries[i].smio_low = 0; |
| 1086 | } |
| 1087 | |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
| 1091 | /* |
| 1092 | * -------------------------------------------------------- Voltage Tables -------------------------------------------------------------------------- |
| 1093 | * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries. |
| 1094 | */ |
| 1095 | |
| 1096 | static void tonga_trim_voltage_table_to_fit_state_table( |
| 1097 | struct pp_hwmgr *hwmgr, |
| 1098 | uint32_t max_voltage_steps, |
| 1099 | pp_atomctrl_voltage_table *voltage_table) |
| 1100 | { |
| 1101 | unsigned int i, diff; |
| 1102 | |
| 1103 | if (voltage_table->count <= max_voltage_steps) { |
| 1104 | return; |
| 1105 | } |
| 1106 | |
| 1107 | diff = voltage_table->count - max_voltage_steps; |
| 1108 | |
| 1109 | for (i = 0; i < max_voltage_steps; i++) { |
| 1110 | voltage_table->entries[i] = voltage_table->entries[i + diff]; |
| 1111 | } |
| 1112 | |
| 1113 | voltage_table->count = max_voltage_steps; |
| 1114 | |
| 1115 | return; |
| 1116 | } |
| 1117 | |
| 1118 | /** |
| 1119 | * Create Voltage Tables. |
| 1120 | * |
| 1121 | * @param hwmgr the address of the powerplay hardware manager. |
| 1122 | * @return always 0 |
| 1123 | */ |
| 1124 | int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr) |
| 1125 | { |
| 1126 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1127 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1128 | int result; |
| 1129 | |
| 1130 | /* MVDD has only GPIO voltage control */ |
| 1131 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1132 | result = atomctrl_get_voltage_table_v3(hwmgr, |
| 1133 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table)); |
| 1134 | PP_ASSERT_WITH_CODE((0 == result), |
| 1135 | "Failed to retrieve MVDD table.", return result;); |
| 1136 | } |
| 1137 | |
| 1138 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { |
| 1139 | /* GPIO voltage */ |
| 1140 | result = atomctrl_get_voltage_table_v3(hwmgr, |
| 1141 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table)); |
| 1142 | PP_ASSERT_WITH_CODE((0 == result), |
| 1143 | "Failed to retrieve VDDCI table.", return result;); |
| 1144 | } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { |
| 1145 | /* SVI2 voltage */ |
| 1146 | result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr, |
| 1147 | pptable_info->vdd_dep_on_mclk); |
| 1148 | PP_ASSERT_WITH_CODE((0 == result), |
| 1149 | "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;); |
| 1150 | } |
| 1151 | |
| 1152 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { |
| 1153 | /* VDDGFX has only SVI2 voltage control */ |
| 1154 | result = tonga_get_svi2_vdd_voltage_table(hwmgr, |
| 1155 | pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table)); |
| 1156 | PP_ASSERT_WITH_CODE((0 == result), |
| 1157 | "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); |
| 1158 | } |
| 1159 | |
| 1160 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1161 | /* VDDC has only SVI2 voltage control */ |
| 1162 | result = tonga_get_svi2_vdd_voltage_table(hwmgr, |
| 1163 | pptable_info->vddc_lookup_table, &(data->vddc_voltage_table)); |
| 1164 | PP_ASSERT_WITH_CODE((0 == result), |
| 1165 | "Failed to retrieve SVI2 VDDC table from lookup table.", return result;); |
| 1166 | } |
| 1167 | |
| 1168 | PP_ASSERT_WITH_CODE( |
| 1169 | (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)), |
| 1170 | "Too many voltage values for VDDC. Trimming to fit state table.", |
| 1171 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1172 | SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)); |
| 1173 | ); |
| 1174 | |
| 1175 | PP_ASSERT_WITH_CODE( |
| 1176 | (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)), |
| 1177 | "Too many voltage values for VDDGFX. Trimming to fit state table.", |
| 1178 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1179 | SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table)); |
| 1180 | ); |
| 1181 | |
| 1182 | PP_ASSERT_WITH_CODE( |
| 1183 | (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)), |
| 1184 | "Too many voltage values for VDDCI. Trimming to fit state table.", |
| 1185 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1186 | SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)); |
| 1187 | ); |
| 1188 | |
| 1189 | PP_ASSERT_WITH_CODE( |
| 1190 | (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)), |
| 1191 | "Too many voltage values for MVDD. Trimming to fit state table.", |
| 1192 | tonga_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1193 | SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)); |
| 1194 | ); |
| 1195 | |
| 1196 | return 0; |
| 1197 | } |
| 1198 | |
| 1199 | /** |
| 1200 | * Vddc table preparation for SMC. |
| 1201 | * |
| 1202 | * @param hwmgr the address of the hardware manager |
| 1203 | * @param table the SMC DPM table structure to be populated |
| 1204 | * @return always 0 |
| 1205 | */ |
| 1206 | static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, |
| 1207 | SMU72_Discrete_DpmTable *table) |
| 1208 | { |
| 1209 | unsigned int count; |
| 1210 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1211 | |
| 1212 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1213 | table->VddcLevelCount = data->vddc_voltage_table.count; |
| 1214 | for (count = 0; count < table->VddcLevelCount; count++) { |
| 1215 | table->VddcTable[count] = |
| 1216 | PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1217 | } |
| 1218 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); |
| 1219 | } |
| 1220 | return 0; |
| 1221 | } |
| 1222 | |
| 1223 | /** |
| 1224 | * VddGfx table preparation for SMC. |
| 1225 | * |
| 1226 | * @param hwmgr the address of the hardware manager |
| 1227 | * @param table the SMC DPM table structure to be populated |
| 1228 | * @return always 0 |
| 1229 | */ |
| 1230 | static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr, |
| 1231 | SMU72_Discrete_DpmTable *table) |
| 1232 | { |
| 1233 | unsigned int count; |
| 1234 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1235 | |
| 1236 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { |
| 1237 | table->VddGfxLevelCount = data->vddgfx_voltage_table.count; |
| 1238 | for (count = 0; count < data->vddgfx_voltage_table.count; count++) { |
| 1239 | table->VddGfxTable[count] = |
| 1240 | PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1241 | } |
| 1242 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount); |
| 1243 | } |
| 1244 | return 0; |
| 1245 | } |
| 1246 | |
| 1247 | /** |
| 1248 | * Vddci table preparation for SMC. |
| 1249 | * |
| 1250 | * @param *hwmgr The address of the hardware manager. |
| 1251 | * @param *table The SMC DPM table structure to be populated. |
| 1252 | * @return 0 |
| 1253 | */ |
| 1254 | static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, |
| 1255 | SMU72_Discrete_DpmTable *table) |
| 1256 | { |
| 1257 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1258 | uint32_t count; |
| 1259 | |
| 1260 | table->VddciLevelCount = data->vddci_voltage_table.count; |
| 1261 | for (count = 0; count < table->VddciLevelCount; count++) { |
| 1262 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { |
| 1263 | table->VddciTable[count] = |
| 1264 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1265 | } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { |
| 1266 | table->SmioTable1.Pattern[count].Voltage = |
| 1267 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1268 | /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */ |
| 1269 | table->SmioTable1.Pattern[count].Smio = |
| 1270 | (uint8_t) count; |
| 1271 | table->Smio[count] |= |
| 1272 | data->vddci_voltage_table.entries[count].smio_low; |
| 1273 | table->VddciTable[count] = |
| 1274 | PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1275 | } |
| 1276 | } |
| 1277 | |
| 1278 | table->SmioMask1 = data->vddci_voltage_table.mask_low; |
| 1279 | CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); |
| 1280 | |
| 1281 | return 0; |
| 1282 | } |
| 1283 | |
| 1284 | /** |
| 1285 | * Mvdd table preparation for SMC. |
| 1286 | * |
| 1287 | * @param *hwmgr The address of the hardware manager. |
| 1288 | * @param *table The SMC DPM table structure to be populated. |
| 1289 | * @return 0 |
| 1290 | */ |
| 1291 | static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, |
| 1292 | SMU72_Discrete_DpmTable *table) |
| 1293 | { |
| 1294 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1295 | uint32_t count; |
| 1296 | |
| 1297 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1298 | table->MvddLevelCount = data->mvdd_voltage_table.count; |
| 1299 | for (count = 0; count < table->MvddLevelCount; count++) { |
| 1300 | table->SmioTable2.Pattern[count].Voltage = |
| 1301 | PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); |
| 1302 | /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ |
| 1303 | table->SmioTable2.Pattern[count].Smio = |
| 1304 | (uint8_t) count; |
| 1305 | table->Smio[count] |= |
| 1306 | data->mvdd_voltage_table.entries[count].smio_low; |
| 1307 | } |
Huang Rui | 1dfefee | 2016-07-06 09:32:24 +0800 | [diff] [blame] | 1308 | table->SmioMask2 = data->mvdd_voltage_table.mask_low; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1309 | |
| 1310 | CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); |
| 1311 | } |
| 1312 | |
| 1313 | return 0; |
| 1314 | } |
| 1315 | |
| 1316 | /** |
| 1317 | * Convert a voltage value in mv unit to VID number required by SMU firmware |
| 1318 | */ |
| 1319 | static uint8_t convert_to_vid(uint16_t vddc) |
| 1320 | { |
| 1321 | return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); |
| 1322 | } |
| 1323 | |
| 1324 | |
| 1325 | /** |
| 1326 | * Preparation of vddc and vddgfx CAC tables for SMC. |
| 1327 | * |
| 1328 | * @param hwmgr the address of the hardware manager |
| 1329 | * @param table the SMC DPM table structure to be populated |
| 1330 | * @return always 0 |
| 1331 | */ |
| 1332 | static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, |
| 1333 | SMU72_Discrete_DpmTable *table) |
| 1334 | { |
| 1335 | uint32_t count; |
| 1336 | uint8_t index; |
| 1337 | int result = 0; |
| 1338 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1339 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1340 | struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table; |
| 1341 | struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table; |
| 1342 | |
| 1343 | /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */ |
| 1344 | uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount); |
| 1345 | uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount); |
| 1346 | |
| 1347 | for (count = 0; count < vddcLevelCount; count++) { |
| 1348 | /* We are populating vddc CAC data to BapmVddc table in split and merged mode */ |
| 1349 | index = tonga_get_voltage_index(vddc_lookup_table, |
| 1350 | data->vddc_voltage_table.entries[count].value); |
| 1351 | table->BapmVddcVidLoSidd[count] = |
| 1352 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); |
| 1353 | table->BapmVddcVidHiSidd[count] = |
| 1354 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); |
| 1355 | table->BapmVddcVidHiSidd2[count] = |
| 1356 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); |
| 1357 | } |
| 1358 | |
| 1359 | if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) { |
| 1360 | /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */ |
| 1361 | for (count = 0; count < vddgfxLevelCount; count++) { |
| 1362 | index = tonga_get_voltage_index(vddgfx_lookup_table, |
| 1363 | data->vddgfx_voltage_table.entries[count].value); |
| 1364 | table->BapmVddGfxVidLoSidd[count] = |
| 1365 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low); |
| 1366 | table->BapmVddGfxVidHiSidd[count] = |
| 1367 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid); |
| 1368 | table->BapmVddGfxVidHiSidd2[count] = |
| 1369 | convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high); |
| 1370 | } |
| 1371 | } else { |
| 1372 | for (count = 0; count < vddcLevelCount; count++) { |
| 1373 | index = tonga_get_voltage_index(vddc_lookup_table, |
| 1374 | data->vddc_voltage_table.entries[count].value); |
| 1375 | table->BapmVddGfxVidLoSidd[count] = |
| 1376 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); |
| 1377 | table->BapmVddGfxVidHiSidd[count] = |
| 1378 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); |
| 1379 | table->BapmVddGfxVidHiSidd2[count] = |
| 1380 | convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); |
| 1381 | } |
| 1382 | } |
| 1383 | |
| 1384 | return result; |
| 1385 | } |
| 1386 | |
| 1387 | |
| 1388 | /** |
| 1389 | * Preparation of voltage tables for SMC. |
| 1390 | * |
| 1391 | * @param hwmgr the address of the hardware manager |
| 1392 | * @param table the SMC DPM table structure to be populated |
| 1393 | * @return always 0 |
| 1394 | */ |
| 1395 | |
| 1396 | int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, |
| 1397 | SMU72_Discrete_DpmTable *table) |
| 1398 | { |
| 1399 | int result; |
| 1400 | |
| 1401 | result = tonga_populate_smc_vddc_table(hwmgr, table); |
| 1402 | PP_ASSERT_WITH_CODE(0 == result, |
| 1403 | "can not populate VDDC voltage table to SMC", return -1); |
| 1404 | |
| 1405 | result = tonga_populate_smc_vdd_ci_table(hwmgr, table); |
| 1406 | PP_ASSERT_WITH_CODE(0 == result, |
| 1407 | "can not populate VDDCI voltage table to SMC", return -1); |
| 1408 | |
| 1409 | result = tonga_populate_smc_vdd_gfx_table(hwmgr, table); |
| 1410 | PP_ASSERT_WITH_CODE(0 == result, |
| 1411 | "can not populate VDDGFX voltage table to SMC", return -1); |
| 1412 | |
| 1413 | result = tonga_populate_smc_mvdd_table(hwmgr, table); |
| 1414 | PP_ASSERT_WITH_CODE(0 == result, |
| 1415 | "can not populate MVDD voltage table to SMC", return -1); |
| 1416 | |
| 1417 | result = tonga_populate_cac_tables(hwmgr, table); |
| 1418 | PP_ASSERT_WITH_CODE(0 == result, |
| 1419 | "can not populate CAC voltage tables to SMC", return -1); |
| 1420 | |
| 1421 | return 0; |
| 1422 | } |
| 1423 | |
| 1424 | /** |
| 1425 | * Populates the SMC VRConfig field in DPM table. |
| 1426 | * |
| 1427 | * @param hwmgr the address of the hardware manager |
| 1428 | * @param table the SMC DPM table structure to be populated |
| 1429 | * @return always 0 |
| 1430 | */ |
| 1431 | static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, |
| 1432 | SMU72_Discrete_DpmTable *table) |
| 1433 | { |
| 1434 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1435 | uint16_t config; |
| 1436 | |
| 1437 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { |
| 1438 | /* Splitted mode */ |
| 1439 | config = VR_SVI2_PLANE_1; |
| 1440 | table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); |
| 1441 | |
| 1442 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1443 | config = VR_SVI2_PLANE_2; |
| 1444 | table->VRConfig |= config; |
| 1445 | } else { |
| 1446 | printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n"); |
| 1447 | } |
| 1448 | } else { |
| 1449 | /* Merged mode */ |
| 1450 | config = VR_MERGED_WITH_VDDC; |
| 1451 | table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); |
| 1452 | |
| 1453 | /* Set Vddc Voltage Controller */ |
| 1454 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1455 | config = VR_SVI2_PLANE_1; |
| 1456 | table->VRConfig |= config; |
| 1457 | } else { |
| 1458 | printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n"); |
| 1459 | } |
| 1460 | } |
| 1461 | |
| 1462 | /* Set Vddci Voltage Controller */ |
| 1463 | if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) { |
| 1464 | config = VR_SVI2_PLANE_2; /* only in merged mode */ |
| 1465 | table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); |
| 1466 | } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) { |
| 1467 | config = VR_SMIO_PATTERN_1; |
| 1468 | table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); |
| 1469 | } |
| 1470 | |
| 1471 | /* Set Mvdd Voltage Controller */ |
| 1472 | if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1473 | config = VR_SMIO_PATTERN_2; |
| 1474 | table->VRConfig |= (config<<VRCONF_MVDD_SHIFT); |
| 1475 | } |
| 1476 | |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
| 1480 | static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, |
| 1481 | phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table, |
| 1482 | uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) |
| 1483 | { |
| 1484 | uint32_t i = 0; |
| 1485 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1486 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1487 | |
| 1488 | /* clock - voltage dependency table is empty table */ |
| 1489 | if (allowed_clock_voltage_table->count == 0) |
| 1490 | return -1; |
| 1491 | |
| 1492 | for (i = 0; i < allowed_clock_voltage_table->count; i++) { |
| 1493 | /* find first sclk bigger than request */ |
| 1494 | if (allowed_clock_voltage_table->entries[i].clk >= clock) { |
| 1495 | voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1496 | allowed_clock_voltage_table->entries[i].vddgfx); |
| 1497 | |
| 1498 | voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1499 | allowed_clock_voltage_table->entries[i].vddc); |
| 1500 | |
| 1501 | if (allowed_clock_voltage_table->entries[i].vddci) { |
| 1502 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1503 | allowed_clock_voltage_table->entries[i].vddci); |
| 1504 | } else { |
| 1505 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1506 | allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta); |
| 1507 | } |
| 1508 | |
| 1509 | if (allowed_clock_voltage_table->entries[i].mvdd) { |
| 1510 | *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd; |
| 1511 | } |
| 1512 | |
| 1513 | voltage->Phases = 1; |
| 1514 | return 0; |
| 1515 | } |
| 1516 | } |
| 1517 | |
| 1518 | /* sclk is bigger than max sclk in the dependence table */ |
| 1519 | voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1520 | allowed_clock_voltage_table->entries[i-1].vddgfx); |
| 1521 | voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1522 | allowed_clock_voltage_table->entries[i-1].vddc); |
| 1523 | |
| 1524 | if (allowed_clock_voltage_table->entries[i-1].vddci) { |
| 1525 | voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1526 | allowed_clock_voltage_table->entries[i-1].vddci); |
| 1527 | } |
| 1528 | if (allowed_clock_voltage_table->entries[i-1].mvdd) { |
| 1529 | *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd; |
| 1530 | } |
| 1531 | |
| 1532 | return 0; |
| 1533 | } |
| 1534 | |
| 1535 | /** |
| 1536 | * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value |
| 1537 | * |
| 1538 | * @param hwmgr the address of the powerplay hardware manager. |
| 1539 | * @return always 0 |
| 1540 | */ |
| 1541 | int tonga_reset_to_default(struct pp_hwmgr *hwmgr) |
| 1542 | { |
| 1543 | return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1; |
| 1544 | } |
| 1545 | |
| 1546 | int tonga_populate_memory_timing_parameters( |
| 1547 | struct pp_hwmgr *hwmgr, |
| 1548 | uint32_t engine_clock, |
| 1549 | uint32_t memory_clock, |
| 1550 | struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs |
| 1551 | ) |
| 1552 | { |
| 1553 | uint32_t dramTiming; |
| 1554 | uint32_t dramTiming2; |
| 1555 | uint32_t burstTime; |
| 1556 | int result; |
| 1557 | |
| 1558 | result = atomctrl_set_engine_dram_timings_rv770(hwmgr, |
| 1559 | engine_clock, memory_clock); |
| 1560 | |
| 1561 | PP_ASSERT_WITH_CODE(result == 0, |
| 1562 | "Error calling VBIOS to set DRAM_TIMING.", return result); |
| 1563 | |
| 1564 | dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); |
| 1565 | dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); |
| 1566 | burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); |
| 1567 | |
| 1568 | arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); |
| 1569 | arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); |
| 1570 | arb_regs->McArbBurstTime = (uint8_t)burstTime; |
| 1571 | |
| 1572 | return 0; |
| 1573 | } |
| 1574 | |
| 1575 | /** |
| 1576 | * Setup parameters for the MC ARB. |
| 1577 | * |
| 1578 | * @param hwmgr the address of the powerplay hardware manager. |
| 1579 | * @return always 0 |
| 1580 | * This function is to be called from the SetPowerState table. |
| 1581 | */ |
| 1582 | int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) |
| 1583 | { |
| 1584 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1585 | int result = 0; |
| 1586 | SMU72_Discrete_MCArbDramTimingTable arb_regs; |
| 1587 | uint32_t i, j; |
| 1588 | |
| 1589 | memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); |
| 1590 | |
| 1591 | for (i = 0; i < data->dpm_table.sclk_table.count; i++) { |
| 1592 | for (j = 0; j < data->dpm_table.mclk_table.count; j++) { |
| 1593 | result = tonga_populate_memory_timing_parameters |
| 1594 | (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, |
| 1595 | data->dpm_table.mclk_table.dpm_levels[j].value, |
| 1596 | &arb_regs.entries[i][j]); |
| 1597 | |
| 1598 | if (0 != result) { |
| 1599 | break; |
| 1600 | } |
| 1601 | } |
| 1602 | } |
| 1603 | |
| 1604 | if (0 == result) { |
| 1605 | result = tonga_copy_bytes_to_smc( |
| 1606 | hwmgr->smumgr, |
| 1607 | data->arb_table_start, |
| 1608 | (uint8_t *)&arb_regs, |
| 1609 | sizeof(SMU72_Discrete_MCArbDramTimingTable), |
| 1610 | data->sram_end |
| 1611 | ); |
| 1612 | } |
| 1613 | |
| 1614 | return result; |
| 1615 | } |
| 1616 | |
| 1617 | static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table) |
| 1618 | { |
| 1619 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1620 | struct tonga_dpm_table *dpm_table = &data->dpm_table; |
| 1621 | uint32_t i; |
| 1622 | |
| 1623 | /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ |
| 1624 | for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { |
| 1625 | table->LinkLevel[i].PcieGenSpeed = |
| 1626 | (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; |
| 1627 | table->LinkLevel[i].PcieLaneCount = |
| 1628 | (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); |
| 1629 | table->LinkLevel[i].EnabledForActivity = |
| 1630 | 1; |
| 1631 | table->LinkLevel[i].SPC = |
| 1632 | (uint8_t)(data->pcie_spc_cap & 0xff); |
| 1633 | table->LinkLevel[i].DownThreshold = |
| 1634 | PP_HOST_TO_SMC_UL(5); |
| 1635 | table->LinkLevel[i].UpThreshold = |
| 1636 | PP_HOST_TO_SMC_UL(30); |
| 1637 | } |
| 1638 | |
| 1639 | data->smc_state_table.LinkLevelCount = |
| 1640 | (uint8_t)dpm_table->pcie_speed_table.count; |
| 1641 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = |
| 1642 | tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); |
| 1643 | |
| 1644 | return 0; |
| 1645 | } |
| 1646 | |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 1647 | static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, |
| 1648 | SMU72_Discrete_DpmTable *table) |
| 1649 | { |
| 1650 | int result = 0; |
| 1651 | |
| 1652 | uint8_t count; |
| 1653 | pp_atomctrl_clock_dividers_vi dividers; |
| 1654 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1655 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1656 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1657 | |
| 1658 | table->UvdLevelCount = (uint8_t) (mm_table->count); |
| 1659 | table->UvdBootLevel = 0; |
| 1660 | |
| 1661 | for (count = 0; count < table->UvdLevelCount; count++) { |
| 1662 | table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; |
| 1663 | table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; |
| 1664 | table->UvdLevel[count].MinVoltage.Vddc = |
| 1665 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1666 | mm_table->entries[count].vddc); |
| 1667 | table->UvdLevel[count].MinVoltage.VddGfx = |
| 1668 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1669 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1670 | mm_table->entries[count].vddgfx) : 0; |
| 1671 | table->UvdLevel[count].MinVoltage.Vddci = |
| 1672 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1673 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1674 | table->UvdLevel[count].MinVoltage.Phases = 1; |
| 1675 | |
| 1676 | /* retrieve divider value for VBIOS */ |
| 1677 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1678 | table->UvdLevel[count].VclkFrequency, ÷rs); |
| 1679 | PP_ASSERT_WITH_CODE((0 == result), |
| 1680 | "can not find divide id for Vclk clock", return result); |
| 1681 | |
| 1682 | table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; |
| 1683 | |
| 1684 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1685 | table->UvdLevel[count].DclkFrequency, ÷rs); |
| 1686 | PP_ASSERT_WITH_CODE((0 == result), |
| 1687 | "can not find divide id for Dclk clock", return result); |
| 1688 | |
| 1689 | table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; |
| 1690 | |
| 1691 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); |
| 1692 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); |
| 1693 | //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage); |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1694 | } |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 1695 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1696 | return result; |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 1697 | |
| 1698 | } |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1699 | |
| 1700 | static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr, |
| 1701 | SMU72_Discrete_DpmTable *table) |
| 1702 | { |
| 1703 | int result = 0; |
| 1704 | |
| 1705 | uint8_t count; |
| 1706 | pp_atomctrl_clock_dividers_vi dividers; |
| 1707 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1708 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1709 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1710 | |
| 1711 | table->VceLevelCount = (uint8_t) (mm_table->count); |
| 1712 | table->VceBootLevel = 0; |
| 1713 | |
| 1714 | for (count = 0; count < table->VceLevelCount; count++) { |
| 1715 | table->VceLevel[count].Frequency = |
| 1716 | mm_table->entries[count].eclk; |
| 1717 | table->VceLevel[count].MinVoltage.Vddc = |
| 1718 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1719 | mm_table->entries[count].vddc); |
| 1720 | table->VceLevel[count].MinVoltage.VddGfx = |
| 1721 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1722 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1723 | mm_table->entries[count].vddgfx) : 0; |
| 1724 | table->VceLevel[count].MinVoltage.Vddci = |
| 1725 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1726 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1727 | table->VceLevel[count].MinVoltage.Phases = 1; |
| 1728 | |
| 1729 | /* retrieve divider value for VBIOS */ |
| 1730 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1731 | table->VceLevel[count].Frequency, ÷rs); |
| 1732 | PP_ASSERT_WITH_CODE((0 == result), |
| 1733 | "can not find divide id for VCE engine clock", return result); |
| 1734 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1735 | table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1736 | |
| 1737 | CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); |
| 1738 | } |
| 1739 | |
| 1740 | return result; |
| 1741 | } |
| 1742 | |
| 1743 | static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr, |
| 1744 | SMU72_Discrete_DpmTable *table) |
| 1745 | { |
| 1746 | int result = 0; |
| 1747 | uint8_t count; |
| 1748 | pp_atomctrl_clock_dividers_vi dividers; |
| 1749 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1750 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1751 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1752 | |
| 1753 | table->AcpLevelCount = (uint8_t) (mm_table->count); |
| 1754 | table->AcpBootLevel = 0; |
| 1755 | |
| 1756 | for (count = 0; count < table->AcpLevelCount; count++) { |
| 1757 | table->AcpLevel[count].Frequency = |
| 1758 | pptable_info->mm_dep_table->entries[count].aclk; |
| 1759 | table->AcpLevel[count].MinVoltage.Vddc = |
| 1760 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1761 | mm_table->entries[count].vddc); |
| 1762 | table->AcpLevel[count].MinVoltage.VddGfx = |
| 1763 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1764 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1765 | mm_table->entries[count].vddgfx) : 0; |
| 1766 | table->AcpLevel[count].MinVoltage.Vddci = |
| 1767 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1768 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1769 | table->AcpLevel[count].MinVoltage.Phases = 1; |
| 1770 | |
| 1771 | /* retrieve divider value for VBIOS */ |
| 1772 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1773 | table->AcpLevel[count].Frequency, ÷rs); |
| 1774 | PP_ASSERT_WITH_CODE((0 == result), |
| 1775 | "can not find divide id for engine clock", return result); |
| 1776 | |
| 1777 | table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
| 1778 | |
| 1779 | CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); |
| 1780 | } |
| 1781 | |
| 1782 | return result; |
| 1783 | } |
| 1784 | |
| 1785 | static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr, |
| 1786 | SMU72_Discrete_DpmTable *table) |
| 1787 | { |
| 1788 | int result = 0; |
| 1789 | uint8_t count; |
| 1790 | pp_atomctrl_clock_dividers_vi dividers; |
| 1791 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1792 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1793 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 1794 | |
| 1795 | table->SamuBootLevel = 0; |
| 1796 | table->SamuLevelCount = (uint8_t) (mm_table->count); |
| 1797 | |
| 1798 | for (count = 0; count < table->SamuLevelCount; count++) { |
| 1799 | /* not sure whether we need evclk or not */ |
| 1800 | table->SamuLevel[count].Frequency = |
| 1801 | pptable_info->mm_dep_table->entries[count].samclock; |
| 1802 | table->SamuLevel[count].MinVoltage.Vddc = |
| 1803 | tonga_get_voltage_index(pptable_info->vddc_lookup_table, |
| 1804 | mm_table->entries[count].vddc); |
| 1805 | table->SamuLevel[count].MinVoltage.VddGfx = |
| 1806 | (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ? |
| 1807 | tonga_get_voltage_index(pptable_info->vddgfx_lookup_table, |
| 1808 | mm_table->entries[count].vddgfx) : 0; |
| 1809 | table->SamuLevel[count].MinVoltage.Vddci = |
| 1810 | tonga_get_voltage_id(&data->vddci_voltage_table, |
| 1811 | mm_table->entries[count].vddc - data->vddc_vddci_delta); |
| 1812 | table->SamuLevel[count].MinVoltage.Phases = 1; |
| 1813 | |
| 1814 | /* retrieve divider value for VBIOS */ |
| 1815 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 1816 | table->SamuLevel[count].Frequency, ÷rs); |
| 1817 | PP_ASSERT_WITH_CODE((0 == result), |
| 1818 | "can not find divide id for samu clock", return result); |
| 1819 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1820 | table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1821 | |
| 1822 | CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); |
| 1823 | } |
| 1824 | |
| 1825 | return result; |
| 1826 | } |
| 1827 | |
| 1828 | /** |
| 1829 | * Populates the SMC MCLK structure using the provided memory clock |
| 1830 | * |
| 1831 | * @param hwmgr the address of the hardware manager |
| 1832 | * @param memory_clock the memory clock to use to populate the structure |
| 1833 | * @param sclk the SMC SCLK structure to be populated |
| 1834 | */ |
| 1835 | static int tonga_calculate_mclk_params( |
| 1836 | struct pp_hwmgr *hwmgr, |
| 1837 | uint32_t memory_clock, |
| 1838 | SMU72_Discrete_MemoryLevel *mclk, |
| 1839 | bool strobe_mode, |
| 1840 | bool dllStateOn |
| 1841 | ) |
| 1842 | { |
| 1843 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 1844 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; |
| 1845 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; |
| 1846 | uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; |
| 1847 | uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; |
| 1848 | uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; |
| 1849 | uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; |
| 1850 | uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; |
| 1851 | uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; |
| 1852 | uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; |
| 1853 | |
| 1854 | pp_atomctrl_memory_clock_param mpll_param; |
| 1855 | int result; |
| 1856 | |
| 1857 | result = atomctrl_get_memory_pll_dividers_si(hwmgr, |
| 1858 | memory_clock, &mpll_param, strobe_mode); |
| 1859 | PP_ASSERT_WITH_CODE(0 == result, |
| 1860 | "Error retrieving Memory Clock Parameters from VBIOS.", return result); |
| 1861 | |
| 1862 | /* MPLL_FUNC_CNTL setup*/ |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 1863 | mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 1864 | |
| 1865 | /* MPLL_FUNC_CNTL_1 setup*/ |
| 1866 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, |
| 1867 | MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); |
| 1868 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, |
| 1869 | MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); |
| 1870 | mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, |
| 1871 | MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); |
| 1872 | |
| 1873 | /* MPLL_AD_FUNC_CNTL setup*/ |
| 1874 | mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, |
| 1875 | MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); |
| 1876 | |
| 1877 | if (data->is_memory_GDDR5) { |
| 1878 | /* MPLL_DQ_FUNC_CNTL setup*/ |
| 1879 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, |
| 1880 | MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); |
| 1881 | mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, |
| 1882 | MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); |
| 1883 | } |
| 1884 | |
| 1885 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 1886 | PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { |
| 1887 | /* |
| 1888 | ************************************ |
| 1889 | Fref = Reference Frequency |
| 1890 | NF = Feedback divider ratio |
| 1891 | NR = Reference divider ratio |
| 1892 | Fnom = Nominal VCO output frequency = Fref * NF / NR |
| 1893 | Fs = Spreading Rate |
| 1894 | D = Percentage down-spread / 2 |
| 1895 | Fint = Reference input frequency to PFD = Fref / NR |
| 1896 | NS = Spreading rate divider ratio = int(Fint / (2 * Fs)) |
| 1897 | CLKS = NS - 1 = ISS_STEP_NUM[11:0] |
| 1898 | NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2) |
| 1899 | CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] |
| 1900 | ************************************* |
| 1901 | */ |
| 1902 | pp_atomctrl_internal_ss_info ss_info; |
| 1903 | uint32_t freq_nom; |
| 1904 | uint32_t tmp; |
| 1905 | uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); |
| 1906 | |
| 1907 | /* for GDDR5 for all modes and DDR3 */ |
| 1908 | if (1 == mpll_param.qdr) |
| 1909 | freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); |
| 1910 | else |
| 1911 | freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); |
| 1912 | |
| 1913 | /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ |
| 1914 | tmp = (freq_nom / reference_clock); |
| 1915 | tmp = tmp * tmp; |
| 1916 | |
| 1917 | if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { |
| 1918 | /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */ |
| 1919 | /* ss.Info.speed_spectrum_rate -- in unit of khz */ |
| 1920 | /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */ |
| 1921 | /* = reference_clock * 5 / speed_spectrum_rate */ |
| 1922 | uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; |
| 1923 | |
| 1924 | /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */ |
| 1925 | /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */ |
| 1926 | uint32_t clkv = |
| 1927 | (uint32_t)((((131 * ss_info.speed_spectrum_percentage * |
| 1928 | ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); |
| 1929 | |
| 1930 | mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); |
| 1931 | mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); |
| 1932 | } |
| 1933 | } |
| 1934 | |
| 1935 | /* MCLK_PWRMGT_CNTL setup */ |
| 1936 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 1937 | MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); |
| 1938 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 1939 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); |
| 1940 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 1941 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); |
| 1942 | |
| 1943 | |
| 1944 | /* Save the result data to outpupt memory level structure */ |
| 1945 | mclk->MclkFrequency = memory_clock; |
| 1946 | mclk->MpllFuncCntl = mpll_func_cntl; |
| 1947 | mclk->MpllFuncCntl_1 = mpll_func_cntl_1; |
| 1948 | mclk->MpllFuncCntl_2 = mpll_func_cntl_2; |
| 1949 | mclk->MpllAdFuncCntl = mpll_ad_func_cntl; |
| 1950 | mclk->MpllDqFuncCntl = mpll_dq_func_cntl; |
| 1951 | mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; |
| 1952 | mclk->DllCntl = dll_cntl; |
| 1953 | mclk->MpllSs1 = mpll_ss1; |
| 1954 | mclk->MpllSs2 = mpll_ss2; |
| 1955 | |
| 1956 | return 0; |
| 1957 | } |
| 1958 | |
| 1959 | static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, |
| 1960 | bool strobe_mode) |
| 1961 | { |
| 1962 | uint8_t mc_para_index; |
| 1963 | |
| 1964 | if (strobe_mode) { |
| 1965 | if (memory_clock < 12500) { |
| 1966 | mc_para_index = 0x00; |
| 1967 | } else if (memory_clock > 47500) { |
| 1968 | mc_para_index = 0x0f; |
| 1969 | } else { |
| 1970 | mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); |
| 1971 | } |
| 1972 | } else { |
| 1973 | if (memory_clock < 65000) { |
| 1974 | mc_para_index = 0x00; |
| 1975 | } else if (memory_clock > 135000) { |
| 1976 | mc_para_index = 0x0f; |
| 1977 | } else { |
| 1978 | mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); |
| 1979 | } |
| 1980 | } |
| 1981 | |
| 1982 | return mc_para_index; |
| 1983 | } |
| 1984 | |
| 1985 | static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) |
| 1986 | { |
| 1987 | uint8_t mc_para_index; |
| 1988 | |
| 1989 | if (memory_clock < 10000) { |
| 1990 | mc_para_index = 0; |
| 1991 | } else if (memory_clock >= 80000) { |
| 1992 | mc_para_index = 0x0f; |
| 1993 | } else { |
| 1994 | mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); |
| 1995 | } |
| 1996 | |
| 1997 | return mc_para_index; |
| 1998 | } |
| 1999 | |
| 2000 | static int tonga_populate_single_memory_level( |
| 2001 | struct pp_hwmgr *hwmgr, |
| 2002 | uint32_t memory_clock, |
| 2003 | SMU72_Discrete_MemoryLevel *memory_level |
| 2004 | ) |
| 2005 | { |
| 2006 | uint32_t minMvdd = 0; |
| 2007 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2008 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2009 | int result = 0; |
| 2010 | bool dllStateOn; |
| 2011 | struct cgs_display_info info = {0}; |
| 2012 | |
| 2013 | |
| 2014 | if (NULL != pptable_info->vdd_dep_on_mclk) { |
| 2015 | result = tonga_get_dependecy_volt_by_clk(hwmgr, |
| 2016 | pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd); |
| 2017 | PP_ASSERT_WITH_CODE((0 == result), |
| 2018 | "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); |
| 2019 | } |
| 2020 | |
| 2021 | if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) { |
| 2022 | memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value; |
| 2023 | } else { |
| 2024 | memory_level->MinMvdd = minMvdd; |
| 2025 | } |
| 2026 | memory_level->EnabledForThrottle = 1; |
| 2027 | memory_level->EnabledForActivity = 0; |
| 2028 | memory_level->UpHyst = 0; |
| 2029 | memory_level->DownHyst = 100; |
| 2030 | memory_level->VoltageDownHyst = 0; |
| 2031 | |
| 2032 | /* Indicates maximum activity level for this performance level.*/ |
| 2033 | memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target; |
| 2034 | memory_level->StutterEnable = 0; |
| 2035 | memory_level->StrobeEnable = 0; |
| 2036 | memory_level->EdcReadEnable = 0; |
| 2037 | memory_level->EdcWriteEnable = 0; |
| 2038 | memory_level->RttEnable = 0; |
| 2039 | |
| 2040 | /* default set to low watermark. Highest level will be set to high later.*/ |
| 2041 | memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2042 | |
| 2043 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 2044 | data->display_timing.num_existing_displays = info.display_count; |
| 2045 | |
| 2046 | if ((data->mclk_stutter_mode_threshold != 0) && |
Alex Deucher | 7e8d1fb | 2016-04-08 16:42:38 -0400 | [diff] [blame] | 2047 | (memory_clock <= data->mclk_stutter_mode_threshold) && |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 2048 | (!data->is_uvd_enabled) |
Alex Deucher | 7e8d1fb | 2016-04-08 16:42:38 -0400 | [diff] [blame] | 2049 | && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) |
| 2050 | && (data->display_timing.num_existing_displays <= 2) |
| 2051 | && (data->display_timing.num_existing_displays != 0)) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2052 | memory_level->StutterEnable = 1; |
| 2053 | |
| 2054 | /* decide strobe mode*/ |
| 2055 | memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) && |
| 2056 | (memory_clock <= data->mclk_strobe_mode_threshold); |
| 2057 | |
| 2058 | /* decide EDC mode and memory clock ratio*/ |
| 2059 | if (data->is_memory_GDDR5) { |
| 2060 | memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock, |
| 2061 | memory_level->StrobeEnable); |
| 2062 | |
| 2063 | if ((data->mclk_edc_enable_threshold != 0) && |
| 2064 | (memory_clock > data->mclk_edc_enable_threshold)) { |
| 2065 | memory_level->EdcReadEnable = 1; |
| 2066 | } |
| 2067 | |
| 2068 | if ((data->mclk_edc_wr_enable_threshold != 0) && |
| 2069 | (memory_clock > data->mclk_edc_wr_enable_threshold)) { |
| 2070 | memory_level->EdcWriteEnable = 1; |
| 2071 | } |
| 2072 | |
| 2073 | if (memory_level->StrobeEnable) { |
| 2074 | if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >= |
| 2075 | ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) { |
| 2076 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; |
| 2077 | } else { |
| 2078 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; |
| 2079 | } |
| 2080 | |
| 2081 | } else { |
| 2082 | dllStateOn = data->dll_defaule_on; |
| 2083 | } |
| 2084 | } else { |
| 2085 | memory_level->StrobeRatio = |
| 2086 | tonga_get_ddr3_mclk_frequency_ratio(memory_clock); |
| 2087 | dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; |
| 2088 | } |
| 2089 | |
| 2090 | result = tonga_calculate_mclk_params(hwmgr, |
| 2091 | memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn); |
| 2092 | |
| 2093 | if (0 == result) { |
| 2094 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd); |
| 2095 | /* MCLK frequency in units of 10KHz*/ |
| 2096 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); |
| 2097 | /* Indicates maximum activity level for this performance level.*/ |
| 2098 | CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); |
| 2099 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); |
| 2100 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); |
| 2101 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); |
| 2102 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); |
| 2103 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); |
| 2104 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); |
| 2105 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); |
| 2106 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); |
| 2107 | CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); |
| 2108 | } |
| 2109 | |
| 2110 | return result; |
| 2111 | } |
| 2112 | |
| 2113 | /** |
| 2114 | * Populates the SMC MVDD structure using the provided memory clock. |
| 2115 | * |
| 2116 | * @param hwmgr the address of the hardware manager |
| 2117 | * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. |
| 2118 | * @param voltage the SMC VOLTAGE structure to be populated |
| 2119 | */ |
| 2120 | int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern) |
| 2121 | { |
| 2122 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2123 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2124 | uint32_t i = 0; |
| 2125 | |
| 2126 | if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) { |
| 2127 | /* find mvdd value which clock is more than request */ |
| 2128 | for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) { |
| 2129 | if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) { |
| 2130 | /* Always round to higher voltage. */ |
| 2131 | smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value; |
| 2132 | break; |
| 2133 | } |
| 2134 | } |
| 2135 | |
| 2136 | PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count, |
| 2137 | "MVDD Voltage is outside the supported range.", return -1); |
| 2138 | |
| 2139 | } else { |
| 2140 | return -1; |
| 2141 | } |
| 2142 | |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
| 2146 | |
| 2147 | static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr, |
| 2148 | SMU72_Discrete_DpmTable *table) |
| 2149 | { |
| 2150 | int result = 0; |
| 2151 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2152 | pp_atomctrl_clock_dividers_vi dividers; |
| 2153 | SMIO_Pattern voltage_level; |
| 2154 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; |
| 2155 | uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; |
| 2156 | uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; |
| 2157 | uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; |
| 2158 | |
| 2159 | /* The ACPI state should not do DPM on DC (or ever).*/ |
| 2160 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; |
| 2161 | |
| 2162 | table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage; |
| 2163 | |
| 2164 | /* assign zero for now*/ |
| 2165 | table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); |
| 2166 | |
| 2167 | /* get the engine clock dividers for this clock value*/ |
| 2168 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, |
| 2169 | table->ACPILevel.SclkFrequency, ÷rs); |
| 2170 | |
| 2171 | PP_ASSERT_WITH_CODE(result == 0, |
| 2172 | "Error retrieving Engine Clock dividers from VBIOS.", return result); |
| 2173 | |
| 2174 | /* divider ID for required SCLK*/ |
| 2175 | table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; |
| 2176 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2177 | table->ACPILevel.DeepSleepDivId = 0; |
| 2178 | |
| 2179 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2180 | CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); |
| 2181 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2182 | CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); |
| 2183 | spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, |
| 2184 | CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); |
| 2185 | |
| 2186 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; |
| 2187 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; |
| 2188 | table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; |
| 2189 | table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; |
| 2190 | table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; |
| 2191 | table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; |
| 2192 | table->ACPILevel.CcPwrDynRm = 0; |
| 2193 | table->ACPILevel.CcPwrDynRm1 = 0; |
| 2194 | |
| 2195 | |
| 2196 | /* For various features to be enabled/disabled while this level is active.*/ |
| 2197 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); |
| 2198 | /* SCLK frequency in units of 10KHz*/ |
| 2199 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); |
| 2200 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); |
| 2201 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); |
| 2202 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); |
| 2203 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); |
| 2204 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); |
| 2205 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); |
| 2206 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); |
| 2207 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); |
| 2208 | |
| 2209 | /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ |
| 2210 | table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage; |
| 2211 | |
| 2212 | /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/ |
| 2213 | |
| 2214 | if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level)) |
| 2215 | table->MemoryACPILevel.MinMvdd = |
| 2216 | PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); |
| 2217 | else |
| 2218 | table->MemoryACPILevel.MinMvdd = 0; |
| 2219 | |
| 2220 | /* Force reset on DLL*/ |
| 2221 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2222 | MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); |
| 2223 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2224 | MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); |
| 2225 | |
| 2226 | /* Disable DLL in ACPIState*/ |
| 2227 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2228 | MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); |
| 2229 | mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, |
| 2230 | MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); |
| 2231 | |
| 2232 | /* Enable DLL bypass signal*/ |
| 2233 | dll_cntl = PHM_SET_FIELD(dll_cntl, |
| 2234 | DLL_CNTL, MRDCK0_BYPASS, 0); |
| 2235 | dll_cntl = PHM_SET_FIELD(dll_cntl, |
| 2236 | DLL_CNTL, MRDCK1_BYPASS, 0); |
| 2237 | |
| 2238 | table->MemoryACPILevel.DllCntl = |
| 2239 | PP_HOST_TO_SMC_UL(dll_cntl); |
| 2240 | table->MemoryACPILevel.MclkPwrmgtCntl = |
| 2241 | PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); |
| 2242 | table->MemoryACPILevel.MpllAdFuncCntl = |
| 2243 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); |
| 2244 | table->MemoryACPILevel.MpllDqFuncCntl = |
| 2245 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); |
| 2246 | table->MemoryACPILevel.MpllFuncCntl = |
| 2247 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); |
| 2248 | table->MemoryACPILevel.MpllFuncCntl_1 = |
| 2249 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); |
| 2250 | table->MemoryACPILevel.MpllFuncCntl_2 = |
| 2251 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); |
| 2252 | table->MemoryACPILevel.MpllSs1 = |
| 2253 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); |
| 2254 | table->MemoryACPILevel.MpllSs2 = |
| 2255 | PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); |
| 2256 | |
| 2257 | table->MemoryACPILevel.EnabledForThrottle = 0; |
| 2258 | table->MemoryACPILevel.EnabledForActivity = 0; |
| 2259 | table->MemoryACPILevel.UpHyst = 0; |
| 2260 | table->MemoryACPILevel.DownHyst = 100; |
| 2261 | table->MemoryACPILevel.VoltageDownHyst = 0; |
| 2262 | /* Indicates maximum activity level for this performance level.*/ |
| 2263 | table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); |
| 2264 | |
| 2265 | table->MemoryACPILevel.StutterEnable = 0; |
| 2266 | table->MemoryACPILevel.StrobeEnable = 0; |
| 2267 | table->MemoryACPILevel.EdcReadEnable = 0; |
| 2268 | table->MemoryACPILevel.EdcWriteEnable = 0; |
| 2269 | table->MemoryACPILevel.RttEnable = 0; |
| 2270 | |
| 2271 | return result; |
| 2272 | } |
| 2273 | |
| 2274 | static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level) |
| 2275 | { |
| 2276 | int result = 0; |
| 2277 | uint32_t i; |
| 2278 | |
| 2279 | for (i = 0; i < table->count; i++) { |
| 2280 | if (value == table->dpm_levels[i].value) { |
| 2281 | *boot_level = i; |
| 2282 | result = 0; |
| 2283 | } |
| 2284 | } |
| 2285 | return result; |
| 2286 | } |
| 2287 | |
| 2288 | static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, |
| 2289 | SMU72_Discrete_DpmTable *table) |
| 2290 | { |
| 2291 | int result = 0; |
| 2292 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2293 | |
| 2294 | table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */ |
| 2295 | table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */ |
| 2296 | |
| 2297 | /* find boot level from dpm table*/ |
| 2298 | result = tonga_find_boot_level(&(data->dpm_table.sclk_table), |
| 2299 | data->vbios_boot_state.sclk_bootup_value, |
| 2300 | (uint32_t *)&(data->smc_state_table.GraphicsBootLevel)); |
| 2301 | |
| 2302 | if (0 != result) { |
| 2303 | data->smc_state_table.GraphicsBootLevel = 0; |
| 2304 | printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ |
| 2305 | in dependency table. Using Graphics DPM level 0!"); |
| 2306 | result = 0; |
| 2307 | } |
| 2308 | |
| 2309 | result = tonga_find_boot_level(&(data->dpm_table.mclk_table), |
| 2310 | data->vbios_boot_state.mclk_bootup_value, |
| 2311 | (uint32_t *)&(data->smc_state_table.MemoryBootLevel)); |
| 2312 | |
| 2313 | if (0 != result) { |
| 2314 | data->smc_state_table.MemoryBootLevel = 0; |
| 2315 | printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ |
| 2316 | in dependency table. Using Memory DPM level 0!"); |
| 2317 | result = 0; |
| 2318 | } |
| 2319 | |
| 2320 | table->BootVoltage.Vddc = |
| 2321 | tonga_get_voltage_id(&(data->vddc_voltage_table), |
| 2322 | data->vbios_boot_state.vddc_bootup_value); |
| 2323 | table->BootVoltage.VddGfx = |
| 2324 | tonga_get_voltage_id(&(data->vddgfx_voltage_table), |
| 2325 | data->vbios_boot_state.vddgfx_bootup_value); |
| 2326 | table->BootVoltage.Vddci = |
| 2327 | tonga_get_voltage_id(&(data->vddci_voltage_table), |
| 2328 | data->vbios_boot_state.vddci_bootup_value); |
| 2329 | table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; |
| 2330 | |
| 2331 | CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); |
| 2332 | |
| 2333 | return result; |
| 2334 | } |
| 2335 | |
| 2336 | |
| 2337 | /** |
| 2338 | * Calculates the SCLK dividers using the provided engine clock |
| 2339 | * |
| 2340 | * @param hwmgr the address of the hardware manager |
| 2341 | * @param engine_clock the engine clock to use to populate the structure |
| 2342 | * @param sclk the SMC SCLK structure to be populated |
| 2343 | */ |
| 2344 | int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, |
| 2345 | uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) |
| 2346 | { |
| 2347 | const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2348 | pp_atomctrl_clock_dividers_vi dividers; |
| 2349 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; |
| 2350 | uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; |
| 2351 | uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; |
| 2352 | uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; |
| 2353 | uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; |
| 2354 | uint32_t reference_clock; |
| 2355 | uint32_t reference_divider; |
| 2356 | uint32_t fbdiv; |
| 2357 | int result; |
| 2358 | |
| 2359 | /* get the engine clock dividers for this clock value*/ |
| 2360 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); |
| 2361 | |
| 2362 | PP_ASSERT_WITH_CODE(result == 0, |
| 2363 | "Error retrieving Engine Clock dividers from VBIOS.", return result); |
| 2364 | |
| 2365 | /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/ |
| 2366 | reference_clock = atomctrl_get_reference_clock(hwmgr); |
| 2367 | |
| 2368 | reference_divider = 1 + dividers.uc_pll_ref_div; |
| 2369 | |
| 2370 | /* low 14 bits is fraction and high 12 bits is divider*/ |
| 2371 | fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; |
| 2372 | |
| 2373 | /* SPLL_FUNC_CNTL setup*/ |
| 2374 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2375 | CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); |
| 2376 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, |
| 2377 | CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); |
| 2378 | |
| 2379 | /* SPLL_FUNC_CNTL_3 setup*/ |
| 2380 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, |
| 2381 | CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); |
| 2382 | |
| 2383 | /* set to use fractional accumulation*/ |
| 2384 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, |
| 2385 | CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); |
| 2386 | |
| 2387 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2388 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { |
| 2389 | pp_atomctrl_internal_ss_info ss_info; |
| 2390 | |
| 2391 | uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; |
| 2392 | if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { |
| 2393 | /* |
| 2394 | * ss_info.speed_spectrum_percentage -- in unit of 0.01% |
| 2395 | * ss_info.speed_spectrum_rate -- in unit of khz |
| 2396 | */ |
| 2397 | /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */ |
| 2398 | uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); |
| 2399 | |
| 2400 | /* clkv = 2 * D * fbdiv / NS */ |
| 2401 | uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); |
| 2402 | |
| 2403 | cg_spll_spread_spectrum = |
| 2404 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS); |
| 2405 | cg_spll_spread_spectrum = |
| 2406 | PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); |
| 2407 | cg_spll_spread_spectrum_2 = |
| 2408 | PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV); |
| 2409 | } |
| 2410 | } |
| 2411 | |
| 2412 | sclk->SclkFrequency = engine_clock; |
| 2413 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; |
| 2414 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; |
| 2415 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; |
| 2416 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; |
| 2417 | sclk->SclkDid = (uint8_t)dividers.pll_post_divider; |
| 2418 | |
| 2419 | return 0; |
| 2420 | } |
| 2421 | |
Nils Wallménius | 438498a | 2016-05-05 09:07:48 +0200 | [diff] [blame] | 2422 | static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock, |
| 2423 | uint32_t min_engine_clock_in_sr) |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2424 | { |
| 2425 | uint32_t i, temp; |
Nils Wallménius | 9887e42 | 2016-05-05 09:07:46 +0200 | [diff] [blame] | 2426 | uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK); |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2427 | |
| 2428 | PP_ASSERT_WITH_CODE((engine_clock >= min), |
| 2429 | "Engine clock can't satisfy stutter requirement!", return 0); |
| 2430 | |
| 2431 | for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) { |
Nils Wallménius | 354ef92 | 2016-05-05 09:07:47 +0200 | [diff] [blame] | 2432 | temp = engine_clock >> i; |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2433 | |
| 2434 | if(temp >= min || i == 0) |
| 2435 | break; |
| 2436 | } |
| 2437 | return (uint8_t)i; |
| 2438 | } |
| 2439 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2440 | /** |
| 2441 | * Populates single SMC SCLK structure using the provided engine clock |
| 2442 | * |
| 2443 | * @param hwmgr the address of the hardware manager |
| 2444 | * @param engine_clock the engine clock to use to populate the structure |
| 2445 | * @param sclk the SMC SCLK structure to be populated |
| 2446 | */ |
| 2447 | static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level) |
| 2448 | { |
| 2449 | int result; |
| 2450 | uint32_t threshold; |
| 2451 | uint32_t mvdd; |
| 2452 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2453 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2454 | |
| 2455 | result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); |
| 2456 | |
| 2457 | |
| 2458 | /* populate graphics levels*/ |
| 2459 | result = tonga_get_dependecy_volt_by_clk(hwmgr, |
| 2460 | pptable_info->vdd_dep_on_sclk, engine_clock, |
| 2461 | &graphic_level->MinVoltage, &mvdd); |
| 2462 | PP_ASSERT_WITH_CODE((0 == result), |
| 2463 | "can not find VDDC voltage value for VDDC \ |
| 2464 | engine clock dependency table", return result); |
| 2465 | |
| 2466 | /* SCLK frequency in units of 10KHz*/ |
| 2467 | graphic_level->SclkFrequency = engine_clock; |
| 2468 | |
| 2469 | /* Indicates maximum activity level for this performance level. 50% for now*/ |
| 2470 | graphic_level->ActivityLevel = sclk_activity_level_threshold; |
| 2471 | |
| 2472 | graphic_level->CcPwrDynRm = 0; |
| 2473 | graphic_level->CcPwrDynRm1 = 0; |
| 2474 | /* this level can be used if activity is high enough.*/ |
| 2475 | graphic_level->EnabledForActivity = 0; |
| 2476 | /* this level can be used for throttling.*/ |
| 2477 | graphic_level->EnabledForThrottle = 1; |
| 2478 | graphic_level->UpHyst = 0; |
| 2479 | graphic_level->DownHyst = 0; |
| 2480 | graphic_level->VoltageDownHyst = 0; |
| 2481 | graphic_level->PowerThrottle = 0; |
| 2482 | |
| 2483 | threshold = engine_clock * data->fast_watemark_threshold / 100; |
| 2484 | /* |
| 2485 | *get the DAL clock. do it in funture. |
| 2486 | PECI_GetMinClockSettings(hwmgr->peci, &minClocks); |
| 2487 | data->display_timing.min_clock_insr = minClocks.engineClockInSR; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2488 | */ |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2489 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2490 | PHM_PlatformCaps_SclkDeepSleep)) |
| 2491 | graphic_level->DeepSleepDivId = |
Nils Wallménius | 438498a | 2016-05-05 09:07:48 +0200 | [diff] [blame] | 2492 | tonga_get_sleep_divider_id_from_clock(engine_clock, |
Eric Huang | a4333b4 | 2016-03-30 16:30:12 -0400 | [diff] [blame] | 2493 | data->display_timing.min_clock_insr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2494 | |
| 2495 | /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ |
| 2496 | graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2497 | |
| 2498 | if (0 == result) { |
| 2499 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/ |
| 2500 | /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/ |
| 2501 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); |
| 2502 | CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); |
| 2503 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); |
| 2504 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); |
| 2505 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); |
| 2506 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); |
| 2507 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); |
| 2508 | CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); |
| 2509 | } |
| 2510 | |
| 2511 | return result; |
| 2512 | } |
| 2513 | |
| 2514 | /** |
| 2515 | * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states |
| 2516 | * |
| 2517 | * @param hwmgr the address of the hardware manager |
| 2518 | */ |
| 2519 | static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) |
| 2520 | { |
| 2521 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2522 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2523 | struct tonga_dpm_table *dpm_table = &data->dpm_table; |
| 2524 | phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; |
| 2525 | uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; |
| 2526 | int result = 0; |
| 2527 | uint32_t level_array_adress = data->dpm_table_start + |
| 2528 | offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); |
| 2529 | uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) * |
| 2530 | SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/ |
| 2531 | SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; |
| 2532 | uint32_t i, maxEntry; |
| 2533 | uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0; |
| 2534 | PECI_RegistryValue reg_value; |
| 2535 | memset(levels, 0x00, level_array_size); |
| 2536 | |
| 2537 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
| 2538 | result = tonga_populate_single_graphic_level(hwmgr, |
| 2539 | dpm_table->sclk_table.dpm_levels[i].value, |
| 2540 | (uint16_t)data->activity_target[i], |
| 2541 | &(data->smc_state_table.GraphicsLevel[i])); |
| 2542 | |
| 2543 | if (0 != result) |
| 2544 | return result; |
| 2545 | |
| 2546 | /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ |
| 2547 | if (i > 1) |
| 2548 | data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; |
| 2549 | |
| 2550 | if (0 == i) { |
| 2551 | reg_value = 0; |
| 2552 | if (reg_value != 0) |
| 2553 | data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value; |
| 2554 | } |
| 2555 | |
| 2556 | if (1 == i) { |
| 2557 | reg_value = 0; |
| 2558 | if (reg_value != 0) |
| 2559 | data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value; |
| 2560 | } |
| 2561 | } |
| 2562 | |
| 2563 | /* Only enable level 0 for now. */ |
| 2564 | data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; |
| 2565 | |
| 2566 | /* set highest level watermark to high */ |
| 2567 | if (dpm_table->sclk_table.count > 1) |
| 2568 | data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = |
| 2569 | PPSMC_DISPLAY_WATERMARK_HIGH; |
| 2570 | |
| 2571 | data->smc_state_table.GraphicsDpmLevelCount = |
| 2572 | (uint8_t)dpm_table->sclk_table.count; |
| 2573 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = |
| 2574 | tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); |
| 2575 | |
| 2576 | if (pcie_table != NULL) { |
| 2577 | PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), |
| 2578 | "There must be 1 or more PCIE levels defined in PPTable.", return -1); |
| 2579 | maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/ |
| 2580 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
| 2581 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = |
| 2582 | (uint8_t) ((i < maxEntry) ? i : maxEntry); |
| 2583 | } |
| 2584 | } else { |
| 2585 | if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) |
| 2586 | printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!"); |
| 2587 | |
| 2588 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && |
| 2589 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2590 | (1<<(highest_pcie_level_enabled+1))) != 0)) { |
| 2591 | highest_pcie_level_enabled++; |
| 2592 | } |
| 2593 | |
| 2594 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && |
| 2595 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2596 | (1<<lowest_pcie_level_enabled)) == 0)) { |
| 2597 | lowest_pcie_level_enabled++; |
| 2598 | } |
| 2599 | |
| 2600 | while ((count < highest_pcie_level_enabled) && |
| 2601 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2602 | (1<<(lowest_pcie_level_enabled+1+count))) == 0)) { |
| 2603 | count++; |
| 2604 | } |
| 2605 | mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ? |
| 2606 | (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled; |
| 2607 | |
| 2608 | |
| 2609 | /* set pcieDpmLevel to highest_pcie_level_enabled*/ |
| 2610 | for (i = 2; i < dpm_table->sclk_table.count; i++) { |
| 2611 | data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; |
| 2612 | } |
| 2613 | |
| 2614 | /* set pcieDpmLevel to lowest_pcie_level_enabled*/ |
| 2615 | data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; |
| 2616 | |
| 2617 | /* set pcieDpmLevel to mid_pcie_level_enabled*/ |
| 2618 | data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; |
| 2619 | } |
| 2620 | /* level count will send to smc once at init smc table and never change*/ |
| 2621 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); |
| 2622 | |
| 2623 | if (0 != result) |
| 2624 | return result; |
| 2625 | |
| 2626 | return 0; |
| 2627 | } |
| 2628 | |
| 2629 | /** |
| 2630 | * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states |
| 2631 | * |
| 2632 | * @param hwmgr the address of the hardware manager |
| 2633 | */ |
| 2634 | |
| 2635 | static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) |
| 2636 | { |
| 2637 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2638 | struct tonga_dpm_table *dpm_table = &data->dpm_table; |
| 2639 | int result; |
| 2640 | /* populate MCLK dpm table to SMU7 */ |
| 2641 | uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel); |
| 2642 | uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY; |
| 2643 | SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel; |
| 2644 | uint32_t i; |
| 2645 | |
| 2646 | memset(levels, 0x00, level_array_size); |
| 2647 | |
| 2648 | for (i = 0; i < dpm_table->mclk_table.count; i++) { |
| 2649 | PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), |
| 2650 | "can not populate memory level as memory clock is zero", return -1); |
| 2651 | result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, |
| 2652 | &(data->smc_state_table.MemoryLevel[i])); |
| 2653 | if (0 != result) { |
| 2654 | return result; |
| 2655 | } |
| 2656 | } |
| 2657 | |
| 2658 | /* Only enable level 0 for now.*/ |
| 2659 | data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; |
| 2660 | |
| 2661 | /* |
| 2662 | * in order to prevent MC activity from stutter mode to push DPM up. |
| 2663 | * the UVD change complements this by putting the MCLK in a higher state |
| 2664 | * by default such that we are not effected by up threshold or and MCLK DPM latency. |
| 2665 | */ |
| 2666 | data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; |
| 2667 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel); |
| 2668 | |
| 2669 | data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; |
| 2670 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); |
| 2671 | /* set highest level watermark to high*/ |
| 2672 | data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; |
| 2673 | |
| 2674 | /* level count will send to smc once at init smc table and never change*/ |
| 2675 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, |
| 2676 | level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end); |
| 2677 | |
| 2678 | if (0 != result) { |
| 2679 | return result; |
| 2680 | } |
| 2681 | |
| 2682 | return 0; |
| 2683 | } |
| 2684 | |
| 2685 | struct TONGA_DLL_SPEED_SETTING { |
| 2686 | uint16_t Min; /* Minimum Data Rate*/ |
| 2687 | uint16_t Max; /* Maximum Data Rate*/ |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 2688 | uint32_t dll_speed; /* The desired DLL_SPEED setting*/ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2689 | }; |
| 2690 | |
| 2691 | static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) |
| 2692 | { |
| 2693 | return 0; |
| 2694 | } |
| 2695 | |
| 2696 | /* ---------------------------------------- ULV related functions ----------------------------------------------------*/ |
| 2697 | |
| 2698 | |
| 2699 | static int tonga_reset_single_dpm_table( |
| 2700 | struct pp_hwmgr *hwmgr, |
| 2701 | struct tonga_single_dpm_table *dpm_table, |
| 2702 | uint32_t count) |
| 2703 | { |
| 2704 | uint32_t i; |
| 2705 | if (!(count <= MAX_REGULAR_DPM_NUMBER)) |
| 2706 | printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \ |
| 2707 | table entries to exceed max number! \n"); |
| 2708 | |
| 2709 | dpm_table->count = count; |
| 2710 | for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2711 | dpm_table->dpm_levels[i].enabled = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2712 | } |
| 2713 | |
| 2714 | return 0; |
| 2715 | } |
| 2716 | |
| 2717 | static void tonga_setup_pcie_table_entry( |
| 2718 | struct tonga_single_dpm_table *dpm_table, |
| 2719 | uint32_t index, uint32_t pcie_gen, |
| 2720 | uint32_t pcie_lanes) |
| 2721 | { |
| 2722 | dpm_table->dpm_levels[index].value = pcie_gen; |
| 2723 | dpm_table->dpm_levels[index].param1 = pcie_lanes; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2724 | dpm_table->dpm_levels[index].enabled = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2725 | } |
| 2726 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2727 | static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr) |
| 2728 | { |
| 2729 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2730 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2731 | phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; |
| 2732 | uint32_t i, maxEntry; |
| 2733 | |
| 2734 | if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) { |
| 2735 | data->pcie_gen_power_saving = data->pcie_gen_performance; |
| 2736 | data->pcie_lane_power_saving = data->pcie_lane_performance; |
| 2737 | } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) { |
| 2738 | data->pcie_gen_performance = data->pcie_gen_power_saving; |
| 2739 | data->pcie_lane_performance = data->pcie_lane_power_saving; |
| 2740 | } |
| 2741 | |
| 2742 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK); |
| 2743 | |
| 2744 | if (pcie_table != NULL) { |
| 2745 | /* |
| 2746 | * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue). |
| 2747 | * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry. |
| 2748 | */ |
| 2749 | maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ? |
| 2750 | SMU72_MAX_LEVELS_LINK : pcie_table->count; |
| 2751 | for (i = 1; i < maxEntry; i++) { |
| 2752 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1, |
| 2753 | get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed), |
| 2754 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2755 | } |
| 2756 | data->dpm_table.pcie_speed_table.count = maxEntry - 1; |
| 2757 | } else { |
| 2758 | /* Hardcode Pcie Table */ |
| 2759 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, |
| 2760 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), |
| 2761 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2762 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, |
| 2763 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), |
| 2764 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2765 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, |
| 2766 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2767 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2768 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, |
| 2769 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2770 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2771 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, |
| 2772 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2773 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2774 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, |
| 2775 | get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen), |
| 2776 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2777 | data->dpm_table.pcie_speed_table.count = 6; |
| 2778 | } |
| 2779 | /* Populate last level for boot PCIE level, but do not increment count. */ |
| 2780 | tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, |
| 2781 | data->dpm_table.pcie_speed_table.count, |
| 2782 | get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), |
| 2783 | get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); |
| 2784 | |
| 2785 | return 0; |
| 2786 | |
| 2787 | } |
| 2788 | |
| 2789 | /* |
| 2790 | * This function is to initalize all DPM state tables for SMU7 based on the dependency table. |
| 2791 | * Dynamic state patching function will then trim these state tables to the allowed range based |
| 2792 | * on the power policy or external client requests, such as UVD request, etc. |
| 2793 | */ |
| 2794 | static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) |
| 2795 | { |
| 2796 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2797 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2798 | uint32_t i; |
| 2799 | |
| 2800 | phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table = |
| 2801 | pptable_info->vdd_dep_on_sclk; |
| 2802 | phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table = |
| 2803 | pptable_info->vdd_dep_on_mclk; |
| 2804 | |
| 2805 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, |
| 2806 | "SCLK dependency table is missing. This table is mandatory", return -1); |
| 2807 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, |
| 2808 | "SCLK dependency table has to have is missing. This table is mandatory", return -1); |
| 2809 | |
| 2810 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, |
| 2811 | "MCLK dependency table is missing. This table is mandatory", return -1); |
| 2812 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, |
| 2813 | "VMCLK dependency table has to have is missing. This table is mandatory", return -1); |
| 2814 | |
| 2815 | /* clear the state table to reset everything to default */ |
| 2816 | memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); |
| 2817 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS); |
| 2818 | tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY); |
| 2819 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */ |
| 2820 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/ |
| 2821 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/ |
| 2822 | /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/ |
| 2823 | |
| 2824 | PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, |
| 2825 | "SCLK dependency table is missing. This table is mandatory", return -1); |
| 2826 | /* Initialize Sclk DPM table based on allow Sclk values*/ |
| 2827 | data->dpm_table.sclk_table.count = 0; |
| 2828 | |
| 2829 | for (i = 0; i < allowed_vdd_sclk_table->count; i++) { |
| 2830 | if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != |
| 2831 | allowed_vdd_sclk_table->entries[i].clk) { |
| 2832 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = |
| 2833 | allowed_vdd_sclk_table->entries[i].clk; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2834 | data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = true; /*(i==0) ? 1 : 0; to do */ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2835 | data->dpm_table.sclk_table.count++; |
| 2836 | } |
| 2837 | } |
| 2838 | |
| 2839 | PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, |
| 2840 | "MCLK dependency table is missing. This table is mandatory", return -1); |
| 2841 | /* Initialize Mclk DPM table based on allow Mclk values */ |
| 2842 | data->dpm_table.mclk_table.count = 0; |
| 2843 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { |
| 2844 | if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != |
| 2845 | allowed_vdd_mclk_table->entries[i].clk) { |
| 2846 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = |
| 2847 | allowed_vdd_mclk_table->entries[i].clk; |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 2848 | data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = true; /*(i==0) ? 1 : 0; */ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2849 | data->dpm_table.mclk_table.count++; |
| 2850 | } |
| 2851 | } |
| 2852 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2853 | /* setup PCIE gen speed levels*/ |
| 2854 | tonga_setup_default_pcie_tables(hwmgr); |
| 2855 | |
| 2856 | /* save a copy of the default DPM table*/ |
| 2857 | memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table)); |
| 2858 | |
| 2859 | return 0; |
| 2860 | } |
| 2861 | |
| 2862 | int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr, |
| 2863 | const struct tonga_power_state *bootState) |
| 2864 | { |
| 2865 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2866 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2867 | uint8_t count, level; |
| 2868 | |
| 2869 | count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count); |
| 2870 | for (level = 0; level < count; level++) { |
| 2871 | if (pptable_info->vdd_dep_on_sclk->entries[level].clk >= |
| 2872 | bootState->performance_levels[0].engine_clock) { |
| 2873 | data->smc_state_table.GraphicsBootLevel = level; |
| 2874 | break; |
| 2875 | } |
| 2876 | } |
| 2877 | |
| 2878 | count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count); |
| 2879 | for (level = 0; level < count; level++) { |
| 2880 | if (pptable_info->vdd_dep_on_mclk->entries[level].clk >= |
| 2881 | bootState->performance_levels[0].memory_clock) { |
| 2882 | data->smc_state_table.MemoryBootLevel = level; |
| 2883 | break; |
| 2884 | } |
| 2885 | } |
| 2886 | |
| 2887 | return 0; |
| 2888 | } |
| 2889 | |
| 2890 | /** |
| 2891 | * Initializes the SMC table and uploads it |
| 2892 | * |
| 2893 | * @param hwmgr the address of the powerplay hardware manager. |
| 2894 | * @param pInput the pointer to input data (PowerState) |
| 2895 | * @return always 0 |
| 2896 | */ |
| 2897 | int tonga_init_smc_table(struct pp_hwmgr *hwmgr) |
| 2898 | { |
| 2899 | int result; |
| 2900 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 2901 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2902 | SMU72_Discrete_DpmTable *table = &(data->smc_state_table); |
| 2903 | const phw_tonga_ulv_parm *ulv = &(data->ulv); |
| 2904 | uint8_t i; |
| 2905 | PECI_RegistryValue reg_value; |
| 2906 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; |
| 2907 | |
| 2908 | result = tonga_setup_default_dpm_tables(hwmgr); |
| 2909 | PP_ASSERT_WITH_CODE(0 == result, |
| 2910 | "Failed to setup default DPM tables!", return result;); |
| 2911 | memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table)); |
| 2912 | if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) { |
| 2913 | tonga_populate_smc_voltage_tables(hwmgr, table); |
| 2914 | } |
| 2915 | |
| 2916 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2917 | PHM_PlatformCaps_AutomaticDCTransition)) { |
| 2918 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; |
| 2919 | } |
| 2920 | |
| 2921 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2922 | PHM_PlatformCaps_StepVddc)) { |
| 2923 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; |
| 2924 | } |
| 2925 | |
| 2926 | if (data->is_memory_GDDR5) { |
| 2927 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; |
| 2928 | } |
| 2929 | |
| 2930 | i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN); |
| 2931 | |
| 2932 | if (i == 1 || i == 0) { |
| 2933 | table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL; |
| 2934 | } |
| 2935 | |
| 2936 | if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) { |
| 2937 | PP_ASSERT_WITH_CODE(0 == result, |
| 2938 | "Failed to initialize ULV state!", return result;); |
| 2939 | |
| 2940 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2941 | ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter); |
| 2942 | } |
| 2943 | |
| 2944 | result = tonga_populate_smc_link_level(hwmgr, table); |
| 2945 | PP_ASSERT_WITH_CODE(0 == result, |
| 2946 | "Failed to initialize Link Level!", return result;); |
| 2947 | |
| 2948 | result = tonga_populate_all_graphic_levels(hwmgr); |
| 2949 | PP_ASSERT_WITH_CODE(0 == result, |
| 2950 | "Failed to initialize Graphics Level!", return result;); |
| 2951 | |
| 2952 | result = tonga_populate_all_memory_levels(hwmgr); |
| 2953 | PP_ASSERT_WITH_CODE(0 == result, |
| 2954 | "Failed to initialize Memory Level!", return result;); |
| 2955 | |
| 2956 | result = tonga_populate_smv_acpi_level(hwmgr, table); |
| 2957 | PP_ASSERT_WITH_CODE(0 == result, |
| 2958 | "Failed to initialize ACPI Level!", return result;); |
| 2959 | |
| 2960 | result = tonga_populate_smc_vce_level(hwmgr, table); |
| 2961 | PP_ASSERT_WITH_CODE(0 == result, |
| 2962 | "Failed to initialize VCE Level!", return result;); |
| 2963 | |
| 2964 | result = tonga_populate_smc_acp_level(hwmgr, table); |
| 2965 | PP_ASSERT_WITH_CODE(0 == result, |
| 2966 | "Failed to initialize ACP Level!", return result;); |
| 2967 | |
| 2968 | result = tonga_populate_smc_samu_level(hwmgr, table); |
| 2969 | PP_ASSERT_WITH_CODE(0 == result, |
| 2970 | "Failed to initialize SAMU Level!", return result;); |
| 2971 | |
| 2972 | /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */ |
| 2973 | /* need to populate the ARB settings for the initial state. */ |
| 2974 | result = tonga_program_memory_timing_parameters(hwmgr); |
| 2975 | PP_ASSERT_WITH_CODE(0 == result, |
| 2976 | "Failed to Write ARB settings for the initial state.", return result;); |
| 2977 | |
Alex Deucher | 0104aa2 | 2015-11-13 10:46:30 -0500 | [diff] [blame] | 2978 | result = tonga_populate_smc_uvd_level(hwmgr, table); |
| 2979 | PP_ASSERT_WITH_CODE(0 == result, |
| 2980 | "Failed to initialize UVD Level!", return result;); |
| 2981 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 2982 | result = tonga_populate_smc_boot_level(hwmgr, table); |
| 2983 | PP_ASSERT_WITH_CODE(0 == result, |
| 2984 | "Failed to initialize Boot Level!", return result;); |
| 2985 | |
| 2986 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2987 | PHM_PlatformCaps_ClockStretcher)) { |
| 2988 | result = tonga_populate_clock_stretcher_data_table(hwmgr); |
| 2989 | PP_ASSERT_WITH_CODE(0 == result, |
| 2990 | "Failed to populate Clock Stretcher Data Table!", return result;); |
| 2991 | } |
| 2992 | table->GraphicsVoltageChangeEnable = 1; |
| 2993 | table->GraphicsThermThrottleEnable = 1; |
| 2994 | table->GraphicsInterval = 1; |
| 2995 | table->VoltageInterval = 1; |
| 2996 | table->ThermalInterval = 1; |
| 2997 | table->TemperatureLimitHigh = |
| 2998 | pptable_info->cac_dtp_table->usTargetOperatingTemp * |
| 2999 | TONGA_Q88_FORMAT_CONVERSION_UNIT; |
| 3000 | table->TemperatureLimitLow = |
| 3001 | (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) * |
| 3002 | TONGA_Q88_FORMAT_CONVERSION_UNIT; |
| 3003 | table->MemoryVoltageChangeEnable = 1; |
| 3004 | table->MemoryInterval = 1; |
| 3005 | table->VoltageResponseTime = 0; |
| 3006 | table->PhaseResponseTime = 0; |
| 3007 | table->MemoryThermThrottleEnable = 1; |
| 3008 | |
| 3009 | /* |
| 3010 | * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had) |
| 3011 | * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again |
| 3012 | * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay |
| 3013 | * To avoid it, we set PCIeBootLinkLevel to highest dpm level |
| 3014 | */ |
| 3015 | PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), |
| 3016 | "There must be 1 or more PCIE levels defined in PPTable.", |
| 3017 | return -1); |
| 3018 | |
| 3019 | table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); |
| 3020 | |
| 3021 | table->PCIeGenInterval = 1; |
| 3022 | |
| 3023 | result = tonga_populate_vr_config(hwmgr, table); |
| 3024 | PP_ASSERT_WITH_CODE(0 == result, |
| 3025 | "Failed to populate VRConfig setting!", return result); |
| 3026 | |
| 3027 | table->ThermGpio = 17; |
| 3028 | table->SclkStepSize = 0x4000; |
| 3029 | |
| 3030 | reg_value = 0; |
| 3031 | if ((0 == reg_value) && |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 3032 | (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, |
| 3033 | &gpio_pin_assignment))) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3034 | table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
| 3035 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3036 | PHM_PlatformCaps_RegulatorHot); |
| 3037 | } else { |
| 3038 | table->VRHotGpio = TONGA_UNUSED_GPIO_PIN; |
| 3039 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3040 | PHM_PlatformCaps_RegulatorHot); |
| 3041 | } |
| 3042 | |
| 3043 | /* ACDC Switch GPIO */ |
| 3044 | reg_value = 0; |
| 3045 | if ((0 == reg_value) && |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 3046 | (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, |
| 3047 | &gpio_pin_assignment))) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3048 | table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
| 3049 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3050 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3051 | } else { |
| 3052 | table->AcDcGpio = TONGA_UNUSED_GPIO_PIN; |
| 3053 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3054 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3055 | } |
| 3056 | |
| 3057 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3058 | PHM_PlatformCaps_Falcon_QuickTransition); |
| 3059 | |
| 3060 | reg_value = 0; |
| 3061 | if (1 == reg_value) { |
| 3062 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3063 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3064 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3065 | PHM_PlatformCaps_Falcon_QuickTransition); |
| 3066 | } |
| 3067 | |
| 3068 | reg_value = 0; |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 3069 | if ((0 == reg_value) && (atomctrl_get_pp_assign_pin(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3070 | THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) { |
| 3071 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3072 | PHM_PlatformCaps_ThermalOutGPIO); |
| 3073 | |
| 3074 | table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; |
| 3075 | |
| 3076 | table->ThermOutPolarity = |
| 3077 | (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & |
| 3078 | (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0; |
| 3079 | |
| 3080 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; |
| 3081 | |
| 3082 | /* if required, combine VRHot/PCC with thermal out GPIO*/ |
| 3083 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3084 | PHM_PlatformCaps_RegulatorHot) && |
| 3085 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3086 | PHM_PlatformCaps_CombinePCCWithThermalSignal)){ |
| 3087 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; |
| 3088 | } |
| 3089 | } else { |
| 3090 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3091 | PHM_PlatformCaps_ThermalOutGPIO); |
| 3092 | |
| 3093 | table->ThermOutGpio = 17; |
| 3094 | table->ThermOutPolarity = 1; |
| 3095 | table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; |
| 3096 | } |
| 3097 | |
| 3098 | for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) { |
| 3099 | table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); |
| 3100 | } |
| 3101 | CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); |
| 3102 | CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); |
| 3103 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); |
| 3104 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); |
| 3105 | CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); |
| 3106 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); |
| 3107 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); |
| 3108 | CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); |
| 3109 | CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); |
| 3110 | |
| 3111 | /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ |
| 3112 | result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start + |
| 3113 | offsetof(SMU72_Discrete_DpmTable, SystemFlags), |
| 3114 | (uint8_t *)&(table->SystemFlags), |
| 3115 | sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController), |
| 3116 | data->sram_end); |
| 3117 | |
| 3118 | PP_ASSERT_WITH_CODE(0 == result, |
| 3119 | "Failed to upload dpm data to SMC memory!", return result;); |
| 3120 | |
| 3121 | return result; |
| 3122 | } |
| 3123 | |
| 3124 | /* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/ |
| 3125 | static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr) |
| 3126 | { |
| 3127 | return; |
| 3128 | } |
| 3129 | |
| 3130 | int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) |
| 3131 | { |
| 3132 | PPSMC_Result result; |
| 3133 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3134 | |
| 3135 | /* Apply minimum voltage based on DAL's request level */ |
| 3136 | tonga_apply_dal_minimum_voltage_request(hwmgr); |
| 3137 | |
| 3138 | if (0 == data->sclk_dpm_key_disabled) { |
| 3139 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 3140 | if (tonga_is_dpm_running(hwmgr)) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3141 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); |
| 3142 | |
| 3143 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 3144 | result = smum_send_msg_to_smc_with_parameter( |
| 3145 | hwmgr->smumgr, |
| 3146 | (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 3147 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
| 3148 | PP_ASSERT_WITH_CODE((0 == result), |
| 3149 | "Set Sclk Dpm enable Mask failed", return -1); |
| 3150 | } |
| 3151 | } |
| 3152 | |
| 3153 | if (0 == data->mclk_dpm_key_disabled) { |
| 3154 | /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 3155 | if (tonga_is_dpm_running(hwmgr)) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3156 | printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); |
| 3157 | |
| 3158 | if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
| 3159 | result = smum_send_msg_to_smc_with_parameter( |
| 3160 | hwmgr->smumgr, |
| 3161 | (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask, |
| 3162 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); |
| 3163 | PP_ASSERT_WITH_CODE((0 == result), |
| 3164 | "Set Mclk Dpm enable Mask failed", return -1); |
| 3165 | } |
| 3166 | } |
| 3167 | |
| 3168 | return 0; |
| 3169 | } |
| 3170 | |
| 3171 | |
| 3172 | int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr) |
| 3173 | { |
| 3174 | uint32_t level, tmp; |
| 3175 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3176 | |
| 3177 | if (0 == data->pcie_dpm_key_disabled) { |
| 3178 | /* PCIE */ |
| 3179 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { |
| 3180 | level = 0; |
| 3181 | tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; |
| 3182 | while (tmp >>= 1) |
| 3183 | level++ ; |
| 3184 | |
| 3185 | if (0 != level) { |
| 3186 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)), |
| 3187 | "force highest pcie dpm state failed!", return -1); |
| 3188 | } |
| 3189 | } |
| 3190 | } |
| 3191 | |
| 3192 | if (0 == data->sclk_dpm_key_disabled) { |
| 3193 | /* SCLK */ |
| 3194 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) { |
| 3195 | level = 0; |
| 3196 | tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; |
| 3197 | while (tmp >>= 1) |
| 3198 | level++ ; |
| 3199 | |
| 3200 | if (0 != level) { |
| 3201 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)), |
| 3202 | "force highest sclk dpm state failed!", return -1); |
| 3203 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 3204 | CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level) |
| 3205 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
| 3206 | Curr_Sclk_Index does not match the level \n"); |
| 3207 | |
| 3208 | } |
| 3209 | } |
| 3210 | } |
| 3211 | |
| 3212 | if (0 == data->mclk_dpm_key_disabled) { |
| 3213 | /* MCLK */ |
| 3214 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { |
| 3215 | level = 0; |
| 3216 | tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; |
| 3217 | while (tmp >>= 1) |
| 3218 | level++ ; |
| 3219 | |
| 3220 | if (0 != level) { |
| 3221 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)), |
| 3222 | "force highest mclk dpm state failed!", return -1); |
| 3223 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 3224 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level) |
| 3225 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3226 | Curr_Mclk_Index does not match the level \n"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3227 | } |
| 3228 | } |
| 3229 | } |
| 3230 | |
| 3231 | return 0; |
| 3232 | } |
| 3233 | |
| 3234 | /** |
| 3235 | * Find the MC microcode version and store it in the HwMgr struct |
| 3236 | * |
| 3237 | * @param hwmgr the address of the powerplay hardware manager. |
| 3238 | * @return always 0 |
| 3239 | */ |
| 3240 | int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr) |
| 3241 | { |
| 3242 | cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); |
| 3243 | |
| 3244 | hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); |
| 3245 | |
| 3246 | return 0; |
| 3247 | } |
| 3248 | |
| 3249 | /** |
| 3250 | * Initialize Dynamic State Adjustment Rule Settings |
| 3251 | * |
| 3252 | * @param hwmgr the address of the powerplay hardware manager. |
| 3253 | */ |
| 3254 | int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr) |
| 3255 | { |
| 3256 | uint32_t table_size; |
| 3257 | struct phm_clock_voltage_dependency_table *table_clk_vlt; |
| 3258 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3259 | |
| 3260 | hwmgr->dyn_state.mclk_sclk_ratio = 4; |
| 3261 | hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */ |
| 3262 | hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */ |
| 3263 | |
| 3264 | /* initialize vddc_dep_on_dal_pwrl table */ |
| 3265 | table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record); |
Edward O'Callaghan | 5969a8c | 2016-07-12 10:17:55 +1000 | [diff] [blame] | 3266 | table_clk_vlt = kzalloc(table_size, GFP_KERNEL); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3267 | |
| 3268 | if (NULL == table_clk_vlt) { |
| 3269 | printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n"); |
| 3270 | return -ENOMEM; |
| 3271 | } else { |
| 3272 | table_clk_vlt->count = 4; |
| 3273 | table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; |
| 3274 | table_clk_vlt->entries[0].v = 0; |
| 3275 | table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; |
| 3276 | table_clk_vlt->entries[1].v = 720; |
| 3277 | table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; |
| 3278 | table_clk_vlt->entries[2].v = 810; |
| 3279 | table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; |
| 3280 | table_clk_vlt->entries[3].v = 900; |
| 3281 | pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt; |
| 3282 | hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; |
| 3283 | } |
| 3284 | |
| 3285 | return 0; |
| 3286 | } |
| 3287 | |
| 3288 | static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr) |
| 3289 | { |
| 3290 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3291 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3292 | |
| 3293 | phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = |
| 3294 | pptable_info->vdd_dep_on_sclk; |
| 3295 | phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = |
| 3296 | pptable_info->vdd_dep_on_mclk; |
| 3297 | |
| 3298 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 3299 | "VDD dependency on SCLK table is missing. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3300 | This table is mandatory", return -1); |
| 3301 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 3302 | "VDD dependency on SCLK table has to have is missing. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3303 | This table is mandatory", return -1); |
| 3304 | |
| 3305 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 3306 | "VDD dependency on MCLK table is missing. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3307 | This table is mandatory", return -1); |
| 3308 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, |
| 3309 | "VDD dependency on MCLK table has to have is missing. \ |
| 3310 | This table is mandatory", return -1); |
| 3311 | |
| 3312 | data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc; |
| 3313 | data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; |
| 3314 | |
| 3315 | pptable_info->max_clock_voltage_on_ac.sclk = |
| 3316 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; |
| 3317 | pptable_info->max_clock_voltage_on_ac.mclk = |
| 3318 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; |
| 3319 | pptable_info->max_clock_voltage_on_ac.vddc = |
| 3320 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; |
| 3321 | pptable_info->max_clock_voltage_on_ac.vddci = |
| 3322 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; |
| 3323 | |
| 3324 | hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = |
| 3325 | pptable_info->max_clock_voltage_on_ac.sclk; |
| 3326 | hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = |
| 3327 | pptable_info->max_clock_voltage_on_ac.mclk; |
| 3328 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = |
| 3329 | pptable_info->max_clock_voltage_on_ac.vddc; |
| 3330 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = |
| 3331 | pptable_info->max_clock_voltage_on_ac.vddci; |
| 3332 | |
| 3333 | return 0; |
| 3334 | } |
| 3335 | |
| 3336 | int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr) |
| 3337 | { |
| 3338 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3339 | int result = 1; |
| 3340 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 3341 | PP_ASSERT_WITH_CODE (!tonga_is_dpm_running(hwmgr), |
| 3342 | "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.", |
| 3343 | return result); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3344 | |
| 3345 | if (0 == data->pcie_dpm_key_disabled) { |
| 3346 | PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( |
| 3347 | hwmgr->smumgr, |
| 3348 | PPSMC_MSG_PCIeDPM_UnForceLevel)), |
| 3349 | "unforce pcie level failed!", |
| 3350 | return -1); |
| 3351 | } |
| 3352 | |
| 3353 | result = tonga_upload_dpm_level_enable_mask(hwmgr); |
| 3354 | |
| 3355 | return result; |
| 3356 | } |
| 3357 | |
| 3358 | static uint32_t tonga_get_lowest_enable_level( |
| 3359 | struct pp_hwmgr *hwmgr, uint32_t level_mask) |
| 3360 | { |
| 3361 | uint32_t level = 0; |
| 3362 | |
| 3363 | while (0 == (level_mask & (1 << level))) |
| 3364 | level++; |
| 3365 | |
| 3366 | return level; |
| 3367 | } |
| 3368 | |
| 3369 | static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr) |
| 3370 | { |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3371 | uint32_t level; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3372 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3373 | |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3374 | if (0 == data->pcie_dpm_key_disabled) { |
| 3375 | /* PCIE */ |
| 3376 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) { |
| 3377 | level = tonga_get_lowest_enable_level(hwmgr, |
| 3378 | data->dpm_level_enable_mask.pcie_dpm_enable_mask); |
| 3379 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)), |
| 3380 | "force lowest pcie dpm state failed!", return -1); |
| 3381 | } |
| 3382 | } |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3383 | |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3384 | if (0 == data->sclk_dpm_key_disabled) { |
| 3385 | /* SCLK */ |
| 3386 | if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 3387 | level = tonga_get_lowest_enable_level(hwmgr, |
| 3388 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3389 | |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3390 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)), |
| 3391 | "force sclk dpm state failed!", return -1); |
| 3392 | |
| 3393 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 3394 | CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level) |
| 3395 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3396 | Curr_Sclk_Index does not match the level \n"); |
Alex Deucher | 9fe1837 | 2015-11-11 00:23:57 -0500 | [diff] [blame] | 3397 | } |
| 3398 | } |
| 3399 | |
| 3400 | if (0 == data->mclk_dpm_key_disabled) { |
| 3401 | /* MCLK */ |
| 3402 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) { |
| 3403 | level = tonga_get_lowest_enable_level(hwmgr, |
| 3404 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); |
| 3405 | PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)), |
| 3406 | "force lowest mclk dpm state failed!", return -1); |
| 3407 | if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 3408 | TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level) |
| 3409 | printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \ |
| 3410 | Curr_Mclk_Index does not match the level \n"); |
| 3411 | } |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3412 | } |
| 3413 | |
| 3414 | return 0; |
| 3415 | } |
| 3416 | |
| 3417 | static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr) |
| 3418 | { |
| 3419 | uint8_t entryId; |
| 3420 | uint8_t voltageId; |
| 3421 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3422 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3423 | |
| 3424 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; |
| 3425 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; |
| 3426 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 3427 | |
| 3428 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3429 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 3430 | voltageId = sclk_table->entries[entryId].vddInd; |
| 3431 | sclk_table->entries[entryId].vddgfx = |
| 3432 | pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd; |
| 3433 | } |
| 3434 | } else { |
| 3435 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 3436 | voltageId = sclk_table->entries[entryId].vddInd; |
| 3437 | sclk_table->entries[entryId].vddc = |
| 3438 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 3439 | } |
| 3440 | } |
| 3441 | |
| 3442 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { |
| 3443 | voltageId = mclk_table->entries[entryId].vddInd; |
| 3444 | mclk_table->entries[entryId].vddc = |
| 3445 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 3446 | } |
| 3447 | |
| 3448 | for (entryId = 0; entryId < mm_table->count; ++entryId) { |
| 3449 | voltageId = mm_table->entries[entryId].vddcInd; |
| 3450 | mm_table->entries[entryId].vddc = |
| 3451 | pptable_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 3452 | } |
| 3453 | |
| 3454 | return 0; |
| 3455 | |
| 3456 | } |
| 3457 | |
| 3458 | static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) |
| 3459 | { |
| 3460 | uint8_t entryId; |
| 3461 | phm_ppt_v1_voltage_lookup_record v_record; |
| 3462 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3463 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3464 | |
| 3465 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; |
| 3466 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; |
| 3467 | |
| 3468 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3469 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 3470 | if (sclk_table->entries[entryId].vdd_offset & (1 << 15)) |
| 3471 | v_record.us_vdd = sclk_table->entries[entryId].vddgfx + |
| 3472 | sclk_table->entries[entryId].vdd_offset - 0xFFFF; |
| 3473 | else |
| 3474 | v_record.us_vdd = sclk_table->entries[entryId].vddgfx + |
| 3475 | sclk_table->entries[entryId].vdd_offset; |
| 3476 | |
| 3477 | sclk_table->entries[entryId].vddc = |
| 3478 | v_record.us_cac_low = v_record.us_cac_mid = |
| 3479 | v_record.us_cac_high = v_record.us_vdd; |
| 3480 | |
| 3481 | tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); |
| 3482 | } |
| 3483 | |
| 3484 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { |
| 3485 | if (mclk_table->entries[entryId].vdd_offset & (1 << 15)) |
| 3486 | v_record.us_vdd = mclk_table->entries[entryId].vddc + |
| 3487 | mclk_table->entries[entryId].vdd_offset - 0xFFFF; |
| 3488 | else |
| 3489 | v_record.us_vdd = mclk_table->entries[entryId].vddc + |
| 3490 | mclk_table->entries[entryId].vdd_offset; |
| 3491 | |
| 3492 | mclk_table->entries[entryId].vddgfx = v_record.us_cac_low = |
| 3493 | v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; |
| 3494 | tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); |
| 3495 | } |
| 3496 | } |
| 3497 | |
| 3498 | return 0; |
| 3499 | |
| 3500 | } |
| 3501 | |
| 3502 | static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) |
| 3503 | { |
| 3504 | uint32_t entryId; |
| 3505 | phm_ppt_v1_voltage_lookup_record v_record; |
| 3506 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3507 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3508 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; |
| 3509 | |
| 3510 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3511 | for (entryId = 0; entryId < mm_table->count; entryId++) { |
| 3512 | if (mm_table->entries[entryId].vddgfx_offset & (1 << 15)) |
| 3513 | v_record.us_vdd = mm_table->entries[entryId].vddc + |
| 3514 | mm_table->entries[entryId].vddgfx_offset - 0xFFFF; |
| 3515 | else |
| 3516 | v_record.us_vdd = mm_table->entries[entryId].vddc + |
| 3517 | mm_table->entries[entryId].vddgfx_offset; |
| 3518 | |
| 3519 | /* Add the calculated VDDGFX to the VDDGFX lookup table */ |
| 3520 | mm_table->entries[entryId].vddgfx = v_record.us_cac_low = |
| 3521 | v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; |
| 3522 | tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); |
| 3523 | } |
| 3524 | } |
| 3525 | return 0; |
| 3526 | } |
| 3527 | |
| 3528 | |
| 3529 | /** |
| 3530 | * Change virtual leakage voltage to actual value. |
| 3531 | * |
| 3532 | * @param hwmgr the address of the powerplay hardware manager. |
| 3533 | * @param pointer to changing voltage |
| 3534 | * @param pointer to leakage table |
| 3535 | */ |
| 3536 | static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, |
| 3537 | uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable) |
| 3538 | { |
| 3539 | uint32_t leakage_index; |
| 3540 | |
| 3541 | /* search for leakage voltage ID 0xff01 ~ 0xff08 */ |
| 3542 | for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) { |
| 3543 | /* if this voltage matches a leakage voltage ID */ |
| 3544 | /* patch with actual leakage voltage */ |
| 3545 | if (pLeakageTable->leakage_id[leakage_index] == *voltage) { |
| 3546 | *voltage = pLeakageTable->actual_voltage[leakage_index]; |
| 3547 | break; |
| 3548 | } |
| 3549 | } |
| 3550 | |
| 3551 | if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) |
| 3552 | printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n"); |
| 3553 | } |
| 3554 | |
| 3555 | /** |
| 3556 | * Patch voltage lookup table by EVV leakages. |
| 3557 | * |
| 3558 | * @param hwmgr the address of the powerplay hardware manager. |
| 3559 | * @param pointer to voltage lookup table |
| 3560 | * @param pointer to leakage table |
| 3561 | * @return always 0 |
| 3562 | */ |
| 3563 | static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, |
| 3564 | phm_ppt_v1_voltage_lookup_table *lookup_table, |
| 3565 | phw_tonga_leakage_voltage *pLeakageTable) |
| 3566 | { |
| 3567 | uint32_t i; |
| 3568 | |
| 3569 | for (i = 0; i < lookup_table->count; i++) { |
| 3570 | tonga_patch_with_vdd_leakage(hwmgr, |
| 3571 | &lookup_table->entries[i].us_vdd, pLeakageTable); |
| 3572 | } |
| 3573 | |
| 3574 | return 0; |
| 3575 | } |
| 3576 | |
| 3577 | static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr, |
| 3578 | phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc) |
| 3579 | { |
| 3580 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3581 | |
| 3582 | tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable); |
| 3583 | hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = |
| 3584 | pptable_info->max_clock_voltage_on_dc.vddc; |
| 3585 | |
| 3586 | return 0; |
| 3587 | } |
| 3588 | |
| 3589 | static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage( |
| 3590 | struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable, |
| 3591 | uint16_t *Vddgfx) |
| 3592 | { |
| 3593 | tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable); |
| 3594 | return 0; |
| 3595 | } |
| 3596 | |
| 3597 | int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr, |
| 3598 | phm_ppt_v1_voltage_lookup_table *lookup_table) |
| 3599 | { |
| 3600 | uint32_t table_size, i, j; |
| 3601 | phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; |
| 3602 | table_size = lookup_table->count; |
| 3603 | |
| 3604 | PP_ASSERT_WITH_CODE(0 != lookup_table->count, |
| 3605 | "Lookup table is empty", return -1); |
| 3606 | |
| 3607 | /* Sorting voltages */ |
| 3608 | for (i = 0; i < table_size - 1; i++) { |
| 3609 | for (j = i + 1; j > 0; j--) { |
| 3610 | if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) { |
| 3611 | tmp_voltage_lookup_record = lookup_table->entries[j-1]; |
| 3612 | lookup_table->entries[j-1] = lookup_table->entries[j]; |
| 3613 | lookup_table->entries[j] = tmp_voltage_lookup_record; |
| 3614 | } |
| 3615 | } |
| 3616 | } |
| 3617 | |
| 3618 | return 0; |
| 3619 | } |
| 3620 | |
| 3621 | static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr) |
| 3622 | { |
| 3623 | int result = 0; |
| 3624 | int tmp_result; |
| 3625 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 3626 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3627 | |
| 3628 | if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) { |
| 3629 | tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr, |
| 3630 | pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); |
| 3631 | if (tmp_result != 0) |
| 3632 | result = tmp_result; |
| 3633 | |
| 3634 | tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr, |
| 3635 | &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx); |
| 3636 | if (tmp_result != 0) |
| 3637 | result = tmp_result; |
| 3638 | } else { |
| 3639 | tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr, |
| 3640 | pptable_info->vddc_lookup_table, &(data->vddc_leakage)); |
| 3641 | if (tmp_result != 0) |
| 3642 | result = tmp_result; |
| 3643 | |
| 3644 | tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr, |
| 3645 | &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc); |
| 3646 | if (tmp_result != 0) |
| 3647 | result = tmp_result; |
| 3648 | } |
| 3649 | |
| 3650 | tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr); |
| 3651 | if (tmp_result != 0) |
| 3652 | result = tmp_result; |
| 3653 | |
| 3654 | tmp_result = tonga_calc_voltage_dependency_tables(hwmgr); |
| 3655 | if (tmp_result != 0) |
| 3656 | result = tmp_result; |
| 3657 | |
| 3658 | tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr); |
| 3659 | if (tmp_result != 0) |
| 3660 | result = tmp_result; |
| 3661 | |
| 3662 | tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table); |
| 3663 | if (tmp_result != 0) |
| 3664 | result = tmp_result; |
| 3665 | |
| 3666 | tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table); |
| 3667 | if (tmp_result != 0) |
| 3668 | result = tmp_result; |
| 3669 | |
| 3670 | return result; |
| 3671 | } |
| 3672 | |
| 3673 | int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr) |
| 3674 | { |
| 3675 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3676 | data->low_sclk_interrupt_threshold = 0; |
| 3677 | |
| 3678 | return 0; |
| 3679 | } |
| 3680 | |
| 3681 | int tonga_setup_asic_task(struct pp_hwmgr *hwmgr) |
| 3682 | { |
| 3683 | int tmp_result, result = 0; |
| 3684 | |
| 3685 | tmp_result = tonga_read_clock_registers(hwmgr); |
| 3686 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3687 | "Failed to read clock registers!", result = tmp_result); |
| 3688 | |
| 3689 | tmp_result = tonga_get_memory_type(hwmgr); |
| 3690 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3691 | "Failed to get memory type!", result = tmp_result); |
| 3692 | |
| 3693 | tmp_result = tonga_enable_acpi_power_management(hwmgr); |
| 3694 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3695 | "Failed to enable ACPI power management!", result = tmp_result); |
| 3696 | |
| 3697 | tmp_result = tonga_init_power_gate_state(hwmgr); |
| 3698 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3699 | "Failed to init power gate state!", result = tmp_result); |
| 3700 | |
| 3701 | tmp_result = tonga_get_mc_microcode_version(hwmgr); |
| 3702 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3703 | "Failed to get MC microcode version!", result = tmp_result); |
| 3704 | |
| 3705 | tmp_result = tonga_init_sclk_threshold(hwmgr); |
| 3706 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3707 | "Failed to init sclk threshold!", result = tmp_result); |
| 3708 | |
| 3709 | return result; |
| 3710 | } |
| 3711 | |
| 3712 | /** |
| 3713 | * Enable voltage control |
| 3714 | * |
| 3715 | * @param hwmgr the address of the powerplay hardware manager. |
| 3716 | * @return always 0 |
| 3717 | */ |
| 3718 | int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr) |
| 3719 | { |
| 3720 | /* enable voltage control */ |
| 3721 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); |
| 3722 | |
| 3723 | return 0; |
| 3724 | } |
| 3725 | |
| 3726 | /** |
| 3727 | * Checks if we want to support voltage control |
| 3728 | * |
| 3729 | * @param hwmgr the address of the powerplay hardware manager. |
| 3730 | */ |
| 3731 | bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr) |
| 3732 | { |
| 3733 | const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 3734 | |
| 3735 | return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control); |
| 3736 | } |
| 3737 | |
| 3738 | /*---------------------------MC----------------------------*/ |
| 3739 | |
| 3740 | uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr) |
| 3741 | { |
| 3742 | return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); |
| 3743 | } |
| 3744 | |
| 3745 | bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) |
| 3746 | { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 3747 | bool result = true; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3748 | |
| 3749 | switch (inReg) { |
| 3750 | case mmMC_SEQ_RAS_TIMING: |
| 3751 | *outReg = mmMC_SEQ_RAS_TIMING_LP; |
| 3752 | break; |
| 3753 | |
| 3754 | case mmMC_SEQ_DLL_STBY: |
| 3755 | *outReg = mmMC_SEQ_DLL_STBY_LP; |
| 3756 | break; |
| 3757 | |
| 3758 | case mmMC_SEQ_G5PDX_CMD0: |
| 3759 | *outReg = mmMC_SEQ_G5PDX_CMD0_LP; |
| 3760 | break; |
| 3761 | |
| 3762 | case mmMC_SEQ_G5PDX_CMD1: |
| 3763 | *outReg = mmMC_SEQ_G5PDX_CMD1_LP; |
| 3764 | break; |
| 3765 | |
| 3766 | case mmMC_SEQ_G5PDX_CTRL: |
| 3767 | *outReg = mmMC_SEQ_G5PDX_CTRL_LP; |
| 3768 | break; |
| 3769 | |
| 3770 | case mmMC_SEQ_CAS_TIMING: |
| 3771 | *outReg = mmMC_SEQ_CAS_TIMING_LP; |
| 3772 | break; |
| 3773 | |
| 3774 | case mmMC_SEQ_MISC_TIMING: |
| 3775 | *outReg = mmMC_SEQ_MISC_TIMING_LP; |
| 3776 | break; |
| 3777 | |
| 3778 | case mmMC_SEQ_MISC_TIMING2: |
| 3779 | *outReg = mmMC_SEQ_MISC_TIMING2_LP; |
| 3780 | break; |
| 3781 | |
| 3782 | case mmMC_SEQ_PMG_DVS_CMD: |
| 3783 | *outReg = mmMC_SEQ_PMG_DVS_CMD_LP; |
| 3784 | break; |
| 3785 | |
| 3786 | case mmMC_SEQ_PMG_DVS_CTL: |
| 3787 | *outReg = mmMC_SEQ_PMG_DVS_CTL_LP; |
| 3788 | break; |
| 3789 | |
| 3790 | case mmMC_SEQ_RD_CTL_D0: |
| 3791 | *outReg = mmMC_SEQ_RD_CTL_D0_LP; |
| 3792 | break; |
| 3793 | |
| 3794 | case mmMC_SEQ_RD_CTL_D1: |
| 3795 | *outReg = mmMC_SEQ_RD_CTL_D1_LP; |
| 3796 | break; |
| 3797 | |
| 3798 | case mmMC_SEQ_WR_CTL_D0: |
| 3799 | *outReg = mmMC_SEQ_WR_CTL_D0_LP; |
| 3800 | break; |
| 3801 | |
| 3802 | case mmMC_SEQ_WR_CTL_D1: |
| 3803 | *outReg = mmMC_SEQ_WR_CTL_D1_LP; |
| 3804 | break; |
| 3805 | |
| 3806 | case mmMC_PMG_CMD_EMRS: |
| 3807 | *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP; |
| 3808 | break; |
| 3809 | |
| 3810 | case mmMC_PMG_CMD_MRS: |
| 3811 | *outReg = mmMC_SEQ_PMG_CMD_MRS_LP; |
| 3812 | break; |
| 3813 | |
| 3814 | case mmMC_PMG_CMD_MRS1: |
| 3815 | *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP; |
| 3816 | break; |
| 3817 | |
| 3818 | case mmMC_SEQ_PMG_TIMING: |
| 3819 | *outReg = mmMC_SEQ_PMG_TIMING_LP; |
| 3820 | break; |
| 3821 | |
| 3822 | case mmMC_PMG_CMD_MRS2: |
| 3823 | *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP; |
| 3824 | break; |
| 3825 | |
| 3826 | case mmMC_SEQ_WR_CTL_2: |
| 3827 | *outReg = mmMC_SEQ_WR_CTL_2_LP; |
| 3828 | break; |
| 3829 | |
| 3830 | default: |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 3831 | result = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3832 | break; |
| 3833 | } |
| 3834 | |
| 3835 | return result; |
| 3836 | } |
| 3837 | |
| 3838 | int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table) |
| 3839 | { |
| 3840 | uint32_t i; |
| 3841 | uint16_t address; |
| 3842 | |
| 3843 | for (i = 0; i < table->last; i++) { |
| 3844 | table->mc_reg_address[i].s0 = |
| 3845 | tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) |
| 3846 | ? address : table->mc_reg_address[i].s1; |
| 3847 | } |
| 3848 | return 0; |
| 3849 | } |
| 3850 | |
| 3851 | int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table) |
| 3852 | { |
| 3853 | uint8_t i, j; |
| 3854 | |
| 3855 | PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3856 | "Invalid VramInfo table.", return -1); |
| 3857 | PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), |
| 3858 | "Invalid VramInfo table.", return -1); |
| 3859 | |
| 3860 | for (i = 0; i < table->last; i++) { |
| 3861 | ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; |
| 3862 | } |
| 3863 | ni_table->last = table->last; |
| 3864 | |
| 3865 | for (i = 0; i < table->num_entries; i++) { |
| 3866 | ni_table->mc_reg_table_entry[i].mclk_max = |
| 3867 | table->mc_reg_table_entry[i].mclk_max; |
| 3868 | for (j = 0; j < table->last; j++) { |
| 3869 | ni_table->mc_reg_table_entry[i].mc_data[j] = |
| 3870 | table->mc_reg_table_entry[i].mc_data[j]; |
| 3871 | } |
| 3872 | } |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 3873 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 3874 | ni_table->num_entries = table->num_entries; |
| 3875 | |
| 3876 | return 0; |
| 3877 | } |
| 3878 | |
| 3879 | /** |
| 3880 | * VBIOS omits some information to reduce size, we need to recover them here. |
| 3881 | * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. |
| 3882 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] |
| 3883 | * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0]. |
| 3884 | * 3. need to set these data for each clock range |
| 3885 | * |
| 3886 | * @param hwmgr the address of the powerplay hardware manager. |
| 3887 | * @param table the address of MCRegTable |
| 3888 | * @return always 0 |
| 3889 | */ |
| 3890 | int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table) |
| 3891 | { |
| 3892 | uint8_t i, j, k; |
| 3893 | uint32_t temp_reg; |
| 3894 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 3895 | |
| 3896 | for (i = 0, j = table->last; i < table->last; i++) { |
| 3897 | PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3898 | "Invalid VramInfo table.", return -1); |
| 3899 | switch (table->mc_reg_address[i].s1) { |
| 3900 | /* |
| 3901 | * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0]. |
| 3902 | * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0] |
| 3903 | */ |
| 3904 | case mmMC_SEQ_MISC1: |
| 3905 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); |
| 3906 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; |
| 3907 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; |
| 3908 | for (k = 0; k < table->num_entries; k++) { |
| 3909 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3910 | ((temp_reg & 0xffff0000)) | |
| 3911 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); |
| 3912 | } |
| 3913 | j++; |
| 3914 | PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3915 | "Invalid VramInfo table.", return -1); |
| 3916 | |
| 3917 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); |
| 3918 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; |
| 3919 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; |
| 3920 | for (k = 0; k < table->num_entries; k++) { |
| 3921 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3922 | (temp_reg & 0xffff0000) | |
| 3923 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
| 3924 | |
| 3925 | if (!data->is_memory_GDDR5) { |
| 3926 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; |
| 3927 | } |
| 3928 | } |
| 3929 | j++; |
| 3930 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3931 | "Invalid VramInfo table.", return -1); |
| 3932 | |
| 3933 | if (!data->is_memory_GDDR5) { |
| 3934 | table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; |
| 3935 | table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; |
| 3936 | for (k = 0; k < table->num_entries; k++) { |
| 3937 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3938 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; |
| 3939 | } |
| 3940 | j++; |
| 3941 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3942 | "Invalid VramInfo table.", return -1); |
| 3943 | } |
| 3944 | |
| 3945 | break; |
| 3946 | |
| 3947 | case mmMC_SEQ_RESERVE_M: |
| 3948 | temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); |
| 3949 | table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; |
| 3950 | table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; |
| 3951 | for (k = 0; k < table->num_entries; k++) { |
| 3952 | table->mc_reg_table_entry[k].mc_data[j] = |
| 3953 | (temp_reg & 0xffff0000) | |
| 3954 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
| 3955 | } |
| 3956 | j++; |
| 3957 | PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), |
| 3958 | "Invalid VramInfo table.", return -1); |
| 3959 | break; |
| 3960 | |
| 3961 | default: |
| 3962 | break; |
| 3963 | } |
| 3964 | |
| 3965 | } |
| 3966 | |
| 3967 | table->last = j; |
| 3968 | |
| 3969 | return 0; |
| 3970 | } |
| 3971 | |
| 3972 | int tonga_set_valid_flag(phw_tonga_mc_reg_table *table) |
| 3973 | { |
| 3974 | uint8_t i, j; |
| 3975 | for (i = 0; i < table->last; i++) { |
| 3976 | for (j = 1; j < table->num_entries; j++) { |
| 3977 | if (table->mc_reg_table_entry[j-1].mc_data[i] != |
| 3978 | table->mc_reg_table_entry[j].mc_data[i]) { |
| 3979 | table->validflag |= (1<<i); |
| 3980 | break; |
| 3981 | } |
| 3982 | } |
| 3983 | } |
| 3984 | |
| 3985 | return 0; |
| 3986 | } |
| 3987 | |
| 3988 | int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 3989 | { |
| 3990 | int result; |
| 3991 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 3992 | pp_atomctrl_mc_reg_table *table; |
| 3993 | phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table; |
| 3994 | uint8_t module_index = tonga_get_memory_modile_index(hwmgr); |
| 3995 | |
| 3996 | table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); |
| 3997 | |
| 3998 | if (NULL == table) |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 3999 | return -ENOMEM; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4000 | |
| 4001 | /* Program additional LP registers that are no longer programmed by VBIOS */ |
| 4002 | cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); |
| 4003 | cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); |
| 4004 | cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); |
| 4005 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); |
| 4006 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); |
| 4007 | cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); |
| 4008 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); |
| 4009 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); |
| 4010 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); |
| 4011 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); |
| 4012 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); |
| 4013 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); |
| 4014 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); |
| 4015 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); |
| 4016 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); |
| 4017 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); |
| 4018 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); |
| 4019 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); |
| 4020 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); |
| 4021 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); |
| 4022 | |
| 4023 | memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); |
| 4024 | |
| 4025 | result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); |
| 4026 | |
| 4027 | if (0 == result) |
| 4028 | result = tonga_copy_vbios_smc_reg_table(table, ni_table); |
| 4029 | |
| 4030 | if (0 == result) { |
| 4031 | tonga_set_s0_mc_reg_index(ni_table); |
| 4032 | result = tonga_set_mc_special_registers(hwmgr, ni_table); |
| 4033 | } |
| 4034 | |
| 4035 | if (0 == result) |
| 4036 | tonga_set_valid_flag(ni_table); |
| 4037 | |
| 4038 | kfree(table); |
| 4039 | return result; |
| 4040 | } |
| 4041 | |
| 4042 | /* |
| 4043 | * Copy one arb setting to another and then switch the active set. |
| 4044 | * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants. |
| 4045 | */ |
| 4046 | int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, |
| 4047 | uint32_t arbFreqSrc, uint32_t arbFreqDest) |
| 4048 | { |
| 4049 | uint32_t mc_arb_dram_timing; |
| 4050 | uint32_t mc_arb_dram_timing2; |
| 4051 | uint32_t burst_time; |
| 4052 | uint32_t mc_cg_config; |
| 4053 | |
| 4054 | switch (arbFreqSrc) { |
| 4055 | case MC_CG_ARB_FREQ_F0: |
| 4056 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); |
| 4057 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); |
| 4058 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); |
| 4059 | break; |
| 4060 | |
| 4061 | case MC_CG_ARB_FREQ_F1: |
| 4062 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); |
| 4063 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); |
| 4064 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); |
| 4065 | break; |
| 4066 | |
| 4067 | default: |
| 4068 | return -1; |
| 4069 | } |
| 4070 | |
| 4071 | switch (arbFreqDest) { |
| 4072 | case MC_CG_ARB_FREQ_F0: |
| 4073 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); |
| 4074 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); |
| 4075 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); |
| 4076 | break; |
| 4077 | |
| 4078 | case MC_CG_ARB_FREQ_F1: |
| 4079 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); |
| 4080 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); |
| 4081 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); |
| 4082 | break; |
| 4083 | |
| 4084 | default: |
| 4085 | return -1; |
| 4086 | } |
| 4087 | |
| 4088 | mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); |
| 4089 | mc_cg_config |= 0x0000000F; |
| 4090 | cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); |
| 4091 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest); |
| 4092 | |
| 4093 | return 0; |
| 4094 | } |
| 4095 | |
| 4096 | /** |
| 4097 | * Initial switch from ARB F0->F1 |
| 4098 | * |
| 4099 | * @param hwmgr the address of the powerplay hardware manager. |
| 4100 | * @return always 0 |
| 4101 | * This function is to be called from the SetPowerState table. |
| 4102 | */ |
| 4103 | int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) |
| 4104 | { |
| 4105 | return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); |
| 4106 | } |
| 4107 | |
| 4108 | /** |
| 4109 | * Initialize the ARB DRAM timing table's index field. |
| 4110 | * |
| 4111 | * @param hwmgr the address of the powerplay hardware manager. |
| 4112 | * @return always 0 |
| 4113 | */ |
| 4114 | int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) |
| 4115 | { |
| 4116 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4117 | uint32_t tmp; |
| 4118 | int result; |
| 4119 | |
| 4120 | /* |
| 4121 | * This is a read-modify-write on the first byte of the ARB table. |
| 4122 | * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'. |
| 4123 | * This solution is ugly, but we never write the whole table only individual fields in it. |
| 4124 | * In reality this field should not be in that structure but in a soft register. |
| 4125 | */ |
| 4126 | result = tonga_read_smc_sram_dword(hwmgr->smumgr, |
| 4127 | data->arb_table_start, &tmp, data->sram_end); |
| 4128 | |
| 4129 | if (0 != result) |
| 4130 | return result; |
| 4131 | |
| 4132 | tmp &= 0x00FFFFFF; |
| 4133 | tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; |
| 4134 | |
| 4135 | return tonga_write_smc_sram_dword(hwmgr->smumgr, |
| 4136 | data->arb_table_start, tmp, data->sram_end); |
| 4137 | } |
| 4138 | |
| 4139 | int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table) |
| 4140 | { |
| 4141 | const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4142 | |
| 4143 | uint32_t i, j; |
| 4144 | |
| 4145 | for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) { |
| 4146 | if (data->tonga_mc_reg_table.validflag & 1<<j) { |
| 4147 | PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE, |
| 4148 | "Index of mc_reg_table->address[] array out of boundary", return -1); |
| 4149 | mc_reg_table->address[i].s0 = |
| 4150 | PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0); |
| 4151 | mc_reg_table->address[i].s1 = |
| 4152 | PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1); |
| 4153 | i++; |
| 4154 | } |
| 4155 | } |
| 4156 | |
| 4157 | mc_reg_table->last = (uint8_t)i; |
| 4158 | |
| 4159 | return 0; |
| 4160 | } |
| 4161 | |
| 4162 | /*convert register values from driver to SMC format */ |
| 4163 | void tonga_convert_mc_registers( |
| 4164 | const phw_tonga_mc_reg_entry * pEntry, |
| 4165 | SMU72_Discrete_MCRegisterSet *pData, |
| 4166 | uint32_t numEntries, uint32_t validflag) |
| 4167 | { |
| 4168 | uint32_t i, j; |
| 4169 | |
| 4170 | for (i = 0, j = 0; j < numEntries; j++) { |
| 4171 | if (validflag & 1<<j) { |
| 4172 | pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]); |
| 4173 | i++; |
| 4174 | } |
| 4175 | } |
| 4176 | } |
| 4177 | |
| 4178 | /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */ |
| 4179 | int tonga_convert_mc_reg_table_entry_to_smc( |
| 4180 | struct pp_hwmgr *hwmgr, |
| 4181 | const uint32_t memory_clock, |
| 4182 | SMU72_Discrete_MCRegisterSet *mc_reg_table_data |
| 4183 | ) |
| 4184 | { |
| 4185 | const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4186 | uint32_t i = 0; |
| 4187 | |
| 4188 | for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) { |
| 4189 | if (memory_clock <= |
| 4190 | data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) { |
| 4191 | break; |
| 4192 | } |
| 4193 | } |
| 4194 | |
| 4195 | if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0)) |
| 4196 | --i; |
| 4197 | |
| 4198 | tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i], |
| 4199 | mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag); |
| 4200 | |
| 4201 | return 0; |
| 4202 | } |
| 4203 | |
| 4204 | int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, |
| 4205 | SMU72_Discrete_MCRegisters *mc_reg_table) |
| 4206 | { |
| 4207 | int result = 0; |
| 4208 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4209 | int res; |
| 4210 | uint32_t i; |
| 4211 | |
| 4212 | for (i = 0; i < data->dpm_table.mclk_table.count; i++) { |
| 4213 | res = tonga_convert_mc_reg_table_entry_to_smc( |
| 4214 | hwmgr, |
| 4215 | data->dpm_table.mclk_table.dpm_levels[i].value, |
| 4216 | &mc_reg_table->data[i] |
| 4217 | ); |
| 4218 | |
| 4219 | if (0 != res) |
| 4220 | result = res; |
| 4221 | } |
| 4222 | |
| 4223 | return result; |
| 4224 | } |
| 4225 | |
| 4226 | int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 4227 | { |
| 4228 | int result; |
| 4229 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4230 | |
| 4231 | memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters)); |
| 4232 | result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table)); |
| 4233 | PP_ASSERT_WITH_CODE(0 == result, |
| 4234 | "Failed to initialize MCRegTable for the MC register addresses!", return result;); |
| 4235 | |
| 4236 | result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table); |
| 4237 | PP_ASSERT_WITH_CODE(0 == result, |
| 4238 | "Failed to initialize MCRegTable for driver state!", return result;); |
| 4239 | |
| 4240 | return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start, |
| 4241 | (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end); |
| 4242 | } |
| 4243 | |
| 4244 | /** |
| 4245 | * Programs static screed detection parameters |
| 4246 | * |
| 4247 | * @param hwmgr the address of the powerplay hardware manager. |
| 4248 | * @return always 0 |
| 4249 | */ |
| 4250 | int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) |
| 4251 | { |
| 4252 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 4253 | |
| 4254 | /* Set static screen threshold unit*/ |
| 4255 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 4256 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, |
| 4257 | data->static_screen_threshold_unit); |
| 4258 | /* Set static screen threshold*/ |
| 4259 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, |
| 4260 | CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, |
| 4261 | data->static_screen_threshold); |
| 4262 | |
| 4263 | return 0; |
| 4264 | } |
| 4265 | |
| 4266 | /** |
| 4267 | * Setup display gap for glitch free memory clock switching. |
| 4268 | * |
| 4269 | * @param hwmgr the address of the powerplay hardware manager. |
| 4270 | * @return always 0 |
| 4271 | */ |
| 4272 | int tonga_enable_display_gap(struct pp_hwmgr *hwmgr) |
| 4273 | { |
| 4274 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, |
| 4275 | CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); |
| 4276 | |
| 4277 | display_gap = PHM_SET_FIELD(display_gap, |
| 4278 | CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE); |
| 4279 | |
| 4280 | display_gap = PHM_SET_FIELD(display_gap, |
| 4281 | CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); |
| 4282 | |
| 4283 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4284 | ixCG_DISPLAY_GAP_CNTL, display_gap); |
| 4285 | |
| 4286 | return 0; |
| 4287 | } |
| 4288 | |
| 4289 | /** |
| 4290 | * Programs activity state transition voting clients |
| 4291 | * |
| 4292 | * @param hwmgr the address of the powerplay hardware manager. |
| 4293 | * @return always 0 |
| 4294 | */ |
| 4295 | int tonga_program_voting_clients(struct pp_hwmgr *hwmgr) |
| 4296 | { |
| 4297 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
| 4298 | |
| 4299 | /* Clear reset for voting clients before enabling DPM */ |
| 4300 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 4301 | SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); |
| 4302 | PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 4303 | SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); |
| 4304 | |
| 4305 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4306 | ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); |
| 4307 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4308 | ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); |
| 4309 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4310 | ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); |
| 4311 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4312 | ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); |
| 4313 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4314 | ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); |
| 4315 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4316 | ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); |
| 4317 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4318 | ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); |
| 4319 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4320 | ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); |
| 4321 | |
| 4322 | return 0; |
| 4323 | } |
| 4324 | |
| 4325 | |
| 4326 | int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr) |
| 4327 | { |
| 4328 | int tmp_result, result = 0; |
| 4329 | |
| 4330 | tmp_result = tonga_check_for_dpm_stopped(hwmgr); |
| 4331 | |
| 4332 | if (cf_tonga_voltage_control(hwmgr)) { |
| 4333 | tmp_result = tonga_enable_voltage_control(hwmgr); |
| 4334 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4335 | "Failed to enable voltage control!", result = tmp_result); |
| 4336 | |
| 4337 | tmp_result = tonga_construct_voltage_tables(hwmgr); |
| 4338 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4339 | "Failed to contruct voltage tables!", result = tmp_result); |
| 4340 | } |
| 4341 | |
| 4342 | tmp_result = tonga_initialize_mc_reg_table(hwmgr); |
| 4343 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4344 | "Failed to initialize MC reg table!", result = tmp_result); |
| 4345 | |
| 4346 | tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr); |
| 4347 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4348 | "Failed to program static screen threshold parameters!", result = tmp_result); |
| 4349 | |
| 4350 | tmp_result = tonga_enable_display_gap(hwmgr); |
| 4351 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4352 | "Failed to enable display gap!", result = tmp_result); |
| 4353 | |
| 4354 | tmp_result = tonga_program_voting_clients(hwmgr); |
| 4355 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4356 | "Failed to program voting clients!", result = tmp_result); |
| 4357 | |
| 4358 | tmp_result = tonga_process_firmware_header(hwmgr); |
| 4359 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4360 | "Failed to process firmware header!", result = tmp_result); |
| 4361 | |
| 4362 | tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr); |
| 4363 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4364 | "Failed to initialize switch from ArbF0 to F1!", result = tmp_result); |
| 4365 | |
| 4366 | tmp_result = tonga_init_smc_table(hwmgr); |
| 4367 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4368 | "Failed to initialize SMC table!", result = tmp_result); |
| 4369 | |
| 4370 | tmp_result = tonga_init_arb_table_index(hwmgr); |
| 4371 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4372 | "Failed to initialize ARB table index!", result = tmp_result); |
| 4373 | |
| 4374 | tmp_result = tonga_populate_initial_mc_reg_table(hwmgr); |
| 4375 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4376 | "Failed to populate initialize MC Reg table!", result = tmp_result); |
| 4377 | |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 4378 | tmp_result = tonga_notify_smc_display_change(hwmgr, false); |
| 4379 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4380 | "Failed to notify no display!", result = tmp_result); |
| 4381 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4382 | /* enable SCLK control */ |
| 4383 | tmp_result = tonga_enable_sclk_control(hwmgr); |
| 4384 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4385 | "Failed to enable SCLK control!", result = tmp_result); |
| 4386 | |
| 4387 | /* enable DPM */ |
| 4388 | tmp_result = tonga_start_dpm(hwmgr); |
| 4389 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4390 | "Failed to start DPM!", result = tmp_result); |
| 4391 | |
| 4392 | return result; |
| 4393 | } |
| 4394 | |
| 4395 | int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr) |
| 4396 | { |
| 4397 | int tmp_result, result = 0; |
| 4398 | |
| 4399 | tmp_result = tonga_check_for_dpm_running(hwmgr); |
| 4400 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4401 | "SMC is still running!", return 0); |
| 4402 | |
| 4403 | tmp_result = tonga_stop_dpm(hwmgr); |
| 4404 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4405 | "Failed to stop DPM!", result = tmp_result); |
| 4406 | |
| 4407 | tmp_result = tonga_reset_to_default(hwmgr); |
| 4408 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4409 | "Failed to reset to default!", result = tmp_result); |
| 4410 | |
| 4411 | return result; |
| 4412 | } |
| 4413 | |
| 4414 | int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr) |
| 4415 | { |
| 4416 | int result; |
| 4417 | |
| 4418 | result = tonga_set_boot_state(hwmgr); |
| 4419 | if (0 != result) |
| 4420 | printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n"); |
| 4421 | |
| 4422 | return result; |
| 4423 | } |
| 4424 | |
| 4425 | int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) |
| 4426 | { |
Eric Huang | 92dea67 | 2016-04-15 17:14:53 -0400 | [diff] [blame] | 4427 | return phm_hwmgr_backend_fini(hwmgr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4428 | } |
| 4429 | |
| 4430 | /** |
| 4431 | * Initializes the Volcanic Islands Hardware Manager |
| 4432 | * |
| 4433 | * @param hwmgr the address of the powerplay hardware manager. |
| 4434 | * @return 1 if success; otherwise appropriate error code. |
| 4435 | */ |
| 4436 | int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) |
| 4437 | { |
| 4438 | int result = 0; |
| 4439 | SMU72_Discrete_DpmTable *table = NULL; |
Eric Huang | 76ad42c | 2016-06-02 16:15:59 -0400 | [diff] [blame] | 4440 | tonga_hwmgr *data; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4441 | pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; |
| 4442 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 4443 | phw_tonga_ulv_parm *ulv; |
Alex Deucher | 52b52a8 | 2016-02-05 11:11:51 -0500 | [diff] [blame] | 4444 | struct cgs_system_info sys_info = {0}; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4445 | |
| 4446 | PP_ASSERT_WITH_CODE((NULL != hwmgr), |
| 4447 | "Invalid Parameter!", return -1;); |
| 4448 | |
Eric Huang | 76ad42c | 2016-06-02 16:15:59 -0400 | [diff] [blame] | 4449 | data = kzalloc(sizeof(struct tonga_hwmgr), GFP_KERNEL); |
| 4450 | if (data == NULL) |
| 4451 | return -ENOMEM; |
| 4452 | |
| 4453 | hwmgr->backend = data; |
| 4454 | |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4455 | data->dll_defaule_on = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4456 | data->sram_end = SMC_RAM_END; |
| 4457 | |
| 4458 | data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4459 | data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4460 | data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4461 | data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4462 | data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4463 | data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4464 | data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4465 | data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT; |
| 4466 | |
| 4467 | data->vddc_vddci_delta = VDDC_VDDCI_DELTA; |
| 4468 | data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA; |
| 4469 | data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT; |
| 4470 | |
| 4471 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4472 | PHM_PlatformCaps_DisableVoltageIsland); |
| 4473 | |
| 4474 | data->sclk_dpm_key_disabled = 0; |
| 4475 | data->mclk_dpm_key_disabled = 0; |
| 4476 | data->pcie_dpm_key_disabled = 0; |
| 4477 | data->pcc_monitor_enabled = 0; |
| 4478 | |
| 4479 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4480 | PHM_PlatformCaps_UnTabledHardwareInterface); |
| 4481 | |
| 4482 | data->gpio_debug = 0; |
| 4483 | data->engine_clock_data = 0; |
| 4484 | data->memory_clock_data = 0; |
| 4485 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4486 | PHM_PlatformCaps_DynamicPatchPowerState); |
| 4487 | |
| 4488 | /* need to set voltage control types before EVV patching*/ |
| 4489 | data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE; |
| 4490 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE; |
| 4491 | data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE; |
| 4492 | data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE; |
Rex Zhu | a2fb493 | 2016-06-13 17:46:31 +0800 | [diff] [blame] | 4493 | data->force_pcie_gen = PP_PCIEGenInvalid; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4494 | |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4495 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4496 | VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { |
| 4497 | data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; |
| 4498 | } |
| 4499 | |
| 4500 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4501 | PHM_PlatformCaps_ControlVDDGFX)) { |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4502 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4503 | VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { |
| 4504 | data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; |
| 4505 | } |
| 4506 | } |
| 4507 | |
| 4508 | if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) { |
| 4509 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4510 | PHM_PlatformCaps_ControlVDDGFX); |
| 4511 | } |
| 4512 | |
| 4513 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4514 | PHM_PlatformCaps_EnableMVDDControl)) { |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4515 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4516 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) { |
| 4517 | data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO; |
| 4518 | } |
| 4519 | } |
| 4520 | |
| 4521 | if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) { |
| 4522 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4523 | PHM_PlatformCaps_EnableMVDDControl); |
| 4524 | } |
| 4525 | |
| 4526 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4527 | PHM_PlatformCaps_ControlVDDCI)) { |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4528 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4529 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) |
| 4530 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO; |
Eric Huang | 3ec2cdb | 2015-11-09 17:35:45 -0500 | [diff] [blame] | 4531 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4532 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) |
| 4533 | data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2; |
| 4534 | } |
| 4535 | |
| 4536 | if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control) |
| 4537 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4538 | PHM_PlatformCaps_ControlVDDCI); |
| 4539 | |
| 4540 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4541 | PHM_PlatformCaps_TablelessHardwareInterface); |
| 4542 | |
| 4543 | if (pptable_info->cac_dtp_table->usClockStretchAmount != 0) |
| 4544 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4545 | PHM_PlatformCaps_ClockStretcher); |
| 4546 | |
| 4547 | /* Initializes DPM default values*/ |
| 4548 | tonga_initialize_dpm_defaults(hwmgr); |
| 4549 | |
| 4550 | /* Get leakage voltage based on leakage ID.*/ |
| 4551 | PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)), |
| 4552 | "Get EVV Voltage Failed. Abort Driver loading!", return -1); |
| 4553 | |
| 4554 | tonga_complete_dependency_tables(hwmgr); |
| 4555 | |
| 4556 | /* Parse pptable data read from VBIOS*/ |
| 4557 | tonga_set_private_var_based_on_pptale(hwmgr); |
| 4558 | |
| 4559 | /* ULV Support*/ |
| 4560 | ulv = &(data->ulv); |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4561 | ulv->ulv_supported = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4562 | |
| 4563 | /* Initalize Dynamic State Adjustment Rule Settings*/ |
| 4564 | result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr); |
Alex Deucher | aa22ae4 | 2015-12-11 12:39:01 -0500 | [diff] [blame] | 4565 | if (result) |
| 4566 | printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n"); |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4567 | data->uvd_enabled = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4568 | |
| 4569 | table = &(data->smc_state_table); |
| 4570 | |
| 4571 | /* |
| 4572 | * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, |
| 4573 | * Peak Current Control feature is enabled and we should program PCC HW register |
| 4574 | */ |
Rex Zhu | e013c91 | 2016-06-29 19:48:58 +0800 | [diff] [blame] | 4575 | if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4576 | uint32_t temp_reg = cgs_read_ind_register(hwmgr->device, |
| 4577 | CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); |
| 4578 | |
| 4579 | switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { |
| 4580 | case 0: |
| 4581 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4582 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); |
| 4583 | break; |
| 4584 | case 1: |
| 4585 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4586 | CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); |
| 4587 | break; |
| 4588 | case 2: |
| 4589 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4590 | CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); |
| 4591 | break; |
| 4592 | case 3: |
| 4593 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4594 | CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); |
| 4595 | break; |
| 4596 | case 4: |
| 4597 | temp_reg = PHM_SET_FIELD(temp_reg, |
| 4598 | CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); |
| 4599 | break; |
| 4600 | default: |
| 4601 | printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \ |
| 4602 | Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n"); |
| 4603 | break; |
| 4604 | } |
| 4605 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 4606 | ixCNB_PWRMGT_CNTL, temp_reg); |
| 4607 | } |
| 4608 | |
| 4609 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4610 | PHM_PlatformCaps_EnableSMU7ThermalManagement); |
| 4611 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4612 | PHM_PlatformCaps_SMU7); |
| 4613 | |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4614 | data->vddc_phase_shed_control = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4615 | |
Alex Deucher | 3d5afb4 | 2016-02-04 23:47:38 -0500 | [diff] [blame] | 4616 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4617 | PHM_PlatformCaps_UVDPowerGating); |
Alex Deucher | f997e6f | 2016-02-04 23:48:51 -0500 | [diff] [blame] | 4618 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 4619 | PHM_PlatformCaps_VCEPowerGating); |
Alex Deucher | 52b52a8 | 2016-02-05 11:11:51 -0500 | [diff] [blame] | 4620 | sys_info.size = sizeof(struct cgs_system_info); |
| 4621 | sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; |
| 4622 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 4623 | if (!result) { |
| 4624 | if (sys_info.value & AMD_PG_SUPPORT_UVD) |
| 4625 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4626 | PHM_PlatformCaps_UVDPowerGating); |
| 4627 | if (sys_info.value & AMD_PG_SUPPORT_VCE) |
| 4628 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 4629 | PHM_PlatformCaps_VCEPowerGating); |
| 4630 | } |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4631 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4632 | if (0 == result) { |
Edward O'Callaghan | ed5121a | 2016-07-12 10:17:52 +1000 | [diff] [blame] | 4633 | data->is_tlu_enabled = false; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4634 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = |
| 4635 | TONGA_MAX_HARDWARE_POWERLEVELS; |
| 4636 | hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; |
| 4637 | hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; |
| 4638 | |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4639 | sys_info.size = sizeof(struct cgs_system_info); |
| 4640 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; |
| 4641 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 4642 | if (result) |
Huang Rui | d1371f8 | 2016-06-22 13:49:48 +0800 | [diff] [blame] | 4643 | data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4644 | else |
| 4645 | data->pcie_gen_cap = (uint32_t)sys_info.value; |
| 4646 | if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) |
| 4647 | data->pcie_spc_cap = 20; |
| 4648 | sys_info.size = sizeof(struct cgs_system_info); |
| 4649 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; |
| 4650 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 4651 | if (result) |
Huang Rui | d1371f8 | 2016-06-22 13:49:48 +0800 | [diff] [blame] | 4652 | data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; |
Alex Deucher | 834b694 | 2015-11-11 20:58:55 -0500 | [diff] [blame] | 4653 | else |
| 4654 | data->pcie_lane_cap = (uint32_t)sys_info.value; |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4655 | } else { |
| 4656 | /* Ignore return value in here, we are cleaning up a mess. */ |
| 4657 | tonga_hwmgr_backend_fini(hwmgr); |
| 4658 | } |
| 4659 | |
| 4660 | return result; |
| 4661 | } |
| 4662 | |
| 4663 | static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr, |
| 4664 | enum amd_dpm_forced_level level) |
| 4665 | { |
| 4666 | int ret = 0; |
| 4667 | |
| 4668 | switch (level) { |
| 4669 | case AMD_DPM_FORCED_LEVEL_HIGH: |
| 4670 | ret = tonga_force_dpm_highest(hwmgr); |
| 4671 | if (ret) |
| 4672 | return ret; |
| 4673 | break; |
| 4674 | case AMD_DPM_FORCED_LEVEL_LOW: |
| 4675 | ret = tonga_force_dpm_lowest(hwmgr); |
| 4676 | if (ret) |
| 4677 | return ret; |
| 4678 | break; |
| 4679 | case AMD_DPM_FORCED_LEVEL_AUTO: |
| 4680 | ret = tonga_unforce_dpm_levels(hwmgr); |
| 4681 | if (ret) |
| 4682 | return ret; |
| 4683 | break; |
| 4684 | default: |
| 4685 | break; |
| 4686 | } |
| 4687 | |
| 4688 | hwmgr->dpm_level = level; |
| 4689 | return ret; |
| 4690 | } |
| 4691 | |
| 4692 | static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, |
| 4693 | struct pp_power_state *prequest_ps, |
| 4694 | const struct pp_power_state *pcurrent_ps) |
| 4695 | { |
| 4696 | struct tonga_power_state *tonga_ps = |
| 4697 | cast_phw_tonga_power_state(&prequest_ps->hardware); |
| 4698 | |
| 4699 | uint32_t sclk; |
| 4700 | uint32_t mclk; |
| 4701 | struct PP_Clocks minimum_clocks = {0}; |
| 4702 | bool disable_mclk_switching; |
| 4703 | bool disable_mclk_switching_for_frame_lock; |
| 4704 | struct cgs_display_info info = {0}; |
| 4705 | const struct phm_clock_and_voltage_limits *max_limits; |
| 4706 | uint32_t i; |
| 4707 | tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4708 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 4709 | |
| 4710 | int32_t count; |
| 4711 | int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; |
| 4712 | |
| 4713 | data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); |
| 4714 | |
| 4715 | PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2, |
| 4716 | "VI should always have 2 performance levels", |
| 4717 | ); |
| 4718 | |
| 4719 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? |
| 4720 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : |
| 4721 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); |
| 4722 | |
| 4723 | if (PP_PowerSource_DC == hwmgr->power_source) { |
| 4724 | for (i = 0; i < tonga_ps->performance_level_count; i++) { |
| 4725 | if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk) |
| 4726 | tonga_ps->performance_levels[i].memory_clock = max_limits->mclk; |
| 4727 | if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk) |
| 4728 | tonga_ps->performance_levels[i].engine_clock = max_limits->sclk; |
| 4729 | } |
| 4730 | } |
| 4731 | |
| 4732 | tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk; |
| 4733 | tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk; |
| 4734 | |
| 4735 | tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk; |
| 4736 | |
| 4737 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 4738 | |
| 4739 | /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ |
| 4740 | |
| 4741 | /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ |
| 4742 | |
| 4743 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { |
| 4744 | |
| 4745 | max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); |
| 4746 | stable_pstate_sclk = (max_limits->sclk * 75) / 100; |
| 4747 | |
| 4748 | for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { |
| 4749 | if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) { |
| 4750 | stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk; |
| 4751 | break; |
| 4752 | } |
| 4753 | } |
| 4754 | |
| 4755 | if (count < 0) |
| 4756 | stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk; |
| 4757 | |
| 4758 | stable_pstate_mclk = max_limits->mclk; |
| 4759 | |
| 4760 | minimum_clocks.engineClock = stable_pstate_sclk; |
| 4761 | minimum_clocks.memoryClock = stable_pstate_mclk; |
| 4762 | } |
| 4763 | |
| 4764 | if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) |
| 4765 | minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; |
| 4766 | |
| 4767 | if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) |
| 4768 | minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; |
| 4769 | |
| 4770 | tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; |
| 4771 | |
| 4772 | if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { |
| 4773 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock), |
| 4774 | "Overdrive sclk exceeds limit", |
| 4775 | hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock); |
| 4776 | |
| 4777 | if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) |
| 4778 | tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive; |
| 4779 | } |
| 4780 | |
| 4781 | if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { |
| 4782 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock), |
| 4783 | "Overdrive mclk exceeds limit", |
| 4784 | hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock); |
| 4785 | |
| 4786 | if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) |
| 4787 | tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive; |
| 4788 | } |
| 4789 | |
| 4790 | disable_mclk_switching_for_frame_lock = phm_cap_enabled( |
| 4791 | hwmgr->platform_descriptor.platformCaps, |
| 4792 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); |
| 4793 | |
| 4794 | disable_mclk_switching = (1 < info.display_count) || |
| 4795 | disable_mclk_switching_for_frame_lock; |
| 4796 | |
| 4797 | sclk = tonga_ps->performance_levels[0].engine_clock; |
| 4798 | mclk = tonga_ps->performance_levels[0].memory_clock; |
| 4799 | |
| 4800 | if (disable_mclk_switching) |
| 4801 | mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock; |
| 4802 | |
| 4803 | if (sclk < minimum_clocks.engineClock) |
| 4804 | sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock; |
| 4805 | |
| 4806 | if (mclk < minimum_clocks.memoryClock) |
| 4807 | mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock; |
| 4808 | |
| 4809 | tonga_ps->performance_levels[0].engine_clock = sclk; |
| 4810 | tonga_ps->performance_levels[0].memory_clock = mclk; |
| 4811 | |
| 4812 | tonga_ps->performance_levels[1].engine_clock = |
| 4813 | (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ? |
| 4814 | tonga_ps->performance_levels[1].engine_clock : |
| 4815 | tonga_ps->performance_levels[0].engine_clock; |
| 4816 | |
| 4817 | if (disable_mclk_switching) { |
| 4818 | if (mclk < tonga_ps->performance_levels[1].memory_clock) |
| 4819 | mclk = tonga_ps->performance_levels[1].memory_clock; |
| 4820 | |
| 4821 | tonga_ps->performance_levels[0].memory_clock = mclk; |
| 4822 | tonga_ps->performance_levels[1].memory_clock = mclk; |
| 4823 | } else { |
| 4824 | if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock) |
| 4825 | tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock; |
| 4826 | } |
| 4827 | |
| 4828 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { |
| 4829 | for (i=0; i < tonga_ps->performance_level_count; i++) { |
| 4830 | tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk; |
| 4831 | tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk; |
| 4832 | tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; |
| 4833 | tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; |
| 4834 | } |
| 4835 | } |
| 4836 | |
| 4837 | return 0; |
| 4838 | } |
| 4839 | |
| 4840 | int tonga_get_power_state_size(struct pp_hwmgr *hwmgr) |
| 4841 | { |
| 4842 | return sizeof(struct tonga_power_state); |
| 4843 | } |
| 4844 | |
| 4845 | static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) |
| 4846 | { |
| 4847 | struct pp_power_state *ps; |
| 4848 | struct tonga_power_state *tonga_ps; |
| 4849 | |
| 4850 | if (hwmgr == NULL) |
| 4851 | return -EINVAL; |
| 4852 | |
| 4853 | ps = hwmgr->request_ps; |
| 4854 | |
| 4855 | if (ps == NULL) |
| 4856 | return -EINVAL; |
| 4857 | |
| 4858 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 4859 | |
| 4860 | if (low) |
| 4861 | return tonga_ps->performance_levels[0].memory_clock; |
| 4862 | else |
| 4863 | return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; |
| 4864 | } |
| 4865 | |
| 4866 | static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) |
| 4867 | { |
| 4868 | struct pp_power_state *ps; |
| 4869 | struct tonga_power_state *tonga_ps; |
| 4870 | |
| 4871 | if (hwmgr == NULL) |
| 4872 | return -EINVAL; |
| 4873 | |
| 4874 | ps = hwmgr->request_ps; |
| 4875 | |
| 4876 | if (ps == NULL) |
| 4877 | return -EINVAL; |
| 4878 | |
| 4879 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 4880 | |
| 4881 | if (low) |
| 4882 | return tonga_ps->performance_levels[0].engine_clock; |
| 4883 | else |
| 4884 | return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; |
| 4885 | } |
| 4886 | |
| 4887 | static uint16_t tonga_get_current_pcie_speed( |
| 4888 | struct pp_hwmgr *hwmgr) |
| 4889 | { |
| 4890 | uint32_t speed_cntl = 0; |
| 4891 | |
| 4892 | speed_cntl = cgs_read_ind_register(hwmgr->device, |
| 4893 | CGS_IND_REG__PCIE, |
| 4894 | ixPCIE_LC_SPEED_CNTL); |
| 4895 | return((uint16_t)PHM_GET_FIELD(speed_cntl, |
| 4896 | PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); |
| 4897 | } |
| 4898 | |
| 4899 | static int tonga_get_current_pcie_lane_number( |
| 4900 | struct pp_hwmgr *hwmgr) |
| 4901 | { |
| 4902 | uint32_t link_width; |
| 4903 | |
| 4904 | link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, |
| 4905 | CGS_IND_REG__PCIE, |
| 4906 | PCIE_LC_LINK_WIDTH_CNTL, |
| 4907 | LC_LINK_WIDTH_RD); |
| 4908 | |
| 4909 | PP_ASSERT_WITH_CODE((7 >= link_width), |
| 4910 | "Invalid PCIe lane width!", return 0); |
| 4911 | |
| 4912 | return decode_pcie_lane_width(link_width); |
| 4913 | } |
| 4914 | |
| 4915 | static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, |
| 4916 | struct pp_hw_power_state *hw_ps) |
| 4917 | { |
| 4918 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4919 | struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps; |
| 4920 | ATOM_FIRMWARE_INFO_V2_2 *fw_info; |
| 4921 | uint16_t size; |
| 4922 | uint8_t frev, crev; |
| 4923 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 4924 | |
| 4925 | /* First retrieve the Boot clocks and VDDC from the firmware info table. |
| 4926 | * We assume here that fw_info is unchanged if this call fails. |
| 4927 | */ |
| 4928 | fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( |
| 4929 | hwmgr->device, index, |
| 4930 | &size, &frev, &crev); |
| 4931 | if (!fw_info) |
| 4932 | /* During a test, there is no firmware info table. */ |
| 4933 | return 0; |
| 4934 | |
| 4935 | /* Patch the state. */ |
| 4936 | data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock); |
| 4937 | data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock); |
| 4938 | data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage); |
| 4939 | data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage); |
| 4940 | data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage); |
| 4941 | data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr); |
| 4942 | data->vbios_boot_state.pcie_lane_bootup_value = |
| 4943 | (uint16_t)tonga_get_current_pcie_lane_number(hwmgr); |
| 4944 | |
| 4945 | /* set boot power state */ |
| 4946 | ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; |
| 4947 | ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; |
| 4948 | ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; |
| 4949 | ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; |
| 4950 | |
| 4951 | return 0; |
| 4952 | } |
| 4953 | |
| 4954 | static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, |
| 4955 | void *state, struct pp_power_state *power_state, |
| 4956 | void *pp_table, uint32_t classification_flag) |
| 4957 | { |
| 4958 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 4959 | |
| 4960 | struct tonga_power_state *tonga_ps = |
| 4961 | (struct tonga_power_state *)(&(power_state->hardware)); |
| 4962 | |
| 4963 | struct tonga_performance_level *performance_level; |
| 4964 | |
| 4965 | ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; |
| 4966 | |
| 4967 | ATOM_Tonga_POWERPLAYTABLE *powerplay_table = |
| 4968 | (ATOM_Tonga_POWERPLAYTABLE *)pp_table; |
| 4969 | |
| 4970 | ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = |
| 4971 | (ATOM_Tonga_SCLK_Dependency_Table *) |
Rex Zhu | c9fe74e | 2015-11-16 11:24:35 +0800 | [diff] [blame] | 4972 | (((unsigned long)powerplay_table) + |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4973 | le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); |
| 4974 | |
| 4975 | ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = |
| 4976 | (ATOM_Tonga_MCLK_Dependency_Table *) |
Rex Zhu | c9fe74e | 2015-11-16 11:24:35 +0800 | [diff] [blame] | 4977 | (((unsigned long)powerplay_table) + |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 4978 | le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); |
| 4979 | |
| 4980 | /* The following fields are not initialized here: id orderedList allStatesList */ |
| 4981 | power_state->classification.ui_label = |
| 4982 | (le16_to_cpu(state_entry->usClassification) & |
| 4983 | ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> |
| 4984 | ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; |
| 4985 | power_state->classification.flags = classification_flag; |
| 4986 | /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ |
| 4987 | |
| 4988 | power_state->classification.temporary_state = false; |
| 4989 | power_state->classification.to_be_deleted = false; |
| 4990 | |
| 4991 | power_state->validation.disallowOnDC = |
| 4992 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC)); |
| 4993 | |
| 4994 | power_state->pcie.lanes = 0; |
| 4995 | |
| 4996 | power_state->display.disableFrameModulation = false; |
| 4997 | power_state->display.limitRefreshrate = false; |
| 4998 | power_state->display.enableVariBright = |
| 4999 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT)); |
| 5000 | |
| 5001 | power_state->validation.supportedPowerLevels = 0; |
| 5002 | power_state->uvd_clocks.VCLK = 0; |
| 5003 | power_state->uvd_clocks.DCLK = 0; |
| 5004 | power_state->temperatures.min = 0; |
| 5005 | power_state->temperatures.max = 0; |
| 5006 | |
| 5007 | performance_level = &(tonga_ps->performance_levels |
| 5008 | [tonga_ps->performance_level_count++]); |
| 5009 | |
| 5010 | PP_ASSERT_WITH_CODE( |
| 5011 | (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS), |
| 5012 | "Performance levels exceeds SMC limit!", |
| 5013 | return -1); |
| 5014 | |
| 5015 | PP_ASSERT_WITH_CODE( |
| 5016 | (tonga_ps->performance_level_count <= |
| 5017 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), |
| 5018 | "Performance levels exceeds Driver limit!", |
| 5019 | return -1); |
| 5020 | |
| 5021 | /* Performance levels are arranged from low to high. */ |
| 5022 | performance_level->memory_clock = |
| 5023 | le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk); |
| 5024 | |
| 5025 | performance_level->engine_clock = |
| 5026 | le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk); |
| 5027 | |
| 5028 | performance_level->pcie_gen = get_pcie_gen_support( |
| 5029 | data->pcie_gen_cap, |
| 5030 | state_entry->ucPCIEGenLow); |
| 5031 | |
| 5032 | performance_level->pcie_lane = get_pcie_lane_support( |
| 5033 | data->pcie_lane_cap, |
| 5034 | state_entry->ucPCIELaneHigh); |
| 5035 | |
| 5036 | performance_level = |
| 5037 | &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]); |
| 5038 | |
| 5039 | performance_level->memory_clock = |
| 5040 | le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk); |
| 5041 | |
| 5042 | performance_level->engine_clock = |
| 5043 | le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk); |
| 5044 | |
| 5045 | performance_level->pcie_gen = get_pcie_gen_support( |
| 5046 | data->pcie_gen_cap, |
| 5047 | state_entry->ucPCIEGenHigh); |
| 5048 | |
| 5049 | performance_level->pcie_lane = get_pcie_lane_support( |
| 5050 | data->pcie_lane_cap, |
| 5051 | state_entry->ucPCIELaneHigh); |
| 5052 | |
| 5053 | return 0; |
| 5054 | } |
| 5055 | |
| 5056 | static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr, |
| 5057 | unsigned long entry_index, struct pp_power_state *ps) |
| 5058 | { |
| 5059 | int result; |
| 5060 | struct tonga_power_state *tonga_ps; |
| 5061 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5062 | |
| 5063 | struct phm_ppt_v1_information *table_info = |
| 5064 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 5065 | |
| 5066 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = |
| 5067 | table_info->vdd_dep_on_mclk; |
| 5068 | |
| 5069 | ps->hardware.magic = PhwTonga_Magic; |
| 5070 | |
| 5071 | tonga_ps = cast_phw_tonga_power_state(&(ps->hardware)); |
| 5072 | |
| 5073 | result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps, |
| 5074 | tonga_get_pp_table_entry_callback_func); |
| 5075 | |
| 5076 | /* This is the earliest time we have all the dependency table and the VBIOS boot state |
| 5077 | * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state |
| 5078 | * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state |
| 5079 | */ |
| 5080 | if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { |
| 5081 | if (dep_mclk_table->entries[0].clk != |
| 5082 | data->vbios_boot_state.mclk_bootup_value) |
| 5083 | printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " |
| 5084 | "does not match VBIOS boot MCLK level"); |
| 5085 | if (dep_mclk_table->entries[0].vddci != |
| 5086 | data->vbios_boot_state.vddci_bootup_value) |
| 5087 | printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " |
| 5088 | "does not match VBIOS boot VDDCI level"); |
| 5089 | } |
| 5090 | |
| 5091 | /* set DC compatible flag if this state supports DC */ |
| 5092 | if (!ps->validation.disallowOnDC) |
| 5093 | tonga_ps->dc_compatible = true; |
| 5094 | |
| 5095 | if (ps->classification.flags & PP_StateClassificationFlag_ACPI) |
| 5096 | data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen; |
| 5097 | else if (ps->classification.flags & PP_StateClassificationFlag_Boot) { |
| 5098 | if (data->bacos.best_match == 0xffff) { |
| 5099 | /* For V.I. use boot state as base BACO state */ |
| 5100 | data->bacos.best_match = PP_StateClassificationFlag_Boot; |
| 5101 | data->bacos.performance_level = tonga_ps->performance_levels[0]; |
| 5102 | } |
| 5103 | } |
| 5104 | |
| 5105 | tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK; |
| 5106 | tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK; |
| 5107 | |
| 5108 | if (!result) { |
| 5109 | uint32_t i; |
| 5110 | |
| 5111 | switch (ps->classification.ui_label) { |
| 5112 | case PP_StateUILabel_Performance: |
| 5113 | data->use_pcie_performance_levels = true; |
| 5114 | |
| 5115 | for (i = 0; i < tonga_ps->performance_level_count; i++) { |
| 5116 | if (data->pcie_gen_performance.max < |
| 5117 | tonga_ps->performance_levels[i].pcie_gen) |
| 5118 | data->pcie_gen_performance.max = |
| 5119 | tonga_ps->performance_levels[i].pcie_gen; |
| 5120 | |
| 5121 | if (data->pcie_gen_performance.min > |
| 5122 | tonga_ps->performance_levels[i].pcie_gen) |
| 5123 | data->pcie_gen_performance.min = |
| 5124 | tonga_ps->performance_levels[i].pcie_gen; |
| 5125 | |
| 5126 | if (data->pcie_lane_performance.max < |
| 5127 | tonga_ps->performance_levels[i].pcie_lane) |
| 5128 | data->pcie_lane_performance.max = |
| 5129 | tonga_ps->performance_levels[i].pcie_lane; |
| 5130 | |
| 5131 | if (data->pcie_lane_performance.min > |
| 5132 | tonga_ps->performance_levels[i].pcie_lane) |
| 5133 | data->pcie_lane_performance.min = |
| 5134 | tonga_ps->performance_levels[i].pcie_lane; |
| 5135 | } |
| 5136 | break; |
| 5137 | case PP_StateUILabel_Battery: |
| 5138 | data->use_pcie_power_saving_levels = true; |
| 5139 | |
| 5140 | for (i = 0; i < tonga_ps->performance_level_count; i++) { |
| 5141 | if (data->pcie_gen_power_saving.max < |
| 5142 | tonga_ps->performance_levels[i].pcie_gen) |
| 5143 | data->pcie_gen_power_saving.max = |
| 5144 | tonga_ps->performance_levels[i].pcie_gen; |
| 5145 | |
| 5146 | if (data->pcie_gen_power_saving.min > |
| 5147 | tonga_ps->performance_levels[i].pcie_gen) |
| 5148 | data->pcie_gen_power_saving.min = |
| 5149 | tonga_ps->performance_levels[i].pcie_gen; |
| 5150 | |
| 5151 | if (data->pcie_lane_power_saving.max < |
| 5152 | tonga_ps->performance_levels[i].pcie_lane) |
| 5153 | data->pcie_lane_power_saving.max = |
| 5154 | tonga_ps->performance_levels[i].pcie_lane; |
| 5155 | |
| 5156 | if (data->pcie_lane_power_saving.min > |
| 5157 | tonga_ps->performance_levels[i].pcie_lane) |
| 5158 | data->pcie_lane_power_saving.min = |
| 5159 | tonga_ps->performance_levels[i].pcie_lane; |
| 5160 | } |
| 5161 | break; |
| 5162 | default: |
| 5163 | break; |
| 5164 | } |
| 5165 | } |
| 5166 | return 0; |
| 5167 | } |
| 5168 | |
| 5169 | static void |
| 5170 | tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) |
| 5171 | { |
Rex Zhu | ab4f4b1 | 2016-01-06 17:17:53 +0800 | [diff] [blame] | 5172 | uint32_t sclk, mclk, activity_percent; |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5173 | uint32_t offset; |
| 5174 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5175 | |
| 5176 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency)); |
| 5177 | |
| 5178 | sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 5179 | |
| 5180 | smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency)); |
| 5181 | |
| 5182 | mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 5183 | seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100); |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5184 | |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5185 | offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity); |
Rex Zhu | ab4f4b1 | 2016-01-06 17:17:53 +0800 | [diff] [blame] | 5186 | activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); |
| 5187 | activity_percent += 0x80; |
| 5188 | activity_percent >>= 8; |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5189 | |
Rex Zhu | ab4f4b1 | 2016-01-06 17:17:53 +0800 | [diff] [blame] | 5190 | seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent); |
Rex Zhu | 9c5f8de | 2015-12-08 14:31:13 +0800 | [diff] [blame] | 5191 | |
Rex Zhu | d27d494 | 2016-03-01 17:04:12 +0800 | [diff] [blame] | 5192 | seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en"); |
| 5193 | |
| 5194 | seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5195 | } |
| 5196 | |
| 5197 | static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) |
| 5198 | { |
| 5199 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5200 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5201 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5202 | struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table); |
| 5203 | uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; |
| 5204 | struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table); |
| 5205 | uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; |
| 5206 | struct PP_Clocks min_clocks = {0}; |
| 5207 | uint32_t i; |
| 5208 | struct cgs_display_info info = {0}; |
| 5209 | |
| 5210 | data->need_update_smu7_dpm_table = 0; |
| 5211 | |
| 5212 | for (i = 0; i < psclk_table->count; i++) { |
| 5213 | if (sclk == psclk_table->dpm_levels[i].value) |
| 5214 | break; |
| 5215 | } |
| 5216 | |
| 5217 | if (i >= psclk_table->count) |
| 5218 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; |
| 5219 | else { |
| 5220 | /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/ |
| 5221 | if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR) |
| 5222 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; |
| 5223 | } |
| 5224 | |
| 5225 | for (i=0; i < pmclk_table->count; i++) { |
| 5226 | if (mclk == pmclk_table->dpm_levels[i].value) |
| 5227 | break; |
| 5228 | } |
| 5229 | |
| 5230 | if (i >= pmclk_table->count) |
| 5231 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; |
| 5232 | |
| 5233 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5234 | |
| 5235 | if (data->display_timing.num_existing_displays != info.display_count) |
| 5236 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; |
| 5237 | |
| 5238 | return 0; |
| 5239 | } |
| 5240 | |
| 5241 | static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps) |
| 5242 | { |
| 5243 | uint32_t i; |
| 5244 | uint32_t sclk, max_sclk = 0; |
| 5245 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5246 | struct tonga_dpm_table *pdpm_table = &data->dpm_table; |
| 5247 | |
| 5248 | for (i = 0; i < hw_ps->performance_level_count; i++) { |
| 5249 | sclk = hw_ps->performance_levels[i].engine_clock; |
| 5250 | if (max_sclk < sclk) |
| 5251 | max_sclk = sclk; |
| 5252 | } |
| 5253 | |
| 5254 | for (i = 0; i < pdpm_table->sclk_table.count; i++) { |
| 5255 | if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk) |
| 5256 | return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ? |
| 5257 | pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value : |
| 5258 | pdpm_table->pcie_speed_table.dpm_levels[i].value); |
| 5259 | } |
| 5260 | |
| 5261 | return 0; |
| 5262 | } |
| 5263 | |
| 5264 | static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input) |
| 5265 | { |
| 5266 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5267 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5268 | const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5269 | const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state); |
| 5270 | |
| 5271 | uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps); |
| 5272 | uint16_t current_link_speed; |
| 5273 | |
| 5274 | if (data->force_pcie_gen == PP_PCIEGenInvalid) |
| 5275 | current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps); |
| 5276 | else |
| 5277 | current_link_speed = data->force_pcie_gen; |
| 5278 | |
| 5279 | data->force_pcie_gen = PP_PCIEGenInvalid; |
| 5280 | data->pspp_notify_required = false; |
| 5281 | if (target_link_speed > current_link_speed) { |
| 5282 | switch(target_link_speed) { |
| 5283 | case PP_PCIEGen3: |
| 5284 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) |
| 5285 | break; |
| 5286 | data->force_pcie_gen = PP_PCIEGen2; |
| 5287 | if (current_link_speed == PP_PCIEGen2) |
| 5288 | break; |
| 5289 | case PP_PCIEGen2: |
| 5290 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) |
| 5291 | break; |
| 5292 | default: |
| 5293 | data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr); |
| 5294 | break; |
| 5295 | } |
| 5296 | } else { |
| 5297 | if (target_link_speed < current_link_speed) |
| 5298 | data->pspp_notify_required = true; |
| 5299 | } |
| 5300 | |
| 5301 | return 0; |
| 5302 | } |
| 5303 | |
| 5304 | static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 5305 | { |
| 5306 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5307 | |
| 5308 | if (0 == data->need_update_smu7_dpm_table) |
| 5309 | return 0; |
| 5310 | |
| 5311 | if ((0 == data->sclk_dpm_key_disabled) && |
| 5312 | (data->need_update_smu7_dpm_table & |
| 5313 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 5314 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5315 | "Trying to freeze SCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5316 | ); |
| 5317 | PP_ASSERT_WITH_CODE( |
| 5318 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5319 | PPSMC_MSG_SCLKDPM_FreezeLevel), |
| 5320 | "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", |
| 5321 | return -1); |
| 5322 | } |
| 5323 | |
| 5324 | if ((0 == data->mclk_dpm_key_disabled) && |
| 5325 | (data->need_update_smu7_dpm_table & |
| 5326 | DPMTABLE_OD_UPDATE_MCLK)) { |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 5327 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5328 | "Trying to freeze MCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5329 | ); |
| 5330 | PP_ASSERT_WITH_CODE( |
| 5331 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5332 | PPSMC_MSG_MCLKDPM_FreezeLevel), |
| 5333 | "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", |
| 5334 | return -1); |
| 5335 | } |
| 5336 | |
| 5337 | return 0; |
| 5338 | } |
| 5339 | |
| 5340 | static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input) |
| 5341 | { |
| 5342 | int result = 0; |
| 5343 | |
| 5344 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5345 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5346 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5347 | uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock; |
| 5348 | uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock; |
| 5349 | struct tonga_dpm_table *pdpm_table = &data->dpm_table; |
| 5350 | |
| 5351 | struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table; |
| 5352 | uint32_t dpm_count, clock_percent; |
| 5353 | uint32_t i; |
| 5354 | |
| 5355 | if (0 == data->need_update_smu7_dpm_table) |
| 5356 | return 0; |
| 5357 | |
| 5358 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { |
| 5359 | pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk; |
| 5360 | |
| 5361 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || |
| 5362 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { |
| 5363 | /* Need to do calculation based on the golden DPM table |
| 5364 | * as the Heatmap GPU Clock axis is also based on the default values |
| 5365 | */ |
| 5366 | PP_ASSERT_WITH_CODE( |
| 5367 | (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0), |
| 5368 | "Divide by 0!", |
| 5369 | return -1); |
| 5370 | dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2; |
| 5371 | for (i = dpm_count; i > 1; i--) { |
| 5372 | if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) { |
| 5373 | clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) / |
| 5374 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; |
| 5375 | |
| 5376 | pdpm_table->sclk_table.dpm_levels[i].value = |
| 5377 | pgolden_dpm_table->sclk_table.dpm_levels[i].value + |
| 5378 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5379 | |
| 5380 | } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) { |
| 5381 | clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) / |
| 5382 | pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value; |
| 5383 | |
| 5384 | pdpm_table->sclk_table.dpm_levels[i].value = |
| 5385 | pgolden_dpm_table->sclk_table.dpm_levels[i].value - |
| 5386 | (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5387 | } else |
| 5388 | pdpm_table->sclk_table.dpm_levels[i].value = |
| 5389 | pgolden_dpm_table->sclk_table.dpm_levels[i].value; |
| 5390 | } |
| 5391 | } |
| 5392 | } |
| 5393 | |
| 5394 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { |
| 5395 | pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk; |
| 5396 | |
| 5397 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || |
| 5398 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { |
| 5399 | |
| 5400 | PP_ASSERT_WITH_CODE( |
| 5401 | (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0), |
| 5402 | "Divide by 0!", |
| 5403 | return -1); |
| 5404 | dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2; |
| 5405 | for (i = dpm_count; i > 1; i--) { |
| 5406 | if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) { |
| 5407 | clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) / |
| 5408 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; |
| 5409 | |
| 5410 | pdpm_table->mclk_table.dpm_levels[i].value = |
| 5411 | pgolden_dpm_table->mclk_table.dpm_levels[i].value + |
| 5412 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5413 | |
| 5414 | } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) { |
| 5415 | clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) / |
| 5416 | pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value; |
| 5417 | |
| 5418 | pdpm_table->mclk_table.dpm_levels[i].value = |
| 5419 | pgolden_dpm_table->mclk_table.dpm_levels[i].value - |
| 5420 | (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100; |
| 5421 | } else |
| 5422 | pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value; |
| 5423 | } |
| 5424 | } |
| 5425 | } |
| 5426 | |
| 5427 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { |
Eric Huang | e2ed8a1 | 2016-05-12 14:41:04 -0400 | [diff] [blame] | 5428 | result = tonga_populate_all_graphic_levels(hwmgr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5429 | PP_ASSERT_WITH_CODE((0 == result), |
| 5430 | "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", |
| 5431 | return result); |
| 5432 | } |
| 5433 | |
| 5434 | if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { |
| 5435 | /*populate MCLK dpm table to SMU7 */ |
| 5436 | result = tonga_populate_all_memory_levels(hwmgr); |
| 5437 | PP_ASSERT_WITH_CODE((0 == result), |
| 5438 | "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", |
| 5439 | return result); |
| 5440 | } |
| 5441 | |
| 5442 | return result; |
| 5443 | } |
| 5444 | |
| 5445 | static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr, |
| 5446 | struct tonga_single_dpm_table * pdpm_table, |
| 5447 | uint32_t low_limit, uint32_t high_limit) |
| 5448 | { |
| 5449 | uint32_t i; |
| 5450 | |
| 5451 | for (i = 0; i < pdpm_table->count; i++) { |
| 5452 | if ((pdpm_table->dpm_levels[i].value < low_limit) || |
| 5453 | (pdpm_table->dpm_levels[i].value > high_limit)) |
| 5454 | pdpm_table->dpm_levels[i].enabled = false; |
| 5455 | else |
| 5456 | pdpm_table->dpm_levels[i].enabled = true; |
| 5457 | } |
| 5458 | return 0; |
| 5459 | } |
| 5460 | |
| 5461 | static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state) |
| 5462 | { |
| 5463 | int result = 0; |
| 5464 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5465 | uint32_t high_limit_count; |
| 5466 | |
| 5467 | PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1), |
| 5468 | "power state did not have any performance level", |
| 5469 | return -1); |
| 5470 | |
| 5471 | high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1; |
| 5472 | |
| 5473 | tonga_trim_single_dpm_states(hwmgr, |
| 5474 | &(data->dpm_table.sclk_table), |
| 5475 | hw_state->performance_levels[0].engine_clock, |
| 5476 | hw_state->performance_levels[high_limit_count].engine_clock); |
| 5477 | |
| 5478 | tonga_trim_single_dpm_states(hwmgr, |
| 5479 | &(data->dpm_table.mclk_table), |
| 5480 | hw_state->performance_levels[0].memory_clock, |
| 5481 | hw_state->performance_levels[high_limit_count].memory_clock); |
| 5482 | |
| 5483 | return result; |
| 5484 | } |
| 5485 | |
| 5486 | static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input) |
| 5487 | { |
| 5488 | int result; |
| 5489 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5490 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5491 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5492 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5493 | result = tonga_trim_dpm_states(hwmgr, tonga_ps); |
| 5494 | if (0 != result) |
| 5495 | return result; |
| 5496 | |
| 5497 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); |
| 5498 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); |
| 5499 | data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask; |
| 5500 | if (data->uvd_enabled) |
| 5501 | data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; |
| 5502 | |
| 5503 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); |
| 5504 | |
| 5505 | return 0; |
| 5506 | } |
| 5507 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5508 | int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5509 | { |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5510 | return smum_send_msg_to_smc(hwmgr->smumgr, enable ? |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5511 | (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable : |
| 5512 | (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable); |
| 5513 | } |
| 5514 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5515 | int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) |
| 5516 | { |
| 5517 | return smum_send_msg_to_smc(hwmgr->smumgr, enable ? |
| 5518 | (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable : |
| 5519 | (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable); |
| 5520 | } |
| 5521 | |
| 5522 | int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) |
| 5523 | { |
| 5524 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5525 | uint32_t mm_boot_level_offset, mm_boot_level_value; |
| 5526 | struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 5527 | |
| 5528 | if (!bgate) { |
| 5529 | data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1); |
| 5530 | mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); |
| 5531 | mm_boot_level_offset /= 4; |
| 5532 | mm_boot_level_offset *= 4; |
| 5533 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset); |
| 5534 | mm_boot_level_value &= 0x00FFFFFF; |
| 5535 | mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24; |
| 5536 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); |
| 5537 | |
| 5538 | if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) || |
| 5539 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) |
| 5540 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 5541 | PPSMC_MSG_UVDDPM_SetEnabledMask, |
| 5542 | (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); |
| 5543 | } |
| 5544 | |
| 5545 | return tonga_enable_disable_uvd_dpm(hwmgr, !bgate); |
| 5546 | } |
| 5547 | |
| 5548 | int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5549 | { |
| 5550 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5551 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5552 | const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5553 | const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state); |
| 5554 | |
| 5555 | uint32_t mm_boot_level_offset, mm_boot_level_value; |
| 5556 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 5557 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5558 | if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5559 | data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1); |
| 5560 | |
| 5561 | mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel); |
| 5562 | mm_boot_level_offset /= 4; |
| 5563 | mm_boot_level_offset *= 4; |
| 5564 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset); |
| 5565 | mm_boot_level_value &= 0xFF00FFFF; |
| 5566 | mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; |
| 5567 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); |
| 5568 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5569 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) |
| 5570 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 5571 | PPSMC_MSG_VCEDPM_SetEnabledMask, |
| 5572 | (uint32_t)(1 << data->smc_state_table.VceBootLevel)); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5573 | |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 5574 | tonga_enable_disable_vce_dpm(hwmgr, true); |
| 5575 | } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0) |
| 5576 | tonga_enable_disable_vce_dpm(hwmgr, false); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5577 | |
| 5578 | return 0; |
| 5579 | } |
| 5580 | |
| 5581 | static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 5582 | { |
| 5583 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5584 | |
| 5585 | uint32_t address; |
| 5586 | int32_t result; |
| 5587 | |
| 5588 | if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) |
| 5589 | return 0; |
| 5590 | |
| 5591 | |
| 5592 | memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters)); |
| 5593 | |
| 5594 | result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table)); |
| 5595 | |
| 5596 | if(result != 0) |
| 5597 | return result; |
| 5598 | |
| 5599 | |
| 5600 | address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); |
| 5601 | |
| 5602 | return tonga_copy_bytes_to_smc(hwmgr->smumgr, address, |
| 5603 | (uint8_t *)&data->mc_reg_table.data[0], |
| 5604 | sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, |
| 5605 | data->sram_end); |
| 5606 | } |
| 5607 | |
| 5608 | static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr) |
| 5609 | { |
| 5610 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5611 | |
| 5612 | if (data->need_update_smu7_dpm_table & |
| 5613 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) |
| 5614 | return tonga_program_memory_timing_parameters(hwmgr); |
| 5615 | |
| 5616 | return 0; |
| 5617 | } |
| 5618 | |
| 5619 | static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 5620 | { |
| 5621 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5622 | |
| 5623 | if (0 == data->need_update_smu7_dpm_table) |
| 5624 | return 0; |
| 5625 | |
| 5626 | if ((0 == data->sclk_dpm_key_disabled) && |
| 5627 | (data->need_update_smu7_dpm_table & |
| 5628 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { |
| 5629 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 5630 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5631 | "Trying to Unfreeze SCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5632 | ); |
| 5633 | PP_ASSERT_WITH_CODE( |
| 5634 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5635 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), |
| 5636 | "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", |
| 5637 | return -1); |
| 5638 | } |
| 5639 | |
| 5640 | if ((0 == data->mclk_dpm_key_disabled) && |
| 5641 | (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { |
| 5642 | |
Edward O'Callaghan | 4ba27f9 | 2016-07-12 10:17:56 +1000 | [diff] [blame^] | 5643 | PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr), |
| 5644 | "Trying to Unfreeze MCLK DPM when DPM is disabled", |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 5645 | ); |
| 5646 | PP_ASSERT_WITH_CODE( |
| 5647 | 0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 5648 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), |
| 5649 | "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", |
| 5650 | return -1); |
| 5651 | } |
| 5652 | |
| 5653 | data->need_update_smu7_dpm_table = 0; |
| 5654 | |
| 5655 | return 0; |
| 5656 | } |
| 5657 | |
| 5658 | static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input) |
| 5659 | { |
| 5660 | const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; |
| 5661 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5662 | const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); |
| 5663 | uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps); |
| 5664 | uint8_t request; |
| 5665 | |
| 5666 | if (data->pspp_notify_required || |
| 5667 | data->pcie_performance_request) { |
| 5668 | if (target_link_speed == PP_PCIEGen3) |
| 5669 | request = PCIE_PERF_REQ_GEN3; |
| 5670 | else if (target_link_speed == PP_PCIEGen2) |
| 5671 | request = PCIE_PERF_REQ_GEN2; |
| 5672 | else |
| 5673 | request = PCIE_PERF_REQ_GEN1; |
| 5674 | |
| 5675 | if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) { |
| 5676 | data->pcie_performance_request = false; |
| 5677 | return 0; |
| 5678 | } |
| 5679 | |
| 5680 | if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) { |
| 5681 | if (PP_PCIEGen2 == target_link_speed) |
| 5682 | printk("PSPP request to switch to Gen2 from Gen3 Failed!"); |
| 5683 | else |
| 5684 | printk("PSPP request to switch to Gen1 from Gen2 Failed!"); |
| 5685 | } |
| 5686 | } |
| 5687 | |
| 5688 | data->pcie_performance_request = false; |
| 5689 | return 0; |
| 5690 | } |
| 5691 | |
| 5692 | static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) |
| 5693 | { |
| 5694 | int tmp_result, result = 0; |
| 5695 | |
| 5696 | tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input); |
| 5697 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result); |
| 5698 | |
| 5699 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { |
| 5700 | tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input); |
| 5701 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result); |
| 5702 | } |
| 5703 | |
| 5704 | tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr); |
| 5705 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result); |
| 5706 | |
| 5707 | tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); |
| 5708 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result); |
| 5709 | |
| 5710 | tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input); |
| 5711 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result); |
| 5712 | |
| 5713 | tmp_result = tonga_update_vce_dpm(hwmgr, input); |
| 5714 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result); |
| 5715 | |
| 5716 | tmp_result = tonga_update_sclk_threshold(hwmgr); |
| 5717 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result); |
| 5718 | |
| 5719 | tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr); |
| 5720 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result); |
| 5721 | |
| 5722 | tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr); |
| 5723 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result); |
| 5724 | |
| 5725 | tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr); |
| 5726 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result); |
| 5727 | |
| 5728 | tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr); |
| 5729 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result); |
| 5730 | |
| 5731 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { |
| 5732 | tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input); |
| 5733 | PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result); |
| 5734 | } |
| 5735 | |
| 5736 | return result; |
| 5737 | } |
| 5738 | |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5739 | /** |
| 5740 | * Set maximum target operating fan output PWM |
| 5741 | * |
| 5742 | * @param pHwMgr: the address of the powerplay hardware manager. |
| 5743 | * @param usMaxFanPwm: max operating fan PWM in percents |
| 5744 | * @return The response that came from the SMC. |
| 5745 | */ |
| 5746 | static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) |
| 5747 | { |
| 5748 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; |
| 5749 | |
| 5750 | if (phm_is_hw_access_blocked(hwmgr)) |
| 5751 | return 0; |
| 5752 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 5753 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1); |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5754 | } |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 5755 | |
| 5756 | int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) |
| 5757 | { |
| 5758 | uint32_t num_active_displays = 0; |
| 5759 | struct cgs_display_info info = {0}; |
| 5760 | info.mode_info = NULL; |
| 5761 | |
| 5762 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5763 | |
| 5764 | num_active_displays = info.display_count; |
| 5765 | |
| 5766 | if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ |
| 5767 | tonga_notify_smc_display_change(hwmgr, false); |
| 5768 | else |
| 5769 | tonga_notify_smc_display_change(hwmgr, true); |
| 5770 | |
| 5771 | return 0; |
| 5772 | } |
| 5773 | |
| 5774 | /** |
| 5775 | * Programs the display gap |
| 5776 | * |
| 5777 | * @param hwmgr the address of the powerplay hardware manager. |
| 5778 | * @return always OK |
| 5779 | */ |
| 5780 | int tonga_program_display_gap(struct pp_hwmgr *hwmgr) |
| 5781 | { |
| 5782 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5783 | uint32_t num_active_displays = 0; |
| 5784 | uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); |
| 5785 | uint32_t display_gap2; |
| 5786 | uint32_t pre_vbi_time_in_us; |
| 5787 | uint32_t frame_time_in_us; |
| 5788 | uint32_t ref_clock; |
| 5789 | uint32_t refresh_rate = 0; |
| 5790 | struct cgs_display_info info = {0}; |
| 5791 | struct cgs_mode_info mode_info; |
| 5792 | |
| 5793 | info.mode_info = &mode_info; |
| 5794 | |
| 5795 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5796 | num_active_displays = info.display_count; |
| 5797 | |
| 5798 | display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); |
| 5799 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); |
| 5800 | |
| 5801 | ref_clock = mode_info.ref_clock; |
| 5802 | refresh_rate = mode_info.refresh_rate; |
| 5803 | |
| 5804 | if(0 == refresh_rate) |
| 5805 | refresh_rate = 60; |
| 5806 | |
| 5807 | frame_time_in_us = 1000000 / refresh_rate; |
| 5808 | |
| 5809 | pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; |
| 5810 | display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); |
| 5811 | |
| 5812 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); |
| 5813 | |
| 5814 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64); |
| 5815 | |
| 5816 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); |
| 5817 | |
| 5818 | if (num_active_displays == 1) |
| 5819 | tonga_notify_smc_display_change(hwmgr, true); |
| 5820 | |
| 5821 | return 0; |
| 5822 | } |
| 5823 | |
| 5824 | int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr) |
| 5825 | { |
| 5826 | |
| 5827 | tonga_program_display_gap(hwmgr); |
| 5828 | |
| 5829 | /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */ |
| 5830 | return 0; |
| 5831 | } |
| 5832 | |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5833 | /** |
| 5834 | * Set maximum target operating fan output RPM |
| 5835 | * |
| 5836 | * @param pHwMgr: the address of the powerplay hardware manager. |
| 5837 | * @param usMaxFanRpm: max operating fan RPM value. |
| 5838 | * @return The response that came from the SMC. |
| 5839 | */ |
| 5840 | static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) |
| 5841 | { |
| 5842 | hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm; |
| 5843 | |
| 5844 | if (phm_is_hw_access_blocked(hwmgr)) |
| 5845 | return 0; |
| 5846 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 5847 | return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1); |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5848 | } |
| 5849 | |
| 5850 | uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr) |
| 5851 | { |
| 5852 | uint32_t reference_clock; |
| 5853 | uint32_t tc; |
| 5854 | uint32_t divide; |
| 5855 | |
| 5856 | ATOM_FIRMWARE_INFO *fw_info; |
| 5857 | uint16_t size; |
| 5858 | uint8_t frev, crev; |
| 5859 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 5860 | |
| 5861 | tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); |
| 5862 | |
| 5863 | if (tc) |
| 5864 | return TCLK; |
| 5865 | |
| 5866 | fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index, |
| 5867 | &size, &frev, &crev); |
| 5868 | |
| 5869 | if (!fw_info) |
| 5870 | return 0; |
| 5871 | |
Rex Zhu | dcf799e | 2016-03-23 15:12:48 +0800 | [diff] [blame] | 5872 | reference_clock = le16_to_cpu(fw_info->usReferenceClock); |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 5873 | |
| 5874 | divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); |
| 5875 | |
| 5876 | if (0 != divide) |
| 5877 | return reference_clock / 4; |
| 5878 | |
| 5879 | return reference_clock; |
| 5880 | } |
| 5881 | |
| 5882 | int tonga_dpm_set_interrupt_state(void *private_data, |
| 5883 | unsigned src_id, unsigned type, |
| 5884 | int enabled) |
| 5885 | { |
| 5886 | uint32_t cg_thermal_int; |
| 5887 | struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr; |
| 5888 | |
| 5889 | if (hwmgr == NULL) |
| 5890 | return -EINVAL; |
| 5891 | |
| 5892 | switch (type) { |
| 5893 | case AMD_THERMAL_IRQ_LOW_TO_HIGH: |
| 5894 | if (enabled) { |
| 5895 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5896 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; |
| 5897 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5898 | } else { |
| 5899 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5900 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; |
| 5901 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5902 | } |
| 5903 | break; |
| 5904 | |
| 5905 | case AMD_THERMAL_IRQ_HIGH_TO_LOW: |
| 5906 | if (enabled) { |
| 5907 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5908 | cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; |
| 5909 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5910 | } else { |
| 5911 | cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT); |
| 5912 | cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; |
| 5913 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int); |
| 5914 | } |
| 5915 | break; |
| 5916 | default: |
| 5917 | break; |
| 5918 | } |
| 5919 | return 0; |
| 5920 | } |
| 5921 | |
| 5922 | int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, |
| 5923 | const void *thermal_interrupt_info) |
| 5924 | { |
| 5925 | int result; |
| 5926 | const struct pp_interrupt_registration_info *info = |
| 5927 | (const struct pp_interrupt_registration_info *)thermal_interrupt_info; |
| 5928 | |
| 5929 | if (info == NULL) |
| 5930 | return -EINVAL; |
| 5931 | |
| 5932 | result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST, |
| 5933 | tonga_dpm_set_interrupt_state, |
| 5934 | info->call_back, info->context); |
| 5935 | |
| 5936 | if (result) |
| 5937 | return -EINVAL; |
| 5938 | |
| 5939 | result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST, |
| 5940 | tonga_dpm_set_interrupt_state, |
| 5941 | info->call_back, info->context); |
| 5942 | |
| 5943 | if (result) |
| 5944 | return -EINVAL; |
| 5945 | |
| 5946 | return 0; |
| 5947 | } |
| 5948 | |
Rex Zhu | e829ecd | 2015-11-04 11:21:35 +0800 | [diff] [blame] | 5949 | bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) |
| 5950 | { |
| 5951 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 5952 | bool is_update_required = false; |
| 5953 | struct cgs_display_info info = {0,0,NULL}; |
| 5954 | |
| 5955 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 5956 | |
| 5957 | if (data->display_timing.num_existing_displays != info.display_count) |
| 5958 | is_update_required = true; |
| 5959 | /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL |
| 5960 | if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { |
| 5961 | cgs_get_min_clock_settings(hwmgr->device, &min_clocks); |
| 5962 | if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) |
| 5963 | is_update_required = true; |
| 5964 | */ |
| 5965 | return is_update_required; |
| 5966 | } |
| 5967 | |
| 5968 | static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1, |
| 5969 | const struct tonga_performance_level *pl2) |
| 5970 | { |
| 5971 | return ((pl1->memory_clock == pl2->memory_clock) && |
| 5972 | (pl1->engine_clock == pl2->engine_clock) && |
| 5973 | (pl1->pcie_gen == pl2->pcie_gen) && |
| 5974 | (pl1->pcie_lane == pl2->pcie_lane)); |
| 5975 | } |
| 5976 | |
| 5977 | int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) |
| 5978 | { |
| 5979 | const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1); |
| 5980 | const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2); |
| 5981 | int i; |
| 5982 | |
Rex Zhu | c15c8d7 | 2016-01-06 16:48:38 +0800 | [diff] [blame] | 5983 | if (equal == NULL || psa == NULL || psb == NULL) |
Rex Zhu | e829ecd | 2015-11-04 11:21:35 +0800 | [diff] [blame] | 5984 | return -EINVAL; |
| 5985 | |
| 5986 | /* If the two states don't even have the same number of performance levels they cannot be the same state. */ |
| 5987 | if (psa->performance_level_count != psb->performance_level_count) { |
| 5988 | *equal = false; |
| 5989 | return 0; |
| 5990 | } |
| 5991 | |
| 5992 | for (i = 0; i < psa->performance_level_count; i++) { |
| 5993 | if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { |
| 5994 | /* If we have found even one performance level pair that is different the states are different. */ |
| 5995 | *equal = false; |
| 5996 | return 0; |
| 5997 | } |
| 5998 | } |
| 5999 | |
| 6000 | /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ |
| 6001 | *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK)); |
| 6002 | *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK)); |
| 6003 | *equal &= (psa->sclk_threshold == psb->sclk_threshold); |
| 6004 | *equal &= (psa->acp_clk == psb->acp_clk); |
| 6005 | |
| 6006 | return 0; |
| 6007 | } |
| 6008 | |
Eric Huang | 9dcfc19 | 2015-12-04 10:57:22 -0500 | [diff] [blame] | 6009 | static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) |
| 6010 | { |
| 6011 | if (mode) { |
| 6012 | /* stop auto-manage */ |
| 6013 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 6014 | PHM_PlatformCaps_MicrocodeFanControl)) |
| 6015 | tonga_fan_ctrl_stop_smc_fan_control(hwmgr); |
| 6016 | tonga_fan_ctrl_set_static_mode(hwmgr, mode); |
| 6017 | } else |
| 6018 | /* restart auto-manage */ |
| 6019 | tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr); |
| 6020 | |
| 6021 | return 0; |
| 6022 | } |
| 6023 | |
| 6024 | static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr) |
| 6025 | { |
| 6026 | if (hwmgr->fan_ctrl_is_in_default_mode) |
| 6027 | return hwmgr->fan_ctrl_default_mode; |
| 6028 | else |
| 6029 | return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 6030 | CG_FDO_CTRL2, FDO_PWM_MODE); |
| 6031 | } |
| 6032 | |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6033 | static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6034 | enum pp_clock_type type, uint32_t mask) |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6035 | { |
| 6036 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6037 | |
| 6038 | if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) |
| 6039 | return -EINVAL; |
| 6040 | |
| 6041 | switch (type) { |
| 6042 | case PP_SCLK: |
| 6043 | if (!data->sclk_dpm_key_disabled) |
| 6044 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 6045 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6046 | data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6047 | break; |
| 6048 | case PP_MCLK: |
| 6049 | if (!data->mclk_dpm_key_disabled) |
| 6050 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 6051 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6052 | data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6053 | break; |
| 6054 | case PP_PCIE: |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6055 | { |
| 6056 | uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; |
| 6057 | uint32_t level = 0; |
| 6058 | |
| 6059 | while (tmp >>= 1) |
| 6060 | level++; |
| 6061 | |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6062 | if (!data->pcie_dpm_key_disabled) |
| 6063 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 6064 | PPSMC_MSG_PCIeDPM_ForceLevel, |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6065 | level); |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6066 | break; |
Eric Huang | 5632708 | 2016-04-12 14:57:23 -0400 | [diff] [blame] | 6067 | } |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6068 | default: |
| 6069 | break; |
| 6070 | } |
| 6071 | |
| 6072 | return 0; |
| 6073 | } |
| 6074 | |
| 6075 | static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr, |
| 6076 | enum pp_clock_type type, char *buf) |
| 6077 | { |
| 6078 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6079 | struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); |
| 6080 | struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); |
| 6081 | struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); |
| 6082 | int i, now, size = 0; |
| 6083 | uint32_t clock, pcie_speed; |
| 6084 | |
| 6085 | switch (type) { |
| 6086 | case PP_SCLK: |
| 6087 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); |
| 6088 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 6089 | |
| 6090 | for (i = 0; i < sclk_table->count; i++) { |
| 6091 | if (clock > sclk_table->dpm_levels[i].value) |
| 6092 | continue; |
| 6093 | break; |
| 6094 | } |
| 6095 | now = i; |
| 6096 | |
| 6097 | for (i = 0; i < sclk_table->count; i++) |
| 6098 | size += sprintf(buf + size, "%d: %uMhz %s\n", |
| 6099 | i, sclk_table->dpm_levels[i].value / 100, |
| 6100 | (i == now) ? "*" : ""); |
| 6101 | break; |
| 6102 | case PP_MCLK: |
| 6103 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); |
| 6104 | clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 6105 | |
| 6106 | for (i = 0; i < mclk_table->count; i++) { |
| 6107 | if (clock > mclk_table->dpm_levels[i].value) |
| 6108 | continue; |
| 6109 | break; |
| 6110 | } |
| 6111 | now = i; |
| 6112 | |
| 6113 | for (i = 0; i < mclk_table->count; i++) |
| 6114 | size += sprintf(buf + size, "%d: %uMhz %s\n", |
| 6115 | i, mclk_table->dpm_levels[i].value / 100, |
| 6116 | (i == now) ? "*" : ""); |
| 6117 | break; |
| 6118 | case PP_PCIE: |
| 6119 | pcie_speed = tonga_get_current_pcie_speed(hwmgr); |
| 6120 | for (i = 0; i < pcie_table->count; i++) { |
| 6121 | if (pcie_speed != pcie_table->dpm_levels[i].value) |
| 6122 | continue; |
| 6123 | break; |
| 6124 | } |
| 6125 | now = i; |
| 6126 | |
| 6127 | for (i = 0; i < pcie_table->count; i++) |
| 6128 | size += sprintf(buf + size, "%d: %s %s\n", i, |
| 6129 | (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : |
| 6130 | (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : |
| 6131 | (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", |
| 6132 | (i == now) ? "*" : ""); |
| 6133 | break; |
| 6134 | default: |
| 6135 | break; |
| 6136 | } |
| 6137 | return size; |
| 6138 | } |
| 6139 | |
Eric Huang | 9ccd4e1 | 2016-05-12 15:10:49 -0400 | [diff] [blame] | 6140 | static int tonga_get_sclk_od(struct pp_hwmgr *hwmgr) |
| 6141 | { |
| 6142 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6143 | struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); |
| 6144 | struct tonga_single_dpm_table *golden_sclk_table = |
| 6145 | &(data->golden_dpm_table.sclk_table); |
| 6146 | int value; |
| 6147 | |
| 6148 | value = (sclk_table->dpm_levels[sclk_table->count - 1].value - |
| 6149 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * |
| 6150 | 100 / |
| 6151 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; |
| 6152 | |
| 6153 | return value; |
| 6154 | } |
| 6155 | |
| 6156 | static int tonga_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) |
| 6157 | { |
| 6158 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6159 | struct tonga_single_dpm_table *golden_sclk_table = |
| 6160 | &(data->golden_dpm_table.sclk_table); |
| 6161 | struct pp_power_state *ps; |
| 6162 | struct tonga_power_state *tonga_ps; |
| 6163 | |
| 6164 | if (value > 20) |
| 6165 | value = 20; |
| 6166 | |
| 6167 | ps = hwmgr->request_ps; |
| 6168 | |
| 6169 | if (ps == NULL) |
| 6170 | return -EINVAL; |
| 6171 | |
| 6172 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 6173 | |
| 6174 | tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].engine_clock = |
| 6175 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * |
| 6176 | value / 100 + |
| 6177 | golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; |
| 6178 | |
| 6179 | return 0; |
| 6180 | } |
| 6181 | |
Eric Huang | f715d5b | 2016-05-24 16:13:25 -0400 | [diff] [blame] | 6182 | static int tonga_get_mclk_od(struct pp_hwmgr *hwmgr) |
| 6183 | { |
| 6184 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6185 | struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); |
| 6186 | struct tonga_single_dpm_table *golden_mclk_table = |
| 6187 | &(data->golden_dpm_table.mclk_table); |
| 6188 | int value; |
| 6189 | |
| 6190 | value = (mclk_table->dpm_levels[mclk_table->count - 1].value - |
| 6191 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * |
| 6192 | 100 / |
| 6193 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; |
| 6194 | |
| 6195 | return value; |
| 6196 | } |
| 6197 | |
| 6198 | static int tonga_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) |
| 6199 | { |
| 6200 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
| 6201 | struct tonga_single_dpm_table *golden_mclk_table = |
| 6202 | &(data->golden_dpm_table.mclk_table); |
| 6203 | struct pp_power_state *ps; |
| 6204 | struct tonga_power_state *tonga_ps; |
| 6205 | |
| 6206 | if (value > 20) |
| 6207 | value = 20; |
| 6208 | |
| 6209 | ps = hwmgr->request_ps; |
| 6210 | |
| 6211 | if (ps == NULL) |
| 6212 | return -EINVAL; |
| 6213 | |
| 6214 | tonga_ps = cast_phw_tonga_power_state(&ps->hardware); |
| 6215 | |
| 6216 | tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock = |
| 6217 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * |
| 6218 | value / 100 + |
| 6219 | golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; |
| 6220 | |
| 6221 | return 0; |
| 6222 | } |
| 6223 | |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6224 | static const struct pp_hwmgr_func tonga_hwmgr_funcs = { |
| 6225 | .backend_init = &tonga_hwmgr_backend_init, |
| 6226 | .backend_fini = &tonga_hwmgr_backend_fini, |
| 6227 | .asic_setup = &tonga_setup_asic_task, |
| 6228 | .dynamic_state_management_enable = &tonga_enable_dpm_tasks, |
Eric Huang | 57461af | 2016-06-06 15:36:42 -0400 | [diff] [blame] | 6229 | .dynamic_state_management_disable = &tonga_disable_dpm_tasks, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6230 | .apply_state_adjust_rules = tonga_apply_state_adjust_rules, |
| 6231 | .force_dpm_level = &tonga_force_dpm_level, |
| 6232 | .power_state_set = tonga_set_power_state_tasks, |
| 6233 | .get_power_state_size = tonga_get_power_state_size, |
| 6234 | .get_mclk = tonga_dpm_get_mclk, |
| 6235 | .get_sclk = tonga_dpm_get_sclk, |
| 6236 | .patch_boot_state = tonga_dpm_patch_boot_state, |
| 6237 | .get_pp_table_entry = tonga_get_pp_table_entry, |
| 6238 | .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, |
| 6239 | .print_current_perforce_level = tonga_print_current_perforce_level, |
Rex Zhu | 0859ed3 | 2015-10-15 21:12:58 +0800 | [diff] [blame] | 6240 | .powerdown_uvd = tonga_phm_powerdown_uvd, |
| 6241 | .powergate_uvd = tonga_phm_powergate_uvd, |
| 6242 | .powergate_vce = tonga_phm_powergate_vce, |
| 6243 | .disable_clock_power_gating = tonga_phm_disable_clock_power_gating, |
Alex Deucher | ce90dbd | 2016-04-28 17:19:41 -0400 | [diff] [blame] | 6244 | .update_clock_gatings = tonga_phm_update_clock_gatings, |
Rex Zhu | bbb207f | 2015-10-16 15:02:04 +0800 | [diff] [blame] | 6245 | .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment, |
| 6246 | .display_config_changed = tonga_display_configuration_changed_task, |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 6247 | .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output, |
| 6248 | .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output, |
| 6249 | .get_temperature = tonga_thermal_get_temperature, |
| 6250 | .stop_thermal_controller = tonga_thermal_stop_thermal_controller, |
| 6251 | .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info, |
| 6252 | .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent, |
| 6253 | .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent, |
| 6254 | .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default, |
| 6255 | .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm, |
| 6256 | .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm, |
| 6257 | .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller, |
| 6258 | .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt, |
Rex Zhu | e829ecd | 2015-11-04 11:21:35 +0800 | [diff] [blame] | 6259 | .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration, |
| 6260 | .check_states_equal = tonga_check_states_equal, |
Eric Huang | 9dcfc19 | 2015-12-04 10:57:22 -0500 | [diff] [blame] | 6261 | .set_fan_control_mode = tonga_set_fan_control_mode, |
| 6262 | .get_fan_control_mode = tonga_get_fan_control_mode, |
Eric Huang | 5d37a63 | 2016-01-22 14:32:41 -0500 | [diff] [blame] | 6263 | .force_clock_level = tonga_force_clock_level, |
| 6264 | .print_clock_levels = tonga_print_clock_levels, |
Eric Huang | 9ccd4e1 | 2016-05-12 15:10:49 -0400 | [diff] [blame] | 6265 | .get_sclk_od = tonga_get_sclk_od, |
| 6266 | .set_sclk_od = tonga_set_sclk_od, |
Eric Huang | f715d5b | 2016-05-24 16:13:25 -0400 | [diff] [blame] | 6267 | .get_mclk_od = tonga_get_mclk_od, |
| 6268 | .set_mclk_od = tonga_set_mclk_od, |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6269 | }; |
| 6270 | |
| 6271 | int tonga_hwmgr_init(struct pp_hwmgr *hwmgr) |
| 6272 | { |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6273 | hwmgr->hwmgr_func = &tonga_hwmgr_funcs; |
| 6274 | hwmgr->pptable_func = &tonga_pptable_funcs; |
Rex Zhu | 1e4854e | 2015-10-20 18:06:23 +0800 | [diff] [blame] | 6275 | pp_tonga_thermal_initialize(hwmgr); |
yanyang1 | c82baa2 | 2015-08-18 15:28:32 +0800 | [diff] [blame] | 6276 | return 0; |
| 6277 | } |
| 6278 | |