blob: 1242beac4e46834fba83b7baede2e4ca83494baa [file] [log] [blame]
Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
Jeeja KPb663a8c2015-10-07 11:31:57 +010027#include "skl-topology.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053028
29#define HDA_MONO 1
30#define HDA_STEREO 2
31
32static struct snd_pcm_hardware azx_pcm_hw = {
33 .info = (SNDRV_PCM_INFO_MMAP |
34 SNDRV_PCM_INFO_INTERLEAVED |
35 SNDRV_PCM_INFO_BLOCK_TRANSFER |
36 SNDRV_PCM_INFO_MMAP_VALID |
37 SNDRV_PCM_INFO_PAUSE |
38 SNDRV_PCM_INFO_SYNC_START |
39 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
40 SNDRV_PCM_INFO_HAS_LINK_ATIME |
41 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
42 .formats = SNDRV_PCM_FMTBIT_S16_LE,
43 .rates = SNDRV_PCM_RATE_48000,
44 .rate_min = 48000,
45 .rate_max = 48000,
46 .channels_min = 2,
47 .channels_max = 2,
48 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
49 .period_bytes_min = 128,
50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
51 .periods_min = 2,
52 .periods_max = AZX_MAX_FRAG,
53 .fifo_size = 0,
54};
55
56static inline
57struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
58{
59 return substream->runtime->private_data;
60}
61
62static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
63{
64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
65 struct hdac_stream *hstream = hdac_stream(stream);
66 struct hdac_bus *bus = hstream->bus;
67
68 return hbus_to_ebus(bus);
69}
70
71static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
72 struct snd_pcm_substream *substream,
73 size_t size)
74{
75 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
76
77 hdac_stream(stream)->bufsize = 0;
78 hdac_stream(stream)->period_bytes = 0;
79 hdac_stream(stream)->format_val = 0;
80
81 return snd_pcm_lib_malloc_pages(substream, size);
82}
83
84static int skl_substream_free_pages(struct hdac_bus *bus,
85 struct snd_pcm_substream *substream)
86{
87 return snd_pcm_lib_free_pages(substream);
88}
89
90static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
91 struct snd_pcm_runtime *runtime)
92{
93 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
94
95 /* avoid wrap-around with wall-clock */
96 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
97 20, 178000000);
98}
99
Jeeja KP05057002015-07-09 15:20:11 +0530100static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
101{
102 if (ebus->ppcap)
103 return HDAC_EXT_STREAM_TYPE_HOST;
104 else
105 return HDAC_EXT_STREAM_TYPE_COUPLED;
106}
107
Jeeja KPa40e6932015-07-09 15:20:08 +0530108static int skl_pcm_open(struct snd_pcm_substream *substream,
109 struct snd_soc_dai *dai)
110{
111 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
112 struct hdac_ext_stream *stream;
113 struct snd_pcm_runtime *runtime = substream->runtime;
114 struct skl_dma_params *dma_params;
115 int ret;
116
117 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
118 ret = pm_runtime_get_sync(dai->dev);
Jeeja KP9270b7b2015-10-22 23:22:34 +0530119 if (ret < 0)
Jeeja KPa40e6932015-07-09 15:20:08 +0530120 return ret;
121
122 stream = snd_hdac_ext_stream_assign(ebus, substream,
Jeeja KP05057002015-07-09 15:20:11 +0530123 skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530124 if (stream == NULL)
125 return -EBUSY;
126
127 skl_set_pcm_constrains(ebus, runtime);
128
129 /*
130 * disable WALLCLOCK timestamps for capture streams
131 * until we figure out how to handle digital inputs
132 */
133 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
134 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
135 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
136 }
137
138 runtime->private_data = stream;
139
140 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
141 if (!dma_params)
142 return -ENOMEM;
143
144 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
145 snd_soc_dai_set_dma_data(dai, substream, dma_params);
146
147 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
148 dma_params->stream_tag);
149 snd_pcm_set_sync(substream);
150
151 return 0;
152}
153
154static int skl_get_format(struct snd_pcm_substream *substream,
155 struct snd_soc_dai *dai)
156{
157 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
158 struct skl_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530159 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530160 int format_val = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530161
Jeeja KP05057002015-07-09 15:20:11 +0530162 if (ebus->ppcap) {
163 struct snd_pcm_runtime *runtime = substream->runtime;
164
165 format_val = snd_hdac_calc_stream_format(runtime->rate,
166 runtime->channels,
167 runtime->format,
168 32, 0);
169 } else {
170 struct snd_soc_dai *codec_dai = rtd->codec_dai;
171
172 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
173 if (dma_params)
174 format_val = dma_params->format;
175 }
Jeeja KPa40e6932015-07-09 15:20:08 +0530176
177 return format_val;
178}
179
180static int skl_pcm_prepare(struct snd_pcm_substream *substream,
181 struct snd_soc_dai *dai)
182{
183 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
184 unsigned int format_val;
185 int err;
186
187 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
188 if (hdac_stream(stream)->prepared) {
189 dev_dbg(dai->dev, "already stream is prepared - returning\n");
190 return 0;
191 }
192
193 format_val = skl_get_format(substream, dai);
194 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
195 hdac_stream(stream)->stream_tag, format_val);
196 snd_hdac_stream_reset(hdac_stream(stream));
197
198 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
199 if (err < 0)
200 return err;
201
202 err = snd_hdac_stream_setup(hdac_stream(stream));
203 if (err < 0)
204 return err;
205
206 hdac_stream(stream)->prepared = 1;
207
208 return err;
209}
210
211static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
212 struct snd_pcm_hw_params *params,
213 struct snd_soc_dai *dai)
214{
215 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KP05057002015-07-09 15:20:11 +0530216 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530217 struct snd_pcm_runtime *runtime = substream->runtime;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100218 struct skl_pipe_params p_params = {0};
219 struct skl_module_cfg *m_cfg;
Jeeja KP05057002015-07-09 15:20:11 +0530220 int ret, dma_id;
Jeeja KPa40e6932015-07-09 15:20:08 +0530221
222 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
223 ret = skl_substream_alloc_pages(ebus, substream,
224 params_buffer_bytes(params));
225 if (ret < 0)
226 return ret;
227
228 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
229 runtime->rate, runtime->channels, runtime->format);
230
Jeeja KP05057002015-07-09 15:20:11 +0530231 dma_id = hdac_stream(stream)->stream_tag - 1;
232 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
233
Jeeja KPb663a8c2015-10-07 11:31:57 +0100234 p_params.s_fmt = snd_pcm_format_width(params_format(params));
235 p_params.ch = params_channels(params);
236 p_params.s_freq = params_rate(params);
237 p_params.host_dma_id = dma_id;
238 p_params.stream = substream->stream;
239
240 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
241 if (m_cfg)
242 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
243
Jeeja KPa40e6932015-07-09 15:20:08 +0530244 return 0;
245}
246
247static void skl_pcm_close(struct snd_pcm_substream *substream,
248 struct snd_soc_dai *dai)
249{
250 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530251 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530252 struct skl_dma_params *dma_params = NULL;
253
254 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KP05057002015-07-09 15:20:11 +0530255
256 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530257
258 dma_params = snd_soc_dai_get_dma_data(dai, substream);
259 /*
260 * now we should set this to NULL as we are freeing by the
261 * dma_params
262 */
263 snd_soc_dai_set_dma_data(dai, substream, NULL);
264
265 pm_runtime_mark_last_busy(dai->dev);
266 pm_runtime_put_autosuspend(dai->dev);
267 kfree(dma_params);
268}
269
270static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
271 struct snd_soc_dai *dai)
272{
273 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
274 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
275
276 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
277
278 snd_hdac_stream_cleanup(hdac_stream(stream));
279 hdac_stream(stream)->prepared = 0;
280
281 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
282}
283
Jeeja KPb663a8c2015-10-07 11:31:57 +0100284static int skl_be_hw_params(struct snd_pcm_substream *substream,
285 struct snd_pcm_hw_params *params,
286 struct snd_soc_dai *dai)
287{
288 struct skl_pipe_params p_params = {0};
289
290 p_params.s_fmt = snd_pcm_format_width(params_format(params));
291 p_params.ch = params_channels(params);
292 p_params.s_freq = params_rate(params);
293 p_params.stream = substream->stream;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100294
Jeeja KP4bd073f2015-10-27 09:22:45 +0900295 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100296}
297
298static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
299 struct snd_soc_dai *dai)
300{
301 struct skl *skl = get_skl_ctx(dai->dev);
302 struct skl_sst *ctx = skl->skl_sst;
303 struct skl_module_cfg *mconfig;
304
305 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
306 if (!mconfig)
307 return -EIO;
308
309 switch (cmd) {
310 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
311 case SNDRV_PCM_TRIGGER_RESUME:
312 return skl_run_pipe(ctx, mconfig->pipe);
313
314 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
315 case SNDRV_PCM_TRIGGER_SUSPEND:
316 return skl_stop_pipe(ctx, mconfig->pipe);
317
318 default:
319 return 0;
320 }
321}
322
Jeeja KP05057002015-07-09 15:20:11 +0530323static int skl_link_hw_params(struct snd_pcm_substream *substream,
324 struct snd_pcm_hw_params *params,
325 struct snd_soc_dai *dai)
326{
327 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
328 struct hdac_ext_stream *link_dev;
329 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
330 struct skl_dma_params *dma_params;
331 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100332 struct skl_pipe_params p_params = {0};
Jeeja KP05057002015-07-09 15:20:11 +0530333
Jeeja KP05057002015-07-09 15:20:11 +0530334 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
335 HDAC_EXT_STREAM_TYPE_LINK);
336 if (!link_dev)
337 return -EBUSY;
338
339 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
340
341 /* set the stream tag in the codec dai dma params */
342 dma_params = (struct skl_dma_params *)
343 snd_soc_dai_get_dma_data(codec_dai, substream);
344 if (dma_params)
345 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
346 snd_soc_dai_set_dma_data(codec_dai, substream, (void *)dma_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100347
348 p_params.s_fmt = snd_pcm_format_width(params_format(params));
349 p_params.ch = params_channels(params);
350 p_params.s_freq = params_rate(params);
351 p_params.stream = substream->stream;
352 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
353
Jeeja KP4bd073f2015-10-27 09:22:45 +0900354 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KP05057002015-07-09 15:20:11 +0530355}
356
357static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
358 struct snd_soc_dai *dai)
359{
360 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
361 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
362 struct hdac_ext_stream *link_dev =
363 snd_soc_dai_get_dma_data(dai, substream);
364 unsigned int format_val = 0;
365 struct skl_dma_params *dma_params;
366 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KP05057002015-07-09 15:20:11 +0530367 struct hdac_ext_link *link;
368
Jeeja KP05057002015-07-09 15:20:11 +0530369 if (link_dev->link_prepared) {
370 dev_dbg(dai->dev, "already stream is prepared - returning\n");
371 return 0;
372 }
Jeeja KP05057002015-07-09 15:20:11 +0530373
374 dma_params = (struct skl_dma_params *)
375 snd_soc_dai_get_dma_data(codec_dai, substream);
376 if (dma_params)
377 format_val = dma_params->format;
378 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
379 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
380
381 snd_hdac_ext_link_stream_reset(link_dev);
382
383 snd_hdac_ext_link_stream_setup(link_dev, format_val);
384
385 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
386 if (!link)
387 return -EINVAL;
388
389 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
390 link_dev->link_prepared = 1;
391
392 return 0;
393}
394
395static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
396 int cmd, struct snd_soc_dai *dai)
397{
398 struct hdac_ext_stream *link_dev =
399 snd_soc_dai_get_dma_data(dai, substream);
400
401 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
402 switch (cmd) {
403 case SNDRV_PCM_TRIGGER_START:
404 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
405 case SNDRV_PCM_TRIGGER_RESUME:
406 snd_hdac_ext_link_stream_start(link_dev);
407 break;
408
409 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
410 case SNDRV_PCM_TRIGGER_SUSPEND:
411 case SNDRV_PCM_TRIGGER_STOP:
412 snd_hdac_ext_link_stream_clear(link_dev);
413 break;
414
415 default:
416 return -EINVAL;
417 }
418 return 0;
419}
420
421static int skl_link_hw_free(struct snd_pcm_substream *substream,
422 struct snd_soc_dai *dai)
423{
424 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
425 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
426 struct hdac_ext_stream *link_dev =
427 snd_soc_dai_get_dma_data(dai, substream);
428 struct hdac_ext_link *link;
429
430 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
431
432 link_dev->link_prepared = 0;
433
434 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
435 if (!link)
436 return -EINVAL;
437
438 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
439 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
440 return 0;
441}
442
Jeeja KPb663a8c2015-10-07 11:31:57 +0100443static int skl_be_startup(struct snd_pcm_substream *substream,
Jeeja KP05057002015-07-09 15:20:11 +0530444 struct snd_soc_dai *dai)
445{
446 return pm_runtime_get_sync(dai->dev);
447}
448
Jeeja KPb663a8c2015-10-07 11:31:57 +0100449static void skl_be_shutdown(struct snd_pcm_substream *substream,
Jeeja KP05057002015-07-09 15:20:11 +0530450 struct snd_soc_dai *dai)
451{
452 pm_runtime_mark_last_busy(dai->dev);
453 pm_runtime_put_autosuspend(dai->dev);
454}
455
Jeeja KPa40e6932015-07-09 15:20:08 +0530456static struct snd_soc_dai_ops skl_pcm_dai_ops = {
457 .startup = skl_pcm_open,
458 .shutdown = skl_pcm_close,
459 .prepare = skl_pcm_prepare,
460 .hw_params = skl_pcm_hw_params,
461 .hw_free = skl_pcm_hw_free,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100462 .trigger = skl_pcm_trigger,
Jeeja KPa40e6932015-07-09 15:20:08 +0530463};
464
Jeeja KP05057002015-07-09 15:20:11 +0530465static struct snd_soc_dai_ops skl_dmic_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100466 .startup = skl_be_startup,
467 .hw_params = skl_be_hw_params,
468 .shutdown = skl_be_shutdown,
469};
470
471static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
472 .startup = skl_be_startup,
473 .hw_params = skl_be_hw_params,
474 .shutdown = skl_be_shutdown,
Jeeja KP05057002015-07-09 15:20:11 +0530475};
476
477static struct snd_soc_dai_ops skl_link_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100478 .startup = skl_be_startup,
Jeeja KP05057002015-07-09 15:20:11 +0530479 .prepare = skl_link_pcm_prepare,
480 .hw_params = skl_link_hw_params,
481 .hw_free = skl_link_hw_free,
482 .trigger = skl_link_pcm_trigger,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100483 .shutdown = skl_be_shutdown,
Jeeja KP05057002015-07-09 15:20:11 +0530484};
485
Jeeja KPa40e6932015-07-09 15:20:08 +0530486static struct snd_soc_dai_driver skl_platform_dai[] = {
487{
488 .name = "System Pin",
489 .ops = &skl_pcm_dai_ops,
490 .playback = {
491 .stream_name = "System Playback",
492 .channels_min = HDA_MONO,
493 .channels_max = HDA_STEREO,
494 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
495 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
496 },
497 .capture = {
498 .stream_name = "System Capture",
499 .channels_min = HDA_MONO,
500 .channels_max = HDA_STEREO,
501 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
502 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
503 },
504},
505{
Jeeja KP05057002015-07-09 15:20:11 +0530506 .name = "Reference Pin",
507 .ops = &skl_pcm_dai_ops,
508 .capture = {
509 .stream_name = "Reference Capture",
510 .channels_min = HDA_MONO,
511 .channels_max = HDA_STEREO,
512 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
513 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
514 },
515},
516{
Jeeja KPa40e6932015-07-09 15:20:08 +0530517 .name = "Deepbuffer Pin",
518 .ops = &skl_pcm_dai_ops,
519 .playback = {
520 .stream_name = "Deepbuffer Playback",
521 .channels_min = HDA_STEREO,
522 .channels_max = HDA_STEREO,
523 .rates = SNDRV_PCM_RATE_48000,
524 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
525 },
526},
527{
528 .name = "LowLatency Pin",
529 .ops = &skl_pcm_dai_ops,
530 .playback = {
531 .stream_name = "Low Latency Playback",
532 .channels_min = HDA_STEREO,
533 .channels_max = HDA_STEREO,
534 .rates = SNDRV_PCM_RATE_48000,
535 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
536 },
537},
Jeeja KP05057002015-07-09 15:20:11 +0530538/* BE CPU Dais */
539{
Jeeja KPb663a8c2015-10-07 11:31:57 +0100540 .name = "SSP0 Pin",
541 .ops = &skl_be_ssp_dai_ops,
542 .playback = {
543 .stream_name = "ssp0 Tx",
544 .channels_min = HDA_STEREO,
545 .channels_max = HDA_STEREO,
546 .rates = SNDRV_PCM_RATE_48000,
547 .formats = SNDRV_PCM_FMTBIT_S16_LE,
548 },
549 .capture = {
550 .stream_name = "ssp0 Rx",
551 .channels_min = HDA_STEREO,
552 .channels_max = HDA_STEREO,
553 .rates = SNDRV_PCM_RATE_48000,
554 .formats = SNDRV_PCM_FMTBIT_S16_LE,
555 },
556},
557{
Jeeja KP05057002015-07-09 15:20:11 +0530558 .name = "iDisp Pin",
559 .ops = &skl_link_dai_ops,
560 .playback = {
561 .stream_name = "iDisp Tx",
562 .channels_min = HDA_STEREO,
563 .channels_max = HDA_STEREO,
564 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
565 .formats = SNDRV_PCM_FMTBIT_S16_LE,
566 },
567},
568{
569 .name = "DMIC01 Pin",
570 .ops = &skl_dmic_dai_ops,
571 .capture = {
572 .stream_name = "DMIC01 Rx",
573 .channels_min = HDA_STEREO,
574 .channels_max = HDA_STEREO,
575 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
576 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
577 },
578},
579{
Jeeja KP05057002015-07-09 15:20:11 +0530580 .name = "HD-Codec Pin",
581 .ops = &skl_link_dai_ops,
582 .playback = {
583 .stream_name = "HD-Codec Tx",
584 .channels_min = HDA_STEREO,
585 .channels_max = HDA_STEREO,
586 .rates = SNDRV_PCM_RATE_48000,
587 .formats = SNDRV_PCM_FMTBIT_S16_LE,
588 },
589 .capture = {
590 .stream_name = "HD-Codec Rx",
591 .channels_min = HDA_STEREO,
592 .channels_max = HDA_STEREO,
593 .rates = SNDRV_PCM_RATE_48000,
594 .formats = SNDRV_PCM_FMTBIT_S16_LE,
595 },
596},
Jeeja KPa40e6932015-07-09 15:20:08 +0530597};
598
599static int skl_platform_open(struct snd_pcm_substream *substream)
600{
601 struct snd_pcm_runtime *runtime;
602 struct snd_soc_pcm_runtime *rtd = substream->private_data;
603 struct snd_soc_dai_link *dai_link = rtd->dai_link;
604
605 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
606 dai_link->cpu_dai_name);
607
608 runtime = substream->runtime;
609 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
610
611 return 0;
612}
613
Jeeja KPb663a8c2015-10-07 11:31:57 +0100614static int skl_coupled_trigger(struct snd_pcm_substream *substream,
Jeeja KPa40e6932015-07-09 15:20:08 +0530615 int cmd)
616{
617 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
618 struct hdac_bus *bus = ebus_to_hbus(ebus);
619 struct hdac_ext_stream *stream;
620 struct snd_pcm_substream *s;
621 bool start;
622 int sbits = 0;
623 unsigned long cookie;
624 struct hdac_stream *hstr;
625
626 stream = get_hdac_ext_stream(substream);
627 hstr = hdac_stream(stream);
628
629 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
630
631 if (!hstr->prepared)
632 return -EPIPE;
633
634 switch (cmd) {
635 case SNDRV_PCM_TRIGGER_START:
636 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
637 case SNDRV_PCM_TRIGGER_RESUME:
638 start = true;
639 break;
640
641 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
642 case SNDRV_PCM_TRIGGER_SUSPEND:
643 case SNDRV_PCM_TRIGGER_STOP:
644 start = false;
645 break;
646
647 default:
648 return -EINVAL;
649 }
650
651 snd_pcm_group_for_each_entry(s, substream) {
652 if (s->pcm->card != substream->pcm->card)
653 continue;
654 stream = get_hdac_ext_stream(s);
655 sbits |= 1 << hdac_stream(stream)->index;
656 snd_pcm_trigger_done(s, substream);
657 }
658
659 spin_lock_irqsave(&bus->reg_lock, cookie);
660
661 /* first, set SYNC bits of corresponding streams */
662 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
663
664 snd_pcm_group_for_each_entry(s, substream) {
665 if (s->pcm->card != substream->pcm->card)
666 continue;
667 stream = get_hdac_ext_stream(s);
668 if (start)
669 snd_hdac_stream_start(hdac_stream(stream), true);
670 else
671 snd_hdac_stream_stop(hdac_stream(stream));
672 }
673 spin_unlock_irqrestore(&bus->reg_lock, cookie);
674
675 snd_hdac_stream_sync(hstr, start, sbits);
676
677 spin_lock_irqsave(&bus->reg_lock, cookie);
678
679 /* reset SYNC bits */
680 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
681 if (start)
682 snd_hdac_stream_timecounter_init(hstr, sbits);
683 spin_unlock_irqrestore(&bus->reg_lock, cookie);
684
685 return 0;
686}
687
Jeeja KPb663a8c2015-10-07 11:31:57 +0100688static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
Jeeja KP05057002015-07-09 15:20:11 +0530689 int cmd)
690{
691 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
692 struct hdac_bus *bus = ebus_to_hbus(ebus);
693 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
694 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
695 struct hdac_ext_stream *stream;
696 int start;
697 unsigned long cookie;
698 struct hdac_stream *hstr;
699
700 dev_dbg(bus->dev, "In %s cmd=%d streamname=%s\n", __func__, cmd, cpu_dai->name);
701
702 stream = get_hdac_ext_stream(substream);
703 hstr = hdac_stream(stream);
704
705 if (!hstr->prepared)
706 return -EPIPE;
707
708 switch (cmd) {
709 case SNDRV_PCM_TRIGGER_START:
710 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
711 case SNDRV_PCM_TRIGGER_RESUME:
712 start = 1;
713 break;
714
715 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
716 case SNDRV_PCM_TRIGGER_SUSPEND:
717 case SNDRV_PCM_TRIGGER_STOP:
718 start = 0;
719 break;
720
721 default:
722 return -EINVAL;
723 }
724
725 spin_lock_irqsave(&bus->reg_lock, cookie);
726
727 if (start)
728 snd_hdac_stream_start(hdac_stream(stream), true);
729 else
730 snd_hdac_stream_stop(hdac_stream(stream));
731
732 if (start)
733 snd_hdac_stream_timecounter_init(hstr, 0);
734
735 spin_unlock_irqrestore(&bus->reg_lock, cookie);
736
737 return 0;
738}
739static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
740 int cmd)
741{
742 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
743
744 if (ebus->ppcap)
Jeeja KPb663a8c2015-10-07 11:31:57 +0100745 return skl_decoupled_trigger(substream, cmd);
Jeeja KP05057002015-07-09 15:20:11 +0530746 else
Jeeja KPb663a8c2015-10-07 11:31:57 +0100747 return skl_coupled_trigger(substream, cmd);
Jeeja KP05057002015-07-09 15:20:11 +0530748}
749
Jeeja KPa40e6932015-07-09 15:20:08 +0530750/* calculate runtime delay from LPIB */
751static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
752 struct hdac_ext_stream *sstream,
753 unsigned int pos)
754{
755 struct hdac_bus *bus = ebus_to_hbus(ebus);
756 struct hdac_stream *hstream = hdac_stream(sstream);
757 struct snd_pcm_substream *substream = hstream->substream;
758 int stream = substream->stream;
759 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
760 int delay;
761
762 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
763 delay = pos - lpib_pos;
764 else
765 delay = lpib_pos - pos;
766
767 if (delay < 0) {
768 if (delay >= hstream->delay_negative_threshold)
769 delay = 0;
770 else
771 delay += hstream->bufsize;
772 }
773
774 if (delay >= hstream->period_bytes) {
775 dev_info(bus->dev,
776 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
777 delay, hstream->period_bytes);
778 delay = 0;
779 }
780
781 return bytes_to_frames(substream->runtime, delay);
782}
783
784static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
785 int codec_delay)
786{
787 struct hdac_stream *hstr = hdac_stream(hstream);
788 struct snd_pcm_substream *substream = hstr->substream;
789 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
790 unsigned int pos;
791 int delay;
792
793 /* use the position buffer as default */
794 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
795
796 if (pos >= hdac_stream(hstream)->bufsize)
797 pos = 0;
798
799 if (substream->runtime) {
800 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
801 + codec_delay;
802 substream->runtime->delay += delay;
803 }
804
805 return pos;
806}
807
808static snd_pcm_uframes_t skl_platform_pcm_pointer
809 (struct snd_pcm_substream *substream)
810{
811 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
812
813 return bytes_to_frames(substream->runtime,
814 skl_get_position(hstream, 0));
815}
816
817static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
818 u64 nsec)
819{
820 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
821 struct snd_soc_dai *codec_dai = rtd->codec_dai;
822 u64 codec_frames, codec_nsecs;
823
824 if (!codec_dai->driver->ops->delay)
825 return nsec;
826
827 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
828 codec_nsecs = div_u64(codec_frames * 1000000000LL,
829 substream->runtime->rate);
830
831 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
832 return nsec + codec_nsecs;
833
834 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
835}
836
837static int skl_get_time_info(struct snd_pcm_substream *substream,
838 struct timespec *system_ts, struct timespec *audio_ts,
839 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
840 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
841{
842 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
843 struct hdac_stream *hstr = hdac_stream(sstream);
844 u64 nsec;
845
846 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
847 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
848
849 snd_pcm_gettime(substream->runtime, system_ts);
850
851 nsec = timecounter_read(&hstr->tc);
852 nsec = div_u64(nsec, 3); /* can be optimized */
853 if (audio_tstamp_config->report_delay)
854 nsec = skl_adjust_codec_delay(substream, nsec);
855
856 *audio_ts = ns_to_timespec(nsec);
857
858 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
859 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
860 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
861
862 } else {
863 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
864 }
865
866 return 0;
867}
868
869static struct snd_pcm_ops skl_platform_ops = {
870 .open = skl_platform_open,
871 .ioctl = snd_pcm_lib_ioctl,
872 .trigger = skl_platform_pcm_trigger,
873 .pointer = skl_platform_pcm_pointer,
874 .get_time_info = skl_get_time_info,
875 .mmap = snd_pcm_lib_default_mmap,
876 .page = snd_pcm_sgbuf_ops_page,
877};
878
879static void skl_pcm_free(struct snd_pcm *pcm)
880{
881 snd_pcm_lib_preallocate_free_for_all(pcm);
882}
883
884#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
885
886static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
887{
888 struct snd_soc_dai *dai = rtd->cpu_dai;
889 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
890 struct snd_pcm *pcm = rtd->pcm;
891 unsigned int size;
892 int retval = 0;
893 struct skl *skl = ebus_to_skl(ebus);
894
895 if (dai->driver->playback.channels_min ||
896 dai->driver->capture.channels_min) {
897 /* buffer pre-allocation */
898 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
899 if (size > MAX_PREALLOC_SIZE)
900 size = MAX_PREALLOC_SIZE;
901 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
902 SNDRV_DMA_TYPE_DEV_SG,
903 snd_dma_pci_data(skl->pci),
904 size, MAX_PREALLOC_SIZE);
905 if (retval) {
906 dev_err(dai->dev, "dma buffer allocationf fail\n");
907 return retval;
908 }
909 }
910
911 return retval;
912}
913
Jeeja KPb663a8c2015-10-07 11:31:57 +0100914static int skl_platform_soc_probe(struct snd_soc_platform *platform)
915{
916 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
917
918 if (ebus->ppcap)
919 return skl_tplg_init(platform, ebus);
920
921 return 0;
922}
Jeeja KPa40e6932015-07-09 15:20:08 +0530923static struct snd_soc_platform_driver skl_platform_drv = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100924 .probe = skl_platform_soc_probe,
Jeeja KPa40e6932015-07-09 15:20:08 +0530925 .ops = &skl_platform_ops,
926 .pcm_new = skl_pcm_new,
927 .pcm_free = skl_pcm_free,
928};
929
930static const struct snd_soc_component_driver skl_component = {
931 .name = "pcm",
932};
933
934int skl_platform_register(struct device *dev)
935{
936 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100937 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
938 struct skl *skl = ebus_to_skl(ebus);
939
940 INIT_LIST_HEAD(&skl->ppl_list);
941 INIT_LIST_HEAD(&skl->dapm_path_list);
Jeeja KPa40e6932015-07-09 15:20:08 +0530942
943 ret = snd_soc_register_platform(dev, &skl_platform_drv);
944 if (ret) {
945 dev_err(dev, "soc platform registration failed %d\n", ret);
946 return ret;
947 }
948 ret = snd_soc_register_component(dev, &skl_component,
949 skl_platform_dai,
950 ARRAY_SIZE(skl_platform_dai));
951 if (ret) {
952 dev_err(dev, "soc component registration failed %d\n", ret);
953 snd_soc_unregister_platform(dev);
954 }
955
956 return ret;
957
958}
959
960int skl_platform_unregister(struct device *dev)
961{
962 snd_soc_unregister_component(dev);
963 snd_soc_unregister_platform(dev);
964 return 0;
965}