Vaibhav Hiremath | f969a6d | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 1 | /* |
| 2 | * AM33XX CM functions |
| 3 | * |
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * Vaibhav Hiremath <hvaibhav@ti.com> |
| 6 | * |
| 7 | * Reference taken from from OMAP4 cminst44xx.c |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation version 2. |
| 12 | * |
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 14 | * kind, whether express or implied; without even the implied warranty |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/types.h> |
| 21 | #include <linux/errno.h> |
| 22 | #include <linux/err.h> |
| 23 | #include <linux/io.h> |
| 24 | |
| 25 | #include <plat/common.h> |
| 26 | |
Paul Walmsley | 4bd5259 | 2012-10-21 01:01:11 -0600 | [diff] [blame^] | 27 | #include "clockdomain.h" |
Vaibhav Hiremath | f969a6d | 2012-06-18 00:47:26 -0600 | [diff] [blame] | 28 | #include "cm.h" |
| 29 | #include "cm33xx.h" |
| 30 | #include "cm-regbits-34xx.h" |
| 31 | #include "cm-regbits-33xx.h" |
| 32 | #include "prm33xx.h" |
| 33 | |
| 34 | /* |
| 35 | * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: |
| 36 | * |
| 37 | * 0x0 func: Module is fully functional, including OCP |
| 38 | * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep |
| 39 | * abortion |
| 40 | * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if |
| 41 | * using separate functional clock |
| 42 | * 0x3 disabled: Module is disabled and cannot be accessed |
| 43 | * |
| 44 | */ |
| 45 | #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 |
| 46 | #define CLKCTRL_IDLEST_INTRANSITION 0x1 |
| 47 | #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 |
| 48 | #define CLKCTRL_IDLEST_DISABLED 0x3 |
| 49 | |
| 50 | /* Private functions */ |
| 51 | |
| 52 | /* Read a register in a CM instance */ |
| 53 | static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) |
| 54 | { |
| 55 | return __raw_readl(cm_base + inst + idx); |
| 56 | } |
| 57 | |
| 58 | /* Write into a register in a CM */ |
| 59 | static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) |
| 60 | { |
| 61 | __raw_writel(val, cm_base + inst + idx); |
| 62 | } |
| 63 | |
| 64 | /* Read-modify-write a register in CM */ |
| 65 | static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) |
| 66 | { |
| 67 | u32 v; |
| 68 | |
| 69 | v = am33xx_cm_read_reg(inst, idx); |
| 70 | v &= ~mask; |
| 71 | v |= bits; |
| 72 | am33xx_cm_write_reg(v, inst, idx); |
| 73 | |
| 74 | return v; |
| 75 | } |
| 76 | |
| 77 | static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx) |
| 78 | { |
| 79 | return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx); |
| 80 | } |
| 81 | |
| 82 | static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx) |
| 83 | { |
| 84 | return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx); |
| 85 | } |
| 86 | |
| 87 | static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) |
| 88 | { |
| 89 | u32 v; |
| 90 | |
| 91 | v = am33xx_cm_read_reg(inst, idx); |
| 92 | v &= mask; |
| 93 | v >>= __ffs(mask); |
| 94 | |
| 95 | return v; |
| 96 | } |
| 97 | |
| 98 | /** |
| 99 | * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield |
| 100 | * @inst: CM instance register offset (*_INST macro) |
| 101 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 102 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
| 103 | * |
| 104 | * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to |
| 105 | * bit 0. |
| 106 | */ |
| 107 | static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) |
| 108 | { |
| 109 | u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); |
| 110 | v &= AM33XX_IDLEST_MASK; |
| 111 | v >>= AM33XX_IDLEST_SHIFT; |
| 112 | return v; |
| 113 | } |
| 114 | |
| 115 | /** |
| 116 | * _is_module_ready - can module registers be accessed without causing an abort? |
| 117 | * @inst: CM instance register offset (*_INST macro) |
| 118 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 119 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
| 120 | * |
| 121 | * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either |
| 122 | * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. |
| 123 | */ |
| 124 | static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) |
| 125 | { |
| 126 | u32 v; |
| 127 | |
| 128 | v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs); |
| 129 | |
| 130 | return (v == CLKCTRL_IDLEST_FUNCTIONAL || |
| 131 | v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; |
| 132 | } |
| 133 | |
| 134 | /** |
| 135 | * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield |
| 136 | * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) |
| 137 | * @inst: CM instance register offset (*_INST macro) |
| 138 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 139 | * |
| 140 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function |
| 141 | * will handle the shift itself. |
| 142 | */ |
| 143 | static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) |
| 144 | { |
| 145 | u32 v; |
| 146 | |
| 147 | v = am33xx_cm_read_reg(inst, cdoffs); |
| 148 | v &= ~AM33XX_CLKTRCTRL_MASK; |
| 149 | v |= c << AM33XX_CLKTRCTRL_SHIFT; |
| 150 | am33xx_cm_write_reg(v, inst, cdoffs); |
| 151 | } |
| 152 | |
| 153 | /* Public functions */ |
| 154 | |
| 155 | /** |
| 156 | * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? |
| 157 | * @inst: CM instance register offset (*_INST macro) |
| 158 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 159 | * |
| 160 | * Returns true if the clockdomain referred to by (@inst, @cdoffs) |
| 161 | * is in hardware-supervised idle mode, or 0 otherwise. |
| 162 | */ |
| 163 | bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) |
| 164 | { |
| 165 | u32 v; |
| 166 | |
| 167 | v = am33xx_cm_read_reg(inst, cdoffs); |
| 168 | v &= AM33XX_CLKTRCTRL_MASK; |
| 169 | v >>= AM33XX_CLKTRCTRL_SHIFT; |
| 170 | |
| 171 | return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; |
| 172 | } |
| 173 | |
| 174 | /** |
| 175 | * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode |
| 176 | * @inst: CM instance register offset (*_INST macro) |
| 177 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 178 | * |
| 179 | * Put a clockdomain referred to by (@inst, @cdoffs) into |
| 180 | * hardware-supervised idle mode. No return value. |
| 181 | */ |
| 182 | void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) |
| 183 | { |
| 184 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); |
| 185 | } |
| 186 | |
| 187 | /** |
| 188 | * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode |
| 189 | * @inst: CM instance register offset (*_INST macro) |
| 190 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 191 | * |
| 192 | * Put a clockdomain referred to by (@inst, @cdoffs) into |
| 193 | * software-supervised idle mode, i.e., controlled manually by the |
| 194 | * Linux OMAP clockdomain code. No return value. |
| 195 | */ |
| 196 | void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) |
| 197 | { |
| 198 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); |
| 199 | } |
| 200 | |
| 201 | /** |
| 202 | * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle |
| 203 | * @inst: CM instance register offset (*_INST macro) |
| 204 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 205 | * |
| 206 | * Put a clockdomain referred to by (@inst, @cdoffs) into idle |
| 207 | * No return value. |
| 208 | */ |
| 209 | void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) |
| 210 | { |
| 211 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); |
| 212 | } |
| 213 | |
| 214 | /** |
| 215 | * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle |
| 216 | * @inst: CM instance register offset (*_INST macro) |
| 217 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 218 | * |
| 219 | * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, |
| 220 | * waking it up. No return value. |
| 221 | */ |
| 222 | void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) |
| 223 | { |
| 224 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); |
| 225 | } |
| 226 | |
| 227 | /* |
| 228 | * |
| 229 | */ |
| 230 | |
| 231 | /** |
| 232 | * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state |
| 233 | * @inst: CM instance register offset (*_INST macro) |
| 234 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 235 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
| 236 | * |
| 237 | * Wait for the module IDLEST to be functional. If the idle state is in any |
| 238 | * the non functional state (trans, idle or disabled), module and thus the |
| 239 | * sysconfig cannot be accessed and will probably lead to an "imprecise |
| 240 | * external abort" |
| 241 | */ |
| 242 | int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) |
| 243 | { |
| 244 | int i = 0; |
| 245 | |
| 246 | if (!clkctrl_offs) |
| 247 | return 0; |
| 248 | |
| 249 | omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), |
| 250 | MAX_MODULE_READY_TIME, i); |
| 251 | |
| 252 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; |
| 253 | } |
| 254 | |
| 255 | /** |
| 256 | * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled' |
| 257 | * state |
| 258 | * @inst: CM instance register offset (*_INST macro) |
| 259 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 260 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
| 261 | * |
| 262 | * Wait for the module IDLEST to be disabled. Some PRCM transition, |
| 263 | * like reset assertion or parent clock de-activation must wait the |
| 264 | * module to be fully disabled. |
| 265 | */ |
| 266 | int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) |
| 267 | { |
| 268 | int i = 0; |
| 269 | |
| 270 | if (!clkctrl_offs) |
| 271 | return 0; |
| 272 | |
| 273 | omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) == |
| 274 | CLKCTRL_IDLEST_DISABLED), |
| 275 | MAX_MODULE_READY_TIME, i); |
| 276 | |
| 277 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; |
| 278 | } |
| 279 | |
| 280 | /** |
| 281 | * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL |
| 282 | * @mode: Module mode (SW or HW) |
| 283 | * @inst: CM instance register offset (*_INST macro) |
| 284 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 285 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
| 286 | * |
| 287 | * No return value. |
| 288 | */ |
| 289 | void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) |
| 290 | { |
| 291 | u32 v; |
| 292 | |
| 293 | v = am33xx_cm_read_reg(inst, clkctrl_offs); |
| 294 | v &= ~AM33XX_MODULEMODE_MASK; |
| 295 | v |= mode << AM33XX_MODULEMODE_SHIFT; |
| 296 | am33xx_cm_write_reg(v, inst, clkctrl_offs); |
| 297 | } |
| 298 | |
| 299 | /** |
| 300 | * am33xx_cm_module_disable - Disable the module inside CLKCTRL |
| 301 | * @inst: CM instance register offset (*_INST macro) |
| 302 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) |
| 303 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
| 304 | * |
| 305 | * No return value. |
| 306 | */ |
| 307 | void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) |
| 308 | { |
| 309 | u32 v; |
| 310 | |
| 311 | v = am33xx_cm_read_reg(inst, clkctrl_offs); |
| 312 | v &= ~AM33XX_MODULEMODE_MASK; |
| 313 | am33xx_cm_write_reg(v, inst, clkctrl_offs); |
| 314 | } |
Paul Walmsley | 4bd5259 | 2012-10-21 01:01:11 -0600 | [diff] [blame^] | 315 | |
| 316 | /* |
| 317 | * Clockdomain low-level functions |
| 318 | */ |
| 319 | |
| 320 | static int am33xx_clkdm_sleep(struct clockdomain *clkdm) |
| 321 | { |
| 322 | am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) |
| 327 | { |
| 328 | am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); |
| 329 | return 0; |
| 330 | } |
| 331 | |
| 332 | static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) |
| 333 | { |
| 334 | am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); |
| 335 | } |
| 336 | |
| 337 | static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) |
| 338 | { |
| 339 | am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); |
| 340 | } |
| 341 | |
| 342 | static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) |
| 343 | { |
| 344 | if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) |
| 345 | return am33xx_clkdm_wakeup(clkdm); |
| 346 | |
| 347 | return 0; |
| 348 | } |
| 349 | |
| 350 | static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) |
| 351 | { |
| 352 | bool hwsup = false; |
| 353 | |
| 354 | hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); |
| 355 | |
| 356 | if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) |
| 357 | am33xx_clkdm_sleep(clkdm); |
| 358 | |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | struct clkdm_ops am33xx_clkdm_operations = { |
| 363 | .clkdm_sleep = am33xx_clkdm_sleep, |
| 364 | .clkdm_wakeup = am33xx_clkdm_wakeup, |
| 365 | .clkdm_allow_idle = am33xx_clkdm_allow_idle, |
| 366 | .clkdm_deny_idle = am33xx_clkdm_deny_idle, |
| 367 | .clkdm_clk_enable = am33xx_clkdm_clk_enable, |
| 368 | .clkdm_clk_disable = am33xx_clkdm_clk_disable, |
| 369 | }; |