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Darius Augulisaa11e382009-01-30 10:32:28 +02001/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
Darius Augulisaa11e382009-01-30 10:32:28 +020014 * Author:
15 * Darius Augulis, Teltonika Inc.
16 *
17 * Desc.:
18 * Implementation of I2C Adapter/Algorithm Driver
19 * for I2C Bus integrated in Freescale i.MX/MXC processors
20 *
21 * Derived from Motorola GSG China I2C example driver
22 *
23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
25 * Copyright (C) 2007 RightHand Technologies, Inc.
26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
27 *
Jingchang Lud533f042013-08-07 17:05:36 +080028 * Copyright 2013 Freescale Semiconductor, Inc.
29 *
Darius Augulisaa11e382009-01-30 10:32:28 +020030 */
31
32/** Includes *******************************************************************
33*******************************************************************************/
34
Yao Yuan2fbed512014-11-18 18:31:05 +080035#include <linux/clk.h>
Yao Yuance1a7882014-11-18 18:31:06 +080036#include <linux/completion.h>
Yao Yuan2fbed512014-11-18 18:31:05 +080037#include <linux/delay.h>
Yao Yuance1a7882014-11-18 18:31:06 +080038#include <linux/dma-mapping.h>
39#include <linux/dmaengine.h>
40#include <linux/dmapool.h>
Yao Yuan2fbed512014-11-18 18:31:05 +080041#include <linux/err.h>
42#include <linux/errno.h>
43#include <linux/i2c.h>
Darius Augulisaa11e382009-01-30 10:32:28 +020044#include <linux/init.h>
Yao Yuan2fbed512014-11-18 18:31:05 +080045#include <linux/interrupt.h>
46#include <linux/io.h>
Darius Augulisaa11e382009-01-30 10:32:28 +020047#include <linux/kernel.h>
48#include <linux/module.h>
Shawn Guodfcd04b2011-09-08 15:09:35 +080049#include <linux/of.h>
50#include <linux/of_device.h>
Yao Yuance1a7882014-11-18 18:31:06 +080051#include <linux/of_dma.h>
Gao Pan1c4b6c32015-10-23 20:28:54 +080052#include <linux/of_gpio.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020053#include <linux/platform_data/i2c-imx.h>
Yao Yuan2fbed512014-11-18 18:31:05 +080054#include <linux/platform_device.h>
55#include <linux/sched.h>
56#include <linux/slab.h>
Darius Augulisaa11e382009-01-30 10:32:28 +020057
58/** Defines ********************************************************************
59*******************************************************************************/
60
61/* This will be the driver name the kernel reports */
62#define DRIVER_NAME "imx-i2c"
63
64/* Default value */
65#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
66
Yao Yuance1a7882014-11-18 18:31:06 +080067/*
68 * Enable DMA if transfer byte size is bigger than this threshold.
69 * As the hardware request, it must bigger than 4 bytes.\
70 * I have set '16' here, maybe it's not the best but I think it's
71 * the appropriate.
72 */
73#define DMA_THRESHOLD 16
74#define DMA_TIMEOUT 1000
75
Jingchang Lu8cc73312013-08-07 17:05:40 +080076/* IMX I2C registers:
77 * the I2C register offset is different between SoCs,
78 * to provid support for all these chips, split the
79 * register offset into a fixed base address and a
80 * variable shift value, then the full register offset
81 * will be calculated by
82 * reg_off = ( reg_base_addr << reg_shift)
83 */
Darius Augulisaa11e382009-01-30 10:32:28 +020084#define IMX_I2C_IADR 0x00 /* i2c slave address */
Jingchang Lu8cc73312013-08-07 17:05:40 +080085#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
86#define IMX_I2C_I2CR 0x02 /* i2c control */
87#define IMX_I2C_I2SR 0x03 /* i2c status */
88#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
89
90#define IMX_I2C_REGSHIFT 2
Jingchang Luad90efa2013-08-07 17:05:43 +080091#define VF610_I2C_REGSHIFT 0
Darius Augulisaa11e382009-01-30 10:32:28 +020092
93/* Bits of IMX I2C registers */
94#define I2SR_RXAK 0x01
95#define I2SR_IIF 0x02
96#define I2SR_SRW 0x04
97#define I2SR_IAL 0x10
98#define I2SR_IBB 0x20
99#define I2SR_IAAS 0x40
100#define I2SR_ICF 0x80
Yao Yuance1a7882014-11-18 18:31:06 +0800101#define I2CR_DMAEN 0x02
Darius Augulisaa11e382009-01-30 10:32:28 +0200102#define I2CR_RSTA 0x04
103#define I2CR_TXAK 0x08
104#define I2CR_MTX 0x10
105#define I2CR_MSTA 0x20
106#define I2CR_IIEN 0x40
107#define I2CR_IEN 0x80
108
Jingchang Lu171408c2013-08-07 17:05:41 +0800109/* register bits different operating codes definition:
110 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
111 * - write zero to clear(w0c) INT flag on i.MX,
112 * - but write one to clear(w1c) INT flag on Vybrid.
113 * 2) I2CR: I2C module enable operation also differ between SoCs:
114 * - set I2CR_IEN bit enable the module on i.MX,
115 * - but clear I2CR_IEN bit enable the module on Vybrid.
116 */
117#define I2SR_CLR_OPCODE_W0C 0x0
118#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
119#define I2CR_IEN_OPCODE_0 0x0
120#define I2CR_IEN_OPCODE_1 I2CR_IEN
121
Darius Augulisaa11e382009-01-30 10:32:28 +0200122/** Variables ******************************************************************
123*******************************************************************************/
124
Darius Augulisaa11e382009-01-30 10:32:28 +0200125/*
126 * sorted list of clock divider, register value pairs
127 * taken from table 26-5, p.26-9, Freescale i.MX
128 * Integrated Portable System Processor Reference Manual
129 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
130 *
131 * Duplicated divider values removed from list
132 */
Jingchang Lud533f042013-08-07 17:05:36 +0800133struct imx_i2c_clk_pair {
134 u16 div;
135 u16 val;
136};
Darius Augulisaa11e382009-01-30 10:32:28 +0200137
Jingchang Lu4b775022013-08-07 17:05:42 +0800138static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
Darius Augulisaa11e382009-01-30 10:32:28 +0200139 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
140 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
141 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
142 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
143 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
144 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
145 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
146 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
147 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
148 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
149 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
150 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
151 { 3072, 0x1E }, { 3840, 0x1F }
152};
153
Jingchang Luad90efa2013-08-07 17:05:43 +0800154/* Vybrid VF610 clock divider, register value pairs */
155static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
156 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
157 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
158 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
159 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
160 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
161 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
162 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
163 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
164 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
165 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
166 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
167 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
168 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
169 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
170 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
171};
172
Shawn Guo5bdfba22012-09-14 15:19:00 +0800173enum imx_i2c_type {
174 IMX1_I2C,
175 IMX21_I2C,
Jingchang Luad90efa2013-08-07 17:05:43 +0800176 VF610_I2C,
Shawn Guo5bdfba22012-09-14 15:19:00 +0800177};
178
Jingchang Lu4b775022013-08-07 17:05:42 +0800179struct imx_i2c_hwdata {
180 enum imx_i2c_type devtype;
181 unsigned regshift;
182 struct imx_i2c_clk_pair *clk_div;
183 unsigned ndivs;
184 unsigned i2sr_clr_opcode;
185 unsigned i2cr_ien_opcode;
186};
187
Yao Yuance1a7882014-11-18 18:31:06 +0800188struct imx_i2c_dma {
189 struct dma_chan *chan_tx;
190 struct dma_chan *chan_rx;
191 struct dma_chan *chan_using;
192 struct completion cmd_complete;
193 dma_addr_t dma_buf;
194 unsigned int dma_len;
195 enum dma_transfer_direction dma_transfer_dir;
196 enum dma_data_direction dma_data_dir;
197};
198
Darius Augulisaa11e382009-01-30 10:32:28 +0200199struct imx_i2c_struct {
200 struct i2c_adapter adapter;
Darius Augulisaa11e382009-01-30 10:32:28 +0200201 struct clk *clk;
202 void __iomem *base;
Darius Augulisaa11e382009-01-30 10:32:28 +0200203 wait_queue_head_t queue;
204 unsigned long i2csr;
Philipp Zabel4e355f52015-01-22 16:17:29 +0100205 unsigned int disable_delay;
Richard Zhao43309f32009-10-17 17:46:22 +0800206 int stopped;
Richard Zhaodb3a3d42009-10-17 17:46:24 +0800207 unsigned int ifdr; /* IMX_I2C_IFDR */
Fugang Duan9b2a6da2014-05-20 10:21:45 +0800208 unsigned int cur_clk;
209 unsigned int bitrate;
Jingchang Lu4b775022013-08-07 17:05:42 +0800210 const struct imx_i2c_hwdata *hwdata;
Gao Pan1c4b6c32015-10-23 20:28:54 +0800211 struct i2c_bus_recovery_info rinfo;
212
213 struct pinctrl *pinctrl;
214 struct pinctrl_state *pinctrl_pins_default;
215 struct pinctrl_state *pinctrl_pins_gpio;
Yao Yuance1a7882014-11-18 18:31:06 +0800216
217 struct imx_i2c_dma *dma;
Jingchang Lu4b775022013-08-07 17:05:42 +0800218};
219
220static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
221 .devtype = IMX1_I2C,
222 .regshift = IMX_I2C_REGSHIFT,
223 .clk_div = imx_i2c_clk_div,
224 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
225 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
226 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
227
228};
229
230static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
231 .devtype = IMX21_I2C,
232 .regshift = IMX_I2C_REGSHIFT,
233 .clk_div = imx_i2c_clk_div,
234 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
235 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
236 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
237
Darius Augulisaa11e382009-01-30 10:32:28 +0200238};
239
Jingchang Luad90efa2013-08-07 17:05:43 +0800240static struct imx_i2c_hwdata vf610_i2c_hwdata = {
241 .devtype = VF610_I2C,
242 .regshift = VF610_I2C_REGSHIFT,
243 .clk_div = vf610_i2c_clk_div,
244 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
245 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
246 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
247
248};
249
Krzysztof Kozlowskie9a02a32015-05-02 00:54:25 +0900250static const struct platform_device_id imx_i2c_devtype[] = {
Shawn Guo5bdfba22012-09-14 15:19:00 +0800251 {
252 .name = "imx1-i2c",
Jingchang Lu4b775022013-08-07 17:05:42 +0800253 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
Shawn Guo5bdfba22012-09-14 15:19:00 +0800254 }, {
255 .name = "imx21-i2c",
Jingchang Lu4b775022013-08-07 17:05:42 +0800256 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
Shawn Guo5bdfba22012-09-14 15:19:00 +0800257 }, {
258 /* sentinel */
259 }
260};
261MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
262
Shawn Guodfcd04b2011-09-08 15:09:35 +0800263static const struct of_device_id i2c_imx_dt_ids[] = {
Jingchang Lu4b775022013-08-07 17:05:42 +0800264 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
265 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
Jingchang Luad90efa2013-08-07 17:05:43 +0800266 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
Shawn Guodfcd04b2011-09-08 15:09:35 +0800267 { /* sentinel */ }
268};
Arnaud Patard \(Rtp\)2f641a82013-06-20 23:07:06 +0200269MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
Shawn Guodfcd04b2011-09-08 15:09:35 +0800270
Shawn Guo5bdfba22012-09-14 15:19:00 +0800271static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
272{
Jingchang Lu4b775022013-08-07 17:05:42 +0800273 return i2c_imx->hwdata->devtype == IMX1_I2C;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800274}
275
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800276static inline void imx_i2c_write_reg(unsigned int val,
277 struct imx_i2c_struct *i2c_imx, unsigned int reg)
278{
Jingchang Lu4b775022013-08-07 17:05:42 +0800279 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800280}
281
282static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
283 unsigned int reg)
284{
Jingchang Lu4b775022013-08-07 17:05:42 +0800285 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800286}
287
Yao Yuance1a7882014-11-18 18:31:06 +0800288/* Functions for DMA support */
289static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
290 dma_addr_t phy_addr)
291{
292 struct imx_i2c_dma *dma;
293 struct dma_slave_config dma_sconfig;
294 struct device *dev = &i2c_imx->adapter.dev;
295 int ret;
296
297 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
298 if (!dma)
299 return;
300
301 dma->chan_tx = dma_request_slave_channel(dev, "tx");
302 if (!dma->chan_tx) {
303 dev_dbg(dev, "can't request DMA tx channel\n");
Yao Yuance1a7882014-11-18 18:31:06 +0800304 goto fail_al;
305 }
306
307 dma_sconfig.dst_addr = phy_addr +
308 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
309 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
310 dma_sconfig.dst_maxburst = 1;
311 dma_sconfig.direction = DMA_MEM_TO_DEV;
312 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
313 if (ret < 0) {
314 dev_dbg(dev, "can't configure tx channel\n");
315 goto fail_tx;
316 }
317
318 dma->chan_rx = dma_request_slave_channel(dev, "rx");
319 if (!dma->chan_rx) {
320 dev_dbg(dev, "can't request DMA rx channel\n");
Yao Yuance1a7882014-11-18 18:31:06 +0800321 goto fail_tx;
322 }
323
324 dma_sconfig.src_addr = phy_addr +
325 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
326 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
327 dma_sconfig.src_maxburst = 1;
328 dma_sconfig.direction = DMA_DEV_TO_MEM;
329 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
330 if (ret < 0) {
331 dev_dbg(dev, "can't configure rx channel\n");
332 goto fail_rx;
333 }
334
335 i2c_imx->dma = dma;
336 init_completion(&dma->cmd_complete);
337 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
338 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
339
340 return;
341
342fail_rx:
343 dma_release_channel(dma->chan_rx);
344fail_tx:
345 dma_release_channel(dma->chan_tx);
346fail_al:
347 devm_kfree(dev, dma);
348 dev_info(dev, "can't use DMA\n");
349}
350
351static void i2c_imx_dma_callback(void *arg)
352{
353 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
354 struct imx_i2c_dma *dma = i2c_imx->dma;
355
356 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
357 dma->dma_len, dma->dma_data_dir);
358 complete(&dma->cmd_complete);
359}
360
361static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
362 struct i2c_msg *msgs)
363{
364 struct imx_i2c_dma *dma = i2c_imx->dma;
365 struct dma_async_tx_descriptor *txdesc;
366 struct device *dev = &i2c_imx->adapter.dev;
367 struct device *chan_dev = dma->chan_using->device->dev;
368
369 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
370 dma->dma_len, dma->dma_data_dir);
371 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
372 dev_err(dev, "DMA mapping failed\n");
373 goto err_map;
374 }
375
376 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
377 dma->dma_len, dma->dma_transfer_dir,
378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
379 if (!txdesc) {
380 dev_err(dev, "Not able to get desc for DMA xfer\n");
381 goto err_desc;
382 }
383
384 txdesc->callback = i2c_imx_dma_callback;
385 txdesc->callback_param = i2c_imx;
386 if (dma_submit_error(dmaengine_submit(txdesc))) {
387 dev_err(dev, "DMA submit failed\n");
388 goto err_submit;
389 }
390
391 dma_async_issue_pending(dma->chan_using);
392 return 0;
393
394err_submit:
395err_desc:
396 dma_unmap_single(chan_dev, dma->dma_buf,
397 dma->dma_len, dma->dma_data_dir);
398err_map:
399 return -EINVAL;
400}
401
402static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
403{
404 struct imx_i2c_dma *dma = i2c_imx->dma;
405
406 dma->dma_buf = 0;
407 dma->dma_len = 0;
408
409 dma_release_channel(dma->chan_tx);
410 dma->chan_tx = NULL;
411
412 dma_release_channel(dma->chan_rx);
413 dma->chan_rx = NULL;
414
415 dma->chan_using = NULL;
416}
417
Darius Augulisaa11e382009-01-30 10:32:28 +0200418/** Functions for IMX I2C adapter driver ***************************************
419*******************************************************************************/
420
Richard Zhao43309f32009-10-17 17:46:22 +0800421static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
Darius Augulisaa11e382009-01-30 10:32:28 +0200422{
423 unsigned long orig_jiffies = jiffies;
Richard Zhao43309f32009-10-17 17:46:22 +0800424 unsigned int temp;
Darius Augulisaa11e382009-01-30 10:32:28 +0200425
426 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
427
Richard Zhao43309f32009-10-17 17:46:22 +0800428 while (1) {
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800429 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
Haibo Chen639a26c2014-09-03 13:52:07 +0800430
431 /* check for arbitration lost */
432 if (temp & I2SR_IAL) {
433 temp &= ~I2SR_IAL;
434 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
435 return -EAGAIN;
436 }
437
Richard Zhao43309f32009-10-17 17:46:22 +0800438 if (for_busy && (temp & I2SR_IBB))
439 break;
440 if (!for_busy && !(temp & I2SR_IBB))
441 break;
Arnaud Patardda9c99f2010-03-23 17:28:28 +0100442 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
Darius Augulisaa11e382009-01-30 10:32:28 +0200443 dev_dbg(&i2c_imx->adapter.dev,
444 "<%s> I2C bus is busy\n", __func__);
Arnaud Patardda9c99f2010-03-23 17:28:28 +0100445 return -ETIMEDOUT;
Darius Augulisaa11e382009-01-30 10:32:28 +0200446 }
447 schedule();
448 }
449
450 return 0;
451}
452
453static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
454{
Marc Kleine-Buddee39428d2010-06-21 09:27:05 +0200455 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
Darius Augulisaa11e382009-01-30 10:32:28 +0200456
Marc Kleine-Buddee39428d2010-06-21 09:27:05 +0200457 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
Darius Augulisaa11e382009-01-30 10:32:28 +0200458 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
459 return -ETIMEDOUT;
460 }
461 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
462 i2c_imx->i2csr = 0;
463 return 0;
464}
465
466static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
467{
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800468 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
Darius Augulisaa11e382009-01-30 10:32:28 +0200469 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
Fabio Estevam4c0657a2015-10-22 14:41:20 -0200470 return -ENXIO; /* No ACK */
Darius Augulisaa11e382009-01-30 10:32:28 +0200471 }
472
473 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
474 return 0;
475}
476
Fugang Duan9b2a6da2014-05-20 10:21:45 +0800477static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
478{
479 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
480 unsigned int i2c_clk_rate;
481 unsigned int div;
482 int i;
483
484 /* Divider value calculation */
485 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
486 if (i2c_imx->cur_clk == i2c_clk_rate)
487 return;
Philipp Zabel4e355f52015-01-22 16:17:29 +0100488
489 i2c_imx->cur_clk = i2c_clk_rate;
Fugang Duan9b2a6da2014-05-20 10:21:45 +0800490
491 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
492 if (div < i2c_clk_div[0].div)
493 i = 0;
494 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
495 i = i2c_imx->hwdata->ndivs - 1;
496 else
Philipp Zabel4e355f52015-01-22 16:17:29 +0100497 for (i = 0; i2c_clk_div[i].div < div; i++)
498 ;
Fugang Duan9b2a6da2014-05-20 10:21:45 +0800499
500 /* Store divider value */
501 i2c_imx->ifdr = i2c_clk_div[i].val;
502
503 /*
504 * There dummy delay is calculated.
505 * It should be about one I2C clock period long.
506 * This delay is used in I2C bus disable function
507 * to fix chip hardware bug.
508 */
509 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
510 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
511
512#ifdef CONFIG_I2C_DEBUG_BUS
513 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
514 i2c_clk_rate, div);
515 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
516 i2c_clk_div[i].val, i2c_clk_div[i].div);
517#endif
518}
519
Richard Zhao43309f32009-10-17 17:46:22 +0800520static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
Darius Augulisaa11e382009-01-30 10:32:28 +0200521{
522 unsigned int temp = 0;
Richard Zhao43309f32009-10-17 17:46:22 +0800523 int result;
Darius Augulisaa11e382009-01-30 10:32:28 +0200524
525 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
526
Fugang Duan9b2a6da2014-05-20 10:21:45 +0800527 i2c_imx_set_clk(i2c_imx);
528
Fabio Estevame5bf2162013-12-04 20:21:37 -0200529 result = clk_prepare_enable(i2c_imx->clk);
530 if (result)
531 return result;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800532 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200533 /* Enable I2C controller */
Jingchang Lu4b775022013-08-07 17:05:42 +0800534 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
535 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
Richard Zhao43309f32009-10-17 17:46:22 +0800536
537 /* Wait controller to be stable */
538 udelay(50);
539
Darius Augulisaa11e382009-01-30 10:32:28 +0200540 /* Start I2C transaction */
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800541 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200542 temp |= I2CR_MSTA;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800543 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
Richard Zhao43309f32009-10-17 17:46:22 +0800544 result = i2c_imx_bus_busy(i2c_imx, 1);
545 if (result)
546 return result;
547 i2c_imx->stopped = 0;
548
Darius Augulisaa11e382009-01-30 10:32:28 +0200549 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
Yao Yuance1a7882014-11-18 18:31:06 +0800550 temp &= ~I2CR_DMAEN;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800551 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
Richard Zhao43309f32009-10-17 17:46:22 +0800552 return result;
Darius Augulisaa11e382009-01-30 10:32:28 +0200553}
554
555static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
556{
557 unsigned int temp = 0;
558
Richard Zhao43309f32009-10-17 17:46:22 +0800559 if (!i2c_imx->stopped) {
560 /* Stop I2C transaction */
561 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800562 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
Richard Zhao43309f32009-10-17 17:46:22 +0800563 temp &= ~(I2CR_MSTA | I2CR_MTX);
Yao Yuance1a7882014-11-18 18:31:06 +0800564 if (i2c_imx->dma)
565 temp &= ~I2CR_DMAEN;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800566 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
Richard Zhao43309f32009-10-17 17:46:22 +0800567 }
Shawn Guo5bdfba22012-09-14 15:19:00 +0800568 if (is_imx1_i2c(i2c_imx)) {
Richard Zhaoa4094a72009-10-17 17:46:23 +0800569 /*
570 * This delay caused by an i.MXL hardware bug.
571 * If no (or too short) delay, no "STOP" bit will be generated.
572 */
573 udelay(i2c_imx->disable_delay);
574 }
Richard Zhao43309f32009-10-17 17:46:22 +0800575
Valentin Longchampa1ee06b2010-01-21 18:55:32 +0100576 if (!i2c_imx->stopped) {
Richard Zhao43309f32009-10-17 17:46:22 +0800577 i2c_imx_bus_busy(i2c_imx, 0);
Valentin Longchampa1ee06b2010-01-21 18:55:32 +0100578 i2c_imx->stopped = 1;
579 }
Richard Zhao43309f32009-10-17 17:46:22 +0800580
Darius Augulisaa11e382009-01-30 10:32:28 +0200581 /* Disable I2C controller */
Jingchang Lu4b775022013-08-07 17:05:42 +0800582 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
583 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
Richard Zhao83914332011-11-15 14:48:08 +0800584 clk_disable_unprepare(i2c_imx->clk);
Darius Augulisaa11e382009-01-30 10:32:28 +0200585}
586
Darius Augulisaa11e382009-01-30 10:32:28 +0200587static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
588{
589 struct imx_i2c_struct *i2c_imx = dev_id;
590 unsigned int temp;
591
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800592 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200593 if (temp & I2SR_IIF) {
594 /* save status register */
595 i2c_imx->i2csr = temp;
596 temp &= ~I2SR_IIF;
Jingchang Lu4b775022013-08-07 17:05:42 +0800597 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800598 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
Marc Kleine-Buddee39428d2010-06-21 09:27:05 +0200599 wake_up(&i2c_imx->queue);
Darius Augulisaa11e382009-01-30 10:32:28 +0200600 return IRQ_HANDLED;
601 }
602
603 return IRQ_NONE;
604}
605
Yao Yuance1a7882014-11-18 18:31:06 +0800606static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
607 struct i2c_msg *msgs)
608{
609 int result;
Nicholas Mc Guire1ac63fe2015-02-08 06:39:56 -0500610 unsigned long time_left;
Yao Yuance1a7882014-11-18 18:31:06 +0800611 unsigned int temp = 0;
612 unsigned long orig_jiffies = jiffies;
613 struct imx_i2c_dma *dma = i2c_imx->dma;
614 struct device *dev = &i2c_imx->adapter.dev;
615
616 dma->chan_using = dma->chan_tx;
617 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
618 dma->dma_data_dir = DMA_TO_DEVICE;
619 dma->dma_len = msgs->len - 1;
620 result = i2c_imx_dma_xfer(i2c_imx, msgs);
621 if (result)
622 return result;
623
624 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
625 temp |= I2CR_DMAEN;
626 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
627
628 /*
629 * Write slave address.
630 * The first byte must be transmitted by the CPU.
631 */
632 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
633 reinit_completion(&i2c_imx->dma->cmd_complete);
Nicholas Mc Guire1ac63fe2015-02-08 06:39:56 -0500634 time_left = wait_for_completion_timeout(
Yao Yuance1a7882014-11-18 18:31:06 +0800635 &i2c_imx->dma->cmd_complete,
636 msecs_to_jiffies(DMA_TIMEOUT));
Nicholas Mc Guire1ac63fe2015-02-08 06:39:56 -0500637 if (time_left == 0) {
Yao Yuance1a7882014-11-18 18:31:06 +0800638 dmaengine_terminate_all(dma->chan_using);
Nicholas Mc Guirecb9eaba2014-12-27 08:33:53 -0500639 return -ETIMEDOUT;
Yao Yuance1a7882014-11-18 18:31:06 +0800640 }
641
642 /* Waiting for transfer complete. */
643 while (1) {
644 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
645 if (temp & I2SR_ICF)
646 break;
647 if (time_after(jiffies, orig_jiffies +
648 msecs_to_jiffies(DMA_TIMEOUT))) {
649 dev_dbg(dev, "<%s> Timeout\n", __func__);
650 return -ETIMEDOUT;
651 }
652 schedule();
653 }
654
655 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
656 temp &= ~I2CR_DMAEN;
657 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
658
659 /* The last data byte must be transferred by the CPU. */
660 imx_i2c_write_reg(msgs->buf[msgs->len-1],
661 i2c_imx, IMX_I2C_I2DR);
662 result = i2c_imx_trx_complete(i2c_imx);
663 if (result)
664 return result;
665
Wolfram Sangf5084932014-11-19 10:11:39 +0100666 return i2c_imx_acked(i2c_imx);
Yao Yuance1a7882014-11-18 18:31:06 +0800667}
668
669static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
670 struct i2c_msg *msgs, bool is_lastmsg)
671{
672 int result;
Nicholas Mc Guire1ac63fe2015-02-08 06:39:56 -0500673 unsigned long time_left;
Yao Yuance1a7882014-11-18 18:31:06 +0800674 unsigned int temp;
675 unsigned long orig_jiffies = jiffies;
676 struct imx_i2c_dma *dma = i2c_imx->dma;
677 struct device *dev = &i2c_imx->adapter.dev;
678
679 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
680 temp |= I2CR_DMAEN;
681 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
682
683 dma->chan_using = dma->chan_rx;
684 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
685 dma->dma_data_dir = DMA_FROM_DEVICE;
686 /* The last two data bytes must be transferred by the CPU. */
687 dma->dma_len = msgs->len - 2;
688 result = i2c_imx_dma_xfer(i2c_imx, msgs);
689 if (result)
690 return result;
691
692 reinit_completion(&i2c_imx->dma->cmd_complete);
Nicholas Mc Guire1ac63fe2015-02-08 06:39:56 -0500693 time_left = wait_for_completion_timeout(
Yao Yuance1a7882014-11-18 18:31:06 +0800694 &i2c_imx->dma->cmd_complete,
695 msecs_to_jiffies(DMA_TIMEOUT));
Nicholas Mc Guire1ac63fe2015-02-08 06:39:56 -0500696 if (time_left == 0) {
Yao Yuance1a7882014-11-18 18:31:06 +0800697 dmaengine_terminate_all(dma->chan_using);
Nicholas Mc Guirecb9eaba2014-12-27 08:33:53 -0500698 return -ETIMEDOUT;
Yao Yuance1a7882014-11-18 18:31:06 +0800699 }
700
701 /* waiting for transfer complete. */
702 while (1) {
703 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
704 if (temp & I2SR_ICF)
705 break;
706 if (time_after(jiffies, orig_jiffies +
707 msecs_to_jiffies(DMA_TIMEOUT))) {
708 dev_dbg(dev, "<%s> Timeout\n", __func__);
709 return -ETIMEDOUT;
710 }
711 schedule();
712 }
713
714 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
715 temp &= ~I2CR_DMAEN;
716 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
717
718 /* read n-1 byte data */
719 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
720 temp |= I2CR_TXAK;
721 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
722
723 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
724 /* read n byte data */
725 result = i2c_imx_trx_complete(i2c_imx);
726 if (result)
727 return result;
728
729 if (is_lastmsg) {
730 /*
731 * It must generate STOP before read I2DR to prevent
732 * controller from generating another clock cycle
733 */
734 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
735 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
736 temp &= ~(I2CR_MSTA | I2CR_MTX);
737 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
738 i2c_imx_bus_busy(i2c_imx, 0);
739 i2c_imx->stopped = 1;
740 } else {
741 /*
742 * For i2c master receiver repeat restart operation like:
743 * read -> repeat MSTA -> read/write
744 * The controller must set MTX before read the last byte in
745 * the first read operation, otherwise the first read cost
746 * one extra clock cycle.
747 */
748 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
749 temp |= I2CR_MTX;
750 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
751 }
752 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
753
754 return 0;
755}
756
Darius Augulisaa11e382009-01-30 10:32:28 +0200757static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
758{
759 int i, result;
760
761 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
762 __func__, msgs->addr << 1);
763
764 /* write slave address */
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800765 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200766 result = i2c_imx_trx_complete(i2c_imx);
767 if (result)
768 return result;
769 result = i2c_imx_acked(i2c_imx);
770 if (result)
771 return result;
772 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
773
774 /* write data */
775 for (i = 0; i < msgs->len; i++) {
776 dev_dbg(&i2c_imx->adapter.dev,
777 "<%s> write byte: B%d=0x%X\n",
778 __func__, i, msgs->buf[i]);
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800779 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200780 result = i2c_imx_trx_complete(i2c_imx);
781 if (result)
782 return result;
783 result = i2c_imx_acked(i2c_imx);
784 if (result)
785 return result;
786 }
787 return 0;
788}
789
Fugang Duan054b62d2014-04-30 14:24:58 +0800790static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
Darius Augulisaa11e382009-01-30 10:32:28 +0200791{
792 int i, result;
793 unsigned int temp;
Kaushal Butala8e8782c2014-04-04 14:56:10 +0200794 int block_data = msgs->flags & I2C_M_RECV_LEN;
Darius Augulisaa11e382009-01-30 10:32:28 +0200795
796 dev_dbg(&i2c_imx->adapter.dev,
797 "<%s> write slave address: addr=0x%x\n",
798 __func__, (msgs->addr << 1) | 0x01);
799
800 /* write slave address */
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800801 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200802 result = i2c_imx_trx_complete(i2c_imx);
803 if (result)
804 return result;
805 result = i2c_imx_acked(i2c_imx);
806 if (result)
807 return result;
808
809 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
810
811 /* setup bus to read data */
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800812 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200813 temp &= ~I2CR_MTX;
Kaushal Butala8e8782c2014-04-04 14:56:10 +0200814
815 /*
816 * Reset the I2CR_TXAK flag initially for SMBus block read since the
817 * length is unknown
818 */
819 if ((msgs->len - 1) || block_data)
Darius Augulisaa11e382009-01-30 10:32:28 +0200820 temp &= ~I2CR_TXAK;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800821 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
822 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
Darius Augulisaa11e382009-01-30 10:32:28 +0200823
824 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
825
Yao Yuance1a7882014-11-18 18:31:06 +0800826 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
827 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
828
Darius Augulisaa11e382009-01-30 10:32:28 +0200829 /* read data */
830 for (i = 0; i < msgs->len; i++) {
Kaushal Butala8e8782c2014-04-04 14:56:10 +0200831 u8 len = 0;
Philipp Zabel4e355f52015-01-22 16:17:29 +0100832
Darius Augulisaa11e382009-01-30 10:32:28 +0200833 result = i2c_imx_trx_complete(i2c_imx);
834 if (result)
835 return result;
Kaushal Butala8e8782c2014-04-04 14:56:10 +0200836 /*
837 * First byte is the length of remaining packet
838 * in the SMBus block data read. Add it to
839 * msgs->len.
840 */
841 if ((!i) && block_data) {
842 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
843 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
844 return -EPROTO;
845 dev_dbg(&i2c_imx->adapter.dev,
846 "<%s> read length: 0x%X\n",
847 __func__, len);
848 msgs->len += len;
849 }
Darius Augulisaa11e382009-01-30 10:32:28 +0200850 if (i == (msgs->len - 1)) {
Fugang Duan054b62d2014-04-30 14:24:58 +0800851 if (is_lastmsg) {
852 /*
853 * It must generate STOP before read I2DR to prevent
854 * controller from generating another clock cycle
855 */
856 dev_dbg(&i2c_imx->adapter.dev,
857 "<%s> clear MSTA\n", __func__);
858 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
859 temp &= ~(I2CR_MSTA | I2CR_MTX);
860 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
861 i2c_imx_bus_busy(i2c_imx, 0);
862 i2c_imx->stopped = 1;
863 } else {
864 /*
865 * For i2c master receiver repeat restart operation like:
866 * read -> repeat MSTA -> read/write
867 * The controller must set MTX before read the last byte in
868 * the first read operation, otherwise the first read cost
869 * one extra clock cycle.
870 */
871 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
872 temp |= I2CR_MTX;
873 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
874 }
Darius Augulisaa11e382009-01-30 10:32:28 +0200875 } else if (i == (msgs->len - 2)) {
876 dev_dbg(&i2c_imx->adapter.dev,
877 "<%s> set TXAK\n", __func__);
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800878 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200879 temp |= I2CR_TXAK;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800880 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200881 }
Kaushal Butala8e8782c2014-04-04 14:56:10 +0200882 if ((!i) && block_data)
883 msgs->buf[0] = len;
884 else
885 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200886 dev_dbg(&i2c_imx->adapter.dev,
887 "<%s> read byte: B%d=0x%X\n",
888 __func__, i, msgs->buf[i]);
889 }
890 return 0;
891}
892
893static int i2c_imx_xfer(struct i2c_adapter *adapter,
894 struct i2c_msg *msgs, int num)
895{
896 unsigned int i, temp;
897 int result;
Fugang Duan054b62d2014-04-30 14:24:58 +0800898 bool is_lastmsg = false;
Darius Augulisaa11e382009-01-30 10:32:28 +0200899 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
900
901 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
902
Richard Zhao43309f32009-10-17 17:46:22 +0800903 /* Start I2C transfer */
904 result = i2c_imx_start(i2c_imx);
Gao Pan1c4b6c32015-10-23 20:28:54 +0800905 if (result) {
906 if (i2c_imx->adapter.bus_recovery_info) {
907 i2c_recover_bus(&i2c_imx->adapter);
908 result = i2c_imx_start(i2c_imx);
909 }
910 }
911
Darius Augulisaa11e382009-01-30 10:32:28 +0200912 if (result)
913 goto fail0;
914
Darius Augulisaa11e382009-01-30 10:32:28 +0200915 /* read/write data */
916 for (i = 0; i < num; i++) {
Fugang Duan054b62d2014-04-30 14:24:58 +0800917 if (i == num - 1)
918 is_lastmsg = true;
919
Darius Augulisaa11e382009-01-30 10:32:28 +0200920 if (i) {
921 dev_dbg(&i2c_imx->adapter.dev,
922 "<%s> repeated start\n", __func__);
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800923 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200924 temp |= I2CR_RSTA;
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800925 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
Richard Zhao43309f32009-10-17 17:46:22 +0800926 result = i2c_imx_bus_busy(i2c_imx, 1);
927 if (result)
928 goto fail0;
Darius Augulisaa11e382009-01-30 10:32:28 +0200929 }
930 dev_dbg(&i2c_imx->adapter.dev,
931 "<%s> transfer message: %d\n", __func__, i);
932 /* write/read data */
933#ifdef CONFIG_I2C_DEBUG_BUS
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800934 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
Philipp Zabel4e355f52015-01-22 16:17:29 +0100935 dev_dbg(&i2c_imx->adapter.dev,
936 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
937 __func__,
Darius Augulisaa11e382009-01-30 10:32:28 +0200938 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
939 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
940 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +0800941 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
Darius Augulisaa11e382009-01-30 10:32:28 +0200942 dev_dbg(&i2c_imx->adapter.dev,
Philipp Zabel4e355f52015-01-22 16:17:29 +0100943 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
944 __func__,
Darius Augulisaa11e382009-01-30 10:32:28 +0200945 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
946 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
947 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
948 (temp & I2SR_RXAK ? 1 : 0));
949#endif
950 if (msgs[i].flags & I2C_M_RD)
Fugang Duan054b62d2014-04-30 14:24:58 +0800951 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
Yao Yuance1a7882014-11-18 18:31:06 +0800952 else {
953 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
954 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
955 else
956 result = i2c_imx_write(i2c_imx, &msgs[i]);
957 }
Arnaud Patardda9c99f2010-03-23 17:28:28 +0100958 if (result)
959 goto fail0;
Darius Augulisaa11e382009-01-30 10:32:28 +0200960 }
961
962fail0:
963 /* Stop I2C transfer */
964 i2c_imx_stop(i2c_imx);
965
966 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
967 (result < 0) ? "error" : "success msg",
968 (result < 0) ? result : num);
969 return (result < 0) ? result : num;
970}
971
Gao Pan1c4b6c32015-10-23 20:28:54 +0800972static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
973{
974 struct imx_i2c_struct *i2c_imx;
975
976 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
977
978 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
979}
980
981static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
982{
983 struct imx_i2c_struct *i2c_imx;
984
985 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
986
987 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
988}
989
990static void i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
991 struct platform_device *pdev)
992{
993 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
994
995 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
996 PINCTRL_STATE_DEFAULT);
997 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
998 "gpio");
999 rinfo->sda_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1000 "sda-gpios", 0, NULL);
1001 rinfo->scl_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1002 "scl-gpios", 0, NULL);
1003
1004 if (!gpio_is_valid(rinfo->sda_gpio) ||
1005 !gpio_is_valid(rinfo->scl_gpio) ||
1006 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1007 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1008 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1009 return;
1010 }
1011
1012 dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n",
1013 rinfo->sda_gpio, rinfo->scl_gpio);
1014
1015 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1016 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1017 rinfo->recover_bus = i2c_generic_gpio_recovery;
1018 i2c_imx->adapter.bus_recovery_info = rinfo;
1019}
1020
Darius Augulisaa11e382009-01-30 10:32:28 +02001021static u32 i2c_imx_func(struct i2c_adapter *adapter)
1022{
Kaushal Butala8e8782c2014-04-04 14:56:10 +02001023 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1024 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
Darius Augulisaa11e382009-01-30 10:32:28 +02001025}
1026
1027static struct i2c_algorithm i2c_imx_algo = {
1028 .master_xfer = i2c_imx_xfer,
1029 .functionality = i2c_imx_func,
1030};
1031
Wolfram Sang36114312013-10-08 22:35:34 +02001032static int i2c_imx_probe(struct platform_device *pdev)
Darius Augulisaa11e382009-01-30 10:32:28 +02001033{
Shawn Guo5bdfba22012-09-14 15:19:00 +08001034 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1035 &pdev->dev);
Darius Augulisaa11e382009-01-30 10:32:28 +02001036 struct imx_i2c_struct *i2c_imx;
1037 struct resource *res;
Jingoo Han6d4028c2013-07-30 16:59:33 +09001038 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
Darius Augulisaa11e382009-01-30 10:32:28 +02001039 void __iomem *base;
Wolfram Sang8c88ab02012-07-08 13:11:43 +02001040 int irq, ret;
Yao Yuance1a7882014-11-18 18:31:06 +08001041 dma_addr_t phy_addr;
Darius Augulisaa11e382009-01-30 10:32:28 +02001042
1043 dev_dbg(&pdev->dev, "<%s>\n", __func__);
1044
Darius Augulisaa11e382009-01-30 10:32:28 +02001045 irq = platform_get_irq(pdev, 0);
1046 if (irq < 0) {
1047 dev_err(&pdev->dev, "can't get irq number\n");
Wolfram Sanga8763f32013-12-12 22:51:31 +01001048 return irq;
Darius Augulisaa11e382009-01-30 10:32:28 +02001049 }
1050
Wolfram Sang3cc2d002013-05-10 10:16:54 +02001051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding84dbf802013-01-21 11:09:03 +01001052 base = devm_ioremap_resource(&pdev->dev, res);
1053 if (IS_ERR(base))
1054 return PTR_ERR(base);
Uwe Kleine-König4927fbf2010-01-08 17:23:17 +01001055
Yao Yuance1a7882014-11-18 18:31:06 +08001056 phy_addr = (dma_addr_t)res->start;
Fabio Estevamd4ffeec2014-11-07 00:44:34 -02001057 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
Jingoo Han46797a22014-05-13 10:51:58 +09001058 if (!i2c_imx)
Richard Zhao9f8a3e72012-06-04 19:04:25 +08001059 return -ENOMEM;
Darius Augulis309c18d2009-03-31 14:52:54 +03001060
Shawn Guo5bdfba22012-09-14 15:19:00 +08001061 if (of_id)
Jingchang Lu4b775022013-08-07 17:05:42 +08001062 i2c_imx->hwdata = of_id->data;
Jingchang Lu0fc13472013-08-07 17:05:38 +08001063 else
Jingchang Lu4b775022013-08-07 17:05:42 +08001064 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1065 platform_get_device_id(pdev)->driver_data;
Shawn Guo5bdfba22012-09-14 15:19:00 +08001066
Darius Augulisaa11e382009-01-30 10:32:28 +02001067 /* Setup i2c_imx driver structure */
Wolfram Sang973c5ed2012-04-19 17:31:01 +02001068 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
Darius Augulisaa11e382009-01-30 10:32:28 +02001069 i2c_imx->adapter.owner = THIS_MODULE;
1070 i2c_imx->adapter.algo = &i2c_imx_algo;
1071 i2c_imx->adapter.dev.parent = &pdev->dev;
Philipp Zabel4e355f52015-01-22 16:17:29 +01001072 i2c_imx->adapter.nr = pdev->id;
Shawn Guodfcd04b2011-09-08 15:09:35 +08001073 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
Darius Augulisaa11e382009-01-30 10:32:28 +02001074 i2c_imx->base = base;
Darius Augulisaa11e382009-01-30 10:32:28 +02001075
1076 /* Get I2C clock */
Fabio Estevam1f09c672012-07-06 15:31:32 -03001077 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
Darius Augulisaa11e382009-01-30 10:32:28 +02001078 if (IS_ERR(i2c_imx->clk)) {
Darius Augulisaa11e382009-01-30 10:32:28 +02001079 dev_err(&pdev->dev, "can't get I2C clock\n");
Richard Zhao9f8a3e72012-06-04 19:04:25 +08001080 return PTR_ERR(i2c_imx->clk);
Darius Augulisaa11e382009-01-30 10:32:28 +02001081 }
Darius Augulisaa11e382009-01-30 10:32:28 +02001082
Jingchang Lu46f28322013-08-07 17:05:37 +08001083 ret = clk_prepare_enable(i2c_imx->clk);
1084 if (ret) {
1085 dev_err(&pdev->dev, "can't enable I2C clock\n");
1086 return ret;
1087 }
Gao Pan1c4b6c32015-10-23 20:28:54 +08001088
1089 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1090 if (IS_ERR(i2c_imx->pinctrl)) {
1091 ret = PTR_ERR(i2c_imx->pinctrl);
1092 goto clk_disable;
1093 }
1094
Darius Augulisaa11e382009-01-30 10:32:28 +02001095 /* Request IRQ */
Richard Zhao9f8a3e72012-06-04 19:04:25 +08001096 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
1097 pdev->name, i2c_imx);
Darius Augulisaa11e382009-01-30 10:32:28 +02001098 if (ret) {
Richard Zhao9f8a3e72012-06-04 19:04:25 +08001099 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
Fabio Estevama4ce47f2014-10-04 09:17:27 -03001100 goto clk_disable;
Darius Augulisaa11e382009-01-30 10:32:28 +02001101 }
1102
1103 /* Init queue */
1104 init_waitqueue_head(&i2c_imx->queue);
1105
1106 /* Set up adapter data */
1107 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1108
1109 /* Set up clock divider */
Fugang Duan9b2a6da2014-05-20 10:21:45 +08001110 i2c_imx->bitrate = IMX_I2C_BIT_RATE;
Shawn Guodfcd04b2011-09-08 15:09:35 +08001111 ret = of_property_read_u32(pdev->dev.of_node,
Fugang Duan9b2a6da2014-05-20 10:21:45 +08001112 "clock-frequency", &i2c_imx->bitrate);
Shawn Guodfcd04b2011-09-08 15:09:35 +08001113 if (ret < 0 && pdata && pdata->bitrate)
Fugang Duan9b2a6da2014-05-20 10:21:45 +08001114 i2c_imx->bitrate = pdata->bitrate;
Darius Augulisaa11e382009-01-30 10:32:28 +02001115
1116 /* Set up chip registers to defaults */
Jingchang Lu4b775022013-08-07 17:05:42 +08001117 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1118 i2c_imx, IMX_I2C_I2CR);
1119 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
Darius Augulisaa11e382009-01-30 10:32:28 +02001120
1121 /* Add I2C adapter */
1122 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1123 if (ret < 0) {
1124 dev_err(&pdev->dev, "registration failed\n");
Fabio Estevama4ce47f2014-10-04 09:17:27 -03001125 goto clk_disable;
Darius Augulisaa11e382009-01-30 10:32:28 +02001126 }
1127
Gao Pan1c4b6c32015-10-23 20:28:54 +08001128 i2c_imx_init_recovery_info(i2c_imx, pdev);
1129
Darius Augulisaa11e382009-01-30 10:32:28 +02001130 /* Set up platform driver data */
1131 platform_set_drvdata(pdev, i2c_imx);
Jingchang Lu46f28322013-08-07 17:05:37 +08001132 clk_disable_unprepare(i2c_imx->clk);
Darius Augulisaa11e382009-01-30 10:32:28 +02001133
Richard Zhao9f8a3e72012-06-04 19:04:25 +08001134 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
Xiubo Li64bdfbf2014-08-06 11:45:08 +08001135 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
Darius Augulisaa11e382009-01-30 10:32:28 +02001136 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1137 i2c_imx->adapter.name);
Fabio Estevam06d141e2012-08-01 17:38:14 -03001138 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
Darius Augulisaa11e382009-01-30 10:32:28 +02001139
Philipp Zabel4e355f52015-01-22 16:17:29 +01001140 /* Init DMA config if supported */
Yao Yuance1a7882014-11-18 18:31:06 +08001141 i2c_imx_dma_request(i2c_imx, phy_addr);
1142
Darius Augulisaa11e382009-01-30 10:32:28 +02001143 return 0; /* Return OK */
Fabio Estevama4ce47f2014-10-04 09:17:27 -03001144
1145clk_disable:
1146 clk_disable_unprepare(i2c_imx->clk);
1147 return ret;
Darius Augulisaa11e382009-01-30 10:32:28 +02001148}
1149
Wolfram Sang36114312013-10-08 22:35:34 +02001150static int i2c_imx_remove(struct platform_device *pdev)
Darius Augulisaa11e382009-01-30 10:32:28 +02001151{
1152 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
Darius Augulisaa11e382009-01-30 10:32:28 +02001153
1154 /* remove adapter */
1155 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1156 i2c_del_adapter(&i2c_imx->adapter);
Darius Augulisaa11e382009-01-30 10:32:28 +02001157
Yao Yuance1a7882014-11-18 18:31:06 +08001158 if (i2c_imx->dma)
1159 i2c_imx_dma_free(i2c_imx);
1160
Darius Augulisaa11e382009-01-30 10:32:28 +02001161 /* setup chip registers to defaults */
Jingchang Lu1d5ef2a2013-08-07 17:05:39 +08001162 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1163 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1164 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1165 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
Darius Augulisaa11e382009-01-30 10:32:28 +02001166
Darius Augulisaa11e382009-01-30 10:32:28 +02001167 return 0;
1168}
1169
1170static struct platform_driver i2c_imx_driver = {
Wolfram Sang36114312013-10-08 22:35:34 +02001171 .probe = i2c_imx_probe,
1172 .remove = i2c_imx_remove,
Darius Augulisaa11e382009-01-30 10:32:28 +02001173 .driver = {
1174 .name = DRIVER_NAME,
Shawn Guodfcd04b2011-09-08 15:09:35 +08001175 .of_match_table = i2c_imx_dt_ids,
Shawn Guo5bdfba22012-09-14 15:19:00 +08001176 },
1177 .id_table = imx_i2c_devtype,
Darius Augulisaa11e382009-01-30 10:32:28 +02001178};
1179
1180static int __init i2c_adap_imx_init(void)
1181{
Wolfram Sang36114312013-10-08 22:35:34 +02001182 return platform_driver_register(&i2c_imx_driver);
Darius Augulisaa11e382009-01-30 10:32:28 +02001183}
Wolfram Sang5d3f3332009-09-19 09:09:50 +02001184subsys_initcall(i2c_adap_imx_init);
Darius Augulisaa11e382009-01-30 10:32:28 +02001185
1186static void __exit i2c_adap_imx_exit(void)
1187{
1188 platform_driver_unregister(&i2c_imx_driver);
1189}
Darius Augulisaa11e382009-01-30 10:32:28 +02001190module_exit(i2c_adap_imx_exit);
1191
1192MODULE_LICENSE("GPL");
1193MODULE_AUTHOR("Darius Augulis");
1194MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1195MODULE_ALIAS("platform:" DRIVER_NAME);