Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1 | if (BF538 || BF539) |
| 2 | |
| 3 | source "arch/blackfin/mach-bf538/boards/Kconfig" |
| 4 | |
| 5 | menu "BF538 Specific Configuration" |
| 6 | |
| 7 | comment "Interrupt Priority Assignment" |
| 8 | menu "Priority" |
| 9 | |
| 10 | config IRQ_PLL_WAKEUP |
| 11 | int "IRQ_PLL_WAKEUP" |
| 12 | default 7 |
| 13 | config IRQ_DMA0_ERROR |
| 14 | int "IRQ_DMA0_ERROR" |
| 15 | default 7 |
| 16 | config IRQ_PPI_ERROR |
| 17 | int "IRQ_PPI_ERROR" |
| 18 | default 7 |
| 19 | config IRQ_SPORT0_ERROR |
| 20 | int "IRQ_SPORT0_ERROR" |
| 21 | default 7 |
| 22 | config IRQ_SPORT1_ERROR |
| 23 | int "IRQ_SPORT1_ERROR" |
| 24 | default 7 |
| 25 | config IRQ_SPI0_ERROR |
| 26 | int "IRQ_SPI0_ERROR" |
| 27 | default 7 |
| 28 | config IRQ_UART0_ERROR |
| 29 | int "IRQ_UART0_ERROR" |
| 30 | default 7 |
| 31 | config IRQ_RTC |
| 32 | int "IRQ_RTC" |
| 33 | default 8 |
| 34 | config IRQ_PPI |
| 35 | int "IRQ_PPI" |
| 36 | default 8 |
| 37 | config IRQ_SPORT0_RX |
| 38 | int "IRQ_SPORT0_RX" |
| 39 | default 9 |
| 40 | config IRQ_SPORT0_TX |
| 41 | int "IRQ_SPORT0_TX" |
| 42 | default 9 |
| 43 | config IRQ_SPORT1_RX |
| 44 | int "IRQ_SPORT1_RX" |
| 45 | default 9 |
| 46 | config IRQ_SPORT1_TX |
| 47 | int "IRQ_SPORT1_TX" |
| 48 | default 9 |
| 49 | config IRQ_SPI0 |
| 50 | int "IRQ_SPI0" |
| 51 | default 10 |
| 52 | config IRQ_UART0_RX |
| 53 | int "IRQ_UART0_RX" |
| 54 | default 10 |
| 55 | config IRQ_UART0_TX |
| 56 | int "IRQ_UART0_TX" |
| 57 | default 10 |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 58 | config IRQ_TIMER0 |
| 59 | int "IRQ_TIMER0" |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 60 | default 7 if TICKSOURCE_GPTMR0 |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 61 | default 8 |
| 62 | config IRQ_TIMER1 |
| 63 | int "IRQ_TIMER1" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 64 | default 11 |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 65 | config IRQ_TIMER2 |
| 66 | int "IRQ_TIMER2" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 67 | default 11 |
| 68 | config IRQ_PORTF_INTA |
| 69 | int "IRQ_PORTF_INTA" |
| 70 | default 12 |
| 71 | config IRQ_PORTF_INTB |
| 72 | int "IRQ_PORTF_INTB" |
| 73 | default 12 |
| 74 | config IRQ_MEM0_DMA0 |
| 75 | int "IRQ_MEM0_DMA0" |
| 76 | default 13 |
| 77 | config IRQ_MEM0_DMA1 |
| 78 | int "IRQ_MEM0_DMA1" |
| 79 | default 13 |
| 80 | config IRQ_WATCH |
| 81 | int "IRQ_WATCH" |
| 82 | default 13 |
| 83 | config IRQ_DMA1_ERROR |
| 84 | int "IRQ_DMA1_ERROR" |
| 85 | default 7 |
| 86 | config IRQ_SPORT2_ERROR |
| 87 | int "IRQ_SPORT2_ERROR" |
| 88 | default 7 |
| 89 | config IRQ_SPORT3_ERROR |
| 90 | int "IRQ_SPORT3_ERROR" |
| 91 | default 7 |
| 92 | config IRQ_SPI1_ERROR |
| 93 | int "IRQ_SPI1_ERROR" |
| 94 | default 7 |
| 95 | config IRQ_SPI2_ERROR |
| 96 | int "IRQ_SPI2_ERROR" |
| 97 | default 7 |
| 98 | config IRQ_UART1_ERROR |
| 99 | int "IRQ_UART1_ERROR" |
| 100 | default 7 |
| 101 | config IRQ_UART2_ERROR |
| 102 | int "IRQ_UART2_ERROR" |
| 103 | default 7 |
| 104 | config IRQ_CAN_ERROR |
| 105 | int "IRQ_CAN_ERROR" |
| 106 | default 7 |
| 107 | config IRQ_SPORT2_RX |
| 108 | int "IRQ_SPORT2_RX" |
| 109 | default 9 |
| 110 | config IRQ_SPORT2_TX |
| 111 | int "IRQ_SPORT2_TX" |
| 112 | default 9 |
| 113 | config IRQ_SPORT3_RX |
| 114 | int "IRQ_SPORT3_RX" |
| 115 | default 9 |
| 116 | config IRQ_SPORT3_TX |
| 117 | int "IRQ_SPORT3_TX" |
| 118 | default 9 |
| 119 | config IRQ_SPI1 |
| 120 | int "IRQ_SPI1" |
| 121 | default 10 |
| 122 | config IRQ_SPI2 |
| 123 | int "IRQ_SPI2" |
| 124 | default 10 |
| 125 | config IRQ_UART1_RX |
| 126 | int "IRQ_UART1_RX" |
| 127 | default 10 |
| 128 | config IRQ_UART1_TX |
| 129 | int "IRQ_UART1_TX" |
| 130 | default 10 |
| 131 | config IRQ_UART2_RX |
| 132 | int "IRQ_UART2_RX" |
| 133 | default 10 |
| 134 | config IRQ_UART2_TX |
| 135 | int "IRQ_UART2_TX" |
| 136 | default 10 |
| 137 | config IRQ_TWI0 |
| 138 | int "IRQ_TWI0" |
| 139 | default 11 |
| 140 | config IRQ_TWI1 |
| 141 | int "IRQ_TWI1" |
| 142 | default 11 |
| 143 | config IRQ_CAN_RX |
| 144 | int "IRQ_CAN_RX" |
| 145 | default 11 |
| 146 | config IRQ_CAN_TX |
| 147 | int "IRQ_CAN_TX" |
| 148 | default 11 |
| 149 | config IRQ_MEM1_DMA0 |
| 150 | int "IRQ_MEM1_DMA0" |
| 151 | default 13 |
| 152 | config IRQ_MEM1_DMA1 |
| 153 | int "IRQ_MEM1_DMA1" |
| 154 | default 13 |
| 155 | |
| 156 | help |
| 157 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. |
| 158 | This applies to all the above. It is not recommended to assign the |
| 159 | highest priority number 7 to UART or any other device. |
| 160 | |
| 161 | endmenu |
| 162 | |
| 163 | endmenu |
| 164 | |
| 165 | endif |