David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/bitops.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/kernel.h> |
| 24 | #include <linux/ktime.h> |
| 25 | #include <linux/list.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/of.h> |
| 28 | #include <linux/of_device.h> |
| 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/pm_opp.h> |
| 31 | #include <linux/slab.h> |
| 32 | #include <linux/sort.h> |
| 33 | #include <linux/string.h> |
| 34 | #include <linux/uaccess.h> |
| 35 | #include <linux/regulator/driver.h> |
| 36 | #include <linux/regulator/machine.h> |
| 37 | #include <linux/regulator/of_regulator.h> |
| 38 | #include <linux/regulator/msm-ldo-regulator.h> |
| 39 | |
| 40 | #include <soc/qcom/spm.h> |
| 41 | |
| 42 | #include "cpr3-regulator.h" |
| 43 | |
| 44 | #define CPR3_REGULATOR_CORNER_INVALID (-1) |
| 45 | #define CPR3_RO_MASK GENMASK(CPR3_RO_COUNT - 1, 0) |
| 46 | |
| 47 | /* CPR3 registers */ |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 48 | #define CPR3_REG_CPR_VERSION 0x0 |
| 49 | #define CPRH_CPR_VERSION_4P5 0x40050000 |
| 50 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 51 | #define CPR3_REG_CPR_CTL 0x4 |
| 52 | #define CPR3_CPR_CTL_LOOP_EN_MASK BIT(0) |
| 53 | #define CPR3_CPR_CTL_LOOP_ENABLE BIT(0) |
| 54 | #define CPR3_CPR_CTL_LOOP_DISABLE 0 |
| 55 | #define CPR3_CPR_CTL_IDLE_CLOCKS_MASK GENMASK(5, 1) |
| 56 | #define CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT 1 |
| 57 | #define CPR3_CPR_CTL_COUNT_MODE_MASK GENMASK(7, 6) |
| 58 | #define CPR3_CPR_CTL_COUNT_MODE_SHIFT 6 |
| 59 | #define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN 0 |
| 60 | #define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MAX 1 |
| 61 | #define CPR3_CPR_CTL_COUNT_MODE_STAGGERED 2 |
| 62 | #define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE 3 |
| 63 | #define CPR3_CPR_CTL_COUNT_REPEAT_MASK GENMASK(31, 9) |
| 64 | #define CPR3_CPR_CTL_COUNT_REPEAT_SHIFT 9 |
| 65 | |
| 66 | #define CPR3_REG_CPR_STATUS 0x8 |
| 67 | #define CPR3_CPR_STATUS_BUSY_MASK BIT(0) |
| 68 | #define CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK BIT(1) |
| 69 | |
| 70 | /* |
| 71 | * This register is not present on controllers that support HW closed-loop |
| 72 | * except CPR4 APSS controller. |
| 73 | */ |
| 74 | #define CPR3_REG_CPR_TIMER_AUTO_CONT 0xC |
| 75 | |
| 76 | #define CPR3_REG_CPR_STEP_QUOT 0x14 |
| 77 | #define CPR3_CPR_STEP_QUOT_MIN_MASK GENMASK(5, 0) |
| 78 | #define CPR3_CPR_STEP_QUOT_MIN_SHIFT 0 |
| 79 | #define CPR3_CPR_STEP_QUOT_MAX_MASK GENMASK(11, 6) |
| 80 | #define CPR3_CPR_STEP_QUOT_MAX_SHIFT 6 |
| 81 | |
| 82 | #define CPR3_REG_GCNT(ro) (0xA0 + 0x4 * (ro)) |
| 83 | |
| 84 | #define CPR3_REG_SENSOR_BYPASS_WRITE(sensor) (0xE0 + 0x4 * ((sensor) / 32)) |
| 85 | #define CPR3_REG_SENSOR_BYPASS_WRITE_BANK(bank) (0xE0 + 0x4 * (bank)) |
| 86 | |
| 87 | #define CPR3_REG_SENSOR_MASK_WRITE(sensor) (0x120 + 0x4 * ((sensor) / 32)) |
| 88 | #define CPR3_REG_SENSOR_MASK_WRITE_BANK(bank) (0x120 + 0x4 * (bank)) |
| 89 | #define CPR3_REG_SENSOR_MASK_READ(sensor) (0x140 + 0x4 * ((sensor) / 32)) |
| 90 | |
| 91 | #define CPR3_REG_SENSOR_OWNER(sensor) (0x200 + 0x4 * (sensor)) |
| 92 | |
| 93 | #define CPR3_REG_CONT_CMD 0x800 |
| 94 | #define CPR3_CONT_CMD_ACK 0x1 |
| 95 | #define CPR3_CONT_CMD_NACK 0x0 |
| 96 | |
| 97 | #define CPR3_REG_THRESH(thread) (0x808 + 0x440 * (thread)) |
| 98 | #define CPR3_THRESH_CONS_DOWN_MASK GENMASK(3, 0) |
| 99 | #define CPR3_THRESH_CONS_DOWN_SHIFT 0 |
| 100 | #define CPR3_THRESH_CONS_UP_MASK GENMASK(7, 4) |
| 101 | #define CPR3_THRESH_CONS_UP_SHIFT 4 |
| 102 | #define CPR3_THRESH_DOWN_THRESH_MASK GENMASK(12, 8) |
| 103 | #define CPR3_THRESH_DOWN_THRESH_SHIFT 8 |
| 104 | #define CPR3_THRESH_UP_THRESH_MASK GENMASK(17, 13) |
| 105 | #define CPR3_THRESH_UP_THRESH_SHIFT 13 |
| 106 | |
| 107 | #define CPR3_REG_RO_MASK(thread) (0x80C + 0x440 * (thread)) |
| 108 | |
| 109 | #define CPR3_REG_RESULT0(thread) (0x810 + 0x440 * (thread)) |
| 110 | #define CPR3_RESULT0_BUSY_MASK BIT(0) |
| 111 | #define CPR3_RESULT0_STEP_DN_MASK BIT(1) |
| 112 | #define CPR3_RESULT0_STEP_UP_MASK BIT(2) |
| 113 | #define CPR3_RESULT0_ERROR_STEPS_MASK GENMASK(7, 3) |
| 114 | #define CPR3_RESULT0_ERROR_STEPS_SHIFT 3 |
| 115 | #define CPR3_RESULT0_ERROR_MASK GENMASK(19, 8) |
| 116 | #define CPR3_RESULT0_ERROR_SHIFT 8 |
| 117 | #define CPR3_RESULT0_NEGATIVE_MASK BIT(20) |
| 118 | |
| 119 | #define CPR3_REG_RESULT1(thread) (0x814 + 0x440 * (thread)) |
| 120 | #define CPR3_RESULT1_QUOT_MIN_MASK GENMASK(11, 0) |
| 121 | #define CPR3_RESULT1_QUOT_MIN_SHIFT 0 |
| 122 | #define CPR3_RESULT1_QUOT_MAX_MASK GENMASK(23, 12) |
| 123 | #define CPR3_RESULT1_QUOT_MAX_SHIFT 12 |
| 124 | #define CPR3_RESULT1_RO_MIN_MASK GENMASK(27, 24) |
| 125 | #define CPR3_RESULT1_RO_MIN_SHIFT 24 |
| 126 | #define CPR3_RESULT1_RO_MAX_MASK GENMASK(31, 28) |
| 127 | #define CPR3_RESULT1_RO_MAX_SHIFT 28 |
| 128 | |
| 129 | #define CPR3_REG_RESULT2(thread) (0x818 + 0x440 * (thread)) |
| 130 | #define CPR3_RESULT2_STEP_QUOT_MIN_MASK GENMASK(5, 0) |
| 131 | #define CPR3_RESULT2_STEP_QUOT_MIN_SHIFT 0 |
| 132 | #define CPR3_RESULT2_STEP_QUOT_MAX_MASK GENMASK(11, 6) |
| 133 | #define CPR3_RESULT2_STEP_QUOT_MAX_SHIFT 6 |
| 134 | #define CPR3_RESULT2_SENSOR_MIN_MASK GENMASK(23, 16) |
| 135 | #define CPR3_RESULT2_SENSOR_MIN_SHIFT 16 |
| 136 | #define CPR3_RESULT2_SENSOR_MAX_MASK GENMASK(31, 24) |
| 137 | #define CPR3_RESULT2_SENSOR_MAX_SHIFT 24 |
| 138 | |
| 139 | #define CPR3_REG_IRQ_EN 0x81C |
| 140 | #define CPR3_REG_IRQ_CLEAR 0x820 |
| 141 | #define CPR3_REG_IRQ_STATUS 0x824 |
| 142 | #define CPR3_IRQ_UP BIT(3) |
| 143 | #define CPR3_IRQ_MID BIT(2) |
| 144 | #define CPR3_IRQ_DOWN BIT(1) |
| 145 | |
| 146 | #define CPR3_REG_TARGET_QUOT(thread, ro) \ |
| 147 | (0x840 + 0x440 * (thread) + 0x4 * (ro)) |
| 148 | |
| 149 | /* Registers found only on controllers that support HW closed-loop. */ |
| 150 | #define CPR3_REG_PD_THROTTLE 0xE8 |
| 151 | #define CPR3_PD_THROTTLE_DISABLE 0x0 |
| 152 | |
| 153 | #define CPR3_REG_HW_CLOSED_LOOP 0x3000 |
| 154 | #define CPR3_HW_CLOSED_LOOP_ENABLE 0x0 |
| 155 | #define CPR3_HW_CLOSED_LOOP_DISABLE 0x1 |
| 156 | |
| 157 | #define CPR3_REG_CPR_TIMER_MID_CONT 0x3004 |
| 158 | #define CPR3_REG_CPR_TIMER_UP_DN_CONT 0x3008 |
| 159 | |
| 160 | #define CPR3_REG_LAST_MEASUREMENT 0x7F8 |
| 161 | #define CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT 0 |
| 162 | #define CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT 4 |
| 163 | #define CPR3_LAST_MEASUREMENT_THREAD_DN(thread) \ |
| 164 | (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT) |
| 165 | #define CPR3_LAST_MEASUREMENT_THREAD_UP(thread) \ |
| 166 | (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT) |
| 167 | #define CPR3_LAST_MEASUREMENT_AGGR_DN BIT(8) |
| 168 | #define CPR3_LAST_MEASUREMENT_AGGR_MID BIT(9) |
| 169 | #define CPR3_LAST_MEASUREMENT_AGGR_UP BIT(10) |
| 170 | #define CPR3_LAST_MEASUREMENT_VALID BIT(11) |
| 171 | #define CPR3_LAST_MEASUREMENT_SAW_ERROR BIT(12) |
| 172 | #define CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK GENMASK(23, 16) |
| 173 | #define CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT 16 |
| 174 | |
| 175 | /* CPR4 controller specific registers and bit definitions */ |
| 176 | #define CPR4_REG_CPR_TIMER_CLAMP 0x10 |
| 177 | #define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27) |
| 178 | |
| 179 | #define CPR4_REG_MISC 0x700 |
Tirupathi Reddy | 718bc80 | 2017-02-09 16:29:24 +0530 | [diff] [blame] | 180 | #define CPR4_MISC_RESET_STEP_QUOT_LOOP_EN BIT(2) |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 181 | #define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK GENMASK(23, 20) |
| 182 | #define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT 20 |
| 183 | #define CPR4_MISC_TEMP_SENSOR_ID_START_MASK GENMASK(27, 24) |
| 184 | #define CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT 24 |
| 185 | #define CPR4_MISC_TEMP_SENSOR_ID_END_MASK GENMASK(31, 28) |
| 186 | #define CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT 28 |
| 187 | |
| 188 | #define CPR4_REG_SAW_ERROR_STEP_LIMIT 0x7A4 |
| 189 | #define CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK GENMASK(4, 0) |
| 190 | #define CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT 0 |
| 191 | #define CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK GENMASK(9, 5) |
| 192 | #define CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT 5 |
| 193 | |
| 194 | #define CPR4_REG_MARGIN_TEMP_CORE_TIMERS 0x7A8 |
| 195 | #define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK GENMASK(28, 18) |
| 196 | #define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT 18 |
| 197 | |
| 198 | #define CPR4_REG_MARGIN_TEMP_CORE(core) (0x7AC + 0x4 * (core)) |
| 199 | #define CPR4_MARGIN_TEMP_CORE_ADJ_MASK GENMASK(7, 0) |
| 200 | #define CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT 8 |
| 201 | |
| 202 | #define CPR4_REG_MARGIN_TEMP_POINT0N1 0x7F0 |
| 203 | #define CPR4_MARGIN_TEMP_POINT0_MASK GENMASK(11, 0) |
| 204 | #define CPR4_MARGIN_TEMP_POINT0_SHIFT 0 |
| 205 | #define CPR4_MARGIN_TEMP_POINT1_MASK GENMASK(23, 12) |
| 206 | #define CPR4_MARGIN_TEMP_POINT1_SHIFT 12 |
| 207 | #define CPR4_REG_MARGIN_TEMP_POINT2 0x7F4 |
| 208 | #define CPR4_MARGIN_TEMP_POINT2_MASK GENMASK(11, 0) |
| 209 | #define CPR4_MARGIN_TEMP_POINT2_SHIFT 0 |
| 210 | |
| 211 | #define CPR4_REG_MARGIN_ADJ_CTL 0x7F8 |
| 212 | #define CPR4_MARGIN_ADJ_CTL_BOOST_EN BIT(0) |
| 213 | #define CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN BIT(1) |
| 214 | #define CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN BIT(2) |
| 215 | #define CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN BIT(3) |
| 216 | #define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK BIT(4) |
| 217 | #define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE BIT(4) |
| 218 | #define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE 0 |
| 219 | #define CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN BIT(7) |
| 220 | #define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN BIT(8) |
| 221 | #define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK GENMASK(16, 12) |
| 222 | #define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT 12 |
| 223 | #define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK GENMASK(21, 19) |
| 224 | #define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT 19 |
| 225 | #define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK GENMASK(25, 22) |
| 226 | #define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT 22 |
| 227 | #define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK GENMASK(31, 26) |
| 228 | #define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT 26 |
| 229 | |
| 230 | #define CPR4_REG_CPR_MASK_THREAD(thread) (0x80C + 0x440 * (thread)) |
| 231 | #define CPR4_CPR_MASK_THREAD_DISABLE_THREAD BIT(31) |
| 232 | #define CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK GENMASK(15, 0) |
| 233 | |
| 234 | /* CPRh controller specific registers and bit definitions */ |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 235 | #define CPRH_REG_CORNER(thread, corner) \ |
| 236 | ((thread)->ctrl->cpr_hw_version >= CPRH_CPR_VERSION_4P5 \ |
| 237 | ? 0x3500 + 0xA0 * (thread)->thread_id + 0x4 * (corner) \ |
| 238 | : 0x3A00 + 0x4 * (corner)) |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 239 | #define CPRH_CORNER_INIT_VOLTAGE_MASK GENMASK(7, 0) |
| 240 | #define CPRH_CORNER_INIT_VOLTAGE_SHIFT 0 |
| 241 | #define CPRH_CORNER_FLOOR_VOLTAGE_MASK GENMASK(15, 8) |
| 242 | #define CPRH_CORNER_FLOOR_VOLTAGE_SHIFT 8 |
| 243 | #define CPRH_CORNER_QUOT_DELTA_MASK GENMASK(24, 16) |
| 244 | #define CPRH_CORNER_QUOT_DELTA_SHIFT 16 |
| 245 | #define CPRH_CORNER_RO_SEL_MASK GENMASK(28, 25) |
| 246 | #define CPRH_CORNER_RO_SEL_SHIFT 25 |
| 247 | #define CPRH_CORNER_CPR_CL_DISABLE BIT(29) |
| 248 | #define CPRH_CORNER_CORE_TEMP_MARGIN_DISABLE BIT(30) |
| 249 | #define CPRH_CORNER_LAST_KNOWN_VOLTAGE_ENABLE BIT(31) |
| 250 | #define CPRH_CORNER_INIT_VOLTAGE_MAX_VALUE 255 |
| 251 | #define CPRH_CORNER_FLOOR_VOLTAGE_MAX_VALUE 255 |
| 252 | #define CPRH_CORNER_QUOT_DELTA_MAX_VALUE 511 |
| 253 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 254 | #define CPRH_REG_CTL(ctrl) \ |
| 255 | ((ctrl)->cpr_hw_version >= CPRH_CPR_VERSION_4P5 ? 0x3A80 : 0x3AA0) |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 256 | #define CPRH_CTL_OSM_ENABLED BIT(0) |
| 257 | #define CPRH_CTL_BASE_VOLTAGE_MASK GENMASK(10, 1) |
| 258 | #define CPRH_CTL_BASE_VOLTAGE_SHIFT 1 |
| 259 | #define CPRH_CTL_INIT_MODE_MASK GENMASK(16, 11) |
| 260 | #define CPRH_CTL_INIT_MODE_SHIFT 11 |
| 261 | #define CPRH_CTL_MODE_SWITCH_DELAY_MASK GENMASK(24, 17) |
| 262 | #define CPRH_CTL_MODE_SWITCH_DELAY_SHIFT 17 |
| 263 | #define CPRH_CTL_VOLTAGE_MULTIPLIER_MASK GENMASK(28, 25) |
| 264 | #define CPRH_CTL_VOLTAGE_MULTIPLIER_SHIFT 25 |
| 265 | #define CPRH_CTL_LAST_KNOWN_VOLTAGE_MARGIN_MASK GENMASK(31, 29) |
| 266 | #define CPRH_CTL_LAST_KNOWN_VOLTAGE_MARGIN_SHIFT 29 |
| 267 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 268 | #define CPRH_REG_STATUS(thread) \ |
| 269 | ((thread)->ctrl->cpr_hw_version >= CPRH_CPR_VERSION_4P5 \ |
| 270 | ? 0x3A84 + 0x4 * (thread)->thread_id : 0x3AA4) |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 271 | #define CPRH_STATUS_CORNER GENMASK(5, 0) |
| 272 | #define CPRH_STATUS_CORNER_LAST_VOLT_MASK GENMASK(17, 6) |
| 273 | #define CPRH_STATUS_CORNER_LAST_VOLT_SHIFT 6 |
| 274 | |
| 275 | #define CPRH_REG_CORNER_BAND 0x3AA8 |
| 276 | #define CPRH_CORNER_BAND_MASK GENMASK(5, 0) |
| 277 | #define CPRH_CORNER_BAND_SHIFT 6 |
| 278 | #define CPRH_CORNER_BAND_MAX_COUNT 4 |
| 279 | |
| 280 | #define CPRH_MARGIN_TEMP_CORE_VBAND(core, vband) \ |
| 281 | ((vband) == 0 ? CPR4_REG_MARGIN_TEMP_CORE(core) \ |
| 282 | : 0x3AB0 + 0x40 * ((vband) - 1) + 0x4 * (core)) |
| 283 | |
Osvaldo Banuelos | d688dded | 2017-03-22 13:35:46 -0700 | [diff] [blame] | 284 | #define CPRH_REG_MISC_REG2 0x3AAC |
| 285 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_MASK GENMASK(31, 29) |
| 286 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_SHIFT 29 |
| 287 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_MASK GENMASK(28, 24) |
| 288 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_SHIFT 24 |
| 289 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_MASK GENMASK(23, 22) |
| 290 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_SHIFT 22 |
| 291 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_MASK GENMASK(21, 20) |
| 292 | #define CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_SHIFT 20 |
Osvaldo Banuelos | 3bdabd0 | 2017-03-22 13:39:39 -0700 | [diff] [blame] | 293 | #define CPRH_MISC_REG2_ACD_NOTWAIT_4_CL_SETTLE_MASK BIT(16) |
| 294 | #define CPRH_MISC_REG2_ACD_NOTWAIT_4_CL_SETTLE_EN BIT(16) |
| 295 | #define CPRH_MISC_REG2_ACD_AVG_FAST_UPDATE_EN_MASK BIT(13) |
| 296 | #define CPRH_MISC_REG2_ACD_AVG_FAST_UPDATE_EN BIT(13) |
Osvaldo Banuelos | d688dded | 2017-03-22 13:35:46 -0700 | [diff] [blame] | 297 | #define CPRH_MISC_REG2_ACD_AVG_EN_MASK BIT(12) |
| 298 | #define CPRH_MISC_REG2_ACD_AVG_ENABLE BIT(12) |
| 299 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 300 | /* SAW module registers */ |
| 301 | #define SAW_REG_AVS_CTL 0x904 |
| 302 | #define SAW_REG_AVS_LIMIT 0x908 |
| 303 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 304 | /* |
| 305 | * The amount of time to wait for the CPR controller to become idle when |
| 306 | * performing an aging measurement. |
| 307 | */ |
| 308 | #define CPR3_AGING_MEASUREMENT_TIMEOUT_NS 5000000 |
| 309 | |
| 310 | /* |
| 311 | * The number of individual aging measurements to perform which are then |
| 312 | * averaged together in order to determine the final aging adjustment value. |
| 313 | */ |
| 314 | #define CPR3_AGING_MEASUREMENT_ITERATIONS 16 |
| 315 | |
| 316 | /* |
| 317 | * Aging measurements for the aged and unaged ring oscillators take place a few |
| 318 | * microseconds apart. If the vdd-supply voltage fluctuates between the two |
| 319 | * measurements, then the difference between them will be incorrect. The |
| 320 | * difference could end up too high or too low. This constant defines the |
| 321 | * number of lowest and highest measurements to ignore when averaging. |
| 322 | */ |
| 323 | #define CPR3_AGING_MEASUREMENT_FILTER 3 |
| 324 | |
| 325 | /* |
| 326 | * The number of times to attempt the full aging measurement sequence before |
| 327 | * declaring a measurement failure. |
| 328 | */ |
| 329 | #define CPR3_AGING_RETRY_COUNT 5 |
| 330 | |
| 331 | /* |
| 332 | * The maximum time to wait in microseconds for a CPR register write to |
| 333 | * complete. |
| 334 | */ |
| 335 | #define CPR3_REGISTER_WRITE_DELAY_US 200 |
| 336 | |
| 337 | /* |
| 338 | * The number of times the CPRh controller multiplies the mode switch |
| 339 | * delay before utilizing it. |
| 340 | */ |
| 341 | #define CPRH_MODE_SWITCH_DELAY_FACTOR 4 |
| 342 | |
| 343 | /* |
| 344 | * The number of times the CPRh controller multiplies the delta quotient |
| 345 | * steps before utilizing it. |
| 346 | */ |
| 347 | #define CPRH_DELTA_QUOT_STEP_FACTOR 4 |
| 348 | |
| 349 | static DEFINE_MUTEX(cpr3_controller_list_mutex); |
| 350 | static LIST_HEAD(cpr3_controller_list); |
| 351 | static struct dentry *cpr3_debugfs_base; |
| 352 | |
| 353 | /** |
| 354 | * cpr3_read() - read four bytes from the memory address specified |
| 355 | * @ctrl: Pointer to the CPR3 controller |
| 356 | * @offset: Offset in bytes from the CPR3 controller's base address |
| 357 | * |
| 358 | * Return: memory address value |
| 359 | */ |
| 360 | static inline u32 cpr3_read(struct cpr3_controller *ctrl, u32 offset) |
| 361 | { |
| 362 | if (!ctrl->cpr_enabled) { |
| 363 | cpr3_err(ctrl, "CPR register reads are not possible when CPR clocks are disabled\n"); |
| 364 | return 0; |
| 365 | } |
| 366 | |
| 367 | return readl_relaxed(ctrl->cpr_ctrl_base + offset); |
| 368 | } |
| 369 | |
| 370 | /** |
| 371 | * cpr3_write() - write four bytes to the memory address specified |
| 372 | * @ctrl: Pointer to the CPR3 controller |
| 373 | * @offset: Offset in bytes from the CPR3 controller's base address |
| 374 | * @value: Value to write to the memory address |
| 375 | * |
| 376 | * Return: none |
| 377 | */ |
| 378 | static inline void cpr3_write(struct cpr3_controller *ctrl, u32 offset, |
| 379 | u32 value) |
| 380 | { |
| 381 | if (!ctrl->cpr_enabled) { |
| 382 | cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n"); |
| 383 | return; |
| 384 | } |
| 385 | |
| 386 | writel_relaxed(value, ctrl->cpr_ctrl_base + offset); |
| 387 | } |
| 388 | |
| 389 | /** |
| 390 | * cpr3_masked_write() - perform a read-modify-write sequence so that only |
| 391 | * masked bits are modified |
| 392 | * @ctrl: Pointer to the CPR3 controller |
| 393 | * @offset: Offset in bytes from the CPR3 controller's base address |
| 394 | * @mask: Mask identifying the bits that should be modified |
| 395 | * @value: Value to write to the memory address |
| 396 | * |
| 397 | * Return: none |
| 398 | */ |
| 399 | static inline void cpr3_masked_write(struct cpr3_controller *ctrl, u32 offset, |
| 400 | u32 mask, u32 value) |
| 401 | { |
| 402 | u32 reg_val, orig_val; |
| 403 | |
| 404 | if (!ctrl->cpr_enabled) { |
| 405 | cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n"); |
| 406 | return; |
| 407 | } |
| 408 | |
| 409 | reg_val = orig_val = readl_relaxed(ctrl->cpr_ctrl_base + offset); |
| 410 | reg_val &= ~mask; |
| 411 | reg_val |= value & mask; |
| 412 | |
| 413 | if (reg_val != orig_val) |
| 414 | writel_relaxed(reg_val, ctrl->cpr_ctrl_base + offset); |
| 415 | } |
| 416 | |
| 417 | /** |
| 418 | * cpr3_ctrl_loop_enable() - enable the CPR sensing loop for a given controller |
| 419 | * @ctrl: Pointer to the CPR3 controller |
| 420 | * |
| 421 | * Return: none |
| 422 | */ |
| 423 | static inline void cpr3_ctrl_loop_enable(struct cpr3_controller *ctrl) |
| 424 | { |
| 425 | if (ctrl->cpr_enabled && !(ctrl->aggr_corner.sdelta |
| 426 | && ctrl->aggr_corner.sdelta->allow_boost)) |
| 427 | cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, |
| 428 | CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_ENABLE); |
| 429 | } |
| 430 | |
| 431 | /** |
| 432 | * cpr3_ctrl_loop_disable() - disable the CPR sensing loop for a given |
| 433 | * controller |
| 434 | * @ctrl: Pointer to the CPR3 controller |
| 435 | * |
| 436 | * Return: none |
| 437 | */ |
| 438 | static inline void cpr3_ctrl_loop_disable(struct cpr3_controller *ctrl) |
| 439 | { |
| 440 | if (ctrl->cpr_enabled) |
| 441 | cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, |
| 442 | CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_DISABLE); |
| 443 | } |
| 444 | |
| 445 | /** |
| 446 | * cpr3_clock_enable() - prepare and enable all clocks used by this CPR3 |
| 447 | * controller |
| 448 | * @ctrl: Pointer to the CPR3 controller |
| 449 | * |
| 450 | * Return: 0 on success, errno on failure |
| 451 | */ |
| 452 | static int cpr3_clock_enable(struct cpr3_controller *ctrl) |
| 453 | { |
| 454 | int rc; |
| 455 | |
| 456 | rc = clk_prepare_enable(ctrl->bus_clk); |
| 457 | if (rc) { |
| 458 | cpr3_err(ctrl, "failed to enable bus clock, rc=%d\n", rc); |
| 459 | return rc; |
| 460 | } |
| 461 | |
| 462 | rc = clk_prepare_enable(ctrl->iface_clk); |
| 463 | if (rc) { |
| 464 | cpr3_err(ctrl, "failed to enable interface clock, rc=%d\n", rc); |
| 465 | clk_disable_unprepare(ctrl->bus_clk); |
| 466 | return rc; |
| 467 | } |
| 468 | |
| 469 | rc = clk_prepare_enable(ctrl->core_clk); |
| 470 | if (rc) { |
| 471 | cpr3_err(ctrl, "failed to enable core clock, rc=%d\n", rc); |
| 472 | clk_disable_unprepare(ctrl->iface_clk); |
| 473 | clk_disable_unprepare(ctrl->bus_clk); |
| 474 | return rc; |
| 475 | } |
| 476 | |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | /** |
| 481 | * cpr3_clock_disable() - disable and unprepare all clocks used by this CPR3 |
| 482 | * controller |
| 483 | * @ctrl: Pointer to the CPR3 controller |
| 484 | * |
| 485 | * Return: none |
| 486 | */ |
| 487 | static void cpr3_clock_disable(struct cpr3_controller *ctrl) |
| 488 | { |
| 489 | clk_disable_unprepare(ctrl->core_clk); |
| 490 | clk_disable_unprepare(ctrl->iface_clk); |
| 491 | clk_disable_unprepare(ctrl->bus_clk); |
| 492 | } |
| 493 | |
| 494 | /** |
| 495 | * cpr3_ctrl_clear_cpr4_config() - clear the CPR4 register configuration |
| 496 | * programmed for current aggregated corner of a given controller |
| 497 | * @ctrl: Pointer to the CPR3 controller |
| 498 | * |
| 499 | * Return: 0 on success, errno on failure |
| 500 | */ |
| 501 | static inline int cpr3_ctrl_clear_cpr4_config(struct cpr3_controller *ctrl) |
| 502 | { |
| 503 | struct cpr4_sdelta *aggr_sdelta = ctrl->aggr_corner.sdelta; |
| 504 | bool cpr_enabled = ctrl->cpr_enabled; |
| 505 | int i, rc = 0; |
| 506 | |
| 507 | if (!aggr_sdelta || !(aggr_sdelta->allow_core_count_adj |
| 508 | || aggr_sdelta->allow_temp_adj || aggr_sdelta->allow_boost)) |
| 509 | /* cpr4 features are not enabled */ |
| 510 | return 0; |
| 511 | |
| 512 | /* Ensure that CPR clocks are enabled before writing to registers. */ |
| 513 | if (!cpr_enabled) { |
| 514 | rc = cpr3_clock_enable(ctrl); |
| 515 | if (rc) { |
| 516 | cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); |
| 517 | return rc; |
| 518 | } |
| 519 | ctrl->cpr_enabled = true; |
| 520 | } |
| 521 | |
| 522 | /* |
| 523 | * Clear feature enable configuration made for current |
| 524 | * aggregated corner. |
| 525 | */ |
| 526 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 527 | CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK |
| 528 | | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN |
| 529 | | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN |
| 530 | | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN |
| 531 | | CPR4_MARGIN_ADJ_CTL_BOOST_EN |
| 532 | | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, 0); |
| 533 | |
| 534 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 535 | CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, |
| 536 | 0 << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); |
| 537 | |
| 538 | for (i = 0; i <= aggr_sdelta->max_core_count; i++) { |
| 539 | /* Clear voltage margin adjustments programmed in TEMP_COREi */ |
| 540 | cpr3_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE(i), 0); |
| 541 | } |
| 542 | |
| 543 | /* Turn off CPR clocks if they were off before this function call. */ |
| 544 | if (!cpr_enabled) { |
| 545 | cpr3_clock_disable(ctrl); |
| 546 | ctrl->cpr_enabled = false; |
| 547 | } |
| 548 | |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | /** |
| 553 | * cpr3_closed_loop_enable() - enable logical CPR closed-loop operation |
| 554 | * @ctrl: Pointer to the CPR3 controller |
| 555 | * |
| 556 | * Return: 0 on success, errno on failure |
| 557 | */ |
| 558 | static int cpr3_closed_loop_enable(struct cpr3_controller *ctrl) |
| 559 | { |
| 560 | int rc; |
| 561 | |
| 562 | if (!ctrl->cpr_allowed_hw || !ctrl->cpr_allowed_sw) { |
| 563 | cpr3_err(ctrl, "cannot enable closed-loop CPR operation because it is disallowed\n"); |
| 564 | return -EPERM; |
| 565 | } else if (ctrl->cpr_enabled) { |
| 566 | /* Already enabled */ |
| 567 | return 0; |
| 568 | } else if (ctrl->cpr_suspended) { |
| 569 | /* |
| 570 | * CPR must remain disabled as the system is entering suspend. |
| 571 | */ |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | rc = cpr3_clock_enable(ctrl); |
| 576 | if (rc) { |
| 577 | cpr3_err(ctrl, "unable to enable CPR clocks, rc=%d\n", rc); |
| 578 | return rc; |
| 579 | } |
| 580 | |
| 581 | ctrl->cpr_enabled = true; |
| 582 | cpr3_debug(ctrl, "CPR closed-loop operation enabled\n"); |
| 583 | |
| 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | /** |
| 588 | * cpr3_closed_loop_disable() - disable logical CPR closed-loop operation |
| 589 | * @ctrl: Pointer to the CPR3 controller |
| 590 | * |
| 591 | * Return: 0 on success, errno on failure |
| 592 | */ |
| 593 | static inline int cpr3_closed_loop_disable(struct cpr3_controller *ctrl) |
| 594 | { |
| 595 | if (!ctrl->cpr_enabled) { |
| 596 | /* Already disabled */ |
| 597 | return 0; |
| 598 | } |
| 599 | |
| 600 | cpr3_clock_disable(ctrl); |
| 601 | ctrl->cpr_enabled = false; |
| 602 | cpr3_debug(ctrl, "CPR closed-loop operation disabled\n"); |
| 603 | |
| 604 | return 0; |
| 605 | } |
| 606 | |
| 607 | /** |
| 608 | * cpr3_regulator_get_gcnt() - returns the GCNT register value corresponding |
| 609 | * to the clock rate and sensor time of the CPR3 controller |
| 610 | * @ctrl: Pointer to the CPR3 controller |
| 611 | * |
| 612 | * Return: GCNT value |
| 613 | */ |
| 614 | static u32 cpr3_regulator_get_gcnt(struct cpr3_controller *ctrl) |
| 615 | { |
| 616 | u64 temp; |
| 617 | unsigned int remainder; |
| 618 | u32 gcnt; |
| 619 | |
| 620 | temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->sensor_time; |
| 621 | remainder = do_div(temp, 1000000000); |
| 622 | if (remainder) |
| 623 | temp++; |
| 624 | /* |
| 625 | * GCNT == 0 corresponds to a single ref clock measurement interval so |
| 626 | * offset GCNT values by 1. |
| 627 | */ |
| 628 | gcnt = temp - 1; |
| 629 | |
| 630 | return gcnt; |
| 631 | } |
| 632 | |
| 633 | /** |
| 634 | * cpr3_regulator_init_thread() - performs hardware initialization of CPR |
| 635 | * thread registers |
| 636 | * @thread: Pointer to the CPR3 thread |
| 637 | * |
| 638 | * CPR interface/bus clocks must be enabled before calling this function. |
| 639 | * |
| 640 | * Return: 0 on success, errno on failure |
| 641 | */ |
| 642 | static int cpr3_regulator_init_thread(struct cpr3_thread *thread) |
| 643 | { |
| 644 | u32 reg; |
| 645 | |
| 646 | reg = (thread->consecutive_up << CPR3_THRESH_CONS_UP_SHIFT) |
| 647 | & CPR3_THRESH_CONS_UP_MASK; |
| 648 | reg |= (thread->consecutive_down << CPR3_THRESH_CONS_DOWN_SHIFT) |
| 649 | & CPR3_THRESH_CONS_DOWN_MASK; |
| 650 | reg |= (thread->up_threshold << CPR3_THRESH_UP_THRESH_SHIFT) |
| 651 | & CPR3_THRESH_UP_THRESH_MASK; |
| 652 | reg |= (thread->down_threshold << CPR3_THRESH_DOWN_THRESH_SHIFT) |
| 653 | & CPR3_THRESH_DOWN_THRESH_MASK; |
| 654 | |
| 655 | cpr3_write(thread->ctrl, CPR3_REG_THRESH(thread->thread_id), reg); |
| 656 | |
| 657 | /* |
| 658 | * Mask all RO's initially so that unused thread doesn't contribute |
| 659 | * to closed-loop voltage. |
| 660 | */ |
| 661 | cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), |
| 662 | CPR3_RO_MASK); |
| 663 | |
| 664 | return 0; |
| 665 | } |
| 666 | |
| 667 | /** |
| 668 | * cpr4_regulator_init_temp_points() - performs hardware initialization of CPR4 |
| 669 | * registers to track tsen temperature data and also specify the |
| 670 | * temperature band range values to apply different voltage margins |
| 671 | * @ctrl: Pointer to the CPR3 controller |
| 672 | * |
| 673 | * CPR interface/bus clocks must be enabled before calling this function. |
| 674 | * |
| 675 | * Return: 0 on success, errno on failure |
| 676 | */ |
| 677 | static int cpr4_regulator_init_temp_points(struct cpr3_controller *ctrl) |
| 678 | { |
| 679 | if (!ctrl->allow_temp_adj) |
| 680 | return 0; |
| 681 | |
| 682 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 683 | CPR4_MISC_TEMP_SENSOR_ID_START_MASK, |
| 684 | ctrl->temp_sensor_id_start |
| 685 | << CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT); |
| 686 | |
| 687 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 688 | CPR4_MISC_TEMP_SENSOR_ID_END_MASK, |
| 689 | ctrl->temp_sensor_id_end |
| 690 | << CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT); |
| 691 | |
| 692 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT2, |
| 693 | CPR4_MARGIN_TEMP_POINT2_MASK, |
| 694 | (ctrl->temp_band_count == 4 ? ctrl->temp_points[2] : 0x7FF) |
| 695 | << CPR4_MARGIN_TEMP_POINT2_SHIFT); |
| 696 | |
| 697 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1, |
| 698 | CPR4_MARGIN_TEMP_POINT1_MASK, |
| 699 | (ctrl->temp_band_count >= 3 ? ctrl->temp_points[1] : 0x7FF) |
| 700 | << CPR4_MARGIN_TEMP_POINT1_SHIFT); |
| 701 | |
| 702 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1, |
| 703 | CPR4_MARGIN_TEMP_POINT0_MASK, |
| 704 | (ctrl->temp_band_count >= 2 ? ctrl->temp_points[0] : 0x7FF) |
| 705 | << CPR4_MARGIN_TEMP_POINT0_SHIFT); |
| 706 | return 0; |
| 707 | } |
| 708 | |
| 709 | /** |
| 710 | * cpr3_regulator_init_cpr4() - performs hardware initialization at the |
| 711 | * controller and thread level required for CPR4 operation. |
| 712 | * @ctrl: Pointer to the CPR3 controller |
| 713 | * |
| 714 | * CPR interface/bus clocks must be enabled before calling this function. |
| 715 | * This function allocates sdelta structures and sdelta tables for aggregated |
| 716 | * corners of the controller and its threads. |
| 717 | * |
| 718 | * Return: 0 on success, errno on failure |
| 719 | */ |
| 720 | static int cpr3_regulator_init_cpr4(struct cpr3_controller *ctrl) |
| 721 | { |
| 722 | struct cpr3_thread *thread; |
| 723 | struct cpr3_regulator *vreg; |
| 724 | struct cpr4_sdelta *sdelta; |
| 725 | int i, j, ctrl_max_core_count, thread_max_core_count, rc = 0; |
| 726 | bool ctrl_valid_sdelta, thread_valid_sdelta; |
| 727 | u32 pmic_step_size = 1; |
| 728 | int thread_id = 0; |
| 729 | u64 temp; |
| 730 | |
Tirupathi Reddy | 718bc80 | 2017-02-09 16:29:24 +0530 | [diff] [blame] | 731 | if (ctrl->reset_step_quot_loop_en) |
| 732 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 733 | CPR4_MISC_RESET_STEP_QUOT_LOOP_EN, |
| 734 | CPR4_MISC_RESET_STEP_QUOT_LOOP_EN); |
| 735 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 736 | if (ctrl->supports_hw_closed_loop) { |
| 737 | if (ctrl->saw_use_unit_mV) |
| 738 | pmic_step_size = ctrl->step_volt / 1000; |
| 739 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 740 | CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK, |
| 741 | (pmic_step_size |
| 742 | << CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT)); |
| 743 | |
| 744 | cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, |
| 745 | CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK, |
| 746 | (ctrl->down_error_step_limit |
| 747 | << CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT)); |
| 748 | |
| 749 | cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, |
| 750 | CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK, |
| 751 | (ctrl->up_error_step_limit |
| 752 | << CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT)); |
| 753 | |
| 754 | /* |
| 755 | * Enable thread aggregation regardless of which threads are |
| 756 | * enabled or disabled. |
| 757 | */ |
| 758 | cpr3_masked_write(ctrl, CPR4_REG_CPR_TIMER_CLAMP, |
| 759 | CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN, |
| 760 | CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN); |
| 761 | |
| 762 | switch (ctrl->thread_count) { |
| 763 | case 0: |
| 764 | /* Disable both threads */ |
| 765 | cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(0), |
| 766 | CPR4_CPR_MASK_THREAD_DISABLE_THREAD |
| 767 | | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, |
| 768 | CPR4_CPR_MASK_THREAD_DISABLE_THREAD |
| 769 | | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); |
| 770 | |
| 771 | cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(1), |
| 772 | CPR4_CPR_MASK_THREAD_DISABLE_THREAD |
| 773 | | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, |
| 774 | CPR4_CPR_MASK_THREAD_DISABLE_THREAD |
| 775 | | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); |
| 776 | break; |
| 777 | case 1: |
| 778 | /* Disable unused thread */ |
| 779 | thread_id = ctrl->thread[0].thread_id ? 0 : 1; |
| 780 | cpr3_masked_write(ctrl, |
| 781 | CPR4_REG_CPR_MASK_THREAD(thread_id), |
| 782 | CPR4_CPR_MASK_THREAD_DISABLE_THREAD |
| 783 | | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, |
| 784 | CPR4_CPR_MASK_THREAD_DISABLE_THREAD |
| 785 | | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); |
| 786 | break; |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | if (!ctrl->allow_core_count_adj && !ctrl->allow_temp_adj |
| 791 | && !ctrl->allow_boost) { |
| 792 | /* |
| 793 | * Skip below configuration as none of the features |
| 794 | * are enabled. |
| 795 | */ |
| 796 | return rc; |
| 797 | } |
| 798 | |
| 799 | if (ctrl->supports_hw_closed_loop) |
| 800 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 801 | CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN, |
| 802 | CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN); |
| 803 | |
| 804 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 805 | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK, |
| 806 | ctrl->step_quot_fixed |
| 807 | << CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT); |
| 808 | |
| 809 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 810 | CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN, |
| 811 | (ctrl->use_dynamic_step_quot |
| 812 | ? CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN : 0)); |
| 813 | |
| 814 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 815 | CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK, |
| 816 | ctrl->initial_temp_band |
| 817 | << CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT); |
| 818 | |
| 819 | rc = cpr4_regulator_init_temp_points(ctrl); |
| 820 | if (rc) { |
| 821 | cpr3_err(ctrl, "initialize temp points failed, rc=%d\n", rc); |
| 822 | return rc; |
| 823 | } |
| 824 | |
| 825 | if (ctrl->voltage_settling_time) { |
| 826 | /* |
| 827 | * Configure the settling timer used to account for |
| 828 | * one VDD supply step. |
| 829 | */ |
| 830 | temp = (u64)ctrl->cpr_clock_rate |
| 831 | * (u64)ctrl->voltage_settling_time; |
| 832 | do_div(temp, 1000000000); |
| 833 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE_TIMERS, |
| 834 | CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK, |
| 835 | temp |
| 836 | << CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT); |
| 837 | } |
| 838 | |
| 839 | /* |
| 840 | * Allocate memory for cpr4_sdelta structure and sdelta table for |
| 841 | * controller aggregated corner by finding the maximum core count |
| 842 | * used by any cpr3 regulators. |
| 843 | */ |
| 844 | ctrl_max_core_count = 1; |
| 845 | ctrl_valid_sdelta = false; |
| 846 | for (i = 0; i < ctrl->thread_count; i++) { |
| 847 | thread = &ctrl->thread[i]; |
| 848 | |
| 849 | /* |
| 850 | * Allocate memory for cpr4_sdelta structure and sdelta table |
| 851 | * for thread aggregated corner by finding the maximum core |
| 852 | * count used by any cpr3 regulators of the thread. |
| 853 | */ |
| 854 | thread_max_core_count = 1; |
| 855 | thread_valid_sdelta = false; |
| 856 | for (j = 0; j < thread->vreg_count; j++) { |
| 857 | vreg = &thread->vreg[j]; |
| 858 | thread_max_core_count = max(thread_max_core_count, |
| 859 | vreg->max_core_count); |
| 860 | thread_valid_sdelta |= (vreg->allow_core_count_adj |
| 861 | | vreg->allow_temp_adj |
| 862 | | vreg->allow_boost); |
| 863 | } |
| 864 | if (thread_valid_sdelta) { |
| 865 | sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), |
| 866 | GFP_KERNEL); |
| 867 | if (!sdelta) |
| 868 | return -ENOMEM; |
| 869 | |
| 870 | sdelta->table = devm_kcalloc(ctrl->dev, |
| 871 | thread_max_core_count |
| 872 | * ctrl->temp_band_count, |
| 873 | sizeof(*sdelta->table), |
| 874 | GFP_KERNEL); |
| 875 | if (!sdelta->table) |
| 876 | return -ENOMEM; |
| 877 | |
| 878 | sdelta->boost_table = devm_kcalloc(ctrl->dev, |
| 879 | ctrl->temp_band_count, |
| 880 | sizeof(*sdelta->boost_table), |
| 881 | GFP_KERNEL); |
| 882 | if (!sdelta->boost_table) |
| 883 | return -ENOMEM; |
| 884 | |
| 885 | thread->aggr_corner.sdelta = sdelta; |
| 886 | } |
| 887 | |
| 888 | ctrl_valid_sdelta |= thread_valid_sdelta; |
| 889 | ctrl_max_core_count = max(ctrl_max_core_count, |
| 890 | thread_max_core_count); |
| 891 | } |
| 892 | |
| 893 | if (ctrl_valid_sdelta) { |
| 894 | sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), GFP_KERNEL); |
| 895 | if (!sdelta) |
| 896 | return -ENOMEM; |
| 897 | |
| 898 | sdelta->table = devm_kcalloc(ctrl->dev, ctrl_max_core_count |
| 899 | * ctrl->temp_band_count, |
| 900 | sizeof(*sdelta->table), GFP_KERNEL); |
| 901 | if (!sdelta->table) |
| 902 | return -ENOMEM; |
| 903 | |
| 904 | sdelta->boost_table = devm_kcalloc(ctrl->dev, |
| 905 | ctrl->temp_band_count, |
| 906 | sizeof(*sdelta->boost_table), |
| 907 | GFP_KERNEL); |
| 908 | if (!sdelta->boost_table) |
| 909 | return -ENOMEM; |
| 910 | |
| 911 | ctrl->aggr_corner.sdelta = sdelta; |
| 912 | } |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | /** |
| 918 | * cpr3_write_temp_core_margin() - programs hardware SDELTA registers with |
| 919 | * the voltage margin adjustments that need to be applied for |
| 920 | * different online core-count and temperature bands. |
| 921 | * @ctrl: Pointer to the CPR3 controller |
| 922 | * @addr: SDELTA register address |
| 923 | * @temp_core_adj: Array of voltage margin values for different temperature |
| 924 | * bands. |
| 925 | * |
| 926 | * CPR interface/bus clocks must be enabled before calling this function. |
| 927 | * |
| 928 | * Return: none |
| 929 | */ |
| 930 | static void cpr3_write_temp_core_margin(struct cpr3_controller *ctrl, |
| 931 | int addr, int *temp_core_adj) |
| 932 | { |
| 933 | int i, margin_steps; |
| 934 | u32 reg = 0; |
| 935 | |
| 936 | for (i = 0; i < ctrl->temp_band_count; i++) { |
| 937 | margin_steps = max(min(temp_core_adj[i], 127), -128); |
| 938 | reg |= (margin_steps & CPR4_MARGIN_TEMP_CORE_ADJ_MASK) << |
| 939 | (i * CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT); |
| 940 | } |
| 941 | |
| 942 | cpr3_write(ctrl, addr, reg); |
| 943 | cpr3_debug(ctrl, "sdelta offset=0x%08x, val=0x%08x\n", addr, reg); |
| 944 | } |
| 945 | |
| 946 | /** |
| 947 | * cpr3_controller_program_sdelta() - programs hardware SDELTA registers with |
| 948 | * the voltage margin adjustments that need to be applied at |
| 949 | * different online core-count and temperature bands. Also, |
| 950 | * programs hardware register configuration for per-online-core |
| 951 | * and per-temperature based adjustments. |
| 952 | * @ctrl: Pointer to the CPR3 controller |
| 953 | * |
| 954 | * CPR interface/bus clocks must be enabled before calling this function. |
| 955 | * |
| 956 | * Return: 0 on success, errno on failure |
| 957 | */ |
| 958 | static int cpr3_controller_program_sdelta(struct cpr3_controller *ctrl) |
| 959 | { |
| 960 | struct cpr3_corner *corner = &ctrl->aggr_corner; |
| 961 | struct cpr4_sdelta *sdelta = corner->sdelta; |
| 962 | int i, index, max_core_count, rc = 0; |
| 963 | bool cpr_enabled = ctrl->cpr_enabled; |
| 964 | |
| 965 | if (!sdelta) |
| 966 | /* cpr4_sdelta not defined for current aggregated corner */ |
| 967 | return 0; |
| 968 | |
| 969 | if (ctrl->supports_hw_closed_loop && ctrl->cpr_enabled) { |
| 970 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 971 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 972 | (ctrl->use_hw_closed_loop && !sdelta->allow_boost) |
| 973 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE : 0); |
| 974 | } |
| 975 | |
| 976 | if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj |
| 977 | && !sdelta->allow_boost) { |
| 978 | /* |
| 979 | * Per-online-core, per-temperature and voltage boost |
| 980 | * adjustments are disabled for this aggregation corner. |
| 981 | */ |
| 982 | return 0; |
| 983 | } |
| 984 | |
| 985 | /* Ensure that CPR clocks are enabled before writing to registers. */ |
| 986 | if (!cpr_enabled) { |
| 987 | rc = cpr3_clock_enable(ctrl); |
| 988 | if (rc) { |
| 989 | cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); |
| 990 | return rc; |
| 991 | } |
| 992 | ctrl->cpr_enabled = true; |
| 993 | } |
| 994 | |
| 995 | max_core_count = sdelta->max_core_count; |
| 996 | |
| 997 | if (sdelta->allow_core_count_adj || sdelta->allow_temp_adj) { |
| 998 | if (sdelta->allow_core_count_adj) { |
| 999 | /* Program TEMP_CORE0 to same margins as TEMP_CORE1 */ |
| 1000 | cpr3_write_temp_core_margin(ctrl, |
| 1001 | CPR4_REG_MARGIN_TEMP_CORE(0), |
| 1002 | &sdelta->table[0]); |
| 1003 | } |
| 1004 | |
| 1005 | for (i = 0; i < max_core_count; i++) { |
| 1006 | index = i * sdelta->temp_band_count; |
| 1007 | /* |
| 1008 | * Program TEMP_COREi with voltage margin adjustments |
| 1009 | * that need to be applied when the number of cores |
| 1010 | * becomes i. |
| 1011 | */ |
| 1012 | cpr3_write_temp_core_margin(ctrl, |
| 1013 | CPR4_REG_MARGIN_TEMP_CORE( |
| 1014 | sdelta->allow_core_count_adj |
| 1015 | ? i + 1 : max_core_count), |
| 1016 | &sdelta->table[index]); |
| 1017 | } |
| 1018 | } |
| 1019 | |
| 1020 | if (sdelta->allow_boost) { |
| 1021 | /* Program only boost_num_cores row of SDELTA */ |
| 1022 | cpr3_write_temp_core_margin(ctrl, |
| 1023 | CPR4_REG_MARGIN_TEMP_CORE(sdelta->boost_num_cores), |
| 1024 | &sdelta->boost_table[0]); |
| 1025 | } |
| 1026 | |
| 1027 | if (!sdelta->allow_core_count_adj && !sdelta->allow_boost) { |
| 1028 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 1029 | CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, |
| 1030 | max_core_count |
| 1031 | << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); |
| 1032 | } |
| 1033 | |
| 1034 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 1035 | CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK |
| 1036 | | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN |
| 1037 | | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN |
| 1038 | | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN |
| 1039 | | CPR4_MARGIN_ADJ_CTL_BOOST_EN, |
| 1040 | max_core_count << CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT |
| 1041 | | ((sdelta->allow_core_count_adj || sdelta->allow_boost) |
| 1042 | ? CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN : 0) |
| 1043 | | ((sdelta->allow_temp_adj && ctrl->supports_hw_closed_loop) |
| 1044 | ? CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN : 0) |
| 1045 | | (((ctrl->use_hw_closed_loop && !sdelta->allow_boost) |
| 1046 | || !ctrl->supports_hw_closed_loop) |
| 1047 | ? CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN : 0) |
| 1048 | | (sdelta->allow_boost |
| 1049 | ? CPR4_MARGIN_ADJ_CTL_BOOST_EN : 0)); |
| 1050 | |
| 1051 | /* |
| 1052 | * Ensure that all previous CPR register writes have completed before |
| 1053 | * continuing. |
| 1054 | */ |
| 1055 | mb(); |
| 1056 | |
| 1057 | /* Turn off CPR clocks if they were off before this function call. */ |
| 1058 | if (!cpr_enabled) { |
| 1059 | cpr3_clock_disable(ctrl); |
| 1060 | ctrl->cpr_enabled = false; |
| 1061 | } |
| 1062 | |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
| 1066 | /** |
| 1067 | * cpr3_regulator_set_base_target_quot() - configure the target quotient |
| 1068 | * for each RO of the CPR3 regulator for CPRh operation. |
| 1069 | * In particular, the quotient of the RO selected for operation |
| 1070 | * should correspond to the lowest target quotient across the |
| 1071 | * corners supported by the single regulator of the CPR3 thread. |
| 1072 | * @vreg: Pointer to the CPR3 regulator |
| 1073 | * @base_quots: Pointer to the base quotient array. The array must be |
| 1074 | * of size CPR3_RO_COUNT and it is populated with the |
| 1075 | * base quotient per-RO. |
| 1076 | * |
| 1077 | * Return: none |
| 1078 | */ |
| 1079 | static void cpr3_regulator_set_base_target_quot(struct cpr3_regulator *vreg, |
| 1080 | u32 *base_quots) |
| 1081 | { |
| 1082 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 1083 | int i, j, ro_mask = CPR3_RO_MASK; |
| 1084 | u32 min_quot; |
| 1085 | |
| 1086 | for (i = 0; i < vreg->corner_count; i++) |
| 1087 | ro_mask &= vreg->corner[i].ro_mask; |
| 1088 | |
| 1089 | /* Unmask the ROs selected for active use. */ |
| 1090 | cpr3_write(ctrl, CPR3_REG_RO_MASK(vreg->thread->thread_id), |
| 1091 | ro_mask); |
| 1092 | |
| 1093 | for (i = 0; i < CPR3_RO_COUNT; i++) { |
| 1094 | for (j = 0, min_quot = INT_MAX; j < vreg->corner_count; j++) |
| 1095 | if (vreg->corner[j].target_quot[i]) |
| 1096 | min_quot = min(min_quot, |
| 1097 | vreg->corner[j].target_quot[i]); |
| 1098 | |
| 1099 | if (min_quot == INT_MAX) |
| 1100 | min_quot = 0; |
| 1101 | |
| 1102 | cpr3_write(ctrl, |
| 1103 | CPR3_REG_TARGET_QUOT(vreg->thread->thread_id, i), |
| 1104 | min_quot); |
| 1105 | |
| 1106 | base_quots[i] = min_quot; |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | /** |
| 1111 | * cpr3_regulator_init_cprh_corners() - configure the per-corner CPRh registers |
| 1112 | * @vreg: Pointer to the CPR3 regulator |
| 1113 | * |
| 1114 | * This function programs the controller registers which contain all information |
| 1115 | * necessary to resolve the closed-loop voltage per-corner at runtime such as |
| 1116 | * open-loop and floor voltages, target quotient delta, and RO select value. |
| 1117 | * These registers also provide a means to disable closed-loop operation, core |
| 1118 | * and temperature adjustments. |
| 1119 | * |
| 1120 | * Return: 0 on success, errno on failure |
| 1121 | */ |
| 1122 | static int cpr3_regulator_init_cprh_corners(struct cpr3_regulator *vreg) |
| 1123 | { |
| 1124 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 1125 | struct cpr3_corner *corner; |
| 1126 | u32 reg, delta_quot_steps, ro_sel; |
| 1127 | u32 *base_quots; |
| 1128 | int open_loop_volt_steps, floor_volt_steps, i, j, rc = 0; |
| 1129 | |
| 1130 | base_quots = kcalloc(CPR3_RO_COUNT, sizeof(*base_quots), |
| 1131 | GFP_KERNEL); |
| 1132 | if (!base_quots) |
| 1133 | return -ENOMEM; |
| 1134 | |
| 1135 | cpr3_regulator_set_base_target_quot(vreg, base_quots); |
| 1136 | |
| 1137 | for (i = 0; i < vreg->corner_count; i++) { |
| 1138 | corner = &vreg->corner[i]; |
| 1139 | for (j = 0, ro_sel = INT_MAX; j < CPR3_RO_COUNT; j++) { |
| 1140 | if (corner->target_quot[j]) { |
| 1141 | ro_sel = j; |
| 1142 | break; |
| 1143 | } |
| 1144 | } |
| 1145 | |
| 1146 | if (ro_sel == INT_MAX) { |
| 1147 | if (!corner->proc_freq) { |
| 1148 | /* |
| 1149 | * Corner is not used as active DCVS set point |
| 1150 | * select RO 0 arbitrarily. |
| 1151 | */ |
| 1152 | ro_sel = 0; |
David Collins | 044e9e7 | 2017-03-06 16:47:09 -0800 | [diff] [blame] | 1153 | } else if (ctrl->ignore_invalid_fuses) { |
| 1154 | /* |
| 1155 | * Fuses are not initialized on some simulator |
| 1156 | * targets. Select RO 0 arbitrarily. |
| 1157 | */ |
| 1158 | cpr3_debug(vreg, "ignored that corner=%d has invalid RO select value\n", |
| 1159 | i); |
| 1160 | ro_sel = 0; |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1161 | } else { |
| 1162 | cpr3_err(vreg, "corner=%d has invalid RO select value\n", |
| 1163 | i); |
| 1164 | rc = -EINVAL; |
| 1165 | goto free_base_quots; |
| 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | open_loop_volt_steps = DIV_ROUND_UP(corner->open_loop_volt - |
| 1170 | ctrl->base_volt, |
| 1171 | ctrl->step_volt); |
| 1172 | floor_volt_steps = DIV_ROUND_UP(corner->floor_volt - |
| 1173 | ctrl->base_volt, |
| 1174 | ctrl->step_volt); |
| 1175 | delta_quot_steps = corner->proc_freq ? |
| 1176 | DIV_ROUND_UP(corner->target_quot[ro_sel] - |
| 1177 | base_quots[ro_sel], |
| 1178 | CPRH_DELTA_QUOT_STEP_FACTOR) : |
| 1179 | 0; |
| 1180 | |
| 1181 | if (open_loop_volt_steps > CPRH_CORNER_INIT_VOLTAGE_MAX_VALUE || |
| 1182 | floor_volt_steps > CPRH_CORNER_FLOOR_VOLTAGE_MAX_VALUE || |
| 1183 | delta_quot_steps > CPRH_CORNER_QUOT_DELTA_MAX_VALUE) { |
| 1184 | cpr3_err(ctrl, "invalid CPRh corner configuration: open_loop_volt_steps=%d (%d max.), floor_volt_steps=%d (%d max), delta_quot_steps=%d (%d max)\n", |
| 1185 | open_loop_volt_steps, |
| 1186 | CPRH_CORNER_INIT_VOLTAGE_MAX_VALUE, |
| 1187 | floor_volt_steps, |
| 1188 | CPRH_CORNER_FLOOR_VOLTAGE_MAX_VALUE, |
| 1189 | delta_quot_steps, |
| 1190 | CPRH_CORNER_QUOT_DELTA_MAX_VALUE); |
| 1191 | rc = -EINVAL; |
| 1192 | goto free_base_quots; |
| 1193 | } |
| 1194 | |
| 1195 | reg = (open_loop_volt_steps << CPRH_CORNER_INIT_VOLTAGE_SHIFT) |
| 1196 | & CPRH_CORNER_INIT_VOLTAGE_MASK; |
| 1197 | reg |= (floor_volt_steps << CPRH_CORNER_FLOOR_VOLTAGE_SHIFT) |
| 1198 | & CPRH_CORNER_FLOOR_VOLTAGE_MASK; |
| 1199 | reg |= (delta_quot_steps << CPRH_CORNER_QUOT_DELTA_SHIFT) |
| 1200 | & CPRH_CORNER_QUOT_DELTA_MASK; |
| 1201 | reg |= (ro_sel << CPRH_CORNER_RO_SEL_SHIFT) |
| 1202 | & CPRH_CORNER_RO_SEL_MASK; |
| 1203 | |
| 1204 | if (corner->use_open_loop) |
| 1205 | reg |= CPRH_CORNER_CPR_CL_DISABLE; |
| 1206 | |
| 1207 | cpr3_debug(ctrl, "corner=%d open_loop_volt_steps=%d, floor_volt_steps=%d, delta_quot_steps=%d, base_volt=%d, step_volt=%d, base_quot=%d\n", |
| 1208 | i, open_loop_volt_steps, floor_volt_steps, |
| 1209 | delta_quot_steps, ctrl->base_volt, |
| 1210 | ctrl->step_volt, base_quots[ro_sel]); |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1211 | cpr3_write(ctrl, CPRH_REG_CORNER(vreg->thread, i), reg); |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1212 | } |
| 1213 | |
| 1214 | free_base_quots: |
| 1215 | kfree(base_quots); |
| 1216 | return rc; |
| 1217 | } |
| 1218 | |
| 1219 | /** |
| 1220 | * cprh_controller_program_sdelta() - programs hardware SDELTA registers with |
| 1221 | * the margins that need to be applied at different online |
| 1222 | * core-count and temperature bands for each corner band. Also, |
| 1223 | * programs hardware register configuration for core-count and |
| 1224 | * temp-based adjustments |
| 1225 | * |
| 1226 | * @ctrl: Pointer to the CPR3 controller |
| 1227 | * |
| 1228 | * CPR interface/bus clocks must be enabled before calling this function. |
| 1229 | * |
| 1230 | * Return: none |
| 1231 | */ |
| 1232 | static void cprh_controller_program_sdelta( |
| 1233 | struct cpr3_controller *ctrl) |
| 1234 | { |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1235 | /* Only thread 0 supports sdelta */ |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1236 | struct cpr3_regulator *vreg = &ctrl->thread[0].vreg[0]; |
| 1237 | struct cprh_corner_band *corner_band; |
| 1238 | struct cpr4_sdelta *sdelta; |
| 1239 | int i, j, index; |
| 1240 | u32 reg = 0; |
| 1241 | |
| 1242 | if (!vreg->allow_core_count_adj && !vreg->allow_temp_adj) |
| 1243 | return; |
| 1244 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1245 | if (vreg->thread->thread_id != 0) { |
| 1246 | cpr3_err(vreg, "core count and temperature based adjustments are only allowed for CPR thread 0\n"); |
| 1247 | return; |
| 1248 | } |
| 1249 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1250 | cpr4_regulator_init_temp_points(ctrl); |
| 1251 | |
| 1252 | for (i = 0; i < CPRH_CORNER_BAND_MAX_COUNT; i++) { |
| 1253 | reg |= (i < vreg->corner_band_count ? |
| 1254 | vreg->corner_band[i].corner |
| 1255 | & CPRH_CORNER_BAND_MASK : |
| 1256 | vreg->corner_count + 1) |
| 1257 | << (i * CPRH_CORNER_BAND_SHIFT); |
| 1258 | } |
| 1259 | |
| 1260 | cpr3_write(ctrl, CPRH_REG_CORNER_BAND, reg); |
| 1261 | |
| 1262 | for (i = 0; i < vreg->corner_band_count; i++) { |
| 1263 | corner_band = &vreg->corner_band[i]; |
| 1264 | sdelta = corner_band->sdelta; |
| 1265 | |
| 1266 | if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj) { |
| 1267 | /* |
| 1268 | * Per-online-core and per-temperature margin |
| 1269 | * adjustments are disabled for this corner band. |
| 1270 | */ |
| 1271 | continue; |
| 1272 | } |
| 1273 | |
| 1274 | if (vreg->allow_core_count_adj) |
| 1275 | cpr3_write_temp_core_margin(ctrl, |
| 1276 | CPRH_MARGIN_TEMP_CORE_VBAND(0, i), |
| 1277 | &sdelta->table[0]); |
| 1278 | |
| 1279 | for (j = 0; j < sdelta->max_core_count; j++) { |
| 1280 | index = j * sdelta->temp_band_count; |
| 1281 | |
| 1282 | cpr3_write_temp_core_margin(ctrl, |
| 1283 | CPRH_MARGIN_TEMP_CORE_VBAND( |
| 1284 | sdelta->allow_core_count_adj |
| 1285 | ? j + 1 : vreg->max_core_count, i), |
| 1286 | &sdelta->table[index]); |
| 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | if (!vreg->allow_core_count_adj) { |
| 1291 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 1292 | CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK, |
| 1293 | vreg->max_core_count |
| 1294 | << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT); |
| 1295 | } |
| 1296 | |
| 1297 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 1298 | CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK |
| 1299 | | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN |
| 1300 | | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN |
| 1301 | | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN |
| 1302 | | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 1303 | vreg->max_core_count << CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT |
| 1304 | | ((vreg->allow_core_count_adj) |
| 1305 | ? CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN : 0) |
| 1306 | | (vreg->allow_temp_adj ? CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN : 0) |
| 1307 | | ((ctrl->use_hw_closed_loop) |
| 1308 | ? CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN : 0) |
| 1309 | | (ctrl->use_hw_closed_loop |
| 1310 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE : 0)); |
| 1311 | |
| 1312 | /* Ensure that previous CPR register writes complete */ |
| 1313 | mb(); |
| 1314 | } |
| 1315 | |
| 1316 | static int cprh_regulator_aging_adjust(struct cpr3_controller *ctrl); |
| 1317 | |
| 1318 | /** |
David Collins | ee80499 | 2017-07-21 15:20:19 -0700 | [diff] [blame] | 1319 | * cpr3_regulator_cprh_initialized() - checks if CPRh has already been |
| 1320 | * initialized by the boot loader |
| 1321 | * @ctrl: Pointer to the CPR3 controller |
| 1322 | * |
| 1323 | * Return: true if CPRh controller is already initialized else false |
| 1324 | */ |
| 1325 | static bool cpr3_regulator_cprh_initialized(struct cpr3_controller *ctrl) |
| 1326 | { |
| 1327 | u32 reg; |
| 1328 | |
| 1329 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) |
| 1330 | return false; |
| 1331 | |
| 1332 | ctrl->cpr_hw_version = readl_relaxed(ctrl->cpr_ctrl_base |
| 1333 | + CPR3_REG_CPR_VERSION); |
| 1334 | reg = readl_relaxed(ctrl->cpr_ctrl_base + CPRH_REG_CTL(ctrl)); |
| 1335 | |
| 1336 | return reg & CPRH_CTL_OSM_ENABLED; |
| 1337 | } |
| 1338 | |
| 1339 | /** |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1340 | * cpr3_regulator_init_cprh() - performs hardware initialization at the |
| 1341 | * controller and thread level required for CPRh operation. |
| 1342 | * @ctrl: Pointer to the CPR3 controller |
| 1343 | * |
| 1344 | * CPR interface/bus clocks must be enabled before calling this function. |
| 1345 | * |
| 1346 | * Return: 0 on success, errno on failure |
| 1347 | */ |
| 1348 | static int cpr3_regulator_init_cprh(struct cpr3_controller *ctrl) |
| 1349 | { |
| 1350 | u32 reg, pmic_step_size = 1; |
| 1351 | u64 temp; |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1352 | int i, rc; |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1353 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1354 | /* One or two threads each with a single regulator supported */ |
| 1355 | if (ctrl->thread_count < 1 || ctrl->thread_count > 2) { |
| 1356 | cpr3_err(ctrl, "expected 1 or 2 threads but found %d\n", |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1357 | ctrl->thread_count); |
| 1358 | return -EINVAL; |
| 1359 | } else if (ctrl->thread[0].vreg_count != 1) { |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1360 | cpr3_err(ctrl, "expected 1 regulator for thread 0 but found %d\n", |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1361 | ctrl->thread[0].vreg_count); |
| 1362 | return -EINVAL; |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1363 | } else if (ctrl->thread_count == 2 && ctrl->thread[1].vreg_count != 1) { |
| 1364 | cpr3_err(ctrl, "expected 1 regulator for thread 1 but found %d\n", |
| 1365 | ctrl->thread[1].vreg_count); |
| 1366 | return -EINVAL; |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1367 | } |
| 1368 | |
| 1369 | rc = cprh_regulator_aging_adjust(ctrl); |
| 1370 | if (rc && rc != -ETIMEDOUT) { |
| 1371 | /* |
| 1372 | * Don't fail initialization if the CPR aging measurement |
| 1373 | * timed out due to sensors not being available. |
| 1374 | */ |
| 1375 | cpr3_err(ctrl, "CPR aging adjustment failed, rc=%d\n", rc); |
| 1376 | return rc; |
| 1377 | } |
| 1378 | |
| 1379 | cprh_controller_program_sdelta(ctrl); |
| 1380 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1381 | for (i = 0; i < ctrl->thread_count; i++) { |
| 1382 | rc = cpr3_regulator_init_cprh_corners(&ctrl->thread[i].vreg[0]); |
| 1383 | if (rc) { |
| 1384 | cpr3_err(ctrl, "failed to initialize CPRh corner registers\n"); |
| 1385 | return rc; |
| 1386 | } |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1387 | } |
| 1388 | |
Tirupathi Reddy | 718bc80 | 2017-02-09 16:29:24 +0530 | [diff] [blame] | 1389 | if (ctrl->reset_step_quot_loop_en) |
| 1390 | cpr3_masked_write(ctrl, CPR4_REG_MISC, |
| 1391 | CPR4_MISC_RESET_STEP_QUOT_LOOP_EN, |
| 1392 | CPR4_MISC_RESET_STEP_QUOT_LOOP_EN); |
| 1393 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1394 | if (ctrl->saw_use_unit_mV) |
| 1395 | pmic_step_size = ctrl->step_volt / 1000; |
| 1396 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 1397 | CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK, |
| 1398 | (pmic_step_size |
| 1399 | << CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT)); |
| 1400 | |
| 1401 | cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, |
| 1402 | CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK, |
| 1403 | (ctrl->down_error_step_limit |
| 1404 | << CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT)); |
| 1405 | |
| 1406 | cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT, |
| 1407 | CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK, |
| 1408 | (ctrl->up_error_step_limit |
| 1409 | << CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT)); |
| 1410 | |
| 1411 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 1412 | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK, |
| 1413 | ctrl->step_quot_fixed |
| 1414 | << CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT); |
| 1415 | |
| 1416 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 1417 | CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN, |
| 1418 | (ctrl->use_dynamic_step_quot |
| 1419 | ? CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN : 0)); |
| 1420 | |
David Collins | 0819398 | 2017-04-19 14:00:12 -0700 | [diff] [blame] | 1421 | if (ctrl->thread_count > 1) |
| 1422 | cpr3_masked_write(ctrl, CPR4_REG_CPR_TIMER_CLAMP, |
| 1423 | CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN, |
| 1424 | CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN); |
| 1425 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1426 | if (ctrl->voltage_settling_time) { |
| 1427 | /* |
| 1428 | * Configure the settling timer used to account for |
| 1429 | * one VDD supply step. |
| 1430 | */ |
| 1431 | temp = (u64)ctrl->cpr_clock_rate |
| 1432 | * (u64)ctrl->voltage_settling_time; |
| 1433 | do_div(temp, 1000000000); |
| 1434 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE_TIMERS, |
| 1435 | CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK, |
| 1436 | temp |
| 1437 | << CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT); |
| 1438 | } |
| 1439 | |
| 1440 | if (ctrl->corner_switch_delay_time) { |
| 1441 | /* |
| 1442 | * Configure the settling timer used to delay |
| 1443 | * following SAW requests |
| 1444 | */ |
| 1445 | temp = (u64)ctrl->cpr_clock_rate |
| 1446 | * (u64)ctrl->corner_switch_delay_time; |
| 1447 | do_div(temp, 1000000000); |
| 1448 | do_div(temp, CPRH_MODE_SWITCH_DELAY_FACTOR); |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1449 | cpr3_masked_write(ctrl, CPRH_REG_CTL(ctrl), |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1450 | CPRH_CTL_MODE_SWITCH_DELAY_MASK, |
| 1451 | temp << CPRH_CTL_MODE_SWITCH_DELAY_SHIFT); |
| 1452 | } |
| 1453 | |
| 1454 | /* |
Osvaldo Banuelos | d688dded | 2017-03-22 13:35:46 -0700 | [diff] [blame] | 1455 | * Configure CPRh ACD AVG registers on controllers |
| 1456 | * that support this feature. |
| 1457 | */ |
| 1458 | if (ctrl->cpr_hw_version >= CPRH_CPR_VERSION_4P5 |
| 1459 | && ctrl->acd_avg_enabled) { |
| 1460 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
| 1461 | CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_MASK, |
| 1462 | ctrl->acd_adj_up_step_limit << |
| 1463 | CPRH_MISC_REG2_ACD_ADJ_STEP_UP_LIMIT_SHIFT); |
| 1464 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
| 1465 | CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_MASK, |
| 1466 | ctrl->acd_adj_down_step_limit << |
| 1467 | CPRH_MISC_REG2_ACD_ADJ_STEP_DOWN_LIMIT_SHIFT); |
| 1468 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
| 1469 | CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_MASK, |
| 1470 | ctrl->acd_adj_up_step_size << |
| 1471 | CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_UP_SHIFT); |
| 1472 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
| 1473 | CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_MASK, |
| 1474 | ctrl->acd_adj_down_step_size << |
| 1475 | CPRH_MISC_REG2_ACD_ADJ_STEP_SIZE_DOWN_SHIFT); |
| 1476 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
Osvaldo Banuelos | 3bdabd0 | 2017-03-22 13:39:39 -0700 | [diff] [blame] | 1477 | CPRH_MISC_REG2_ACD_NOTWAIT_4_CL_SETTLE_MASK, |
| 1478 | (ctrl->acd_notwait_for_cl_settled |
| 1479 | ? CPRH_MISC_REG2_ACD_NOTWAIT_4_CL_SETTLE_EN |
| 1480 | : 0)); |
| 1481 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
| 1482 | CPRH_MISC_REG2_ACD_AVG_FAST_UPDATE_EN_MASK, |
| 1483 | (ctrl->acd_adj_avg_fast_update |
| 1484 | ? CPRH_MISC_REG2_ACD_AVG_FAST_UPDATE_EN |
| 1485 | : 0)); |
| 1486 | cpr3_masked_write(ctrl, CPRH_REG_MISC_REG2, |
Osvaldo Banuelos | d688dded | 2017-03-22 13:35:46 -0700 | [diff] [blame] | 1487 | CPRH_MISC_REG2_ACD_AVG_EN_MASK, |
| 1488 | CPRH_MISC_REG2_ACD_AVG_ENABLE); |
| 1489 | } |
| 1490 | |
| 1491 | /* |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1492 | * Program base voltage and voltage multiplier values which |
| 1493 | * are used for floor and initial voltage calculations by the |
| 1494 | * CPRh controller. |
| 1495 | */ |
| 1496 | reg = (DIV_ROUND_UP(ctrl->base_volt, ctrl->step_volt) |
| 1497 | << CPRH_CTL_BASE_VOLTAGE_SHIFT) |
| 1498 | & CPRH_CTL_BASE_VOLTAGE_MASK; |
| 1499 | reg |= (DIV_ROUND_UP(ctrl->step_volt, 1000) |
| 1500 | << CPRH_CTL_VOLTAGE_MULTIPLIER_SHIFT) |
| 1501 | & CPRH_CTL_VOLTAGE_MULTIPLIER_MASK; |
| 1502 | /* Enable OSM block interface with CPR */ |
| 1503 | reg |= CPRH_CTL_OSM_ENABLED; |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1504 | cpr3_masked_write(ctrl, CPRH_REG_CTL(ctrl), CPRH_CTL_BASE_VOLTAGE_MASK |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1505 | | CPRH_CTL_VOLTAGE_MULTIPLIER_MASK |
| 1506 | | CPRH_CTL_OSM_ENABLED, reg); |
| 1507 | |
| 1508 | /* Enable loop_en */ |
| 1509 | cpr3_ctrl_loop_enable(ctrl); |
| 1510 | |
| 1511 | return 0; |
| 1512 | } |
| 1513 | |
| 1514 | /** |
| 1515 | * cpr3_regulator_init_ctrl() - performs hardware initialization of CPR |
| 1516 | * controller registers |
| 1517 | * @ctrl: Pointer to the CPR3 controller |
| 1518 | * |
| 1519 | * Return: 0 on success, errno on failure |
| 1520 | */ |
| 1521 | static int cpr3_regulator_init_ctrl(struct cpr3_controller *ctrl) |
| 1522 | { |
| 1523 | int i, j, k, m, rc; |
| 1524 | u32 ro_used = 0; |
| 1525 | u32 gcnt, cont_dly, up_down_dly, val; |
| 1526 | u64 temp; |
| 1527 | char *mode; |
| 1528 | |
| 1529 | if (ctrl->core_clk) { |
| 1530 | rc = clk_set_rate(ctrl->core_clk, ctrl->cpr_clock_rate); |
| 1531 | if (rc) { |
| 1532 | cpr3_err(ctrl, "clk_set_rate(core_clk, %u) failed, rc=%d\n", |
| 1533 | ctrl->cpr_clock_rate, rc); |
| 1534 | return rc; |
| 1535 | } |
| 1536 | } |
| 1537 | |
| 1538 | rc = cpr3_clock_enable(ctrl); |
| 1539 | if (rc) { |
| 1540 | cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); |
| 1541 | return rc; |
| 1542 | } |
| 1543 | ctrl->cpr_enabled = true; |
| 1544 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1545 | ctrl->cpr_hw_version = cpr3_read(ctrl, CPR3_REG_CPR_VERSION); |
| 1546 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1547 | /* Find all RO's used by any corner of any regulator. */ |
| 1548 | for (i = 0; i < ctrl->thread_count; i++) |
| 1549 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) |
| 1550 | for (k = 0; k < ctrl->thread[i].vreg[j].corner_count; |
| 1551 | k++) |
| 1552 | for (m = 0; m < CPR3_RO_COUNT; m++) |
| 1553 | if (ctrl->thread[i].vreg[j].corner[k]. |
| 1554 | target_quot[m]) |
| 1555 | ro_used |= BIT(m); |
| 1556 | |
| 1557 | /* Configure the GCNT of the RO's that will be used */ |
| 1558 | gcnt = cpr3_regulator_get_gcnt(ctrl); |
| 1559 | for (i = 0; i < CPR3_RO_COUNT; i++) |
| 1560 | if (ro_used & BIT(i)) |
| 1561 | cpr3_write(ctrl, CPR3_REG_GCNT(i), gcnt); |
| 1562 | |
| 1563 | /* Configure the loop delay time */ |
| 1564 | temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->loop_time; |
| 1565 | do_div(temp, 1000000000); |
| 1566 | cont_dly = temp; |
| 1567 | if (ctrl->supports_hw_closed_loop |
| 1568 | && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) |
| 1569 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly); |
| 1570 | else |
| 1571 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, cont_dly); |
| 1572 | |
| 1573 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 1574 | temp = (u64)ctrl->cpr_clock_rate * |
| 1575 | (u64)ctrl->up_down_delay_time; |
| 1576 | do_div(temp, 1000000000); |
| 1577 | up_down_dly = temp; |
| 1578 | if (ctrl->supports_hw_closed_loop) |
| 1579 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, |
| 1580 | up_down_dly); |
| 1581 | cpr3_debug(ctrl, "up_down_dly=%u, up_down_delay_time=%u ns\n", |
| 1582 | up_down_dly, ctrl->up_down_delay_time); |
| 1583 | } |
| 1584 | |
| 1585 | cpr3_debug(ctrl, "cpr_clock_rate=%u HZ, sensor_time=%u ns, loop_time=%u ns, gcnt=%u, cont_dly=%u\n", |
| 1586 | ctrl->cpr_clock_rate, ctrl->sensor_time, ctrl->loop_time, |
| 1587 | gcnt, cont_dly); |
| 1588 | |
| 1589 | /* Configure CPR sensor operation */ |
| 1590 | val = (ctrl->idle_clocks << CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT) |
| 1591 | & CPR3_CPR_CTL_IDLE_CLOCKS_MASK; |
| 1592 | val |= (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT) |
| 1593 | & CPR3_CPR_CTL_COUNT_MODE_MASK; |
| 1594 | val |= (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT) |
| 1595 | & CPR3_CPR_CTL_COUNT_REPEAT_MASK; |
| 1596 | cpr3_write(ctrl, CPR3_REG_CPR_CTL, val); |
| 1597 | |
| 1598 | cpr3_debug(ctrl, "idle_clocks=%u, count_mode=%u, count_repeat=%u; CPR_CTL=0x%08X\n", |
| 1599 | ctrl->idle_clocks, ctrl->count_mode, ctrl->count_repeat, val); |
| 1600 | |
| 1601 | /* Configure CPR default step quotients */ |
| 1602 | val = (ctrl->step_quot_init_min << CPR3_CPR_STEP_QUOT_MIN_SHIFT) |
| 1603 | & CPR3_CPR_STEP_QUOT_MIN_MASK; |
| 1604 | val |= (ctrl->step_quot_init_max << CPR3_CPR_STEP_QUOT_MAX_SHIFT) |
| 1605 | & CPR3_CPR_STEP_QUOT_MAX_MASK; |
| 1606 | cpr3_write(ctrl, CPR3_REG_CPR_STEP_QUOT, val); |
| 1607 | |
| 1608 | cpr3_debug(ctrl, "step_quot_min=%u, step_quot_max=%u; STEP_QUOT=0x%08X\n", |
| 1609 | ctrl->step_quot_init_min, ctrl->step_quot_init_max, val); |
| 1610 | |
| 1611 | /* Configure the CPR sensor ownership */ |
| 1612 | for (i = 0; i < ctrl->sensor_count; i++) |
| 1613 | cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(i), |
| 1614 | ctrl->sensor_owner[i]); |
| 1615 | |
| 1616 | /* Configure per-thread registers */ |
| 1617 | for (i = 0; i < ctrl->thread_count; i++) { |
| 1618 | rc = cpr3_regulator_init_thread(&ctrl->thread[i]); |
| 1619 | if (rc) { |
| 1620 | cpr3_err(ctrl, "CPR thread register initialization failed, rc=%d\n", |
| 1621 | rc); |
| 1622 | return rc; |
| 1623 | } |
| 1624 | } |
| 1625 | |
| 1626 | if (ctrl->supports_hw_closed_loop) { |
| 1627 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 || |
| 1628 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 1629 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 1630 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 1631 | ctrl->use_hw_closed_loop |
| 1632 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE |
| 1633 | : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); |
| 1634 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 1635 | cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, |
| 1636 | ctrl->use_hw_closed_loop |
| 1637 | ? CPR3_HW_CLOSED_LOOP_ENABLE |
| 1638 | : CPR3_HW_CLOSED_LOOP_DISABLE); |
| 1639 | |
| 1640 | cpr3_debug(ctrl, "PD_THROTTLE=0x%08X\n", |
| 1641 | ctrl->proc_clock_throttle); |
| 1642 | } |
| 1643 | |
| 1644 | if ((ctrl->use_hw_closed_loop || |
| 1645 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) && |
| 1646 | ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 1647 | rc = regulator_enable(ctrl->vdd_limit_regulator); |
| 1648 | if (rc) { |
| 1649 | cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n", |
| 1650 | rc); |
| 1651 | return rc; |
| 1652 | } |
| 1653 | |
| 1654 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 1655 | rc = msm_spm_avs_enable_irq(0, |
| 1656 | MSM_SPM_AVS_IRQ_MAX); |
| 1657 | if (rc) { |
| 1658 | cpr3_err(ctrl, "could not enable max IRQ, rc=%d\n", |
| 1659 | rc); |
| 1660 | return rc; |
| 1661 | } |
| 1662 | } |
| 1663 | } |
| 1664 | } |
| 1665 | |
| 1666 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 1667 | rc = cpr3_regulator_init_cpr4(ctrl); |
| 1668 | if (rc) { |
| 1669 | cpr3_err(ctrl, "CPR4-specific controller initialization failed, rc=%d\n", |
| 1670 | rc); |
| 1671 | return rc; |
| 1672 | } |
| 1673 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 1674 | rc = cpr3_regulator_init_cprh(ctrl); |
| 1675 | if (rc) { |
| 1676 | cpr3_err(ctrl, "CPRh-specific controller initialization failed, rc=%d\n", |
| 1677 | rc); |
| 1678 | return rc; |
| 1679 | } |
| 1680 | } |
| 1681 | |
| 1682 | /* Ensure that all register writes complete before disabling clocks. */ |
| 1683 | wmb(); |
| 1684 | |
| 1685 | /* Keep CPR clocks on for CPRh full HW closed-loop operation */ |
| 1686 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 1687 | cpr3_clock_disable(ctrl); |
| 1688 | ctrl->cpr_enabled = false; |
| 1689 | } |
| 1690 | |
| 1691 | if (!ctrl->cpr_allowed_sw || !ctrl->cpr_allowed_hw) |
| 1692 | mode = "open-loop"; |
| 1693 | else if (ctrl->supports_hw_closed_loop && |
| 1694 | ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) |
| 1695 | mode = ctrl->use_hw_closed_loop |
| 1696 | ? "HW closed-loop" : "SW closed-loop"; |
| 1697 | else if (ctrl->supports_hw_closed_loop && |
| 1698 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) |
| 1699 | mode = ctrl->use_hw_closed_loop |
| 1700 | ? "full HW closed-loop" : "open-loop"; |
| 1701 | else |
| 1702 | mode = "closed-loop"; |
| 1703 | |
| 1704 | cpr3_info(ctrl, "Default CPR mode = %s", mode); |
| 1705 | |
| 1706 | return 0; |
| 1707 | } |
| 1708 | |
| 1709 | /** |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 1710 | * cpr3_regulator_init_hw_closed_loop_dependencies() - perform hardware |
| 1711 | * initialization steps to ensure that CPR HW closed-loop voltage |
| 1712 | * change requests are able to reach the PMIC regulator |
| 1713 | * @pdev: Platform device pointer for the CPR3 controller |
| 1714 | * @ctrl: Pointer to the CPR3 controller |
| 1715 | * |
| 1716 | * Return: 0 on success, errno on failure |
| 1717 | */ |
| 1718 | static int |
| 1719 | cpr3_regulator_init_hw_closed_loop_dependencies(struct platform_device *pdev, |
| 1720 | struct cpr3_controller *ctrl) |
| 1721 | { |
| 1722 | struct resource *res; |
| 1723 | int rc = 0; |
| 1724 | u32 val; |
| 1725 | |
| 1726 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "saw"); |
| 1727 | if (res && res->start) |
| 1728 | ctrl->saw_base = devm_ioremap(&pdev->dev, res->start, |
| 1729 | resource_size(res)); |
| 1730 | |
| 1731 | if (ctrl->saw_base) { |
| 1732 | /* Configure SAW registers directly. */ |
| 1733 | rc = of_property_read_u32(ctrl->dev->of_node, |
| 1734 | "qcom,saw-avs-ctrl", &val); |
| 1735 | if (rc) { |
| 1736 | cpr3_err(ctrl, "unable to read DT property qcom,saw-avs-ctrl, rc=%d\n", |
| 1737 | rc); |
| 1738 | return rc; |
| 1739 | } |
| 1740 | writel_relaxed(val, ctrl->saw_base + SAW_REG_AVS_CTL); |
| 1741 | |
| 1742 | rc = of_property_read_u32(ctrl->dev->of_node, |
| 1743 | "qcom,saw-avs-limit", &val); |
| 1744 | if (rc) { |
| 1745 | cpr3_err(ctrl, "unable to read DT property qcom,saw-avs-limit, rc=%d\n", |
| 1746 | rc); |
| 1747 | return rc; |
| 1748 | } |
| 1749 | writel_relaxed(val, ctrl->saw_base + SAW_REG_AVS_LIMIT); |
| 1750 | } else { |
| 1751 | /* Wait for SPM driver to configure SAW registers. */ |
| 1752 | rc = msm_spm_probe_done(); |
| 1753 | if (rc) { |
| 1754 | if (rc != -EPROBE_DEFER) |
| 1755 | cpr3_err(ctrl, "spm unavailable, rc=%d\n", rc); |
| 1756 | return rc; |
| 1757 | } |
| 1758 | } |
| 1759 | |
| 1760 | return 0; |
| 1761 | } |
| 1762 | |
| 1763 | /** |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 1764 | * cpr3_regulator_set_target_quot() - configure the target quotient for each |
| 1765 | * RO of the CPR3 thread and set the RO mask |
| 1766 | * @thread: Pointer to the CPR3 thread |
| 1767 | * |
| 1768 | * Return: none |
| 1769 | */ |
| 1770 | static void cpr3_regulator_set_target_quot(struct cpr3_thread *thread) |
| 1771 | { |
| 1772 | u32 new_quot, last_quot; |
| 1773 | int i; |
| 1774 | |
| 1775 | if (thread->aggr_corner.ro_mask == CPR3_RO_MASK |
| 1776 | && thread->last_closed_loop_aggr_corner.ro_mask == CPR3_RO_MASK) { |
| 1777 | /* Avoid writing target quotients since all RO's are masked. */ |
| 1778 | return; |
| 1779 | } else if (thread->aggr_corner.ro_mask == CPR3_RO_MASK) { |
| 1780 | cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), |
| 1781 | CPR3_RO_MASK); |
| 1782 | thread->last_closed_loop_aggr_corner.ro_mask = CPR3_RO_MASK; |
| 1783 | /* |
| 1784 | * Only the RO_MASK register needs to be written since all |
| 1785 | * RO's are masked. |
| 1786 | */ |
| 1787 | return; |
| 1788 | } else if (thread->aggr_corner.ro_mask |
| 1789 | != thread->last_closed_loop_aggr_corner.ro_mask) { |
| 1790 | cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id), |
| 1791 | thread->aggr_corner.ro_mask); |
| 1792 | } |
| 1793 | |
| 1794 | for (i = 0; i < CPR3_RO_COUNT; i++) { |
| 1795 | new_quot = thread->aggr_corner.target_quot[i]; |
| 1796 | last_quot = thread->last_closed_loop_aggr_corner.target_quot[i]; |
| 1797 | if (new_quot != last_quot) |
| 1798 | cpr3_write(thread->ctrl, |
| 1799 | CPR3_REG_TARGET_QUOT(thread->thread_id, i), |
| 1800 | new_quot); |
| 1801 | } |
| 1802 | |
| 1803 | thread->last_closed_loop_aggr_corner = thread->aggr_corner; |
| 1804 | } |
| 1805 | |
| 1806 | /** |
| 1807 | * cpr3_update_vreg_closed_loop_volt() - update the last known settled |
| 1808 | * closed loop voltage for a CPR3 regulator |
| 1809 | * @vreg: Pointer to the CPR3 regulator |
| 1810 | * @vdd_volt: Last known settled voltage in microvolts for the |
| 1811 | * VDD supply |
| 1812 | * @reg_last_measurement: Value read from the LAST_MEASUREMENT register |
| 1813 | * |
| 1814 | * Return: none |
| 1815 | */ |
| 1816 | static void cpr3_update_vreg_closed_loop_volt(struct cpr3_regulator *vreg, |
| 1817 | int vdd_volt, u32 reg_last_measurement) |
| 1818 | { |
| 1819 | bool step_dn, step_up, aggr_step_up, aggr_step_dn, aggr_step_mid; |
| 1820 | bool valid, pd_valid, saw_error; |
| 1821 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 1822 | struct cpr3_corner *corner; |
| 1823 | u32 id; |
| 1824 | |
| 1825 | if (vreg->last_closed_loop_corner == CPR3_REGULATOR_CORNER_INVALID) |
| 1826 | return; |
| 1827 | |
| 1828 | corner = &vreg->corner[vreg->last_closed_loop_corner]; |
| 1829 | |
| 1830 | if (vreg->thread->last_closed_loop_aggr_corner.ro_mask |
| 1831 | == CPR3_RO_MASK || !vreg->aggregated) { |
| 1832 | return; |
| 1833 | } else if (!ctrl->cpr_enabled || !ctrl->last_corner_was_closed_loop) { |
| 1834 | return; |
| 1835 | } else if (ctrl->thread_count == 1 |
| 1836 | && vdd_volt >= corner->floor_volt |
| 1837 | && vdd_volt <= corner->ceiling_volt) { |
| 1838 | corner->last_volt = vdd_volt; |
| 1839 | cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n", |
| 1840 | vreg->last_closed_loop_corner, corner->last_volt, |
| 1841 | vreg->last_closed_loop_corner, |
| 1842 | corner->ceiling_volt, |
| 1843 | vreg->last_closed_loop_corner, |
| 1844 | corner->floor_volt); |
| 1845 | return; |
| 1846 | } else if (!ctrl->supports_hw_closed_loop) { |
| 1847 | return; |
| 1848 | } else if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPR3) { |
| 1849 | corner->last_volt = vdd_volt; |
| 1850 | cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n", |
| 1851 | vreg->last_closed_loop_corner, corner->last_volt, |
| 1852 | vreg->last_closed_loop_corner, |
| 1853 | corner->ceiling_volt, |
| 1854 | vreg->last_closed_loop_corner, |
| 1855 | corner->floor_volt); |
| 1856 | return; |
| 1857 | } |
| 1858 | |
| 1859 | /* CPR clocks are on and HW closed loop is supported */ |
| 1860 | valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID); |
| 1861 | if (!valid) { |
| 1862 | cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X valid bit not set\n", |
| 1863 | reg_last_measurement); |
| 1864 | return; |
| 1865 | } |
| 1866 | |
| 1867 | id = vreg->thread->thread_id; |
| 1868 | |
| 1869 | step_dn |
| 1870 | = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_DN(id)); |
| 1871 | step_up |
| 1872 | = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_UP(id)); |
| 1873 | aggr_step_dn = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_DN); |
| 1874 | aggr_step_mid |
| 1875 | = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_MID); |
| 1876 | aggr_step_up = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_UP); |
| 1877 | saw_error = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_SAW_ERROR); |
| 1878 | pd_valid |
| 1879 | = !((((reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK) |
| 1880 | >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT) |
| 1881 | & vreg->pd_bypass_mask) == vreg->pd_bypass_mask); |
| 1882 | |
| 1883 | if (!pd_valid) { |
| 1884 | cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X, all power domains bypassed\n", |
| 1885 | reg_last_measurement); |
| 1886 | return; |
| 1887 | } else if (step_dn && step_up) { |
| 1888 | cpr3_err(vreg, "both up and down status bits set, CPR_LAST_VALID_MEASUREMENT=0x%X\n", |
| 1889 | reg_last_measurement); |
| 1890 | return; |
| 1891 | } else if (aggr_step_dn && step_dn && vdd_volt < corner->last_volt |
| 1892 | && vdd_volt >= corner->floor_volt) { |
| 1893 | corner->last_volt = vdd_volt; |
| 1894 | } else if (aggr_step_up && step_up && vdd_volt > corner->last_volt |
| 1895 | && vdd_volt <= corner->ceiling_volt) { |
| 1896 | corner->last_volt = vdd_volt; |
| 1897 | } else if (aggr_step_mid |
| 1898 | && vdd_volt >= corner->floor_volt |
| 1899 | && vdd_volt <= corner->ceiling_volt) { |
| 1900 | corner->last_volt = vdd_volt; |
| 1901 | } else if (saw_error && (vdd_volt == corner->ceiling_volt |
| 1902 | || vdd_volt == corner->floor_volt)) { |
| 1903 | corner->last_volt = vdd_volt; |
| 1904 | } else { |
| 1905 | cpr3_debug(vreg, "last_volt not updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, vdd_volt=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n", |
| 1906 | vreg->last_closed_loop_corner, corner->last_volt, |
| 1907 | vreg->last_closed_loop_corner, |
| 1908 | corner->ceiling_volt, |
| 1909 | vreg->last_closed_loop_corner, corner->floor_volt, |
| 1910 | vdd_volt, reg_last_measurement); |
| 1911 | return; |
| 1912 | } |
| 1913 | |
| 1914 | cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n", |
| 1915 | vreg->last_closed_loop_corner, corner->last_volt, |
| 1916 | vreg->last_closed_loop_corner, corner->ceiling_volt, |
| 1917 | vreg->last_closed_loop_corner, corner->floor_volt, |
| 1918 | reg_last_measurement); |
| 1919 | } |
| 1920 | |
| 1921 | /** |
| 1922 | * cpr3_regulator_config_ldo_retention() - configure per-regulator LDO retention |
| 1923 | * mode |
| 1924 | * @vreg: Pointer to the CPR3 regulator to configure |
| 1925 | * @ref_volt: Reference voltage used to determine if LDO retention |
| 1926 | * mode can be allowed. It corresponds either to the |
| 1927 | * aggregated floor voltage or the next VDD supply setpoint |
| 1928 | * |
| 1929 | * This function determines if a CPR3 regulator's configuration satisfies safe |
| 1930 | * operating voltages for LDO retention and uses the regulator_allow_bypass() |
| 1931 | * interface on the LDO retention regulator to enable or disable such feature |
| 1932 | * accordingly. |
| 1933 | * |
| 1934 | * Return: 0 on success, errno on failure |
| 1935 | */ |
| 1936 | static int cpr3_regulator_config_ldo_retention(struct cpr3_regulator *vreg, |
| 1937 | int ref_volt) |
| 1938 | { |
| 1939 | struct regulator *ldo_ret_reg = vreg->ldo_ret_regulator; |
| 1940 | int retention_volt, rc; |
| 1941 | enum msm_ldo_supply_mode mode; |
| 1942 | |
| 1943 | if (!ldo_ret_reg) { |
| 1944 | /* LDO retention regulator is not defined */ |
| 1945 | return 0; |
| 1946 | } |
| 1947 | |
| 1948 | retention_volt = regulator_get_voltage(ldo_ret_reg); |
| 1949 | if (retention_volt < 0) { |
| 1950 | cpr3_err(vreg, "regulator_get_voltage(ldo_ret) failed, rc=%d\n", |
| 1951 | retention_volt); |
| 1952 | return retention_volt; |
| 1953 | |
| 1954 | } |
| 1955 | |
| 1956 | mode = ref_volt >= retention_volt + vreg->ldo_min_headroom_volt |
| 1957 | ? LDO_MODE : BHS_MODE; |
| 1958 | |
| 1959 | rc = regulator_allow_bypass(ldo_ret_reg, mode); |
| 1960 | if (rc) |
| 1961 | cpr3_err(vreg, "regulator_allow_bypass(ldo_ret) == %s failed, rc=%d\n", |
| 1962 | mode ? "true" : "false", rc); |
| 1963 | |
| 1964 | return rc; |
| 1965 | } |
| 1966 | |
| 1967 | /** |
| 1968 | * cpr3_regulator_config_kryo_ldo_mem_acc() - configure the mem-acc regulator |
| 1969 | * corner based upon a future Kryo LDO regulator voltage setpoint |
| 1970 | * @vreg: Pointer to the CPR3 regulator |
| 1971 | * @new_volt: New voltage in microvolts that the LDO regulator needs |
| 1972 | * to end up at |
| 1973 | * |
| 1974 | * This function determines if a new LDO regulator set point will result |
| 1975 | * in crossing the voltage threshold that requires reconfiguration of |
| 1976 | * the mem-acc regulator associated with a CPR3 regulator and if so, performs |
| 1977 | * the correct sequence to select the correct mem-acc corner. |
| 1978 | * |
| 1979 | * Return: 0 on success, errno on failure |
| 1980 | */ |
| 1981 | static int cpr3_regulator_config_kryo_ldo_mem_acc(struct cpr3_regulator *vreg, |
| 1982 | int new_volt) |
| 1983 | { |
| 1984 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 1985 | struct regulator *ldo_reg = vreg->ldo_regulator; |
| 1986 | struct regulator *mem_acc_reg = vreg->mem_acc_regulator; |
| 1987 | int mem_acc_volt = ctrl->mem_acc_threshold_volt; |
| 1988 | int last_volt, safe_volt, mem_acc_corn, rc; |
| 1989 | enum msm_apm_supply apm_mode; |
| 1990 | |
| 1991 | if (!mem_acc_reg || !mem_acc_volt || !ldo_reg) |
| 1992 | return 0; |
| 1993 | |
| 1994 | apm_mode = msm_apm_get_supply(ctrl->apm); |
| 1995 | if (apm_mode < 0) { |
| 1996 | cpr3_err(ctrl, "APM get supply failed, rc=%d\n", |
| 1997 | apm_mode); |
| 1998 | return apm_mode; |
| 1999 | } |
| 2000 | |
| 2001 | last_volt = regulator_get_voltage(ldo_reg); |
| 2002 | if (last_volt < 0) { |
| 2003 | cpr3_err(vreg, "regulator_get_voltage(ldo) failed, rc=%d\n", |
| 2004 | last_volt); |
| 2005 | return last_volt; |
| 2006 | } |
| 2007 | |
| 2008 | if (((last_volt < mem_acc_volt && mem_acc_volt <= new_volt) |
| 2009 | || (last_volt >= mem_acc_volt && mem_acc_volt > new_volt))) { |
| 2010 | |
| 2011 | if (apm_mode == ctrl->apm_high_supply) |
| 2012 | safe_volt = min(vreg->ldo_max_volt, mem_acc_volt); |
| 2013 | else |
| 2014 | safe_volt = min(max(ctrl->system_supply_max_volt - |
| 2015 | vreg->ldo_max_headroom_volt, |
| 2016 | mem_acc_volt), vreg->ldo_max_volt); |
| 2017 | |
| 2018 | rc = regulator_set_voltage(ldo_reg, safe_volt, |
| 2019 | max(new_volt, last_volt)); |
| 2020 | if (rc) { |
| 2021 | cpr3_err(ctrl, "regulator_set_voltage(ldo) == %d failed, rc=%d\n", |
| 2022 | mem_acc_volt, rc); |
| 2023 | return rc; |
| 2024 | } |
| 2025 | |
| 2026 | mem_acc_corn = new_volt < mem_acc_volt ? |
| 2027 | ctrl->mem_acc_corner_map[CPR3_MEM_ACC_LOW_CORNER] : |
| 2028 | ctrl->mem_acc_corner_map[CPR3_MEM_ACC_HIGH_CORNER]; |
| 2029 | |
| 2030 | rc = regulator_set_voltage(mem_acc_reg, mem_acc_corn, |
| 2031 | mem_acc_corn); |
| 2032 | if (rc) { |
| 2033 | cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", |
| 2034 | 0, rc); |
| 2035 | return rc; |
| 2036 | } |
| 2037 | } |
| 2038 | |
| 2039 | return 0; |
| 2040 | } |
| 2041 | |
| 2042 | /** |
| 2043 | * cpr3_regulator_kryo_bhs_prepare() - configure the Kryo LDO regulator |
| 2044 | * associated with a CPR3 regulator in preparation for BHS |
| 2045 | * mode switch. |
| 2046 | * @vreg: Pointer to the CPR3 regulator |
| 2047 | * @vdd_volt: Last known settled voltage in microvolts for the VDD |
| 2048 | * supply |
| 2049 | * @vdd_ceiling_volt: Last known aggregated ceiling voltage in microvolts for |
| 2050 | * the VDD supply |
| 2051 | * |
| 2052 | * This function performs the necessary steps prior to switching a Kryo LDO |
| 2053 | * regulator to BHS mode (LDO bypassed mode). |
| 2054 | * |
| 2055 | * Return: 0 on success, errno on failure |
| 2056 | */ |
| 2057 | static int cpr3_regulator_kryo_bhs_prepare(struct cpr3_regulator *vreg, |
| 2058 | int vdd_volt, int vdd_ceiling_volt) |
| 2059 | { |
| 2060 | struct regulator *ldo_reg = vreg->ldo_regulator; |
| 2061 | int bhs_volt, rc; |
| 2062 | |
| 2063 | bhs_volt = vdd_volt - vreg->ldo_min_headroom_volt; |
| 2064 | if (bhs_volt > vreg->ldo_max_volt) { |
| 2065 | cpr3_debug(vreg, "limited to LDO output of %d uV when switching to BHS mode\n", |
| 2066 | vreg->ldo_max_volt); |
| 2067 | bhs_volt = vreg->ldo_max_volt; |
| 2068 | } |
| 2069 | |
| 2070 | rc = cpr3_regulator_config_kryo_ldo_mem_acc(vreg, bhs_volt); |
| 2071 | if (rc) { |
| 2072 | cpr3_err(vreg, "failed to configure mem-acc settings\n"); |
| 2073 | return rc; |
| 2074 | } |
| 2075 | |
| 2076 | rc = regulator_set_voltage(ldo_reg, bhs_volt, min(vdd_ceiling_volt, |
| 2077 | vreg->ldo_max_volt)); |
| 2078 | if (rc) { |
| 2079 | cpr3_err(vreg, "regulator_set_voltage(ldo) == %d failed, rc=%d\n", |
| 2080 | bhs_volt, rc); |
| 2081 | return rc; |
| 2082 | } |
| 2083 | |
| 2084 | return rc; |
| 2085 | } |
| 2086 | |
| 2087 | /** |
| 2088 | * cpr3_regulator_set_bhs_mode() - configure the LDO regulator associated with |
| 2089 | * a CPR3 regulator to BHS mode |
| 2090 | * @vreg: Pointer to the CPR3 regulator |
| 2091 | * @vdd_volt: Last known settled voltage in microvolts for the VDD |
| 2092 | * supply |
| 2093 | * @vdd_ceiling_volt: Last known aggregated ceiling voltage in microvolts for |
| 2094 | * the VDD supply |
| 2095 | * |
| 2096 | * This function performs the necessary steps to switch an LDO regulator |
| 2097 | * to BHS mode (LDO bypassed mode). |
| 2098 | */ |
| 2099 | static int cpr3_regulator_set_bhs_mode(struct cpr3_regulator *vreg, |
| 2100 | int vdd_volt, int vdd_ceiling_volt) |
| 2101 | { |
| 2102 | struct regulator *ldo_reg = vreg->ldo_regulator; |
| 2103 | int rc; |
| 2104 | |
| 2105 | if (vreg->ldo_type == CPR3_LDO_KRYO) { |
| 2106 | rc = cpr3_regulator_kryo_bhs_prepare(vreg, vdd_volt, |
| 2107 | vdd_ceiling_volt); |
| 2108 | if (rc) { |
| 2109 | cpr3_err(vreg, "cpr3 regulator bhs mode prepare failed, rc=%d\n", |
| 2110 | rc); |
| 2111 | return rc; |
| 2112 | } |
| 2113 | } |
| 2114 | |
| 2115 | rc = regulator_allow_bypass(ldo_reg, BHS_MODE); |
| 2116 | if (rc) { |
| 2117 | cpr3_err(vreg, "regulator_allow_bypass(bhs) == %s failed, rc=%d\n", |
| 2118 | BHS_MODE ? "true" : "false", rc); |
| 2119 | return rc; |
| 2120 | } |
| 2121 | vreg->ldo_regulator_bypass = BHS_MODE; |
| 2122 | |
| 2123 | return rc; |
| 2124 | } |
| 2125 | |
| 2126 | /** |
| 2127 | * cpr3_regulator_ldo_apm_prepare() - configure LDO regulators associated |
| 2128 | * with each CPR3 regulator of a CPR3 controller in preparation |
| 2129 | * for an APM switch. |
| 2130 | * @ctrl: Pointer to the CPR3 controller |
| 2131 | * @new_volt: New voltage in microvolts that the VDD supply |
| 2132 | * needs to end up at |
| 2133 | * @last_volt: Last known voltage in microvolts for the VDD supply |
| 2134 | * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max |
| 2135 | * corner aggregated from all CPR3 threads managed by the |
| 2136 | * CPR3 controller |
| 2137 | * |
| 2138 | * This function ensures LDO regulator hardware requirements are met before |
| 2139 | * an APM switch is requested. The function must be called as the last step |
| 2140 | * before switching the APM mode. |
| 2141 | * |
| 2142 | * Return: 0 on success, errno on failure |
| 2143 | */ |
| 2144 | static int cpr3_regulator_ldo_apm_prepare(struct cpr3_controller *ctrl, |
| 2145 | int new_volt, int last_volt, |
| 2146 | struct cpr3_corner *aggr_corner) |
| 2147 | { |
| 2148 | struct cpr3_regulator *vreg; |
| 2149 | struct cpr3_corner *current_corner; |
| 2150 | enum msm_apm_supply apm_mode; |
| 2151 | int i, j, safe_volt, max_volt, ldo_volt, ref_volt, rc; |
| 2152 | |
| 2153 | apm_mode = msm_apm_get_supply(ctrl->apm); |
| 2154 | if (apm_mode < 0) { |
| 2155 | cpr3_err(ctrl, "APM get supply failed, rc=%d\n", apm_mode); |
| 2156 | return apm_mode; |
| 2157 | } |
| 2158 | |
| 2159 | if (apm_mode == ctrl->apm_low_supply || |
| 2160 | new_volt >= ctrl->apm_threshold_volt) |
| 2161 | return 0; |
| 2162 | |
| 2163 | /* |
| 2164 | * Guarantee LDO maximum headroom is not violated when the APM is |
| 2165 | * switched to the system-supply source. |
| 2166 | */ |
| 2167 | for (i = 0; i < ctrl->thread_count; i++) { |
| 2168 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 2169 | vreg = &ctrl->thread[i].vreg[j]; |
| 2170 | |
| 2171 | if (!vreg->vreg_enabled || vreg->current_corner |
| 2172 | == CPR3_REGULATOR_CORNER_INVALID) |
| 2173 | continue; |
| 2174 | |
| 2175 | if (!vreg->ldo_regulator || !vreg->ldo_mode_allowed || |
| 2176 | vreg->ldo_regulator_bypass == BHS_MODE) |
| 2177 | continue; |
| 2178 | |
| 2179 | /* |
| 2180 | * If the new VDD configuration does not satisfy |
| 2181 | * requirements for LDO usage, switch the regulator |
| 2182 | * to BHS mode. By doing so, the LDO maximum headroom |
| 2183 | * does not need to be enforced. |
| 2184 | */ |
| 2185 | current_corner = &vreg->corner[vreg->current_corner]; |
| 2186 | ldo_volt = current_corner->open_loop_volt |
| 2187 | - vreg->ldo_adjust_volt; |
| 2188 | ref_volt = ctrl->use_hw_closed_loop ? |
| 2189 | aggr_corner->floor_volt : |
| 2190 | new_volt; |
| 2191 | |
| 2192 | if (ref_volt < ldo_volt + vreg->ldo_min_headroom_volt |
| 2193 | || ldo_volt < ctrl->system_supply_max_volt - |
| 2194 | vreg->ldo_max_headroom_volt || |
| 2195 | ldo_volt > vreg->ldo_max_volt) { |
| 2196 | rc = cpr3_regulator_set_bhs_mode(vreg, |
| 2197 | last_volt, aggr_corner->ceiling_volt); |
| 2198 | if (rc) |
| 2199 | return rc; |
| 2200 | /* |
| 2201 | * Do not enforce LDO maximum headroom since the |
| 2202 | * regulator is now configured to BHS mode. |
| 2203 | */ |
| 2204 | continue; |
| 2205 | } |
| 2206 | |
| 2207 | safe_volt = min(max(ldo_volt, |
| 2208 | ctrl->system_supply_max_volt |
| 2209 | - vreg->ldo_max_headroom_volt), |
| 2210 | vreg->ldo_max_volt); |
| 2211 | max_volt = min(ctrl->system_supply_max_volt, |
| 2212 | vreg->ldo_max_volt); |
| 2213 | |
| 2214 | rc = regulator_set_voltage(vreg->ldo_regulator, |
| 2215 | safe_volt, max_volt); |
| 2216 | if (rc) { |
| 2217 | cpr3_err(vreg, "regulator_set_voltage(ldo) == %d failed, rc=%d\n", |
| 2218 | safe_volt, rc); |
| 2219 | return rc; |
| 2220 | } |
| 2221 | } |
| 2222 | } |
| 2223 | |
| 2224 | return 0; |
| 2225 | } |
| 2226 | |
| 2227 | /** |
| 2228 | * cpr3_regulator_config_vreg_kryo_ldo() - configure the voltage and bypass |
| 2229 | * state for the Kryo LDO regulator associated with a single CPR3 |
| 2230 | * regulator. |
| 2231 | * |
| 2232 | * @vreg: Pointer to the CPR3 regulator |
| 2233 | * @vdd_floor_volt: Last known aggregated floor voltage in microvolts for |
| 2234 | * the VDD supply |
| 2235 | * @vdd_ceiling_volt: Last known aggregated ceiling voltage in microvolts for |
| 2236 | * the VDD supply |
| 2237 | * @ref_volt: Reference voltage in microvolts corresponds either to |
| 2238 | * the aggregated floor voltage or the next VDD supply |
| 2239 | * setpoint. |
| 2240 | * @last_volt: Last known voltage in microvolts for the VDD supply |
| 2241 | * |
| 2242 | * This function performs all relevant LDO or BHS configurations if a Kryo LDO |
| 2243 | * regulator is specified. |
| 2244 | * |
| 2245 | * Return: 0 on success, errno on failure |
| 2246 | */ |
| 2247 | static int cpr3_regulator_config_vreg_kryo_ldo(struct cpr3_regulator *vreg, |
| 2248 | int vdd_floor_volt, int vdd_ceiling_volt, |
| 2249 | int ref_volt, int last_volt) |
| 2250 | { |
| 2251 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 2252 | struct regulator *ldo_reg = vreg->ldo_regulator; |
| 2253 | struct cpr3_corner *current_corner; |
| 2254 | enum msm_apm_supply apm_mode; |
| 2255 | int rc, ldo_volt, final_ldo_volt, bhs_volt, max_volt, safe_volt; |
| 2256 | |
| 2257 | current_corner = &vreg->corner[vreg->current_corner]; |
| 2258 | ldo_volt = current_corner->open_loop_volt |
| 2259 | - vreg->ldo_adjust_volt; |
| 2260 | bhs_volt = last_volt - vreg->ldo_min_headroom_volt; |
| 2261 | max_volt = min(vdd_ceiling_volt, vreg->ldo_max_volt); |
| 2262 | |
| 2263 | if (ref_volt >= ldo_volt + vreg->ldo_min_headroom_volt && |
| 2264 | ldo_volt >= ctrl->system_supply_max_volt - |
| 2265 | vreg->ldo_max_headroom_volt && |
| 2266 | bhs_volt >= ctrl->system_supply_max_volt - |
| 2267 | vreg->ldo_max_headroom_volt && |
| 2268 | ldo_volt <= vreg->ldo_max_volt) { |
| 2269 | /* LDO minimum and maximum headrooms satisfied */ |
| 2270 | apm_mode = msm_apm_get_supply(ctrl->apm); |
| 2271 | if (apm_mode < 0) { |
| 2272 | cpr3_err(ctrl, "APM get supply failed, rc=%d\n", |
| 2273 | apm_mode); |
| 2274 | return apm_mode; |
| 2275 | } |
| 2276 | |
| 2277 | if (vreg->ldo_regulator_bypass == BHS_MODE) { |
| 2278 | /* |
| 2279 | * BHS to LDO transition. Configure LDO output |
| 2280 | * to min(max LDO output, VDD - LDO headroom) |
| 2281 | * voltage if APM is on high supply source or |
| 2282 | * min(max(system-supply ceiling - LDO max headroom, |
| 2283 | * VDD - LDO headroom), max LDO output) if |
| 2284 | * APM is on low supply source, then switch |
| 2285 | * regulator mode. |
| 2286 | */ |
| 2287 | if (apm_mode == ctrl->apm_high_supply) |
| 2288 | safe_volt = min(vreg->ldo_max_volt, bhs_volt); |
| 2289 | else |
| 2290 | safe_volt = |
| 2291 | min(max(ctrl->system_supply_max_volt - |
| 2292 | vreg->ldo_max_headroom_volt, |
| 2293 | bhs_volt), |
| 2294 | vreg->ldo_max_volt); |
| 2295 | |
| 2296 | rc = cpr3_regulator_config_kryo_ldo_mem_acc(vreg, |
| 2297 | safe_volt); |
| 2298 | if (rc) { |
| 2299 | cpr3_err(vreg, "failed to configure mem-acc settings\n"); |
| 2300 | return rc; |
| 2301 | } |
| 2302 | |
| 2303 | rc = regulator_set_voltage(ldo_reg, safe_volt, |
| 2304 | max_volt); |
| 2305 | if (rc) { |
| 2306 | cpr3_err(vreg, "regulator_set_voltage(ldo) == %d failed, rc=%d\n", |
| 2307 | safe_volt, rc); |
| 2308 | return rc; |
| 2309 | } |
| 2310 | |
| 2311 | rc = regulator_allow_bypass(ldo_reg, LDO_MODE); |
| 2312 | if (rc) { |
| 2313 | cpr3_err(vreg, "regulator_allow_bypass(ldo) == %s failed, rc=%d\n", |
| 2314 | LDO_MODE ? "true" : "false", rc); |
| 2315 | return rc; |
| 2316 | } |
| 2317 | vreg->ldo_regulator_bypass = LDO_MODE; |
| 2318 | } |
| 2319 | |
| 2320 | /* Configure final LDO output voltage */ |
| 2321 | if (apm_mode == ctrl->apm_high_supply) |
| 2322 | final_ldo_volt = max(ldo_volt, |
| 2323 | vdd_ceiling_volt - |
| 2324 | vreg->ldo_max_headroom_volt); |
| 2325 | else |
| 2326 | final_ldo_volt = ldo_volt; |
| 2327 | |
| 2328 | rc = cpr3_regulator_config_kryo_ldo_mem_acc(vreg, |
| 2329 | final_ldo_volt); |
| 2330 | if (rc) { |
| 2331 | cpr3_err(vreg, "failed to configure mem-acc settings\n"); |
| 2332 | return rc; |
| 2333 | } |
| 2334 | |
| 2335 | rc = regulator_set_voltage(ldo_reg, final_ldo_volt, max_volt); |
| 2336 | if (rc) { |
| 2337 | cpr3_err(vreg, "regulator_set_voltage(ldo) == %d failed, rc=%d\n", |
| 2338 | final_ldo_volt, rc); |
| 2339 | return rc; |
| 2340 | } |
| 2341 | } else { |
| 2342 | if (vreg->ldo_regulator_bypass == LDO_MODE) { |
| 2343 | /* LDO to BHS transition */ |
| 2344 | rc = cpr3_regulator_set_bhs_mode(vreg, last_volt, |
| 2345 | vdd_ceiling_volt); |
| 2346 | if (rc) |
| 2347 | return rc; |
| 2348 | } |
| 2349 | } |
| 2350 | |
| 2351 | return 0; |
| 2352 | } |
| 2353 | |
| 2354 | /** |
| 2355 | * cpr3_regulator_config_vreg_ldo300() - configure the voltage and bypass state |
| 2356 | * for the LDO300 regulator associated with a single CPR3 |
| 2357 | * regulator. |
| 2358 | * |
| 2359 | * @vreg: Pointer to the CPR3 regulator |
| 2360 | * @new_volt: New voltage in microvolts that VDD supply needs to |
| 2361 | * end up at |
| 2362 | * @vdd_ceiling_volt: Last known aggregated ceiling voltage in microvolts for |
| 2363 | * the VDD supply |
| 2364 | * |
| 2365 | * This function performs all relevant LDO or BHS configurations for an LDO300 |
| 2366 | * type regulator. |
| 2367 | * |
| 2368 | * Return: 0 on success, errno on failure |
| 2369 | */ |
| 2370 | static int cpr3_regulator_config_vreg_ldo300(struct cpr3_regulator *vreg, |
| 2371 | int new_volt, int vdd_ceiling_volt) |
| 2372 | { |
| 2373 | struct regulator *ldo_reg = vreg->ldo_regulator; |
| 2374 | struct cpr3_corner *corner; |
| 2375 | bool mode; |
| 2376 | int rc = 0; |
| 2377 | |
| 2378 | corner = &vreg->corner[vreg->current_corner]; |
| 2379 | mode = corner->ldo_mode_allowed ? LDO_MODE : BHS_MODE; |
| 2380 | |
| 2381 | if (mode == LDO_MODE) { |
| 2382 | rc = regulator_set_voltage(ldo_reg, new_volt, vdd_ceiling_volt); |
| 2383 | if (rc) { |
| 2384 | cpr3_err(vreg, "regulator_set_voltage(ldo) == %d failed, rc=%d\n", |
| 2385 | new_volt, rc); |
| 2386 | return rc; |
| 2387 | } |
| 2388 | } |
| 2389 | |
| 2390 | if (vreg->ldo_regulator_bypass != mode) { |
| 2391 | rc = regulator_allow_bypass(ldo_reg, mode); |
| 2392 | if (rc) { |
| 2393 | cpr3_err(vreg, "regulator_allow_bypass(%s) is failed, rc=%d\n", |
| 2394 | mode == LDO_MODE ? "ldo" : "bhs", rc); |
| 2395 | return rc; |
| 2396 | } |
| 2397 | vreg->ldo_regulator_bypass = mode; |
| 2398 | } |
| 2399 | |
| 2400 | return rc; |
| 2401 | } |
| 2402 | |
| 2403 | /** |
| 2404 | * cpr3_regulator_config_vreg_ldo() - configure the voltage and bypass state for |
| 2405 | * the LDO regulator associated with a single CPR3 regulator. |
| 2406 | * |
| 2407 | * @vreg: Pointer to the CPR3 regulator |
| 2408 | * @vdd_floor_volt: Last known aggregated floor voltage in microvolts for |
| 2409 | * the VDD supply |
| 2410 | * @vdd_ceiling_volt: Last known aggregated ceiling voltage in microvolts for |
| 2411 | * the VDD supply |
| 2412 | * @new_volt: New voltage in microvolts that VDD supply needs to |
| 2413 | * end up at |
| 2414 | * @last_volt: Last known voltage in microvolts for the VDD supply |
| 2415 | * |
| 2416 | * This function identifies the type of LDO regulator associated with a CPR3 |
| 2417 | * regulator and invokes the LDO specific configuration functions. |
| 2418 | * |
| 2419 | * Return: 0 on success, errno on failure |
| 2420 | */ |
| 2421 | static int cpr3_regulator_config_vreg_ldo(struct cpr3_regulator *vreg, |
| 2422 | int vdd_floor_volt, int vdd_ceiling_volt, |
| 2423 | int new_volt, int last_volt) |
| 2424 | { |
| 2425 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 2426 | int ref_volt, rc; |
| 2427 | |
| 2428 | ref_volt = ctrl->use_hw_closed_loop ? vdd_floor_volt : |
| 2429 | new_volt; |
| 2430 | |
| 2431 | rc = cpr3_regulator_config_ldo_retention(vreg, ref_volt); |
| 2432 | if (rc) |
| 2433 | return rc; |
| 2434 | |
| 2435 | if (!vreg->vreg_enabled || |
| 2436 | vreg->current_corner == CPR3_REGULATOR_CORNER_INVALID) |
| 2437 | return 0; |
| 2438 | |
| 2439 | switch (vreg->ldo_type) { |
| 2440 | case CPR3_LDO_KRYO: |
| 2441 | rc = cpr3_regulator_config_vreg_kryo_ldo(vreg, vdd_floor_volt, |
| 2442 | vdd_ceiling_volt, ref_volt, last_volt); |
| 2443 | if (rc) |
| 2444 | cpr3_err(vreg, "kryo ldo regulator config failed, rc=%d\n", |
| 2445 | rc); |
| 2446 | break; |
| 2447 | case CPR3_LDO300: |
| 2448 | rc = cpr3_regulator_config_vreg_ldo300(vreg, new_volt, |
| 2449 | vdd_ceiling_volt); |
| 2450 | if (rc) |
| 2451 | cpr3_err(vreg, "ldo300 regulator config failed, rc=%d\n", |
| 2452 | rc); |
| 2453 | break; |
| 2454 | default: |
| 2455 | cpr3_err(vreg, "invalid ldo regulator type = %d\n", |
| 2456 | vreg->ldo_type); |
| 2457 | rc = -EINVAL; |
| 2458 | } |
| 2459 | |
| 2460 | return rc; |
| 2461 | } |
| 2462 | |
| 2463 | /** |
| 2464 | * cpr3_regulator_config_ldo() - configure the voltage and bypass state for the |
| 2465 | * LDO regulator associated with each CPR3 regulator of a CPR3 |
| 2466 | * controller |
| 2467 | * @ctrl: Pointer to the CPR3 controller |
| 2468 | * @vdd_floor_volt: Last known aggregated floor voltage in microvolts for |
| 2469 | * the VDD supply |
| 2470 | * @vdd_ceiling_volt: Last known aggregated ceiling voltage in microvolts for |
| 2471 | * the VDD supply |
| 2472 | * @new_volt: New voltage in microvolts that VDD supply needs to |
| 2473 | * end up at |
| 2474 | * @last_volt: Last known voltage in microvolts for the VDD supply |
| 2475 | * |
| 2476 | * Return: 0 on success, errno on failure |
| 2477 | */ |
| 2478 | static int cpr3_regulator_config_ldo(struct cpr3_controller *ctrl, |
| 2479 | int vdd_floor_volt, int vdd_ceiling_volt, |
| 2480 | int new_volt, int last_volt) |
| 2481 | { |
| 2482 | struct cpr3_regulator *vreg; |
| 2483 | int i, j, rc; |
| 2484 | |
| 2485 | for (i = 0; i < ctrl->thread_count; i++) { |
| 2486 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 2487 | vreg = &ctrl->thread[i].vreg[j]; |
| 2488 | |
| 2489 | if (!vreg->ldo_regulator || !vreg->ldo_mode_allowed) |
| 2490 | continue; |
| 2491 | |
| 2492 | rc = cpr3_regulator_config_vreg_ldo(vreg, |
| 2493 | vdd_floor_volt, vdd_ceiling_volt, |
| 2494 | new_volt, last_volt); |
| 2495 | if (rc) |
| 2496 | return rc; |
| 2497 | } |
| 2498 | } |
| 2499 | |
| 2500 | return 0; |
| 2501 | } |
| 2502 | |
| 2503 | /** |
| 2504 | * cpr3_regulator_mem_acc_bhs_used() - determines if mem-acc regulators powered |
| 2505 | * through a BHS are associated with the CPR3 controller or any of |
| 2506 | * the CPR3 regulators it controls. |
| 2507 | * @ctrl: Pointer to the CPR3 controller |
| 2508 | * |
| 2509 | * This function determines if the CPR3 controller or any of its CPR3 regulators |
| 2510 | * need to manage mem-acc regulators that are currently powered through a BHS |
| 2511 | * and whose corner selection is based upon a particular voltage threshold. |
| 2512 | * |
| 2513 | * Return: true or false |
| 2514 | */ |
| 2515 | static bool cpr3_regulator_mem_acc_bhs_used(struct cpr3_controller *ctrl) |
| 2516 | { |
| 2517 | struct cpr3_regulator *vreg; |
| 2518 | int i, j; |
| 2519 | |
| 2520 | if (!ctrl->mem_acc_threshold_volt) |
| 2521 | return false; |
| 2522 | |
| 2523 | if (ctrl->mem_acc_regulator) |
| 2524 | return true; |
| 2525 | |
| 2526 | for (i = 0; i < ctrl->thread_count; i++) { |
| 2527 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 2528 | vreg = &ctrl->thread[i].vreg[j]; |
| 2529 | |
| 2530 | if (vreg->mem_acc_regulator && |
| 2531 | (!vreg->ldo_regulator || |
| 2532 | vreg->ldo_regulator_bypass |
| 2533 | == BHS_MODE)) |
| 2534 | return true; |
| 2535 | } |
| 2536 | } |
| 2537 | |
| 2538 | return false; |
| 2539 | } |
| 2540 | |
| 2541 | /** |
| 2542 | * cpr3_regulator_config_bhs_mem_acc() - configure the mem-acc regulator |
| 2543 | * settings for hardware blocks currently powered through the BHS. |
| 2544 | * @ctrl: Pointer to the CPR3 controller |
| 2545 | * @new_volt: New voltage in microvolts that VDD supply needs to |
| 2546 | * end up at |
| 2547 | * @last_volt: Pointer to the last known voltage in microvolts for the |
| 2548 | * VDD supply |
| 2549 | * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max |
| 2550 | * corner aggregated from all CPR3 threads managed by the |
| 2551 | * CPR3 controller |
| 2552 | * |
| 2553 | * This function programs the mem-acc regulator corners for CPR3 regulators |
| 2554 | * whose LDO regulators are in bypassed state. The function also handles |
| 2555 | * CPR3 controllers which utilize mem-acc regulators that operate independently |
| 2556 | * from the LDO hardware and that must be programmed when the VDD supply |
| 2557 | * crosses a particular voltage threshold. |
| 2558 | * |
| 2559 | * Return: 0 on success, errno on failure. If the VDD supply voltage is |
| 2560 | * modified, last_volt is updated to reflect the new voltage setpoint. |
| 2561 | */ |
| 2562 | static int cpr3_regulator_config_bhs_mem_acc(struct cpr3_controller *ctrl, |
| 2563 | int new_volt, int *last_volt, |
| 2564 | struct cpr3_corner *aggr_corner) |
| 2565 | { |
| 2566 | struct cpr3_regulator *vreg; |
| 2567 | int i, j, rc, mem_acc_corn, safe_volt; |
| 2568 | int mem_acc_volt = ctrl->mem_acc_threshold_volt; |
| 2569 | int ref_volt; |
| 2570 | |
| 2571 | if (!cpr3_regulator_mem_acc_bhs_used(ctrl)) |
| 2572 | return 0; |
| 2573 | |
| 2574 | ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt : |
| 2575 | new_volt; |
| 2576 | |
| 2577 | if (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) || |
| 2578 | (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt))) { |
| 2579 | if (ref_volt < *last_volt) |
| 2580 | safe_volt = max(mem_acc_volt, aggr_corner->last_volt); |
| 2581 | else |
| 2582 | safe_volt = max(mem_acc_volt, *last_volt); |
| 2583 | |
| 2584 | rc = regulator_set_voltage(ctrl->vdd_regulator, safe_volt, |
| 2585 | new_volt < *last_volt ? |
| 2586 | ctrl->aggr_corner.ceiling_volt : |
| 2587 | new_volt); |
| 2588 | if (rc) { |
| 2589 | cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", |
| 2590 | safe_volt, rc); |
| 2591 | return rc; |
| 2592 | } |
| 2593 | |
| 2594 | *last_volt = safe_volt; |
| 2595 | |
| 2596 | mem_acc_corn = ref_volt < mem_acc_volt ? |
| 2597 | ctrl->mem_acc_corner_map[CPR3_MEM_ACC_LOW_CORNER] : |
| 2598 | ctrl->mem_acc_corner_map[CPR3_MEM_ACC_HIGH_CORNER]; |
| 2599 | |
| 2600 | if (ctrl->mem_acc_regulator) { |
| 2601 | rc = regulator_set_voltage(ctrl->mem_acc_regulator, |
| 2602 | mem_acc_corn, mem_acc_corn); |
| 2603 | if (rc) { |
| 2604 | cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", |
| 2605 | mem_acc_corn, rc); |
| 2606 | return rc; |
| 2607 | } |
| 2608 | } |
| 2609 | |
| 2610 | for (i = 0; i < ctrl->thread_count; i++) { |
| 2611 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 2612 | vreg = &ctrl->thread[i].vreg[j]; |
| 2613 | |
| 2614 | if (!vreg->mem_acc_regulator || |
| 2615 | (vreg->ldo_regulator && |
| 2616 | vreg->ldo_regulator_bypass |
| 2617 | == LDO_MODE)) |
| 2618 | continue; |
| 2619 | |
| 2620 | rc = regulator_set_voltage( |
| 2621 | vreg->mem_acc_regulator, mem_acc_corn, |
| 2622 | mem_acc_corn); |
| 2623 | if (rc) { |
| 2624 | cpr3_err(vreg, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", |
| 2625 | mem_acc_corn, rc); |
| 2626 | return rc; |
| 2627 | } |
| 2628 | } |
| 2629 | } |
| 2630 | } |
| 2631 | |
| 2632 | return 0; |
| 2633 | } |
| 2634 | |
| 2635 | /** |
| 2636 | * cpr3_regulator_switch_apm_mode() - switch the mode of the APM controller |
| 2637 | * associated with a given CPR3 controller |
| 2638 | * @ctrl: Pointer to the CPR3 controller |
| 2639 | * @new_volt: New voltage in microvolts that VDD supply needs to |
| 2640 | * end up at |
| 2641 | * @last_volt: Pointer to the last known voltage in microvolts for the |
| 2642 | * VDD supply |
| 2643 | * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max |
| 2644 | * corner aggregated from all CPR3 threads managed by the |
| 2645 | * CPR3 controller |
| 2646 | * |
| 2647 | * This function requests a switch of the APM mode while guaranteeing |
| 2648 | * any LDO regulator hardware requirements are satisfied. The function must |
| 2649 | * be called once it is known a new VDD supply setpoint crosses the APM |
| 2650 | * voltage threshold. |
| 2651 | * |
| 2652 | * Return: 0 on success, errno on failure. If the VDD supply voltage is |
| 2653 | * modified, last_volt is updated to reflect the new voltage setpoint. |
| 2654 | */ |
| 2655 | static int cpr3_regulator_switch_apm_mode(struct cpr3_controller *ctrl, |
| 2656 | int new_volt, int *last_volt, |
| 2657 | struct cpr3_corner *aggr_corner) |
| 2658 | { |
| 2659 | struct regulator *vdd = ctrl->vdd_regulator; |
| 2660 | int apm_volt = ctrl->apm_threshold_volt; |
| 2661 | int orig_last_volt = *last_volt; |
| 2662 | int rc; |
| 2663 | |
| 2664 | rc = regulator_set_voltage(vdd, apm_volt, apm_volt); |
| 2665 | if (rc) { |
| 2666 | cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", |
| 2667 | apm_volt, rc); |
| 2668 | return rc; |
| 2669 | } |
| 2670 | |
| 2671 | *last_volt = apm_volt; |
| 2672 | |
| 2673 | rc = cpr3_regulator_ldo_apm_prepare(ctrl, new_volt, *last_volt, |
| 2674 | aggr_corner); |
| 2675 | if (rc) { |
| 2676 | cpr3_err(ctrl, "unable to prepare LDO state for APM switch, rc=%d\n", |
| 2677 | rc); |
| 2678 | return rc; |
| 2679 | } |
| 2680 | |
| 2681 | rc = msm_apm_set_supply(ctrl->apm, new_volt >= apm_volt |
| 2682 | ? ctrl->apm_high_supply : ctrl->apm_low_supply); |
| 2683 | if (rc) { |
| 2684 | cpr3_err(ctrl, "APM switch failed, rc=%d\n", rc); |
| 2685 | /* Roll back the voltage. */ |
| 2686 | regulator_set_voltage(vdd, orig_last_volt, INT_MAX); |
| 2687 | *last_volt = orig_last_volt; |
| 2688 | return rc; |
| 2689 | } |
| 2690 | return 0; |
| 2691 | } |
| 2692 | |
| 2693 | /** |
| 2694 | * cpr3_regulator_config_voltage_crossings() - configure APM and mem-acc |
| 2695 | * settings depending upon a new VDD supply setpoint |
| 2696 | * |
| 2697 | * @ctrl: Pointer to the CPR3 controller |
| 2698 | * @new_volt: New voltage in microvolts that VDD supply needs to |
| 2699 | * end up at |
| 2700 | * @last_volt: Pointer to the last known voltage in microvolts for the |
| 2701 | * VDD supply |
| 2702 | * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max |
| 2703 | * corner aggregated from all CPR3 threads managed by the |
| 2704 | * CPR3 controller |
| 2705 | * |
| 2706 | * This function handles the APM and mem-acc regulator reconfiguration if |
| 2707 | * the new VDD supply voltage will result in crossing their respective voltage |
| 2708 | * thresholds. |
| 2709 | * |
| 2710 | * Return: 0 on success, errno on failure. If the VDD supply voltage is |
| 2711 | * modified, last_volt is updated to reflect the new voltage setpoint. |
| 2712 | */ |
| 2713 | static int cpr3_regulator_config_voltage_crossings(struct cpr3_controller *ctrl, |
| 2714 | int new_volt, int *last_volt, |
| 2715 | struct cpr3_corner *aggr_corner) |
| 2716 | { |
| 2717 | bool apm_crossing = false, mem_acc_crossing = false; |
| 2718 | bool mem_acc_bhs_used; |
| 2719 | int apm_volt = ctrl->apm_threshold_volt; |
| 2720 | int mem_acc_volt = ctrl->mem_acc_threshold_volt; |
| 2721 | int ref_volt, rc; |
| 2722 | |
| 2723 | if (ctrl->apm && apm_volt > 0 |
| 2724 | && ((*last_volt < apm_volt && apm_volt <= new_volt) |
| 2725 | || (*last_volt >= apm_volt && apm_volt > new_volt))) |
| 2726 | apm_crossing = true; |
| 2727 | |
| 2728 | mem_acc_bhs_used = cpr3_regulator_mem_acc_bhs_used(ctrl); |
| 2729 | |
| 2730 | ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt : |
| 2731 | new_volt; |
| 2732 | |
| 2733 | if (mem_acc_bhs_used && |
| 2734 | (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) || |
| 2735 | (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt)))) |
| 2736 | mem_acc_crossing = true; |
| 2737 | |
| 2738 | if (apm_crossing && mem_acc_crossing) { |
| 2739 | if ((new_volt < *last_volt && apm_volt >= mem_acc_volt) || |
| 2740 | (new_volt >= *last_volt && apm_volt < mem_acc_volt)) { |
| 2741 | rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, |
| 2742 | last_volt, |
| 2743 | aggr_corner); |
| 2744 | if (rc) { |
| 2745 | cpr3_err(ctrl, "unable to switch APM mode\n"); |
| 2746 | return rc; |
| 2747 | } |
| 2748 | |
| 2749 | rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, |
| 2750 | last_volt, aggr_corner); |
| 2751 | if (rc) { |
| 2752 | cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); |
| 2753 | return rc; |
| 2754 | } |
| 2755 | } else { |
| 2756 | rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, |
| 2757 | last_volt, aggr_corner); |
| 2758 | if (rc) { |
| 2759 | cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); |
| 2760 | return rc; |
| 2761 | } |
| 2762 | |
| 2763 | rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, |
| 2764 | last_volt, |
| 2765 | aggr_corner); |
| 2766 | if (rc) { |
| 2767 | cpr3_err(ctrl, "unable to switch APM mode\n"); |
| 2768 | return rc; |
| 2769 | } |
| 2770 | } |
| 2771 | } else if (apm_crossing) { |
| 2772 | rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, last_volt, |
| 2773 | aggr_corner); |
| 2774 | if (rc) { |
| 2775 | cpr3_err(ctrl, "unable to switch APM mode\n"); |
| 2776 | return rc; |
| 2777 | } |
| 2778 | } else if (mem_acc_crossing) { |
| 2779 | rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt, |
| 2780 | last_volt, aggr_corner); |
| 2781 | if (rc) { |
| 2782 | cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n"); |
| 2783 | return rc; |
| 2784 | } |
| 2785 | } |
| 2786 | |
| 2787 | return 0; |
| 2788 | } |
| 2789 | |
| 2790 | /** |
| 2791 | * cpr3_regulator_config_mem_acc() - configure the corner of the mem-acc |
| 2792 | * regulator associated with the CPR3 controller |
| 2793 | * @ctrl: Pointer to the CPR3 controller |
| 2794 | * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max |
| 2795 | * corner aggregated from all CPR3 threads managed by the |
| 2796 | * CPR3 controller |
| 2797 | * |
| 2798 | * Return: 0 on success, errno on failure |
| 2799 | */ |
| 2800 | static int cpr3_regulator_config_mem_acc(struct cpr3_controller *ctrl, |
| 2801 | struct cpr3_corner *aggr_corner) |
| 2802 | { |
| 2803 | int rc; |
| 2804 | |
| 2805 | if (ctrl->mem_acc_regulator && aggr_corner->mem_acc_volt) { |
| 2806 | rc = regulator_set_voltage(ctrl->mem_acc_regulator, |
| 2807 | aggr_corner->mem_acc_volt, |
| 2808 | aggr_corner->mem_acc_volt); |
| 2809 | if (rc) { |
| 2810 | cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n", |
| 2811 | aggr_corner->mem_acc_volt, rc); |
| 2812 | return rc; |
| 2813 | } |
| 2814 | } |
| 2815 | |
| 2816 | return 0; |
| 2817 | } |
| 2818 | |
| 2819 | /** |
| 2820 | * cpr3_regulator_scale_vdd_voltage() - scale the CPR controlled VDD supply |
| 2821 | * voltage to the new level while satisfying any other hardware |
| 2822 | * requirements |
| 2823 | * @ctrl: Pointer to the CPR3 controller |
| 2824 | * @new_volt: New voltage in microvolts that VDD supply needs to end |
| 2825 | * up at |
| 2826 | * @last_volt: Last known voltage in microvolts for the VDD supply |
| 2827 | * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max |
| 2828 | * corner aggregated from all CPR3 threads managed by the |
| 2829 | * CPR3 controller |
| 2830 | * |
| 2831 | * This function scales the CPR controlled VDD supply voltage from its |
| 2832 | * current level to the new voltage that is specified. If the supply is |
| 2833 | * configured to use the APM and the APM threshold is crossed as a result of |
| 2834 | * the voltage scaling, then this function also stops at the APM threshold, |
| 2835 | * switches the APM source, and finally sets the final new voltage. |
| 2836 | * |
| 2837 | * Return: 0 on success, errno on failure |
| 2838 | */ |
| 2839 | static int cpr3_regulator_scale_vdd_voltage(struct cpr3_controller *ctrl, |
| 2840 | int new_volt, int last_volt, |
| 2841 | struct cpr3_corner *aggr_corner) |
| 2842 | { |
| 2843 | struct regulator *vdd = ctrl->vdd_regulator; |
| 2844 | int rc; |
| 2845 | |
| 2846 | if (new_volt < last_volt) { |
| 2847 | if (ctrl->support_ldo300_vreg) { |
| 2848 | rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); |
| 2849 | if (rc) |
| 2850 | return rc; |
| 2851 | } |
| 2852 | |
| 2853 | /* Decreasing VDD voltage */ |
| 2854 | rc = cpr3_regulator_config_ldo(ctrl, aggr_corner->floor_volt, |
| 2855 | ctrl->aggr_corner.ceiling_volt, |
| 2856 | new_volt, last_volt); |
| 2857 | if (rc) { |
| 2858 | cpr3_err(ctrl, "unable to configure LDO state, rc=%d\n", |
| 2859 | rc); |
| 2860 | return rc; |
| 2861 | } |
| 2862 | |
| 2863 | if (!ctrl->support_ldo300_vreg) { |
| 2864 | rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); |
| 2865 | if (rc) |
| 2866 | return rc; |
| 2867 | } |
| 2868 | } else { |
| 2869 | /* Increasing VDD voltage */ |
| 2870 | if (ctrl->system_regulator) { |
| 2871 | rc = regulator_set_voltage(ctrl->system_regulator, |
| 2872 | aggr_corner->system_volt, INT_MAX); |
| 2873 | if (rc) { |
| 2874 | cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n", |
| 2875 | aggr_corner->system_volt, rc); |
| 2876 | return rc; |
| 2877 | } |
| 2878 | } |
| 2879 | } |
| 2880 | |
| 2881 | rc = cpr3_regulator_config_voltage_crossings(ctrl, new_volt, &last_volt, |
| 2882 | aggr_corner); |
| 2883 | if (rc) { |
| 2884 | cpr3_err(ctrl, "unable to handle voltage threshold crossing configurations, rc=%d\n", |
| 2885 | rc); |
| 2886 | return rc; |
| 2887 | } |
| 2888 | |
| 2889 | /* |
| 2890 | * Subtract a small amount from the min_uV parameter so that the |
| 2891 | * set voltage request is not dropped by the framework due to being |
| 2892 | * duplicate. This is needed in order to switch from hardware |
| 2893 | * closed-loop to open-loop successfully. |
| 2894 | */ |
| 2895 | rc = regulator_set_voltage(vdd, new_volt - (ctrl->cpr_enabled ? 0 : 1), |
| 2896 | aggr_corner->ceiling_volt); |
| 2897 | if (rc) { |
| 2898 | cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n", |
| 2899 | new_volt, rc); |
| 2900 | return rc; |
| 2901 | } |
| 2902 | |
| 2903 | if (new_volt == last_volt && ctrl->supports_hw_closed_loop |
| 2904 | && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 2905 | /* |
| 2906 | * CPR4 features enforce voltage reprogramming when the last |
| 2907 | * set voltage and new set voltage are same. This way, we can |
| 2908 | * ensure that SAW PMIC STATUS register is updated with newly |
| 2909 | * programmed voltage. |
| 2910 | */ |
| 2911 | rc = regulator_sync_voltage(vdd); |
| 2912 | if (rc) { |
| 2913 | cpr3_err(ctrl, "regulator_sync_voltage(vdd) == %d failed, rc=%d\n", |
| 2914 | new_volt, rc); |
| 2915 | return rc; |
| 2916 | } |
| 2917 | } |
| 2918 | |
| 2919 | if (new_volt >= last_volt) { |
| 2920 | /* Increasing VDD voltage */ |
| 2921 | rc = cpr3_regulator_config_ldo(ctrl, aggr_corner->floor_volt, |
| 2922 | aggr_corner->ceiling_volt, |
| 2923 | new_volt, new_volt); |
| 2924 | if (rc) { |
| 2925 | cpr3_err(ctrl, "unable to configure LDO state, rc=%d\n", |
| 2926 | rc); |
| 2927 | return rc; |
| 2928 | } |
| 2929 | |
| 2930 | rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner); |
| 2931 | if (rc) |
| 2932 | return rc; |
| 2933 | } else { |
| 2934 | /* Decreasing VDD voltage */ |
| 2935 | if (ctrl->system_regulator) { |
| 2936 | rc = regulator_set_voltage(ctrl->system_regulator, |
| 2937 | aggr_corner->system_volt, INT_MAX); |
| 2938 | if (rc) { |
| 2939 | cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n", |
| 2940 | aggr_corner->system_volt, rc); |
| 2941 | return rc; |
| 2942 | } |
| 2943 | } |
| 2944 | } |
| 2945 | |
| 2946 | return 0; |
| 2947 | } |
| 2948 | |
| 2949 | /** |
| 2950 | * cpr3_regulator_get_dynamic_floor_volt() - returns the current dynamic floor |
| 2951 | * voltage based upon static configurations and the state of all |
| 2952 | * power domains during the last CPR measurement |
| 2953 | * @ctrl: Pointer to the CPR3 controller |
| 2954 | * @reg_last_measurement: Value read from the LAST_MEASUREMENT register |
| 2955 | * |
| 2956 | * When using HW closed-loop, the dynamic floor voltage is always returned |
| 2957 | * regardless of the current state of the power domains. |
| 2958 | * |
| 2959 | * Return: dynamic floor voltage in microvolts or 0 if dynamic floor is not |
| 2960 | * currently required |
| 2961 | */ |
| 2962 | static int cpr3_regulator_get_dynamic_floor_volt(struct cpr3_controller *ctrl, |
| 2963 | u32 reg_last_measurement) |
| 2964 | { |
| 2965 | int dynamic_floor_volt = 0; |
| 2966 | struct cpr3_regulator *vreg; |
| 2967 | bool valid, pd_valid; |
| 2968 | u32 bypass_bits; |
| 2969 | int i, j; |
| 2970 | |
| 2971 | if (!ctrl->supports_hw_closed_loop) |
| 2972 | return 0; |
| 2973 | |
| 2974 | if (likely(!ctrl->use_hw_closed_loop)) { |
| 2975 | valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID); |
| 2976 | bypass_bits |
| 2977 | = (reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK) |
| 2978 | >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT; |
| 2979 | } else { |
| 2980 | /* |
| 2981 | * Ensure that the dynamic floor voltage is always used for |
| 2982 | * HW closed-loop since the conditions below cannot be evaluated |
| 2983 | * after each CPR measurement. |
| 2984 | */ |
| 2985 | valid = false; |
| 2986 | bypass_bits = 0; |
| 2987 | } |
| 2988 | |
| 2989 | for (i = 0; i < ctrl->thread_count; i++) { |
| 2990 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 2991 | vreg = &ctrl->thread[i].vreg[j]; |
| 2992 | |
| 2993 | if (!vreg->uses_dynamic_floor) |
| 2994 | continue; |
| 2995 | |
| 2996 | pd_valid = !((bypass_bits & vreg->pd_bypass_mask) |
| 2997 | == vreg->pd_bypass_mask); |
| 2998 | |
| 2999 | if (!valid || !pd_valid) |
| 3000 | dynamic_floor_volt = max(dynamic_floor_volt, |
| 3001 | vreg->corner[ |
| 3002 | vreg->dynamic_floor_corner].last_volt); |
| 3003 | } |
| 3004 | } |
| 3005 | |
| 3006 | return dynamic_floor_volt; |
| 3007 | } |
| 3008 | |
| 3009 | /** |
| 3010 | * cpr3_regulator_max_sdelta_diff() - returns the maximum voltage difference in |
| 3011 | * microvolts that can result from different operating conditions |
| 3012 | * for the specified sdelta struct |
| 3013 | * @sdelta: Pointer to the sdelta structure |
| 3014 | * @step_volt: Step size in microvolts between available set |
| 3015 | * points of the VDD supply. |
| 3016 | * |
| 3017 | * Return: voltage difference between the highest and lowest adjustments if |
| 3018 | * sdelta and sdelta->table are valid, else 0. |
| 3019 | */ |
| 3020 | static int cpr3_regulator_max_sdelta_diff(const struct cpr4_sdelta *sdelta, |
| 3021 | int step_volt) |
| 3022 | { |
| 3023 | int i, j, index, sdelta_min = INT_MAX, sdelta_max = INT_MIN; |
| 3024 | |
| 3025 | if (!sdelta || !sdelta->table) |
| 3026 | return 0; |
| 3027 | |
| 3028 | for (i = 0; i < sdelta->max_core_count; i++) { |
| 3029 | for (j = 0; j < sdelta->temp_band_count; j++) { |
| 3030 | index = i * sdelta->temp_band_count + j; |
| 3031 | sdelta_min = min(sdelta_min, sdelta->table[index]); |
| 3032 | sdelta_max = max(sdelta_max, sdelta->table[index]); |
| 3033 | } |
| 3034 | } |
| 3035 | |
| 3036 | return (sdelta_max - sdelta_min) * step_volt; |
| 3037 | } |
| 3038 | |
| 3039 | /** |
| 3040 | * cpr3_regulator_aggregate_sdelta() - check open-loop voltages of current |
| 3041 | * aggregated corner and current corner of a given regulator |
| 3042 | * and adjust the sdelta strucuture data of aggregate corner. |
| 3043 | * @aggr_corner: Pointer to accumulated aggregated corner which |
| 3044 | * is both an input and an output |
| 3045 | * @corner: Pointer to the corner to be aggregated with |
| 3046 | * aggr_corner |
| 3047 | * @step_volt: Step size in microvolts between available set |
| 3048 | * points of the VDD supply. |
| 3049 | * |
| 3050 | * Return: none |
| 3051 | */ |
| 3052 | static void cpr3_regulator_aggregate_sdelta( |
| 3053 | struct cpr3_corner *aggr_corner, |
| 3054 | const struct cpr3_corner *corner, int step_volt) |
| 3055 | { |
| 3056 | struct cpr4_sdelta *aggr_sdelta, *sdelta; |
| 3057 | int aggr_core_count, core_count, temp_band_count; |
| 3058 | u32 aggr_index, index; |
| 3059 | int i, j, sdelta_size, cap_steps, adjust_sdelta; |
| 3060 | |
| 3061 | aggr_sdelta = aggr_corner->sdelta; |
| 3062 | sdelta = corner->sdelta; |
| 3063 | |
| 3064 | if (aggr_corner->open_loop_volt < corner->open_loop_volt) { |
| 3065 | /* |
| 3066 | * Found the new dominant regulator as its open-loop requirement |
| 3067 | * is higher than previous dominant regulator. Calculate cap |
| 3068 | * voltage to limit the SDELTA values to make sure the runtime |
| 3069 | * (Core-count/temp) adjustments do not violate other |
| 3070 | * regulators' voltage requirements. Use cpr4_sdelta values of |
| 3071 | * new dominant regulator. |
| 3072 | */ |
| 3073 | aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt, |
| 3074 | (corner->open_loop_volt - |
| 3075 | aggr_corner->open_loop_volt)); |
| 3076 | |
| 3077 | /* Clear old data in the sdelta table */ |
| 3078 | sdelta_size = aggr_sdelta->max_core_count |
| 3079 | * aggr_sdelta->temp_band_count; |
| 3080 | |
| 3081 | if (aggr_sdelta->allow_core_count_adj |
| 3082 | || aggr_sdelta->allow_temp_adj) |
| 3083 | memset(aggr_sdelta->table, 0, sdelta_size |
| 3084 | * sizeof(*aggr_sdelta->table)); |
| 3085 | |
| 3086 | if (sdelta->allow_temp_adj || sdelta->allow_core_count_adj) { |
| 3087 | /* Copy new data in sdelta table */ |
| 3088 | sdelta_size = sdelta->max_core_count |
| 3089 | * sdelta->temp_band_count; |
| 3090 | if (sdelta->table) |
| 3091 | memcpy(aggr_sdelta->table, sdelta->table, |
| 3092 | sdelta_size * sizeof(*sdelta->table)); |
| 3093 | } |
| 3094 | |
| 3095 | if (sdelta->allow_boost) { |
| 3096 | memcpy(aggr_sdelta->boost_table, sdelta->boost_table, |
| 3097 | sdelta->temp_band_count |
| 3098 | * sizeof(*sdelta->boost_table)); |
| 3099 | aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; |
| 3100 | } else if (aggr_sdelta->allow_boost) { |
| 3101 | for (i = 0; i < aggr_sdelta->temp_band_count; i++) { |
| 3102 | adjust_sdelta = (corner->open_loop_volt |
| 3103 | - aggr_corner->open_loop_volt) |
| 3104 | / step_volt; |
| 3105 | aggr_sdelta->boost_table[i] += adjust_sdelta; |
| 3106 | aggr_sdelta->boost_table[i] |
| 3107 | = min(aggr_sdelta->boost_table[i], 0); |
| 3108 | } |
| 3109 | } |
| 3110 | |
| 3111 | aggr_corner->open_loop_volt = corner->open_loop_volt; |
| 3112 | aggr_sdelta->allow_temp_adj = sdelta->allow_temp_adj; |
| 3113 | aggr_sdelta->allow_core_count_adj |
| 3114 | = sdelta->allow_core_count_adj; |
| 3115 | aggr_sdelta->max_core_count = sdelta->max_core_count; |
| 3116 | aggr_sdelta->temp_band_count = sdelta->temp_band_count; |
| 3117 | } else if (aggr_corner->open_loop_volt > corner->open_loop_volt) { |
| 3118 | /* |
| 3119 | * Adjust the cap voltage if the open-loop requirement of new |
| 3120 | * regulator is the next highest. |
| 3121 | */ |
| 3122 | aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt, |
| 3123 | (aggr_corner->open_loop_volt |
| 3124 | - corner->open_loop_volt)); |
| 3125 | |
| 3126 | if (sdelta->allow_boost) { |
| 3127 | for (i = 0; i < aggr_sdelta->temp_band_count; i++) { |
| 3128 | adjust_sdelta = (aggr_corner->open_loop_volt |
| 3129 | - corner->open_loop_volt) |
| 3130 | / step_volt; |
| 3131 | aggr_sdelta->boost_table[i] = |
| 3132 | sdelta->boost_table[i] + adjust_sdelta; |
| 3133 | aggr_sdelta->boost_table[i] |
| 3134 | = min(aggr_sdelta->boost_table[i], 0); |
| 3135 | } |
| 3136 | aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; |
| 3137 | } |
| 3138 | } else { |
| 3139 | /* |
| 3140 | * Found another dominant regulator with same open-loop |
| 3141 | * requirement. Make cap voltage to '0'. Disable core-count |
| 3142 | * adjustments as we couldn't support for both regulators. |
| 3143 | * Keep enable temp based adjustments if enabled for both |
| 3144 | * regulators and choose mininum margin adjustment values |
| 3145 | * between them. |
| 3146 | */ |
| 3147 | aggr_sdelta->cap_volt = 0; |
| 3148 | aggr_sdelta->allow_core_count_adj = false; |
| 3149 | |
| 3150 | if (aggr_sdelta->allow_temp_adj |
| 3151 | && sdelta->allow_temp_adj) { |
| 3152 | aggr_core_count = aggr_sdelta->max_core_count - 1; |
| 3153 | core_count = sdelta->max_core_count - 1; |
| 3154 | temp_band_count = sdelta->temp_band_count; |
| 3155 | for (j = 0; j < temp_band_count; j++) { |
| 3156 | aggr_index = aggr_core_count * temp_band_count |
| 3157 | + j; |
| 3158 | index = core_count * temp_band_count + j; |
| 3159 | aggr_sdelta->table[aggr_index] = |
| 3160 | min(aggr_sdelta->table[aggr_index], |
| 3161 | sdelta->table[index]); |
| 3162 | } |
| 3163 | } else { |
| 3164 | aggr_sdelta->allow_temp_adj = false; |
| 3165 | } |
| 3166 | |
| 3167 | if (sdelta->allow_boost) { |
| 3168 | memcpy(aggr_sdelta->boost_table, sdelta->boost_table, |
| 3169 | sdelta->temp_band_count |
| 3170 | * sizeof(*sdelta->boost_table)); |
| 3171 | aggr_sdelta->boost_num_cores = sdelta->boost_num_cores; |
| 3172 | } |
| 3173 | } |
| 3174 | |
| 3175 | /* Keep non-dominant clients boost enable state */ |
| 3176 | aggr_sdelta->allow_boost |= sdelta->allow_boost; |
| 3177 | if (aggr_sdelta->allow_boost) |
| 3178 | aggr_sdelta->allow_core_count_adj = false; |
| 3179 | |
| 3180 | if (aggr_sdelta->cap_volt && !(aggr_sdelta->cap_volt == INT_MAX)) { |
| 3181 | core_count = aggr_sdelta->max_core_count; |
| 3182 | temp_band_count = aggr_sdelta->temp_band_count; |
| 3183 | /* |
| 3184 | * Convert cap voltage from uV to PMIC steps and use to limit |
| 3185 | * sdelta margin adjustments. |
| 3186 | */ |
| 3187 | cap_steps = aggr_sdelta->cap_volt / step_volt; |
| 3188 | for (i = 0; i < core_count; i++) |
| 3189 | for (j = 0; j < temp_band_count; j++) { |
| 3190 | index = i * temp_band_count + j; |
| 3191 | aggr_sdelta->table[index] = |
| 3192 | min(aggr_sdelta->table[index], |
| 3193 | cap_steps); |
| 3194 | } |
| 3195 | } |
| 3196 | } |
| 3197 | |
| 3198 | /** |
| 3199 | * cpr3_regulator_aggregate_corners() - aggregate two corners together |
| 3200 | * @aggr_corner: Pointer to accumulated aggregated corner which |
| 3201 | * is both an input and an output |
| 3202 | * @corner: Pointer to the corner to be aggregated with |
| 3203 | * aggr_corner |
| 3204 | * @aggr_quot: Flag indicating that target quotients should be |
| 3205 | * aggregated as well. |
| 3206 | * @step_volt: Step size in microvolts between available set |
| 3207 | * points of the VDD supply. |
| 3208 | * |
| 3209 | * Return: none |
| 3210 | */ |
| 3211 | static void cpr3_regulator_aggregate_corners(struct cpr3_corner *aggr_corner, |
| 3212 | const struct cpr3_corner *corner, bool aggr_quot, |
| 3213 | int step_volt) |
| 3214 | { |
| 3215 | int i; |
| 3216 | |
| 3217 | aggr_corner->ceiling_volt |
| 3218 | = max(aggr_corner->ceiling_volt, corner->ceiling_volt); |
| 3219 | aggr_corner->floor_volt |
| 3220 | = max(aggr_corner->floor_volt, corner->floor_volt); |
| 3221 | aggr_corner->last_volt |
| 3222 | = max(aggr_corner->last_volt, corner->last_volt); |
| 3223 | aggr_corner->system_volt |
| 3224 | = max(aggr_corner->system_volt, corner->system_volt); |
| 3225 | aggr_corner->mem_acc_volt |
| 3226 | = max(aggr_corner->mem_acc_volt, corner->mem_acc_volt); |
| 3227 | aggr_corner->irq_en |= corner->irq_en; |
| 3228 | aggr_corner->use_open_loop |= corner->use_open_loop; |
| 3229 | aggr_corner->ldo_mode_allowed |= corner->ldo_mode_allowed; |
| 3230 | |
| 3231 | if (aggr_quot) { |
| 3232 | aggr_corner->ro_mask &= corner->ro_mask; |
| 3233 | |
| 3234 | for (i = 0; i < CPR3_RO_COUNT; i++) |
| 3235 | aggr_corner->target_quot[i] |
| 3236 | = max(aggr_corner->target_quot[i], |
| 3237 | corner->target_quot[i]); |
| 3238 | } |
| 3239 | |
| 3240 | if (aggr_corner->sdelta && corner->sdelta |
| 3241 | && (aggr_corner->sdelta->table |
| 3242 | || aggr_corner->sdelta->boost_table)) { |
| 3243 | cpr3_regulator_aggregate_sdelta(aggr_corner, corner, step_volt); |
| 3244 | } else { |
| 3245 | aggr_corner->open_loop_volt |
| 3246 | = max(aggr_corner->open_loop_volt, |
| 3247 | corner->open_loop_volt); |
| 3248 | } |
| 3249 | } |
| 3250 | |
| 3251 | /** |
| 3252 | * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller |
| 3253 | * to reflect the corners used by all CPR3 regulators as well as |
| 3254 | * the CPR operating mode |
| 3255 | * @ctrl: Pointer to the CPR3 controller |
| 3256 | * |
| 3257 | * This function aggregates the CPR parameters for all CPR3 regulators |
| 3258 | * associated with the VDD supply. Upon success, it sets the aggregated last |
| 3259 | * known good voltage. |
| 3260 | * |
| 3261 | * The VDD supply voltage will not be physically configured unless this |
| 3262 | * condition is met by at least one of the regulators of the controller: |
| 3263 | * regulator->vreg_enabled == true && |
| 3264 | * regulator->current_corner != CPR3_REGULATOR_CORNER_INVALID |
| 3265 | * |
| 3266 | * CPR registers for the controller and each thread are updated as long as |
| 3267 | * ctrl->cpr_enabled == true. |
| 3268 | * |
| 3269 | * Note, CPR3 controller lock must be held by the caller. |
| 3270 | * |
| 3271 | * Return: 0 on success, errno on failure |
| 3272 | */ |
| 3273 | static int _cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl) |
| 3274 | { |
| 3275 | struct cpr3_corner aggr_corner = {}; |
| 3276 | struct cpr3_thread *thread; |
| 3277 | struct cpr3_regulator *vreg; |
| 3278 | struct cpr4_sdelta *sdelta; |
| 3279 | bool valid = false; |
| 3280 | bool thread_valid; |
Channagoud Kadabi | 075db3b | 2017-03-16 14:26:17 -0700 | [diff] [blame] | 3281 | int i, j, rc, new_volt, vdd_volt, dynamic_floor_volt; |
| 3282 | int last_corner_volt = 0; |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 3283 | u32 reg_last_measurement = 0, sdelta_size; |
| 3284 | int *sdelta_table, *boost_table; |
| 3285 | |
| 3286 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 3287 | rc = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 3288 | if (rc) { |
| 3289 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 3290 | rc); |
| 3291 | return rc; |
| 3292 | } |
| 3293 | } |
| 3294 | |
| 3295 | cpr3_ctrl_loop_disable(ctrl); |
| 3296 | |
| 3297 | vdd_volt = regulator_get_voltage(ctrl->vdd_regulator); |
| 3298 | if (vdd_volt < 0) { |
| 3299 | cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n", |
| 3300 | vdd_volt); |
| 3301 | return vdd_volt; |
| 3302 | } |
| 3303 | |
| 3304 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 3305 | /* |
| 3306 | * Save aggregated corner open-loop voltage which was programmed |
| 3307 | * during last corner switch which is used when programming new |
| 3308 | * aggregated corner open-loop voltage. |
| 3309 | */ |
| 3310 | last_corner_volt = ctrl->aggr_corner.open_loop_volt; |
| 3311 | } |
| 3312 | |
| 3313 | if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop && |
| 3314 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) |
| 3315 | reg_last_measurement |
| 3316 | = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT); |
| 3317 | |
| 3318 | aggr_corner.sdelta = ctrl->aggr_corner.sdelta; |
| 3319 | if (aggr_corner.sdelta) { |
| 3320 | sdelta = aggr_corner.sdelta; |
| 3321 | sdelta_table = sdelta->table; |
| 3322 | if (sdelta_table) { |
| 3323 | sdelta_size = sdelta->max_core_count * |
| 3324 | sdelta->temp_band_count; |
| 3325 | memset(sdelta_table, 0, sdelta_size |
| 3326 | * sizeof(*sdelta_table)); |
| 3327 | } |
| 3328 | |
| 3329 | boost_table = sdelta->boost_table; |
| 3330 | if (boost_table) |
| 3331 | memset(boost_table, 0, sdelta->temp_band_count |
| 3332 | * sizeof(*boost_table)); |
| 3333 | |
| 3334 | memset(sdelta, 0, sizeof(*sdelta)); |
| 3335 | sdelta->table = sdelta_table; |
| 3336 | sdelta->cap_volt = INT_MAX; |
| 3337 | sdelta->boost_table = boost_table; |
| 3338 | } |
| 3339 | |
| 3340 | /* Aggregate the requests of all threads */ |
| 3341 | for (i = 0; i < ctrl->thread_count; i++) { |
| 3342 | thread = &ctrl->thread[i]; |
| 3343 | thread_valid = false; |
| 3344 | |
| 3345 | sdelta = thread->aggr_corner.sdelta; |
| 3346 | if (sdelta) { |
| 3347 | sdelta_table = sdelta->table; |
| 3348 | if (sdelta_table) { |
| 3349 | sdelta_size = sdelta->max_core_count * |
| 3350 | sdelta->temp_band_count; |
| 3351 | memset(sdelta_table, 0, sdelta_size |
| 3352 | * sizeof(*sdelta_table)); |
| 3353 | } |
| 3354 | |
| 3355 | boost_table = sdelta->boost_table; |
| 3356 | if (boost_table) |
| 3357 | memset(boost_table, 0, sdelta->temp_band_count |
| 3358 | * sizeof(*boost_table)); |
| 3359 | |
| 3360 | memset(sdelta, 0, sizeof(*sdelta)); |
| 3361 | sdelta->table = sdelta_table; |
| 3362 | sdelta->cap_volt = INT_MAX; |
| 3363 | sdelta->boost_table = boost_table; |
| 3364 | } |
| 3365 | |
| 3366 | memset(&thread->aggr_corner, 0, sizeof(thread->aggr_corner)); |
| 3367 | thread->aggr_corner.sdelta = sdelta; |
| 3368 | thread->aggr_corner.ro_mask = CPR3_RO_MASK; |
| 3369 | |
| 3370 | for (j = 0; j < thread->vreg_count; j++) { |
| 3371 | vreg = &thread->vreg[j]; |
| 3372 | |
| 3373 | if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop) |
| 3374 | cpr3_update_vreg_closed_loop_volt(vreg, |
| 3375 | vdd_volt, reg_last_measurement); |
| 3376 | |
| 3377 | if (!vreg->vreg_enabled |
| 3378 | || vreg->current_corner |
| 3379 | == CPR3_REGULATOR_CORNER_INVALID) { |
| 3380 | /* Cannot participate in aggregation. */ |
| 3381 | vreg->aggregated = false; |
| 3382 | continue; |
| 3383 | } else { |
| 3384 | vreg->aggregated = true; |
| 3385 | thread_valid = true; |
| 3386 | } |
| 3387 | |
| 3388 | cpr3_regulator_aggregate_corners(&thread->aggr_corner, |
| 3389 | &vreg->corner[vreg->current_corner], |
| 3390 | true, ctrl->step_volt); |
| 3391 | } |
| 3392 | |
| 3393 | valid |= thread_valid; |
| 3394 | |
| 3395 | if (thread_valid) |
| 3396 | cpr3_regulator_aggregate_corners(&aggr_corner, |
| 3397 | &thread->aggr_corner, |
| 3398 | false, ctrl->step_volt); |
| 3399 | } |
| 3400 | |
| 3401 | if (valid && ctrl->cpr_allowed_hw && ctrl->cpr_allowed_sw) { |
| 3402 | rc = cpr3_closed_loop_enable(ctrl); |
| 3403 | if (rc) { |
| 3404 | cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc); |
| 3405 | return rc; |
| 3406 | } |
| 3407 | } else { |
| 3408 | rc = cpr3_closed_loop_disable(ctrl); |
| 3409 | if (rc) { |
| 3410 | cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc); |
| 3411 | return rc; |
| 3412 | } |
| 3413 | } |
| 3414 | |
| 3415 | /* No threads are enabled with a valid corner so exit. */ |
| 3416 | if (!valid) |
| 3417 | return 0; |
| 3418 | |
| 3419 | /* |
| 3420 | * When using CPR hardware closed-loop, the voltage may vary anywhere |
| 3421 | * between the floor and ceiling voltage without software notification. |
| 3422 | * Therefore, it is required that the floor to ceiling range for the |
| 3423 | * aggregated corner not intersect the APM threshold voltage. Adjust |
| 3424 | * the floor to ceiling range if this requirement is violated. |
| 3425 | * |
| 3426 | * The following algorithm is applied in the case that |
| 3427 | * floor < threshold <= ceiling: |
| 3428 | * if open_loop >= threshold - adj, then floor = threshold |
| 3429 | * else ceiling = threshold - step |
| 3430 | * where adj = an adjustment factor to ensure sufficient voltage margin |
| 3431 | * and step = VDD output step size |
| 3432 | * |
| 3433 | * The open-loop and last known voltages are also bounded by the new |
| 3434 | * floor or ceiling value as needed. |
| 3435 | */ |
| 3436 | if (ctrl->use_hw_closed_loop |
| 3437 | && aggr_corner.ceiling_volt >= ctrl->apm_threshold_volt |
| 3438 | && aggr_corner.floor_volt < ctrl->apm_threshold_volt) { |
| 3439 | |
| 3440 | if (aggr_corner.open_loop_volt |
| 3441 | >= ctrl->apm_threshold_volt - ctrl->apm_adj_volt) |
| 3442 | aggr_corner.floor_volt = ctrl->apm_threshold_volt; |
| 3443 | else |
| 3444 | aggr_corner.ceiling_volt |
| 3445 | = ctrl->apm_threshold_volt - ctrl->step_volt; |
| 3446 | |
| 3447 | aggr_corner.last_volt |
| 3448 | = max(aggr_corner.last_volt, aggr_corner.floor_volt); |
| 3449 | aggr_corner.last_volt |
| 3450 | = min(aggr_corner.last_volt, aggr_corner.ceiling_volt); |
| 3451 | aggr_corner.open_loop_volt |
| 3452 | = max(aggr_corner.open_loop_volt, aggr_corner.floor_volt); |
| 3453 | aggr_corner.open_loop_volt |
| 3454 | = min(aggr_corner.open_loop_volt, aggr_corner.ceiling_volt); |
| 3455 | } |
| 3456 | |
| 3457 | if (ctrl->use_hw_closed_loop |
| 3458 | && aggr_corner.ceiling_volt >= ctrl->mem_acc_threshold_volt |
| 3459 | && aggr_corner.floor_volt < ctrl->mem_acc_threshold_volt) { |
| 3460 | aggr_corner.floor_volt = ctrl->mem_acc_threshold_volt; |
| 3461 | aggr_corner.last_volt = max(aggr_corner.last_volt, |
| 3462 | aggr_corner.floor_volt); |
| 3463 | aggr_corner.open_loop_volt = max(aggr_corner.open_loop_volt, |
| 3464 | aggr_corner.floor_volt); |
| 3465 | } |
| 3466 | |
| 3467 | if (ctrl->use_hw_closed_loop) { |
| 3468 | dynamic_floor_volt |
| 3469 | = cpr3_regulator_get_dynamic_floor_volt(ctrl, |
| 3470 | reg_last_measurement); |
| 3471 | if (aggr_corner.floor_volt < dynamic_floor_volt) { |
| 3472 | aggr_corner.floor_volt = dynamic_floor_volt; |
| 3473 | aggr_corner.last_volt = max(aggr_corner.last_volt, |
| 3474 | aggr_corner.floor_volt); |
| 3475 | aggr_corner.open_loop_volt |
| 3476 | = max(aggr_corner.open_loop_volt, |
| 3477 | aggr_corner.floor_volt); |
| 3478 | aggr_corner.ceiling_volt = max(aggr_corner.ceiling_volt, |
| 3479 | aggr_corner.floor_volt); |
| 3480 | } |
| 3481 | } |
| 3482 | |
| 3483 | if (ctrl->cpr_enabled && ctrl->last_corner_was_closed_loop) { |
| 3484 | /* |
| 3485 | * Always program open-loop voltage for CPR4 controllers which |
| 3486 | * support hardware closed-loop. Storing the last closed loop |
| 3487 | * voltage in corner structure can still help with debugging. |
| 3488 | */ |
| 3489 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) |
| 3490 | new_volt = aggr_corner.last_volt; |
| 3491 | else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 |
| 3492 | && ctrl->supports_hw_closed_loop) |
| 3493 | new_volt = aggr_corner.open_loop_volt; |
| 3494 | else |
| 3495 | new_volt = min(aggr_corner.last_volt + |
| 3496 | cpr3_regulator_max_sdelta_diff(aggr_corner.sdelta, |
| 3497 | ctrl->step_volt), |
| 3498 | aggr_corner.ceiling_volt); |
| 3499 | } else { |
| 3500 | new_volt = aggr_corner.open_loop_volt; |
| 3501 | aggr_corner.last_volt = aggr_corner.open_loop_volt; |
| 3502 | } |
| 3503 | |
| 3504 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 |
| 3505 | && ctrl->supports_hw_closed_loop) { |
| 3506 | /* |
| 3507 | * Store last aggregated corner open-loop voltage in vdd_volt |
| 3508 | * which is used when programming current aggregated corner |
| 3509 | * required voltage. |
| 3510 | */ |
| 3511 | vdd_volt = last_corner_volt; |
| 3512 | } |
| 3513 | |
| 3514 | cpr3_debug(ctrl, "setting new voltage=%d uV\n", new_volt); |
| 3515 | rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt, |
| 3516 | vdd_volt, &aggr_corner); |
| 3517 | if (rc) { |
| 3518 | cpr3_err(ctrl, "vdd voltage scaling failed, rc=%d\n", rc); |
| 3519 | return rc; |
| 3520 | } |
| 3521 | |
| 3522 | /* Only update registers if CPR is enabled. */ |
| 3523 | if (ctrl->cpr_enabled) { |
| 3524 | if (ctrl->use_hw_closed_loop) { |
| 3525 | /* Hardware closed-loop */ |
| 3526 | |
| 3527 | /* Set ceiling and floor limits in hardware */ |
| 3528 | rc = regulator_set_voltage(ctrl->vdd_limit_regulator, |
| 3529 | aggr_corner.floor_volt, |
| 3530 | aggr_corner.ceiling_volt); |
| 3531 | if (rc) { |
| 3532 | cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n", |
| 3533 | rc); |
| 3534 | return rc; |
| 3535 | } |
| 3536 | } else { |
| 3537 | /* Software closed-loop */ |
| 3538 | |
| 3539 | /* |
| 3540 | * Disable UP or DOWN interrupts when at ceiling or |
| 3541 | * floor respectively. |
| 3542 | */ |
| 3543 | if (new_volt == aggr_corner.floor_volt) |
| 3544 | aggr_corner.irq_en &= ~CPR3_IRQ_DOWN; |
| 3545 | if (new_volt == aggr_corner.ceiling_volt) |
| 3546 | aggr_corner.irq_en &= ~CPR3_IRQ_UP; |
| 3547 | |
| 3548 | cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, |
| 3549 | CPR3_IRQ_UP | CPR3_IRQ_DOWN); |
| 3550 | cpr3_write(ctrl, CPR3_REG_IRQ_EN, aggr_corner.irq_en); |
| 3551 | } |
| 3552 | |
| 3553 | for (i = 0; i < ctrl->thread_count; i++) { |
| 3554 | cpr3_regulator_set_target_quot(&ctrl->thread[i]); |
| 3555 | |
| 3556 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 3557 | vreg = &ctrl->thread[i].vreg[j]; |
| 3558 | |
| 3559 | if (vreg->vreg_enabled) |
| 3560 | vreg->last_closed_loop_corner |
| 3561 | = vreg->current_corner; |
| 3562 | } |
| 3563 | } |
| 3564 | |
| 3565 | if (ctrl->proc_clock_throttle) { |
| 3566 | if (aggr_corner.ceiling_volt > aggr_corner.floor_volt |
| 3567 | && (ctrl->use_hw_closed_loop |
| 3568 | || new_volt < aggr_corner.ceiling_volt)) |
| 3569 | cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, |
| 3570 | ctrl->proc_clock_throttle); |
| 3571 | else |
| 3572 | cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, |
| 3573 | CPR3_PD_THROTTLE_DISABLE); |
| 3574 | } |
| 3575 | |
| 3576 | /* |
| 3577 | * Ensure that all CPR register writes complete before |
| 3578 | * re-enabling CPR loop operation. |
| 3579 | */ |
| 3580 | wmb(); |
| 3581 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 |
| 3582 | && ctrl->vdd_limit_regulator) { |
| 3583 | /* Set ceiling and floor limits in hardware */ |
| 3584 | rc = regulator_set_voltage(ctrl->vdd_limit_regulator, |
| 3585 | aggr_corner.floor_volt, |
| 3586 | aggr_corner.ceiling_volt); |
| 3587 | if (rc) { |
| 3588 | cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n", |
| 3589 | rc); |
| 3590 | return rc; |
| 3591 | } |
| 3592 | } |
| 3593 | |
| 3594 | ctrl->aggr_corner = aggr_corner; |
| 3595 | |
| 3596 | if (ctrl->allow_core_count_adj || ctrl->allow_temp_adj |
| 3597 | || ctrl->allow_boost) { |
| 3598 | rc = cpr3_controller_program_sdelta(ctrl); |
| 3599 | if (rc) { |
| 3600 | cpr3_err(ctrl, "failed to program sdelta, rc=%d\n", rc); |
| 3601 | return rc; |
| 3602 | } |
| 3603 | } |
| 3604 | |
| 3605 | /* |
| 3606 | * Only enable the CPR controller if it is possible to set more than |
| 3607 | * one vdd-supply voltage. |
| 3608 | */ |
| 3609 | if (aggr_corner.ceiling_volt > aggr_corner.floor_volt && |
| 3610 | !aggr_corner.use_open_loop) |
| 3611 | cpr3_ctrl_loop_enable(ctrl); |
| 3612 | |
| 3613 | ctrl->last_corner_was_closed_loop = ctrl->cpr_enabled; |
| 3614 | cpr3_debug(ctrl, "CPR configuration updated\n"); |
| 3615 | |
| 3616 | return 0; |
| 3617 | } |
| 3618 | |
| 3619 | /** |
| 3620 | * cpr3_regulator_wait_for_idle() - wait for the CPR controller to no longer be |
| 3621 | * busy |
| 3622 | * @ctrl: Pointer to the CPR3 controller |
| 3623 | * @max_wait_ns: Max wait time in nanoseconds |
| 3624 | * |
| 3625 | * Return: 0 on success or -ETIMEDOUT if the controller was still busy after |
| 3626 | * the maximum delay time |
| 3627 | */ |
| 3628 | static int cpr3_regulator_wait_for_idle(struct cpr3_controller *ctrl, |
| 3629 | s64 max_wait_ns) |
| 3630 | { |
| 3631 | ktime_t start, end; |
| 3632 | s64 time_ns; |
| 3633 | u32 reg; |
| 3634 | |
| 3635 | /* |
| 3636 | * Ensure that all previous CPR register writes have completed before |
| 3637 | * checking the status register. |
| 3638 | */ |
| 3639 | mb(); |
| 3640 | |
| 3641 | start = ktime_get(); |
| 3642 | do { |
| 3643 | end = ktime_get(); |
| 3644 | time_ns = ktime_to_ns(ktime_sub(end, start)); |
| 3645 | if (time_ns > max_wait_ns) { |
| 3646 | cpr3_err(ctrl, "CPR controller still busy after %lld us\n", |
| 3647 | div_s64(time_ns, 1000)); |
| 3648 | return -ETIMEDOUT; |
| 3649 | } |
| 3650 | usleep_range(50, 100); |
| 3651 | reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); |
| 3652 | } while (reg & CPR3_CPR_STATUS_BUSY_MASK); |
| 3653 | |
| 3654 | return 0; |
| 3655 | } |
| 3656 | |
| 3657 | /** |
| 3658 | * cmp_int() - int comparison function to be passed into the sort() function |
| 3659 | * which leads to ascending sorting |
| 3660 | * @a: First int value |
| 3661 | * @b: Second int value |
| 3662 | * |
| 3663 | * Return: >0 if a > b, 0 if a == b, <0 if a < b |
| 3664 | */ |
| 3665 | static int cmp_int(const void *a, const void *b) |
| 3666 | { |
| 3667 | return *(int *)a - *(int *)b; |
| 3668 | } |
| 3669 | |
| 3670 | /** |
| 3671 | * cpr3_regulator_measure_aging() - measure the quotient difference for the |
| 3672 | * specified CPR aging sensor |
| 3673 | * @ctrl: Pointer to the CPR3 controller |
| 3674 | * @aging_sensor: Aging sensor to measure |
| 3675 | * |
| 3676 | * Note that vdd-supply must be configured to the aging reference voltage before |
| 3677 | * calling this function. |
| 3678 | * |
| 3679 | * Return: 0 on success, errno on failure |
| 3680 | */ |
| 3681 | static int cpr3_regulator_measure_aging(struct cpr3_controller *ctrl, |
| 3682 | struct cpr3_aging_sensor_info *aging_sensor) |
| 3683 | { |
| 3684 | u32 mask, reg, result, quot_min, quot_max, sel_min, sel_max; |
| 3685 | u32 quot_min_scaled, quot_max_scaled; |
| 3686 | u32 gcnt, gcnt_ref, gcnt0_restore, gcnt1_restore, irq_restore; |
| 3687 | u32 ro_mask_restore, cont_dly_restore, up_down_dly_restore = 0; |
| 3688 | int quot_delta, quot_delta_scaled, quot_delta_scaled_sum; |
| 3689 | int *quot_delta_results; |
| 3690 | int rc, rc2, i, aging_measurement_count, filtered_count; |
| 3691 | bool is_aging_measurement; |
| 3692 | |
| 3693 | quot_delta_results = kcalloc(CPR3_AGING_MEASUREMENT_ITERATIONS, |
| 3694 | sizeof(*quot_delta_results), GFP_KERNEL); |
| 3695 | if (!quot_delta_results) |
| 3696 | return -ENOMEM; |
| 3697 | |
| 3698 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 3699 | rc = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 3700 | if (rc) { |
| 3701 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 3702 | rc); |
| 3703 | kfree(quot_delta_results); |
| 3704 | return rc; |
| 3705 | } |
| 3706 | } |
| 3707 | |
| 3708 | cpr3_ctrl_loop_disable(ctrl); |
| 3709 | |
| 3710 | /* Enable up, down, and mid CPR interrupts */ |
| 3711 | irq_restore = cpr3_read(ctrl, CPR3_REG_IRQ_EN); |
| 3712 | cpr3_write(ctrl, CPR3_REG_IRQ_EN, |
| 3713 | CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID); |
| 3714 | |
| 3715 | /* Ensure that the aging sensor is assigned to CPR thread 0 */ |
| 3716 | cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), 0); |
| 3717 | |
| 3718 | /* Switch from HW to SW closed-loop if necessary */ |
| 3719 | if (ctrl->supports_hw_closed_loop) { |
| 3720 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 || |
| 3721 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 3722 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 3723 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 3724 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); |
| 3725 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 3726 | cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, |
| 3727 | CPR3_HW_CLOSED_LOOP_DISABLE); |
| 3728 | } |
| 3729 | } |
| 3730 | |
| 3731 | /* Configure the GCNT for RO0 and RO1 that are used for aging */ |
| 3732 | gcnt0_restore = cpr3_read(ctrl, CPR3_REG_GCNT(0)); |
| 3733 | gcnt1_restore = cpr3_read(ctrl, CPR3_REG_GCNT(1)); |
| 3734 | gcnt_ref = cpr3_regulator_get_gcnt(ctrl); |
| 3735 | gcnt = gcnt_ref * 3 / 2; |
| 3736 | cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt); |
| 3737 | cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt); |
| 3738 | |
| 3739 | /* Unmask all RO's */ |
| 3740 | ro_mask_restore = cpr3_read(ctrl, CPR3_REG_RO_MASK(0)); |
| 3741 | cpr3_write(ctrl, CPR3_REG_RO_MASK(0), 0); |
| 3742 | |
| 3743 | /* |
| 3744 | * Mask all sensors except for the one to measure and bypass all |
| 3745 | * sensors in collapsible domains. |
| 3746 | */ |
| 3747 | for (i = 0; i <= ctrl->sensor_count / 32; i++) { |
| 3748 | mask = GENMASK(min(31, ctrl->sensor_count - i * 32), 0); |
| 3749 | if (aging_sensor->sensor_id / 32 >= i |
| 3750 | && aging_sensor->sensor_id / 32 < (i + 1)) |
| 3751 | mask &= ~BIT(aging_sensor->sensor_id % 32); |
| 3752 | cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), mask); |
| 3753 | cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), |
| 3754 | aging_sensor->bypass_mask[i]); |
| 3755 | } |
| 3756 | |
| 3757 | /* Set CPR loop delays to 0 us */ |
| 3758 | if (ctrl->supports_hw_closed_loop |
| 3759 | && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 3760 | cont_dly_restore = cpr3_read(ctrl, CPR3_REG_CPR_TIMER_MID_CONT); |
| 3761 | up_down_dly_restore = cpr3_read(ctrl, |
| 3762 | CPR3_REG_CPR_TIMER_UP_DN_CONT); |
| 3763 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, 0); |
| 3764 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, 0); |
| 3765 | } else { |
| 3766 | cont_dly_restore = cpr3_read(ctrl, |
| 3767 | CPR3_REG_CPR_TIMER_AUTO_CONT); |
| 3768 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, 0); |
| 3769 | } |
| 3770 | |
| 3771 | /* Set count mode to all-at-once min with no repeat */ |
| 3772 | cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, |
| 3773 | CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK, |
| 3774 | CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN |
| 3775 | << CPR3_CPR_CTL_COUNT_MODE_SHIFT); |
| 3776 | |
| 3777 | cpr3_ctrl_loop_enable(ctrl); |
| 3778 | |
| 3779 | rc = cpr3_regulator_wait_for_idle(ctrl, |
| 3780 | CPR3_AGING_MEASUREMENT_TIMEOUT_NS); |
| 3781 | if (rc) |
| 3782 | goto cleanup; |
| 3783 | |
| 3784 | /* Set count mode to all-at-once aging */ |
| 3785 | cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, CPR3_CPR_CTL_COUNT_MODE_MASK, |
| 3786 | CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE |
| 3787 | << CPR3_CPR_CTL_COUNT_MODE_SHIFT); |
| 3788 | |
| 3789 | aging_measurement_count = 0; |
| 3790 | for (i = 0; i < CPR3_AGING_MEASUREMENT_ITERATIONS; i++) { |
| 3791 | /* Send CONT_NACK */ |
| 3792 | cpr3_write(ctrl, CPR3_REG_CONT_CMD, CPR3_CONT_CMD_NACK); |
| 3793 | |
| 3794 | rc = cpr3_regulator_wait_for_idle(ctrl, |
| 3795 | CPR3_AGING_MEASUREMENT_TIMEOUT_NS); |
| 3796 | if (rc) |
| 3797 | goto cleanup; |
| 3798 | |
| 3799 | /* Check for PAGE_IS_AGE flag in status register */ |
| 3800 | reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); |
| 3801 | is_aging_measurement |
| 3802 | = reg & CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK; |
| 3803 | |
| 3804 | /* Read CPR measurement results */ |
| 3805 | result = cpr3_read(ctrl, CPR3_REG_RESULT1(0)); |
| 3806 | quot_min = (result & CPR3_RESULT1_QUOT_MIN_MASK) |
| 3807 | >> CPR3_RESULT1_QUOT_MIN_SHIFT; |
| 3808 | quot_max = (result & CPR3_RESULT1_QUOT_MAX_MASK) |
| 3809 | >> CPR3_RESULT1_QUOT_MAX_SHIFT; |
| 3810 | sel_min = (result & CPR3_RESULT1_RO_MIN_MASK) |
| 3811 | >> CPR3_RESULT1_RO_MIN_SHIFT; |
| 3812 | sel_max = (result & CPR3_RESULT1_RO_MAX_MASK) |
| 3813 | >> CPR3_RESULT1_RO_MAX_SHIFT; |
| 3814 | |
| 3815 | /* |
| 3816 | * Scale the quotients so that they are equivalent to the fused |
| 3817 | * values. This accounts for the difference in measurement |
| 3818 | * interval times. |
| 3819 | */ |
| 3820 | quot_min_scaled = quot_min * (gcnt_ref + 1) / (gcnt + 1); |
| 3821 | quot_max_scaled = quot_max * (gcnt_ref + 1) / (gcnt + 1); |
| 3822 | |
| 3823 | if (sel_max == 1) { |
| 3824 | quot_delta = quot_max - quot_min; |
| 3825 | quot_delta_scaled = quot_max_scaled - quot_min_scaled; |
| 3826 | } else { |
| 3827 | quot_delta = quot_min - quot_max; |
| 3828 | quot_delta_scaled = quot_min_scaled - quot_max_scaled; |
| 3829 | } |
| 3830 | |
| 3831 | if (is_aging_measurement) |
| 3832 | quot_delta_results[aging_measurement_count++] |
| 3833 | = quot_delta_scaled; |
| 3834 | |
| 3835 | cpr3_debug(ctrl, "aging results: page_is_age=%u, sel_min=%u, sel_max=%u, quot_min=%u, quot_max=%u, quot_delta=%d, quot_min_scaled=%u, quot_max_scaled=%u, quot_delta_scaled=%d\n", |
| 3836 | is_aging_measurement, sel_min, sel_max, quot_min, |
| 3837 | quot_max, quot_delta, quot_min_scaled, quot_max_scaled, |
| 3838 | quot_delta_scaled); |
| 3839 | } |
| 3840 | |
| 3841 | filtered_count |
| 3842 | = aging_measurement_count - CPR3_AGING_MEASUREMENT_FILTER * 2; |
| 3843 | if (filtered_count > 0) { |
| 3844 | sort(quot_delta_results, aging_measurement_count, |
| 3845 | sizeof(*quot_delta_results), cmp_int, NULL); |
| 3846 | |
| 3847 | quot_delta_scaled_sum = 0; |
| 3848 | for (i = 0; i < filtered_count; i++) |
| 3849 | quot_delta_scaled_sum |
| 3850 | += quot_delta_results[i |
| 3851 | + CPR3_AGING_MEASUREMENT_FILTER]; |
| 3852 | |
| 3853 | aging_sensor->measured_quot_diff |
| 3854 | = quot_delta_scaled_sum / filtered_count; |
| 3855 | cpr3_info(ctrl, "average quotient delta=%d (count=%d)\n", |
| 3856 | aging_sensor->measured_quot_diff, |
| 3857 | filtered_count); |
| 3858 | } else { |
| 3859 | cpr3_err(ctrl, "%d aging measurements completed after %d iterations\n", |
| 3860 | aging_measurement_count, |
| 3861 | CPR3_AGING_MEASUREMENT_ITERATIONS); |
| 3862 | rc = -EBUSY; |
| 3863 | } |
| 3864 | |
| 3865 | cleanup: |
| 3866 | kfree(quot_delta_results); |
| 3867 | |
| 3868 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 3869 | rc2 = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 3870 | if (rc2) { |
| 3871 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 3872 | rc2); |
| 3873 | rc = rc2; |
| 3874 | } |
| 3875 | } |
| 3876 | |
| 3877 | cpr3_ctrl_loop_disable(ctrl); |
| 3878 | |
| 3879 | cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_restore); |
| 3880 | |
| 3881 | cpr3_write(ctrl, CPR3_REG_RO_MASK(0), ro_mask_restore); |
| 3882 | |
| 3883 | cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt0_restore); |
| 3884 | cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt1_restore); |
| 3885 | |
| 3886 | if (ctrl->supports_hw_closed_loop |
| 3887 | && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 3888 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly_restore); |
| 3889 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, |
| 3890 | up_down_dly_restore); |
| 3891 | } else { |
| 3892 | cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, |
| 3893 | cont_dly_restore); |
| 3894 | } |
| 3895 | |
| 3896 | for (i = 0; i <= ctrl->sensor_count / 32; i++) { |
| 3897 | cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), 0); |
| 3898 | cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), 0); |
| 3899 | } |
| 3900 | |
| 3901 | cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, |
| 3902 | CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK, |
| 3903 | (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT) |
| 3904 | | (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT)); |
| 3905 | |
| 3906 | cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), |
| 3907 | ctrl->sensor_owner[aging_sensor->sensor_id]); |
| 3908 | |
| 3909 | cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, |
| 3910 | CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID); |
| 3911 | |
| 3912 | if (ctrl->supports_hw_closed_loop) { |
| 3913 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4 || |
| 3914 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 3915 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 3916 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 3917 | ctrl->use_hw_closed_loop |
| 3918 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE |
| 3919 | : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); |
| 3920 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 3921 | cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, |
| 3922 | ctrl->use_hw_closed_loop |
| 3923 | ? CPR3_HW_CLOSED_LOOP_ENABLE |
| 3924 | : CPR3_HW_CLOSED_LOOP_DISABLE); |
| 3925 | } |
| 3926 | } |
| 3927 | |
| 3928 | return rc; |
| 3929 | } |
| 3930 | |
| 3931 | /** |
| 3932 | * cpr3_regulator_readjust_volt_and_quot() - readjust the target quotients as |
| 3933 | * well as the floor, ceiling, and open-loop voltages for the |
| 3934 | * regulator by removing the old adjustment and adding the new one |
| 3935 | * @vreg: Pointer to the CPR3 regulator |
| 3936 | * @old_adjust_volt: Old aging adjustment voltage in microvolts |
| 3937 | * @new_adjust_volt: New aging adjustment voltage in microvolts |
| 3938 | * |
| 3939 | * Also reset the cached closed loop voltage (last_volt) to equal the open-loop |
| 3940 | * voltage for each corner. |
| 3941 | * |
| 3942 | * Return: None |
| 3943 | */ |
| 3944 | static void cpr3_regulator_readjust_volt_and_quot(struct cpr3_regulator *vreg, |
| 3945 | int old_adjust_volt, int new_adjust_volt) |
| 3946 | { |
| 3947 | unsigned long long temp; |
| 3948 | int i, j, old_volt, new_volt, rounded_volt; |
| 3949 | |
| 3950 | if (!vreg->aging_allowed) |
| 3951 | return; |
| 3952 | |
| 3953 | for (i = 0; i < vreg->corner_count; i++) { |
| 3954 | temp = (unsigned long long)old_adjust_volt |
| 3955 | * (unsigned long long)vreg->corner[i].aging_derate; |
| 3956 | do_div(temp, 1000); |
| 3957 | old_volt = temp; |
| 3958 | |
| 3959 | temp = (unsigned long long)new_adjust_volt |
| 3960 | * (unsigned long long)vreg->corner[i].aging_derate; |
| 3961 | do_div(temp, 1000); |
| 3962 | new_volt = temp; |
| 3963 | |
| 3964 | old_volt = min(vreg->aging_max_adjust_volt, old_volt); |
| 3965 | new_volt = min(vreg->aging_max_adjust_volt, new_volt); |
| 3966 | |
| 3967 | for (j = 0; j < CPR3_RO_COUNT; j++) { |
| 3968 | if (vreg->corner[i].target_quot[j] != 0) { |
| 3969 | vreg->corner[i].target_quot[j] |
| 3970 | += cpr3_quot_adjustment( |
| 3971 | vreg->corner[i].ro_scale[j], |
| 3972 | new_volt) |
| 3973 | - cpr3_quot_adjustment( |
| 3974 | vreg->corner[i].ro_scale[j], |
| 3975 | old_volt); |
| 3976 | } |
| 3977 | } |
| 3978 | |
| 3979 | rounded_volt = CPR3_ROUND(new_volt, |
| 3980 | vreg->thread->ctrl->step_volt); |
| 3981 | |
| 3982 | if (!vreg->aging_allow_open_loop_adj) |
| 3983 | rounded_volt = 0; |
| 3984 | |
| 3985 | vreg->corner[i].ceiling_volt |
| 3986 | = vreg->corner[i].unaged_ceiling_volt + rounded_volt; |
| 3987 | vreg->corner[i].ceiling_volt = min(vreg->corner[i].ceiling_volt, |
| 3988 | vreg->corner[i].abs_ceiling_volt); |
| 3989 | vreg->corner[i].floor_volt |
| 3990 | = vreg->corner[i].unaged_floor_volt + rounded_volt; |
| 3991 | vreg->corner[i].floor_volt = min(vreg->corner[i].floor_volt, |
| 3992 | vreg->corner[i].ceiling_volt); |
| 3993 | vreg->corner[i].open_loop_volt |
| 3994 | = vreg->corner[i].unaged_open_loop_volt + rounded_volt; |
| 3995 | vreg->corner[i].open_loop_volt |
| 3996 | = min(vreg->corner[i].open_loop_volt, |
| 3997 | vreg->corner[i].ceiling_volt); |
| 3998 | |
| 3999 | vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt; |
| 4000 | |
| 4001 | cpr3_debug(vreg, "corner %d: applying %d uV closed-loop and %d uV open-loop voltage margin adjustment\n", |
| 4002 | i, new_volt, rounded_volt); |
| 4003 | } |
| 4004 | } |
| 4005 | |
| 4006 | /** |
| 4007 | * cpr3_regulator_set_aging_ref_adjustment() - adjust target quotients for the |
| 4008 | * regulators managed by this CPR controller to account for aging |
| 4009 | * @ctrl: Pointer to the CPR3 controller |
| 4010 | * @ref_adjust_volt: New aging reference adjustment voltage in microvolts to |
| 4011 | * apply to all regulators managed by this CPR controller |
| 4012 | * |
| 4013 | * The existing aging adjustment as defined by ctrl->aging_ref_adjust_volt is |
| 4014 | * first removed and then the adjustment is applied. Lastly, the value of |
| 4015 | * ctrl->aging_ref_adjust_volt is updated to ref_adjust_volt. |
| 4016 | */ |
| 4017 | static void cpr3_regulator_set_aging_ref_adjustment( |
| 4018 | struct cpr3_controller *ctrl, int ref_adjust_volt) |
| 4019 | { |
| 4020 | struct cpr3_regulator *vreg; |
| 4021 | int i, j; |
| 4022 | |
| 4023 | for (i = 0; i < ctrl->thread_count; i++) { |
| 4024 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 4025 | vreg = &ctrl->thread[i].vreg[j]; |
| 4026 | cpr3_regulator_readjust_volt_and_quot(vreg, |
| 4027 | ctrl->aging_ref_adjust_volt, ref_adjust_volt); |
| 4028 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) |
| 4029 | cprh_adjust_voltages_for_apm(vreg); |
| 4030 | } |
| 4031 | } |
| 4032 | |
| 4033 | ctrl->aging_ref_adjust_volt = ref_adjust_volt; |
| 4034 | } |
| 4035 | |
| 4036 | /** |
| 4037 | * cpr3_regulator_aging_adjust() - adjust the target quotients for regulators |
| 4038 | * based on the output of CPR aging sensors |
| 4039 | * @ctrl: Pointer to the CPR3 controller |
| 4040 | * |
| 4041 | * Return: 0 on success, errno on failure |
| 4042 | */ |
| 4043 | static int cpr3_regulator_aging_adjust(struct cpr3_controller *ctrl) |
| 4044 | { |
| 4045 | struct cpr3_regulator *vreg; |
| 4046 | struct cpr3_corner restore_aging_corner; |
| 4047 | struct cpr3_corner *corner; |
| 4048 | int *restore_current_corner; |
| 4049 | bool *restore_vreg_enabled; |
| 4050 | int i, j, id, rc, rc2, vreg_count, aging_volt, max_aging_volt = 0; |
| 4051 | u32 reg; |
| 4052 | |
| 4053 | if (!ctrl->aging_required || !ctrl->cpr_enabled |
| 4054 | || ctrl->aggr_corner.ceiling_volt == 0 |
| 4055 | || ctrl->aggr_corner.ceiling_volt > ctrl->aging_ref_volt) |
| 4056 | return 0; |
| 4057 | |
| 4058 | for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { |
| 4059 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 4060 | vreg = &ctrl->thread[i].vreg[j]; |
| 4061 | vreg_count++; |
| 4062 | |
| 4063 | if (vreg->aging_allowed && vreg->vreg_enabled |
| 4064 | && vreg->current_corner > vreg->aging_corner) |
| 4065 | return 0; |
| 4066 | } |
| 4067 | } |
| 4068 | |
| 4069 | /* Verify that none of the aging sensors are currently masked. */ |
| 4070 | for (i = 0; i < ctrl->aging_sensor_count; i++) { |
| 4071 | id = ctrl->aging_sensor[i].sensor_id; |
| 4072 | reg = cpr3_read(ctrl, CPR3_REG_SENSOR_MASK_READ(id)); |
| 4073 | if (reg & BIT(id % 32)) |
| 4074 | return 0; |
| 4075 | } |
| 4076 | |
| 4077 | /* |
| 4078 | * Verify that the aging possible register (if specified) has an |
| 4079 | * acceptable value. |
| 4080 | */ |
| 4081 | if (ctrl->aging_possible_reg) { |
| 4082 | reg = readl_relaxed(ctrl->aging_possible_reg); |
| 4083 | reg &= ctrl->aging_possible_mask; |
| 4084 | if (reg != ctrl->aging_possible_val) |
| 4085 | return 0; |
| 4086 | } |
| 4087 | |
| 4088 | restore_current_corner = kcalloc(vreg_count, |
| 4089 | sizeof(*restore_current_corner), GFP_KERNEL); |
| 4090 | restore_vreg_enabled = kcalloc(vreg_count, |
| 4091 | sizeof(*restore_vreg_enabled), GFP_KERNEL); |
| 4092 | if (!restore_current_corner || !restore_vreg_enabled) { |
| 4093 | kfree(restore_current_corner); |
| 4094 | kfree(restore_vreg_enabled); |
| 4095 | return -ENOMEM; |
| 4096 | } |
| 4097 | |
| 4098 | /* Force all regulators to the aging corner */ |
| 4099 | for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { |
| 4100 | for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) { |
| 4101 | vreg = &ctrl->thread[i].vreg[j]; |
| 4102 | |
| 4103 | restore_current_corner[vreg_count] |
| 4104 | = vreg->current_corner; |
| 4105 | restore_vreg_enabled[vreg_count] |
| 4106 | = vreg->vreg_enabled; |
| 4107 | |
| 4108 | vreg->current_corner = vreg->aging_corner; |
| 4109 | vreg->vreg_enabled = true; |
| 4110 | } |
| 4111 | } |
| 4112 | |
| 4113 | /* Force one of the regulators to require the aging reference voltage */ |
| 4114 | vreg = &ctrl->thread[0].vreg[0]; |
| 4115 | corner = &vreg->corner[vreg->current_corner]; |
| 4116 | restore_aging_corner = *corner; |
| 4117 | corner->ceiling_volt = ctrl->aging_ref_volt; |
| 4118 | corner->floor_volt = ctrl->aging_ref_volt; |
| 4119 | corner->open_loop_volt = ctrl->aging_ref_volt; |
| 4120 | corner->last_volt = ctrl->aging_ref_volt; |
| 4121 | |
| 4122 | /* Skip last_volt caching */ |
| 4123 | ctrl->last_corner_was_closed_loop = false; |
| 4124 | |
| 4125 | /* Set the vdd supply voltage to the aging reference voltage */ |
| 4126 | rc = _cpr3_regulator_update_ctrl_state(ctrl); |
| 4127 | if (rc) { |
| 4128 | cpr3_err(ctrl, "unable to force vdd-supply to the aging reference voltage=%d uV, rc=%d\n", |
| 4129 | ctrl->aging_ref_volt, rc); |
| 4130 | goto cleanup; |
| 4131 | } |
| 4132 | |
| 4133 | if (ctrl->aging_vdd_mode) { |
| 4134 | rc = regulator_set_mode(ctrl->vdd_regulator, |
| 4135 | ctrl->aging_vdd_mode); |
| 4136 | if (rc) { |
| 4137 | cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", |
| 4138 | ctrl->aging_vdd_mode, rc); |
| 4139 | goto cleanup; |
| 4140 | } |
| 4141 | } |
| 4142 | |
| 4143 | /* Perform aging measurement on all aging sensors */ |
| 4144 | for (i = 0; i < ctrl->aging_sensor_count; i++) { |
| 4145 | for (j = 0; j < CPR3_AGING_RETRY_COUNT; j++) { |
| 4146 | rc = cpr3_regulator_measure_aging(ctrl, |
| 4147 | &ctrl->aging_sensor[i]); |
| 4148 | if (!rc) |
| 4149 | break; |
| 4150 | } |
| 4151 | |
| 4152 | if (!rc) { |
| 4153 | aging_volt = |
| 4154 | cpr3_voltage_adjustment( |
| 4155 | ctrl->aging_sensor[i].ro_scale, |
| 4156 | ctrl->aging_sensor[i].measured_quot_diff |
| 4157 | - ctrl->aging_sensor[i].init_quot_diff); |
| 4158 | max_aging_volt = max(max_aging_volt, aging_volt); |
| 4159 | } else { |
| 4160 | cpr3_err(ctrl, "CPR aging measurement failed after %d tries, rc=%d\n", |
| 4161 | j, rc); |
| 4162 | ctrl->aging_failed = true; |
| 4163 | ctrl->aging_required = false; |
| 4164 | goto cleanup; |
| 4165 | } |
| 4166 | } |
| 4167 | |
| 4168 | cleanup: |
| 4169 | vreg = &ctrl->thread[0].vreg[0]; |
| 4170 | vreg->corner[vreg->current_corner] = restore_aging_corner; |
| 4171 | |
| 4172 | for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) { |
| 4173 | for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) { |
| 4174 | vreg = &ctrl->thread[i].vreg[j]; |
| 4175 | vreg->current_corner |
| 4176 | = restore_current_corner[vreg_count]; |
| 4177 | vreg->vreg_enabled = restore_vreg_enabled[vreg_count]; |
| 4178 | } |
| 4179 | } |
| 4180 | |
| 4181 | kfree(restore_current_corner); |
| 4182 | kfree(restore_vreg_enabled); |
| 4183 | |
| 4184 | /* Adjust the CPR target quotients according to the aging measurement */ |
| 4185 | if (!rc) { |
| 4186 | cpr3_regulator_set_aging_ref_adjustment(ctrl, max_aging_volt); |
| 4187 | |
| 4188 | cpr3_info(ctrl, "aging measurement successful; aging reference adjustment voltage=%d uV\n", |
| 4189 | ctrl->aging_ref_adjust_volt); |
| 4190 | ctrl->aging_succeeded = true; |
| 4191 | ctrl->aging_required = false; |
| 4192 | } |
| 4193 | |
| 4194 | if (ctrl->aging_complete_vdd_mode) { |
| 4195 | rc = regulator_set_mode(ctrl->vdd_regulator, |
| 4196 | ctrl->aging_complete_vdd_mode); |
| 4197 | if (rc) |
| 4198 | cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", |
| 4199 | ctrl->aging_complete_vdd_mode, rc); |
| 4200 | } |
| 4201 | |
| 4202 | /* Skip last_volt caching */ |
| 4203 | ctrl->last_corner_was_closed_loop = false; |
| 4204 | |
| 4205 | /* |
| 4206 | * Restore vdd-supply to the voltage before the aging measurement and |
| 4207 | * restore the CPR3 controller hardware state. |
| 4208 | */ |
| 4209 | rc2 = _cpr3_regulator_update_ctrl_state(ctrl); |
| 4210 | |
| 4211 | /* Stop last_volt caching on for the next request */ |
| 4212 | ctrl->last_corner_was_closed_loop = false; |
| 4213 | |
| 4214 | return rc ? rc : rc2; |
| 4215 | } |
| 4216 | |
| 4217 | /** |
| 4218 | * cprh_regulator_aging_adjust() - adjust the target quotients and open-loop |
| 4219 | * voltages for CPRh regulators based on the output of CPR aging |
| 4220 | * sensors |
| 4221 | * @ctrl: Pointer to the CPR3 controller |
| 4222 | * |
| 4223 | * Return: 0 on success, errno on failure |
| 4224 | */ |
| 4225 | static int cprh_regulator_aging_adjust(struct cpr3_controller *ctrl) |
| 4226 | { |
| 4227 | int i, j, id, rc, rc2, aging_volt, init_volt; |
| 4228 | int max_aging_volt = 0; |
| 4229 | u32 reg; |
| 4230 | |
| 4231 | if (!ctrl->aging_required || !ctrl->cpr_enabled) |
| 4232 | return 0; |
| 4233 | |
| 4234 | if (!ctrl->vdd_regulator) { |
| 4235 | cpr3_err(ctrl, "vdd-supply regulator missing\n"); |
| 4236 | return -ENODEV; |
| 4237 | } |
| 4238 | |
| 4239 | init_volt = regulator_get_voltage(ctrl->vdd_regulator); |
| 4240 | if (init_volt < 0) { |
| 4241 | cpr3_err(ctrl, "could not get vdd-supply voltage, rc=%d\n", |
| 4242 | init_volt); |
| 4243 | return init_volt; |
| 4244 | } |
| 4245 | |
| 4246 | if (init_volt > ctrl->aging_ref_volt) { |
| 4247 | cpr3_info(ctrl, "unable to perform CPR aging measurement as vdd=%d uV > aging voltage=%d uV\n", |
| 4248 | init_volt, ctrl->aging_ref_volt); |
| 4249 | return 0; |
| 4250 | } |
| 4251 | |
| 4252 | /* Verify that none of the aging sensors are currently masked. */ |
| 4253 | for (i = 0; i < ctrl->aging_sensor_count; i++) { |
| 4254 | id = ctrl->aging_sensor[i].sensor_id; |
| 4255 | reg = cpr3_read(ctrl, CPR3_REG_SENSOR_MASK_READ(id)); |
| 4256 | if (reg & BIT(id % 32)) { |
| 4257 | cpr3_info(ctrl, "unable to perform CPR aging measurement as CPR sensor %d is masked\n", |
| 4258 | id); |
| 4259 | return 0; |
| 4260 | } |
| 4261 | } |
| 4262 | |
| 4263 | rc = regulator_set_voltage(ctrl->vdd_regulator, ctrl->aging_ref_volt, |
| 4264 | INT_MAX); |
| 4265 | if (rc) { |
| 4266 | cpr3_err(ctrl, "unable to set vdd-supply to aging voltage=%d uV, rc=%d\n", |
| 4267 | ctrl->aging_ref_volt, rc); |
| 4268 | return rc; |
| 4269 | } |
| 4270 | |
| 4271 | if (ctrl->aging_vdd_mode) { |
| 4272 | rc = regulator_set_mode(ctrl->vdd_regulator, |
| 4273 | ctrl->aging_vdd_mode); |
| 4274 | if (rc) { |
| 4275 | cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", |
| 4276 | ctrl->aging_vdd_mode, rc); |
| 4277 | goto cleanup; |
| 4278 | } |
| 4279 | } |
| 4280 | |
| 4281 | /* Perform aging measurement on all aging sensors */ |
| 4282 | for (i = 0; i < ctrl->aging_sensor_count; i++) { |
| 4283 | for (j = 0; j < CPR3_AGING_RETRY_COUNT; j++) { |
| 4284 | rc = cpr3_regulator_measure_aging(ctrl, |
| 4285 | &ctrl->aging_sensor[i]); |
| 4286 | if (!rc) |
| 4287 | break; |
| 4288 | } |
| 4289 | |
| 4290 | if (!rc) { |
| 4291 | aging_volt = |
| 4292 | cpr3_voltage_adjustment( |
| 4293 | ctrl->aging_sensor[i].ro_scale, |
| 4294 | ctrl->aging_sensor[i].measured_quot_diff |
| 4295 | - ctrl->aging_sensor[i].init_quot_diff); |
| 4296 | max_aging_volt = max(max_aging_volt, aging_volt); |
| 4297 | } else { |
| 4298 | cpr3_err(ctrl, "CPR aging measurement failed after %d tries, rc=%d\n", |
| 4299 | j, rc); |
| 4300 | ctrl->aging_failed = true; |
| 4301 | ctrl->aging_required = false; |
| 4302 | goto cleanup; |
| 4303 | } |
| 4304 | } |
| 4305 | |
| 4306 | cleanup: |
| 4307 | /* Adjust the CPR target quotients according to the aging measurement */ |
| 4308 | if (!rc) { |
| 4309 | cpr3_regulator_set_aging_ref_adjustment(ctrl, max_aging_volt); |
| 4310 | |
| 4311 | cpr3_info(ctrl, "aging measurement successful; aging reference adjustment voltage=%d uV\n", |
| 4312 | ctrl->aging_ref_adjust_volt); |
| 4313 | ctrl->aging_succeeded = true; |
| 4314 | ctrl->aging_required = false; |
| 4315 | } |
| 4316 | |
| 4317 | rc2 = regulator_set_voltage(ctrl->vdd_regulator, init_volt, INT_MAX); |
| 4318 | if (rc2) { |
| 4319 | cpr3_err(ctrl, "unable to reset vdd-supply to initial voltage=%d uV, rc=%d\n", |
| 4320 | init_volt, rc2); |
| 4321 | return rc2; |
| 4322 | } |
| 4323 | |
| 4324 | if (ctrl->aging_complete_vdd_mode) { |
| 4325 | rc2 = regulator_set_mode(ctrl->vdd_regulator, |
| 4326 | ctrl->aging_complete_vdd_mode); |
| 4327 | if (rc2) { |
| 4328 | cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n", |
| 4329 | ctrl->aging_complete_vdd_mode, rc2); |
| 4330 | return rc2; |
| 4331 | } |
| 4332 | } |
| 4333 | |
| 4334 | return rc; |
| 4335 | } |
| 4336 | |
| 4337 | /** |
| 4338 | * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller |
| 4339 | * to reflect the corners used by all CPR3 regulators as well as |
| 4340 | * the CPR operating mode and perform aging adjustments if needed |
| 4341 | * @ctrl: Pointer to the CPR3 controller |
| 4342 | * |
| 4343 | * Note, CPR3 controller lock must be held by the caller. |
| 4344 | * |
| 4345 | * Return: 0 on success, errno on failure |
| 4346 | */ |
| 4347 | static int cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl) |
| 4348 | { |
| 4349 | int rc; |
| 4350 | |
| 4351 | rc = _cpr3_regulator_update_ctrl_state(ctrl); |
| 4352 | if (rc) |
| 4353 | return rc; |
| 4354 | |
| 4355 | return cpr3_regulator_aging_adjust(ctrl); |
| 4356 | } |
| 4357 | |
| 4358 | /** |
| 4359 | * cpr3_regulator_set_voltage() - set the voltage corner for the CPR3 regulator |
| 4360 | * associated with the regulator device |
| 4361 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4362 | * @corner: New voltage corner to set (offset by CPR3_CORNER_OFFSET) |
| 4363 | * @corner_max: Maximum voltage corner allowed (offset by |
| 4364 | * CPR3_CORNER_OFFSET) |
| 4365 | * @selector: Pointer which is filled with the selector value for the |
| 4366 | * corner |
| 4367 | * |
| 4368 | * This function is passed as a callback function into the regulator ops that |
| 4369 | * are registered for each cpr3-regulator device. The VDD voltage will not be |
| 4370 | * physically configured until both this function and cpr3_regulator_enable() |
| 4371 | * are called. |
| 4372 | * |
| 4373 | * Return: 0 on success, errno on failure |
| 4374 | */ |
| 4375 | static int cpr3_regulator_set_voltage(struct regulator_dev *rdev, |
| 4376 | int corner, int corner_max, unsigned int *selector) |
| 4377 | { |
| 4378 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4379 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 4380 | int rc = 0; |
| 4381 | int last_corner; |
| 4382 | |
| 4383 | corner -= CPR3_CORNER_OFFSET; |
| 4384 | corner_max -= CPR3_CORNER_OFFSET; |
| 4385 | *selector = corner; |
| 4386 | |
| 4387 | mutex_lock(&ctrl->lock); |
| 4388 | |
| 4389 | if (!vreg->vreg_enabled) { |
| 4390 | vreg->current_corner = corner; |
| 4391 | cpr3_debug(vreg, "stored corner=%d\n", corner); |
| 4392 | goto done; |
| 4393 | } else if (vreg->current_corner == corner) { |
| 4394 | goto done; |
| 4395 | } |
| 4396 | |
| 4397 | last_corner = vreg->current_corner; |
| 4398 | vreg->current_corner = corner; |
| 4399 | |
| 4400 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 4401 | if (rc) { |
| 4402 | cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); |
| 4403 | vreg->current_corner = last_corner; |
| 4404 | } |
| 4405 | |
| 4406 | cpr3_debug(vreg, "set corner=%d\n", corner); |
| 4407 | done: |
| 4408 | mutex_unlock(&ctrl->lock); |
| 4409 | |
| 4410 | return rc; |
| 4411 | } |
| 4412 | |
| 4413 | /** |
| 4414 | * cpr3_regulator_get_voltage() - get the voltage corner for the CPR3 regulator |
| 4415 | * associated with the regulator device |
| 4416 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4417 | * |
| 4418 | * This function is passed as a callback function into the regulator ops that |
| 4419 | * are registered for each cpr3-regulator device. |
| 4420 | * |
| 4421 | * Return: voltage corner value offset by CPR3_CORNER_OFFSET |
| 4422 | */ |
| 4423 | static int cpr3_regulator_get_voltage(struct regulator_dev *rdev) |
| 4424 | { |
| 4425 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4426 | |
| 4427 | if (vreg->current_corner == CPR3_REGULATOR_CORNER_INVALID) |
| 4428 | return CPR3_CORNER_OFFSET; |
| 4429 | else |
| 4430 | return vreg->current_corner + CPR3_CORNER_OFFSET; |
| 4431 | } |
| 4432 | |
| 4433 | /** |
| 4434 | * cpr3_regulator_list_voltage() - return the voltage corner mapped to the |
| 4435 | * specified selector |
| 4436 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4437 | * @selector: Regulator selector |
| 4438 | * |
| 4439 | * This function is passed as a callback function into the regulator ops that |
| 4440 | * are registered for each cpr3-regulator device. |
| 4441 | * |
| 4442 | * Return: voltage corner value offset by CPR3_CORNER_OFFSET |
| 4443 | */ |
| 4444 | static int cpr3_regulator_list_voltage(struct regulator_dev *rdev, |
| 4445 | unsigned int selector) |
| 4446 | { |
| 4447 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4448 | |
| 4449 | if (selector < vreg->corner_count) |
| 4450 | return selector + CPR3_CORNER_OFFSET; |
| 4451 | else |
| 4452 | return 0; |
| 4453 | } |
| 4454 | |
| 4455 | /** |
| 4456 | * cpr3_regulator_list_corner_voltage() - return the ceiling voltage mapped to |
| 4457 | * the specified voltage corner |
| 4458 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4459 | * @corner: Voltage corner |
| 4460 | * |
| 4461 | * This function is passed as a callback function into the regulator ops that |
| 4462 | * are registered for each cpr3-regulator device. |
| 4463 | * |
| 4464 | * Return: voltage value in microvolts or -EINVAL if the corner is out of range |
| 4465 | */ |
| 4466 | static int cpr3_regulator_list_corner_voltage(struct regulator_dev *rdev, |
| 4467 | int corner) |
| 4468 | { |
| 4469 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4470 | |
| 4471 | corner -= CPR3_CORNER_OFFSET; |
| 4472 | |
| 4473 | if (corner >= 0 && corner < vreg->corner_count) |
| 4474 | return vreg->corner[corner].ceiling_volt; |
| 4475 | else |
| 4476 | return -EINVAL; |
| 4477 | } |
| 4478 | |
| 4479 | /** |
| 4480 | * cpr3_regulator_is_enabled() - return the enable state of the CPR3 regulator |
| 4481 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4482 | * |
| 4483 | * This function is passed as a callback function into the regulator ops that |
| 4484 | * are registered for each cpr3-regulator device. |
| 4485 | * |
| 4486 | * Return: true if regulator is enabled, false if regulator is disabled |
| 4487 | */ |
| 4488 | static int cpr3_regulator_is_enabled(struct regulator_dev *rdev) |
| 4489 | { |
| 4490 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4491 | |
| 4492 | return vreg->vreg_enabled; |
| 4493 | } |
| 4494 | |
| 4495 | /** |
| 4496 | * cpr3_regulator_enable() - enable the CPR3 regulator |
| 4497 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4498 | * |
| 4499 | * This function is passed as a callback function into the regulator ops that |
| 4500 | * are registered for each cpr3-regulator device. |
| 4501 | * |
| 4502 | * Return: 0 on success, errno on failure |
| 4503 | */ |
| 4504 | static int cpr3_regulator_enable(struct regulator_dev *rdev) |
| 4505 | { |
| 4506 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4507 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 4508 | int rc = 0; |
| 4509 | |
| 4510 | if (vreg->vreg_enabled == true) |
| 4511 | return 0; |
| 4512 | |
| 4513 | mutex_lock(&ctrl->lock); |
| 4514 | |
| 4515 | if (ctrl->system_regulator) { |
| 4516 | rc = regulator_enable(ctrl->system_regulator); |
| 4517 | if (rc) { |
| 4518 | cpr3_err(ctrl, "regulator_enable(system) failed, rc=%d\n", |
| 4519 | rc); |
| 4520 | goto done; |
| 4521 | } |
| 4522 | } |
| 4523 | |
| 4524 | rc = regulator_enable(ctrl->vdd_regulator); |
| 4525 | if (rc) { |
| 4526 | cpr3_err(vreg, "regulator_enable(vdd) failed, rc=%d\n", rc); |
| 4527 | goto done; |
| 4528 | } |
| 4529 | |
| 4530 | if (vreg->ldo_regulator) { |
| 4531 | rc = regulator_enable(vreg->ldo_regulator); |
| 4532 | if (rc) { |
| 4533 | cpr3_err(vreg, "regulator_enable(ldo) failed, rc=%d\n", |
| 4534 | rc); |
| 4535 | goto done; |
| 4536 | } |
| 4537 | } |
| 4538 | |
| 4539 | vreg->vreg_enabled = true; |
| 4540 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 4541 | if (rc) { |
| 4542 | cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); |
| 4543 | regulator_disable(ctrl->vdd_regulator); |
| 4544 | vreg->vreg_enabled = false; |
| 4545 | goto done; |
| 4546 | } |
| 4547 | |
| 4548 | cpr3_debug(vreg, "Enabled\n"); |
| 4549 | done: |
| 4550 | mutex_unlock(&ctrl->lock); |
| 4551 | |
| 4552 | return rc; |
| 4553 | } |
| 4554 | |
| 4555 | /** |
| 4556 | * cpr3_regulator_disable() - disable the CPR3 regulator |
| 4557 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4558 | * |
| 4559 | * This function is passed as a callback function into the regulator ops that |
| 4560 | * are registered for each cpr3-regulator device. |
| 4561 | * |
| 4562 | * Return: 0 on success, errno on failure |
| 4563 | */ |
| 4564 | static int cpr3_regulator_disable(struct regulator_dev *rdev) |
| 4565 | { |
| 4566 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4567 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 4568 | int rc, rc2; |
| 4569 | |
| 4570 | if (vreg->vreg_enabled == false) |
| 4571 | return 0; |
| 4572 | |
| 4573 | mutex_lock(&ctrl->lock); |
| 4574 | |
| 4575 | if (vreg->ldo_regulator && vreg->ldo_regulator_bypass == LDO_MODE) { |
| 4576 | rc = regulator_get_voltage(ctrl->vdd_regulator); |
| 4577 | if (rc < 0) { |
| 4578 | cpr3_err(vreg, "regulator_get_voltage(vdd) failed, rc=%d\n", |
| 4579 | rc); |
| 4580 | goto done; |
| 4581 | } |
| 4582 | |
| 4583 | /* Switch back to BHS for safe operation */ |
| 4584 | rc = cpr3_regulator_set_bhs_mode(vreg, rc, |
| 4585 | ctrl->aggr_corner.ceiling_volt); |
| 4586 | if (rc) { |
| 4587 | cpr3_err(vreg, "unable to switch to BHS mode, rc=%d\n", |
| 4588 | rc); |
| 4589 | goto done; |
| 4590 | } |
| 4591 | } |
| 4592 | |
| 4593 | if (vreg->ldo_regulator) { |
| 4594 | rc = regulator_disable(vreg->ldo_regulator); |
| 4595 | if (rc) { |
| 4596 | cpr3_err(vreg, "regulator_disable(ldo) failed, rc=%d\n", |
| 4597 | rc); |
| 4598 | goto done; |
| 4599 | } |
| 4600 | } |
| 4601 | rc = regulator_disable(ctrl->vdd_regulator); |
| 4602 | if (rc) { |
| 4603 | cpr3_err(vreg, "regulator_disable(vdd) failed, rc=%d\n", rc); |
| 4604 | goto done; |
| 4605 | } |
| 4606 | |
| 4607 | vreg->vreg_enabled = false; |
| 4608 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 4609 | if (rc) { |
| 4610 | cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc); |
| 4611 | rc2 = regulator_enable(ctrl->vdd_regulator); |
| 4612 | vreg->vreg_enabled = true; |
| 4613 | goto done; |
| 4614 | } |
| 4615 | |
| 4616 | if (ctrl->system_regulator) { |
| 4617 | rc = regulator_disable(ctrl->system_regulator); |
| 4618 | if (rc) { |
| 4619 | cpr3_err(ctrl, "regulator_disable(system) failed, rc=%d\n", |
| 4620 | rc); |
| 4621 | goto done; |
| 4622 | } |
| 4623 | if (ctrl->support_ldo300_vreg) { |
| 4624 | rc = regulator_set_voltage(ctrl->system_regulator, 0, |
| 4625 | INT_MAX); |
| 4626 | if (rc) |
| 4627 | cpr3_err(ctrl, "failed to set voltage on system rc=%d\n", |
| 4628 | rc); |
| 4629 | goto done; |
| 4630 | } |
| 4631 | } |
| 4632 | |
| 4633 | cpr3_debug(vreg, "Disabled\n"); |
| 4634 | done: |
| 4635 | mutex_unlock(&ctrl->lock); |
| 4636 | |
| 4637 | return rc; |
| 4638 | } |
| 4639 | |
| 4640 | static struct regulator_ops cpr3_regulator_ops = { |
| 4641 | .enable = cpr3_regulator_enable, |
| 4642 | .disable = cpr3_regulator_disable, |
| 4643 | .is_enabled = cpr3_regulator_is_enabled, |
| 4644 | .set_voltage = cpr3_regulator_set_voltage, |
| 4645 | .get_voltage = cpr3_regulator_get_voltage, |
| 4646 | .list_voltage = cpr3_regulator_list_voltage, |
| 4647 | .list_corner_voltage = cpr3_regulator_list_corner_voltage, |
| 4648 | }; |
| 4649 | |
| 4650 | /** |
| 4651 | * cprh_regulator_get_voltage() - get the voltage corner for the CPR3 regulator |
| 4652 | * associated with the regulator device |
| 4653 | * @rdev: Regulator device pointer for the cpr3-regulator |
| 4654 | * |
| 4655 | * This function is passed as a callback function into the regulator ops that |
| 4656 | * are registered for each cpr3-regulator device of a CPRh controller. The |
| 4657 | * corner is read directly from CPRh hardware register. |
| 4658 | * |
| 4659 | * Return: voltage corner value offset by CPR3_CORNER_OFFSET |
| 4660 | */ |
| 4661 | static int cprh_regulator_get_voltage(struct regulator_dev *rdev) |
| 4662 | { |
| 4663 | struct cpr3_regulator *vreg = rdev_get_drvdata(rdev); |
| 4664 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 4665 | bool cpr_enabled; |
| 4666 | u32 reg, rc; |
| 4667 | |
| 4668 | mutex_lock(&ctrl->lock); |
| 4669 | |
| 4670 | cpr_enabled = ctrl->cpr_enabled; |
| 4671 | if (!cpr_enabled) { |
| 4672 | rc = cpr3_clock_enable(ctrl); |
| 4673 | if (rc) { |
| 4674 | cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); |
| 4675 | mutex_unlock(&ctrl->lock); |
| 4676 | return CPR3_REGULATOR_CORNER_INVALID; |
| 4677 | } |
| 4678 | ctrl->cpr_enabled = true; |
| 4679 | } |
| 4680 | |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 4681 | reg = cpr3_read(vreg->thread->ctrl, CPRH_REG_STATUS(vreg->thread)); |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 4682 | |
| 4683 | if (!cpr_enabled) { |
| 4684 | cpr3_clock_disable(ctrl); |
| 4685 | ctrl->cpr_enabled = false; |
| 4686 | } |
| 4687 | |
| 4688 | mutex_unlock(&ctrl->lock); |
| 4689 | |
| 4690 | return (reg & CPRH_STATUS_CORNER) |
| 4691 | + CPR3_CORNER_OFFSET; |
| 4692 | } |
| 4693 | |
| 4694 | static struct regulator_ops cprh_regulator_ops = { |
| 4695 | .get_voltage = cprh_regulator_get_voltage, |
| 4696 | .list_corner_voltage = cpr3_regulator_list_corner_voltage, |
| 4697 | }; |
| 4698 | |
| 4699 | /** |
| 4700 | * cpr3_print_result() - print CPR measurement results to the kernel log for |
| 4701 | * debugging purposes |
| 4702 | * @thread: Pointer to the CPR3 thread |
| 4703 | * |
| 4704 | * Return: None |
| 4705 | */ |
| 4706 | static void cpr3_print_result(struct cpr3_thread *thread) |
| 4707 | { |
| 4708 | struct cpr3_controller *ctrl = thread->ctrl; |
| 4709 | u32 result[3], busy, step_dn, step_up, error_steps, error, negative; |
| 4710 | u32 quot_min, quot_max, ro_min, ro_max, step_quot_min, step_quot_max; |
| 4711 | u32 sensor_min, sensor_max; |
| 4712 | char *sign; |
| 4713 | |
| 4714 | result[0] = cpr3_read(ctrl, CPR3_REG_RESULT0(thread->thread_id)); |
| 4715 | result[1] = cpr3_read(ctrl, CPR3_REG_RESULT1(thread->thread_id)); |
| 4716 | result[2] = cpr3_read(ctrl, CPR3_REG_RESULT2(thread->thread_id)); |
| 4717 | |
| 4718 | busy = !!(result[0] & CPR3_RESULT0_BUSY_MASK); |
| 4719 | step_dn = !!(result[0] & CPR3_RESULT0_STEP_DN_MASK); |
| 4720 | step_up = !!(result[0] & CPR3_RESULT0_STEP_UP_MASK); |
| 4721 | error_steps = (result[0] & CPR3_RESULT0_ERROR_STEPS_MASK) |
| 4722 | >> CPR3_RESULT0_ERROR_STEPS_SHIFT; |
| 4723 | error = (result[0] & CPR3_RESULT0_ERROR_MASK) |
| 4724 | >> CPR3_RESULT0_ERROR_SHIFT; |
| 4725 | negative = !!(result[0] & CPR3_RESULT0_NEGATIVE_MASK); |
| 4726 | |
| 4727 | quot_min = (result[1] & CPR3_RESULT1_QUOT_MIN_MASK) |
| 4728 | >> CPR3_RESULT1_QUOT_MIN_SHIFT; |
| 4729 | quot_max = (result[1] & CPR3_RESULT1_QUOT_MAX_MASK) |
| 4730 | >> CPR3_RESULT1_QUOT_MAX_SHIFT; |
| 4731 | ro_min = (result[1] & CPR3_RESULT1_RO_MIN_MASK) |
| 4732 | >> CPR3_RESULT1_RO_MIN_SHIFT; |
| 4733 | ro_max = (result[1] & CPR3_RESULT1_RO_MAX_MASK) |
| 4734 | >> CPR3_RESULT1_RO_MAX_SHIFT; |
| 4735 | |
| 4736 | step_quot_min = (result[2] & CPR3_RESULT2_STEP_QUOT_MIN_MASK) |
| 4737 | >> CPR3_RESULT2_STEP_QUOT_MIN_SHIFT; |
| 4738 | step_quot_max = (result[2] & CPR3_RESULT2_STEP_QUOT_MAX_MASK) |
| 4739 | >> CPR3_RESULT2_STEP_QUOT_MAX_SHIFT; |
| 4740 | sensor_min = (result[2] & CPR3_RESULT2_SENSOR_MIN_MASK) |
| 4741 | >> CPR3_RESULT2_SENSOR_MIN_SHIFT; |
| 4742 | sensor_max = (result[2] & CPR3_RESULT2_SENSOR_MAX_MASK) |
| 4743 | >> CPR3_RESULT2_SENSOR_MAX_SHIFT; |
| 4744 | |
| 4745 | sign = negative ? "-" : ""; |
| 4746 | cpr3_debug(ctrl, "thread %u: busy=%u, step_dn=%u, step_up=%u, error_steps=%s%u, error=%s%u\n", |
| 4747 | thread->thread_id, busy, step_dn, step_up, sign, error_steps, |
| 4748 | sign, error); |
| 4749 | cpr3_debug(ctrl, "thread %u: quot_min=%u, quot_max=%u, ro_min=%u, ro_max=%u\n", |
| 4750 | thread->thread_id, quot_min, quot_max, ro_min, ro_max); |
| 4751 | cpr3_debug(ctrl, "thread %u: step_quot_min=%u, step_quot_max=%u, sensor_min=%u, sensor_max=%u\n", |
| 4752 | thread->thread_id, step_quot_min, step_quot_max, sensor_min, |
| 4753 | sensor_max); |
| 4754 | } |
| 4755 | |
| 4756 | /** |
| 4757 | * cpr3_thread_busy() - returns if the specified CPR3 thread is busy taking |
| 4758 | * a measurement |
| 4759 | * @thread: Pointer to the CPR3 thread |
| 4760 | * |
| 4761 | * Return: CPR3 busy status |
| 4762 | */ |
| 4763 | static bool cpr3_thread_busy(struct cpr3_thread *thread) |
| 4764 | { |
| 4765 | u32 result; |
| 4766 | |
| 4767 | result = cpr3_read(thread->ctrl, CPR3_REG_RESULT0(thread->thread_id)); |
| 4768 | |
| 4769 | return !!(result & CPR3_RESULT0_BUSY_MASK); |
| 4770 | } |
| 4771 | |
| 4772 | /** |
| 4773 | * cpr3_irq_handler() - CPR interrupt handler callback function used for |
| 4774 | * software closed-loop operation |
| 4775 | * @irq: CPR interrupt number |
| 4776 | * @data: Private data corresponding to the CPR3 controller |
| 4777 | * pointer |
| 4778 | * |
| 4779 | * This function increases or decreases the vdd supply voltage based upon the |
| 4780 | * CPR controller recommendation. |
| 4781 | * |
| 4782 | * Return: IRQ_HANDLED |
| 4783 | */ |
| 4784 | static irqreturn_t cpr3_irq_handler(int irq, void *data) |
| 4785 | { |
| 4786 | struct cpr3_controller *ctrl = data; |
| 4787 | struct cpr3_corner *aggr = &ctrl->aggr_corner; |
| 4788 | u32 cont = CPR3_CONT_CMD_NACK; |
| 4789 | u32 reg_last_measurement = 0; |
| 4790 | struct cpr3_regulator *vreg; |
| 4791 | struct cpr3_corner *corner; |
| 4792 | unsigned long flags; |
| 4793 | int i, j, new_volt, last_volt, dynamic_floor_volt, rc; |
| 4794 | u32 irq_en, status, cpr_status, ctl; |
| 4795 | bool up, down; |
| 4796 | |
| 4797 | mutex_lock(&ctrl->lock); |
| 4798 | |
| 4799 | if (!ctrl->cpr_enabled) { |
| 4800 | cpr3_debug(ctrl, "CPR interrupt received but CPR is disabled\n"); |
| 4801 | mutex_unlock(&ctrl->lock); |
| 4802 | return IRQ_HANDLED; |
| 4803 | } else if (ctrl->use_hw_closed_loop) { |
| 4804 | cpr3_debug(ctrl, "CPR interrupt received but CPR is using HW closed-loop\n"); |
| 4805 | goto done; |
| 4806 | } |
| 4807 | |
| 4808 | /* |
| 4809 | * CPR IRQ status checking and CPR controller disabling must happen |
| 4810 | * atomically and without invening delay in order to avoid an interrupt |
| 4811 | * storm caused by the handler racing with the CPR controller. |
| 4812 | */ |
| 4813 | local_irq_save(flags); |
| 4814 | preempt_disable(); |
| 4815 | |
| 4816 | status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS); |
| 4817 | up = status & CPR3_IRQ_UP; |
| 4818 | down = status & CPR3_IRQ_DOWN; |
| 4819 | |
| 4820 | if (!up && !down) { |
| 4821 | /* |
| 4822 | * Toggle the CPR controller off and then back on since the |
| 4823 | * hardware and software states are out of sync. This condition |
| 4824 | * occurs after an aging measurement completes as the CPR IRQ |
| 4825 | * physically triggers during the aging measurement but the |
| 4826 | * handler is stuck waiting on the mutex lock. |
| 4827 | */ |
| 4828 | cpr3_ctrl_loop_disable(ctrl); |
| 4829 | |
| 4830 | local_irq_restore(flags); |
| 4831 | preempt_enable(); |
| 4832 | |
| 4833 | /* Wait for the loop disable write to complete */ |
| 4834 | mb(); |
| 4835 | |
| 4836 | /* Wait for BUSY=1 and LOOP_EN=0 in CPR controller registers. */ |
| 4837 | for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) { |
| 4838 | cpr_status = cpr3_read(ctrl, CPR3_REG_CPR_STATUS); |
| 4839 | ctl = cpr3_read(ctrl, CPR3_REG_CPR_CTL); |
| 4840 | if (cpr_status & CPR3_CPR_STATUS_BUSY_MASK |
| 4841 | && (ctl & CPR3_CPR_CTL_LOOP_EN_MASK) |
| 4842 | == CPR3_CPR_CTL_LOOP_DISABLE) |
| 4843 | break; |
| 4844 | udelay(10); |
| 4845 | } |
| 4846 | if (i == CPR3_REGISTER_WRITE_DELAY_US / 10) |
| 4847 | cpr3_debug(ctrl, "CPR controller not disabled after %d us\n", |
| 4848 | CPR3_REGISTER_WRITE_DELAY_US); |
| 4849 | |
| 4850 | /* Clear interrupt status */ |
| 4851 | cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, |
| 4852 | CPR3_IRQ_UP | CPR3_IRQ_DOWN); |
| 4853 | |
| 4854 | /* Wait for the interrupt clearing write to complete */ |
| 4855 | mb(); |
| 4856 | |
| 4857 | /* Wait for IRQ_STATUS register to be cleared. */ |
| 4858 | for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) { |
| 4859 | status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS); |
| 4860 | if (!(status & (CPR3_IRQ_UP | CPR3_IRQ_DOWN))) |
| 4861 | break; |
| 4862 | udelay(10); |
| 4863 | } |
| 4864 | if (i == CPR3_REGISTER_WRITE_DELAY_US / 10) |
| 4865 | cpr3_debug(ctrl, "CPR interrupts not cleared after %d us\n", |
| 4866 | CPR3_REGISTER_WRITE_DELAY_US); |
| 4867 | |
| 4868 | cpr3_ctrl_loop_enable(ctrl); |
| 4869 | |
| 4870 | cpr3_debug(ctrl, "CPR interrupt received but no up or down status bit is set\n"); |
| 4871 | |
| 4872 | mutex_unlock(&ctrl->lock); |
| 4873 | return IRQ_HANDLED; |
| 4874 | } else if (up && down) { |
| 4875 | cpr3_debug(ctrl, "both up and down status bits set\n"); |
| 4876 | /* The up flag takes precedence over the down flag. */ |
| 4877 | down = false; |
| 4878 | } |
| 4879 | |
| 4880 | if (ctrl->supports_hw_closed_loop) |
| 4881 | reg_last_measurement |
| 4882 | = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT); |
| 4883 | dynamic_floor_volt = cpr3_regulator_get_dynamic_floor_volt(ctrl, |
| 4884 | reg_last_measurement); |
| 4885 | |
| 4886 | local_irq_restore(flags); |
| 4887 | preempt_enable(); |
| 4888 | |
| 4889 | irq_en = aggr->irq_en; |
| 4890 | last_volt = aggr->last_volt; |
| 4891 | |
| 4892 | for (i = 0; i < ctrl->thread_count; i++) { |
| 4893 | if (cpr3_thread_busy(&ctrl->thread[i])) { |
| 4894 | cpr3_debug(ctrl, "CPR thread %u busy when it should be waiting for SW cont\n", |
| 4895 | ctrl->thread[i].thread_id); |
| 4896 | goto done; |
| 4897 | } |
| 4898 | } |
| 4899 | |
| 4900 | new_volt = up ? last_volt + ctrl->step_volt |
| 4901 | : last_volt - ctrl->step_volt; |
| 4902 | |
| 4903 | /* Re-enable UP/DOWN interrupt when its opposite is received. */ |
| 4904 | irq_en |= up ? CPR3_IRQ_DOWN : CPR3_IRQ_UP; |
| 4905 | |
| 4906 | if (new_volt > aggr->ceiling_volt) { |
| 4907 | new_volt = aggr->ceiling_volt; |
| 4908 | irq_en &= ~CPR3_IRQ_UP; |
| 4909 | cpr3_debug(ctrl, "limiting to ceiling=%d uV\n", |
| 4910 | aggr->ceiling_volt); |
| 4911 | } else if (new_volt < aggr->floor_volt) { |
| 4912 | new_volt = aggr->floor_volt; |
| 4913 | irq_en &= ~CPR3_IRQ_DOWN; |
| 4914 | cpr3_debug(ctrl, "limiting to floor=%d uV\n", aggr->floor_volt); |
| 4915 | } |
| 4916 | |
| 4917 | if (down && new_volt < dynamic_floor_volt) { |
| 4918 | /* |
| 4919 | * The vdd-supply voltage should not be decreased below the |
| 4920 | * dynamic floor voltage. However, it is not necessary (and |
| 4921 | * counter productive) to force the voltage up to this level |
| 4922 | * if it happened to be below it since the closed-loop voltage |
| 4923 | * must have gotten there in a safe manner while the power |
| 4924 | * domains for the CPR3 regulator imposing the dynamic floor |
| 4925 | * were not bypassed. |
| 4926 | */ |
| 4927 | new_volt = last_volt; |
| 4928 | irq_en &= ~CPR3_IRQ_DOWN; |
| 4929 | cpr3_debug(ctrl, "limiting to dynamic floor=%d uV\n", |
| 4930 | dynamic_floor_volt); |
| 4931 | } |
| 4932 | |
| 4933 | for (i = 0; i < ctrl->thread_count; i++) |
| 4934 | cpr3_print_result(&ctrl->thread[i]); |
| 4935 | |
| 4936 | cpr3_debug(ctrl, "%s: new_volt=%d uV, last_volt=%d uV\n", |
| 4937 | up ? "UP" : "DN", new_volt, last_volt); |
| 4938 | |
| 4939 | if (ctrl->proc_clock_throttle && last_volt == aggr->ceiling_volt |
| 4940 | && new_volt < last_volt) |
| 4941 | cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, |
| 4942 | ctrl->proc_clock_throttle); |
| 4943 | |
| 4944 | if (new_volt != last_volt) { |
| 4945 | rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt, |
| 4946 | last_volt, |
| 4947 | aggr); |
| 4948 | if (rc) { |
| 4949 | cpr3_err(ctrl, "scale_vdd() failed to set vdd=%d uV, rc=%d\n", |
| 4950 | new_volt, rc); |
| 4951 | goto done; |
| 4952 | } |
| 4953 | cont = CPR3_CONT_CMD_ACK; |
| 4954 | |
| 4955 | /* |
| 4956 | * Update the closed-loop voltage for all regulators managed |
| 4957 | * by this CPR controller. |
| 4958 | */ |
| 4959 | for (i = 0; i < ctrl->thread_count; i++) { |
| 4960 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 4961 | vreg = &ctrl->thread[i].vreg[j]; |
| 4962 | cpr3_update_vreg_closed_loop_volt(vreg, |
| 4963 | new_volt, reg_last_measurement); |
| 4964 | } |
| 4965 | } |
| 4966 | } |
| 4967 | |
| 4968 | if (ctrl->proc_clock_throttle && new_volt == aggr->ceiling_volt) |
| 4969 | cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, |
| 4970 | CPR3_PD_THROTTLE_DISABLE); |
| 4971 | |
| 4972 | corner = &ctrl->thread[0].vreg[0].corner[ |
| 4973 | ctrl->thread[0].vreg[0].current_corner]; |
| 4974 | |
| 4975 | if (irq_en != aggr->irq_en) { |
| 4976 | aggr->irq_en = irq_en; |
| 4977 | cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_en); |
| 4978 | } |
| 4979 | |
| 4980 | aggr->last_volt = new_volt; |
| 4981 | |
| 4982 | done: |
| 4983 | /* Clear interrupt status */ |
| 4984 | cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, CPR3_IRQ_UP | CPR3_IRQ_DOWN); |
| 4985 | |
| 4986 | /* ACK or NACK the CPR controller */ |
| 4987 | cpr3_write(ctrl, CPR3_REG_CONT_CMD, cont); |
| 4988 | |
| 4989 | mutex_unlock(&ctrl->lock); |
| 4990 | return IRQ_HANDLED; |
| 4991 | } |
| 4992 | |
| 4993 | /** |
| 4994 | * cpr3_ceiling_irq_handler() - CPR ceiling reached interrupt handler callback |
| 4995 | * function used for hardware closed-loop operation |
| 4996 | * @irq: CPR ceiling interrupt number |
| 4997 | * @data: Private data corresponding to the CPR3 controller |
| 4998 | * pointer |
| 4999 | * |
| 5000 | * This function disables processor clock throttling and closed-loop operation |
| 5001 | * when the ceiling voltage is reached. |
| 5002 | * |
| 5003 | * Return: IRQ_HANDLED |
| 5004 | */ |
| 5005 | static irqreturn_t cpr3_ceiling_irq_handler(int irq, void *data) |
| 5006 | { |
| 5007 | struct cpr3_controller *ctrl = data; |
| 5008 | int rc, volt; |
| 5009 | |
| 5010 | mutex_lock(&ctrl->lock); |
| 5011 | |
| 5012 | if (!ctrl->cpr_enabled) { |
| 5013 | cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is disabled\n"); |
| 5014 | goto done; |
| 5015 | } else if (!ctrl->use_hw_closed_loop) { |
| 5016 | cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is using SW closed-loop\n"); |
| 5017 | goto done; |
| 5018 | } |
| 5019 | |
| 5020 | volt = regulator_get_voltage(ctrl->vdd_regulator); |
| 5021 | if (volt < 0) { |
| 5022 | cpr3_err(ctrl, "could not get vdd voltage, rc=%d\n", volt); |
| 5023 | goto done; |
| 5024 | } else if (volt != ctrl->aggr_corner.ceiling_volt) { |
| 5025 | cpr3_debug(ctrl, "CPR ceiling interrupt received but vdd voltage: %d uV != ceiling voltage: %d uV\n", |
| 5026 | volt, ctrl->aggr_corner.ceiling_volt); |
| 5027 | goto done; |
| 5028 | } |
| 5029 | |
| 5030 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 5031 | /* |
| 5032 | * Since the ceiling voltage has been reached, disable processor |
| 5033 | * clock throttling as well as CPR closed-loop operation. |
| 5034 | */ |
| 5035 | cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, |
| 5036 | CPR3_PD_THROTTLE_DISABLE); |
| 5037 | cpr3_ctrl_loop_disable(ctrl); |
| 5038 | cpr3_debug(ctrl, "CPR closed-loop and throttling disabled\n"); |
| 5039 | } |
| 5040 | |
| 5041 | done: |
| 5042 | rc = msm_spm_avs_clear_irq(0, MSM_SPM_AVS_IRQ_MAX); |
| 5043 | if (rc) |
| 5044 | cpr3_err(ctrl, "could not clear max IRQ, rc=%d\n", rc); |
| 5045 | |
| 5046 | mutex_unlock(&ctrl->lock); |
| 5047 | return IRQ_HANDLED; |
| 5048 | } |
| 5049 | |
| 5050 | /** |
| 5051 | * cpr3_regulator_vreg_register() - register a regulator device for a CPR3 |
| 5052 | * regulator |
| 5053 | * @vreg: Pointer to the CPR3 regulator |
| 5054 | * |
| 5055 | * This function initializes all regulator framework related structures and then |
| 5056 | * calls regulator_register() for the CPR3 regulator. |
| 5057 | * |
| 5058 | * Return: 0 on success, errno on failure |
| 5059 | */ |
| 5060 | static int cpr3_regulator_vreg_register(struct cpr3_regulator *vreg) |
| 5061 | { |
| 5062 | struct regulator_config config = {}; |
| 5063 | struct regulator_desc *rdesc; |
| 5064 | struct regulator_init_data *init_data; |
| 5065 | int rc; |
| 5066 | |
| 5067 | init_data = of_get_regulator_init_data(vreg->thread->ctrl->dev, |
| 5068 | vreg->of_node, &vreg->rdesc); |
| 5069 | if (!init_data) { |
| 5070 | cpr3_err(vreg, "regulator init data is missing\n"); |
| 5071 | return -EINVAL; |
| 5072 | } |
| 5073 | |
| 5074 | init_data->constraints.input_uV = init_data->constraints.max_uV; |
| 5075 | rdesc = &vreg->rdesc; |
| 5076 | if (vreg->thread->ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 5077 | /* CPRh regulators are treated as always-on regulators */ |
| 5078 | rdesc->ops = &cprh_regulator_ops; |
| 5079 | } else { |
| 5080 | init_data->constraints.valid_ops_mask |
| 5081 | |= REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS; |
| 5082 | rdesc->ops = &cpr3_regulator_ops; |
| 5083 | } |
| 5084 | |
| 5085 | rdesc->n_voltages = vreg->corner_count; |
| 5086 | rdesc->name = init_data->constraints.name; |
| 5087 | rdesc->owner = THIS_MODULE; |
| 5088 | rdesc->type = REGULATOR_VOLTAGE; |
| 5089 | |
| 5090 | config.dev = vreg->thread->ctrl->dev; |
| 5091 | config.driver_data = vreg; |
| 5092 | config.init_data = init_data; |
| 5093 | config.of_node = vreg->of_node; |
| 5094 | |
| 5095 | vreg->rdev = regulator_register(rdesc, &config); |
| 5096 | if (IS_ERR(vreg->rdev)) { |
| 5097 | rc = PTR_ERR(vreg->rdev); |
| 5098 | cpr3_err(vreg, "regulator_register failed, rc=%d\n", rc); |
| 5099 | return rc; |
| 5100 | } |
| 5101 | |
| 5102 | return 0; |
| 5103 | } |
| 5104 | |
| 5105 | static int debugfs_int_set(void *data, u64 val) |
| 5106 | { |
| 5107 | *(int *)data = val; |
| 5108 | return 0; |
| 5109 | } |
| 5110 | |
| 5111 | static int debugfs_int_get(void *data, u64 *val) |
| 5112 | { |
| 5113 | *val = *(int *)data; |
| 5114 | return 0; |
| 5115 | } |
| 5116 | DEFINE_SIMPLE_ATTRIBUTE(fops_int, debugfs_int_get, debugfs_int_set, "%lld\n"); |
| 5117 | DEFINE_SIMPLE_ATTRIBUTE(fops_int_ro, debugfs_int_get, NULL, "%lld\n"); |
| 5118 | DEFINE_SIMPLE_ATTRIBUTE(fops_int_wo, NULL, debugfs_int_set, "%lld\n"); |
| 5119 | |
| 5120 | /** |
| 5121 | * debugfs_create_int - create a debugfs file that is used to read and write a |
| 5122 | * signed int value |
| 5123 | * @name: Pointer to a string containing the name of the file to |
| 5124 | * create |
| 5125 | * @mode: The permissions that the file should have |
| 5126 | * @parent: Pointer to the parent dentry for this file. This should |
| 5127 | * be a directory dentry if set. If this parameter is |
| 5128 | * %NULL, then the file will be created in the root of the |
| 5129 | * debugfs filesystem. |
| 5130 | * @value: Pointer to the variable that the file should read to and |
| 5131 | * write from |
| 5132 | * |
| 5133 | * This function creates a file in debugfs with the given name that |
| 5134 | * contains the value of the variable @value. If the @mode variable is so |
| 5135 | * set, it can be read from, and written to. |
| 5136 | * |
| 5137 | * This function will return a pointer to a dentry if it succeeds. This |
| 5138 | * pointer must be passed to the debugfs_remove() function when the file is |
| 5139 | * to be removed. If an error occurs, %NULL will be returned. |
| 5140 | */ |
| 5141 | static struct dentry *debugfs_create_int(const char *name, umode_t mode, |
| 5142 | struct dentry *parent, int *value) |
| 5143 | { |
| 5144 | /* if there are no write bits set, make read only */ |
| 5145 | if (!(mode & 0222)) |
| 5146 | return debugfs_create_file(name, mode, parent, value, |
| 5147 | &fops_int_ro); |
| 5148 | /* if there are no read bits set, make write only */ |
| 5149 | if (!(mode & 0444)) |
| 5150 | return debugfs_create_file(name, mode, parent, value, |
| 5151 | &fops_int_wo); |
| 5152 | |
| 5153 | return debugfs_create_file(name, mode, parent, value, &fops_int); |
| 5154 | } |
| 5155 | |
| 5156 | static int debugfs_bool_get(void *data, u64 *val) |
| 5157 | { |
| 5158 | *val = *(bool *)data; |
| 5159 | return 0; |
| 5160 | } |
| 5161 | DEFINE_SIMPLE_ATTRIBUTE(fops_bool_ro, debugfs_bool_get, NULL, "%lld\n"); |
| 5162 | |
| 5163 | /** |
| 5164 | * cpr3_debug_ldo_mode_allowed_set() - debugfs callback used to change the |
| 5165 | * value of the CPR3 regulator ldo_mode_allowed flag |
| 5166 | * @data: Pointer to private data which is equal to the CPR3 |
| 5167 | * regulator pointer |
| 5168 | * @val: New value for ldo_mode_allowed |
| 5169 | * |
| 5170 | * Return: 0 on success, errno on failure |
| 5171 | */ |
| 5172 | static int cpr3_debug_ldo_mode_allowed_set(void *data, u64 val) |
| 5173 | { |
| 5174 | struct cpr3_regulator *vreg = data; |
| 5175 | struct cpr3_controller *ctrl = vreg->thread->ctrl; |
| 5176 | bool allow = !!val; |
| 5177 | int rc, vdd_volt; |
| 5178 | |
| 5179 | mutex_lock(&ctrl->lock); |
| 5180 | |
| 5181 | if (vreg->ldo_mode_allowed == allow) |
| 5182 | goto done; |
| 5183 | |
| 5184 | vreg->ldo_mode_allowed = allow; |
| 5185 | |
| 5186 | if (!allow && vreg->ldo_regulator_bypass == LDO_MODE) { |
| 5187 | vdd_volt = regulator_get_voltage(ctrl->vdd_regulator); |
| 5188 | if (vdd_volt < 0) { |
| 5189 | cpr3_err(vreg, "regulator_get_voltage(vdd) failed, rc=%d\n", |
| 5190 | vdd_volt); |
| 5191 | goto done; |
| 5192 | } |
| 5193 | |
| 5194 | /* Switch back to BHS */ |
| 5195 | rc = cpr3_regulator_set_bhs_mode(vreg, vdd_volt, |
| 5196 | ctrl->aggr_corner.ceiling_volt); |
| 5197 | if (rc) { |
| 5198 | cpr3_err(vreg, "unable to switch to BHS mode, rc=%d\n", |
| 5199 | rc); |
| 5200 | goto done; |
| 5201 | } |
| 5202 | } else { |
| 5203 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 5204 | if (rc) { |
| 5205 | cpr3_err(vreg, "could not change LDO mode=%s, rc=%d\n", |
| 5206 | allow ? "allowed" : "disallowed", rc); |
| 5207 | goto done; |
| 5208 | } |
| 5209 | } |
| 5210 | |
| 5211 | cpr3_debug(vreg, "LDO mode=%s\n", allow ? "allowed" : "disallowed"); |
| 5212 | |
| 5213 | done: |
| 5214 | mutex_unlock(&ctrl->lock); |
| 5215 | return 0; |
| 5216 | } |
| 5217 | |
| 5218 | /** |
| 5219 | * cpr3_debug_ldo_mode_allowed_get() - debugfs callback used to retrieve the |
| 5220 | * value of the CPR3 regulator ldo_mode_allowed flag |
| 5221 | * @data: Pointer to private data which is equal to the CPR3 |
| 5222 | * regulator pointer |
| 5223 | * @val: Output parameter written with a value of the |
| 5224 | * ldo_mode_allowed flag |
| 5225 | * |
| 5226 | * Return: 0 on success, errno on failure |
| 5227 | */ |
| 5228 | static int cpr3_debug_ldo_mode_allowed_get(void *data, u64 *val) |
| 5229 | { |
| 5230 | struct cpr3_regulator *vreg = data; |
| 5231 | |
| 5232 | *val = vreg->ldo_mode_allowed; |
| 5233 | |
| 5234 | return 0; |
| 5235 | } |
| 5236 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_ldo_mode_allowed_fops, |
| 5237 | cpr3_debug_ldo_mode_allowed_get, |
| 5238 | cpr3_debug_ldo_mode_allowed_set, |
| 5239 | "%llu\n"); |
| 5240 | |
| 5241 | /** |
| 5242 | * cpr3_debug_ldo_mode_get() - debugfs callback used to retrieve the state of |
| 5243 | * the CPR3 regulator's LDO |
| 5244 | * @data: Pointer to private data which is equal to the CPR3 |
| 5245 | * regulator pointer |
| 5246 | * @val: Output parameter written with a value of 1 if using |
| 5247 | * LDO mode or 0 if the LDO is bypassed |
| 5248 | * |
| 5249 | * Return: 0 on success, errno on failure |
| 5250 | */ |
| 5251 | static int cpr3_debug_ldo_mode_get(void *data, u64 *val) |
| 5252 | { |
| 5253 | struct cpr3_regulator *vreg = data; |
| 5254 | |
| 5255 | *val = (vreg->ldo_regulator_bypass == LDO_MODE); |
| 5256 | |
| 5257 | return 0; |
| 5258 | } |
| 5259 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_ldo_mode_fops, cpr3_debug_ldo_mode_get, |
| 5260 | NULL, "%llu\n"); |
| 5261 | |
| 5262 | /** |
| 5263 | * struct cpr3_debug_corner_info - data structure used by the |
| 5264 | * cpr3_debugfs_create_corner_int function |
| 5265 | * @vreg: Pointer to the CPR3 regulator |
| 5266 | * @index: Pointer to the corner array index |
| 5267 | * @member_offset: Offset in bytes from the beginning of struct cpr3_corner |
| 5268 | * to the beginning of the value to be read from |
| 5269 | * @corner: Pointer to the CPR3 corner array |
| 5270 | */ |
| 5271 | struct cpr3_debug_corner_info { |
| 5272 | struct cpr3_regulator *vreg; |
| 5273 | int *index; |
| 5274 | size_t member_offset; |
| 5275 | struct cpr3_corner *corner; |
| 5276 | }; |
| 5277 | |
| 5278 | static int cpr3_debug_corner_int_get(void *data, u64 *val) |
| 5279 | { |
| 5280 | struct cpr3_debug_corner_info *info = data; |
| 5281 | struct cpr3_controller *ctrl = info->vreg->thread->ctrl; |
| 5282 | int i; |
| 5283 | |
| 5284 | mutex_lock(&ctrl->lock); |
| 5285 | |
| 5286 | i = *info->index; |
| 5287 | if (i < 0) |
| 5288 | i = 0; |
| 5289 | |
| 5290 | *val = *(int *)((char *)&info->vreg->corner[i] + info->member_offset); |
| 5291 | |
| 5292 | mutex_unlock(&ctrl->lock); |
| 5293 | |
| 5294 | return 0; |
| 5295 | } |
| 5296 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_int_fops, cpr3_debug_corner_int_get, |
| 5297 | NULL, "%lld\n"); |
| 5298 | |
| 5299 | /** |
| 5300 | * cpr3_debugfs_create_corner_int - create a debugfs file that is used to read |
| 5301 | * a signed int value out of a CPR3 regulator's corner array |
| 5302 | * @vreg: Pointer to the CPR3 regulator |
| 5303 | * @name: Pointer to a string containing the name of the file to |
| 5304 | * create |
| 5305 | * @mode: The permissions that the file should have |
| 5306 | * @parent: Pointer to the parent dentry for this file. This should |
| 5307 | * be a directory dentry if set. If this parameter is |
| 5308 | * %NULL, then the file will be created in the root of the |
| 5309 | * debugfs filesystem. |
| 5310 | * @index: Pointer to the corner array index |
| 5311 | * @member_offset: Offset in bytes from the beginning of struct cpr3_corner |
| 5312 | * to the beginning of the value to be read from |
| 5313 | * |
| 5314 | * This function creates a file in debugfs with the given name that |
| 5315 | * contains the value of the int type variable vreg->corner[index].member |
| 5316 | * where member_offset == offsetof(struct cpr3_corner, member). |
| 5317 | */ |
| 5318 | static struct dentry *cpr3_debugfs_create_corner_int( |
| 5319 | struct cpr3_regulator *vreg, const char *name, umode_t mode, |
| 5320 | struct dentry *parent, int *index, size_t member_offset) |
| 5321 | { |
| 5322 | struct cpr3_debug_corner_info *info; |
| 5323 | |
| 5324 | info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL); |
| 5325 | if (!info) |
| 5326 | return NULL; |
| 5327 | |
| 5328 | info->vreg = vreg; |
| 5329 | info->index = index; |
| 5330 | info->member_offset = member_offset; |
| 5331 | |
| 5332 | return debugfs_create_file(name, mode, parent, info, |
| 5333 | &cpr3_debug_corner_int_fops); |
| 5334 | } |
| 5335 | |
| 5336 | static int cpr3_debug_quot_open(struct inode *inode, struct file *file) |
| 5337 | { |
| 5338 | struct cpr3_debug_corner_info *info = inode->i_private; |
| 5339 | struct cpr3_thread *thread = info->vreg->thread; |
| 5340 | int size, i, pos; |
| 5341 | u32 *quot; |
| 5342 | char *buf; |
| 5343 | |
| 5344 | /* |
| 5345 | * Max size: |
| 5346 | * - 10 digits + ' ' or '\n' = 11 bytes per number |
| 5347 | * - terminating '\0' |
| 5348 | */ |
| 5349 | size = CPR3_RO_COUNT * 11; |
| 5350 | buf = kzalloc(size + 1, GFP_KERNEL); |
| 5351 | if (!buf) |
| 5352 | return -ENOMEM; |
| 5353 | |
| 5354 | file->private_data = buf; |
| 5355 | |
| 5356 | mutex_lock(&thread->ctrl->lock); |
| 5357 | |
| 5358 | quot = info->corner[*info->index].target_quot; |
| 5359 | |
| 5360 | for (i = 0, pos = 0; i < CPR3_RO_COUNT; i++) |
| 5361 | pos += scnprintf(buf + pos, size - pos, "%u%c", |
| 5362 | quot[i], i < CPR3_RO_COUNT - 1 ? ' ' : '\n'); |
| 5363 | |
| 5364 | mutex_unlock(&thread->ctrl->lock); |
| 5365 | |
| 5366 | return nonseekable_open(inode, file); |
| 5367 | } |
| 5368 | |
| 5369 | static ssize_t cpr3_debug_quot_read(struct file *file, char __user *buf, |
| 5370 | size_t len, loff_t *ppos) |
| 5371 | { |
| 5372 | return simple_read_from_buffer(buf, len, ppos, file->private_data, |
| 5373 | strlen(file->private_data)); |
| 5374 | } |
| 5375 | |
| 5376 | static int cpr3_debug_quot_release(struct inode *inode, struct file *file) |
| 5377 | { |
| 5378 | kfree(file->private_data); |
| 5379 | |
| 5380 | return 0; |
| 5381 | } |
| 5382 | |
| 5383 | static const struct file_operations cpr3_debug_quot_fops = { |
| 5384 | .owner = THIS_MODULE, |
| 5385 | .open = cpr3_debug_quot_open, |
| 5386 | .release = cpr3_debug_quot_release, |
| 5387 | .read = cpr3_debug_quot_read, |
| 5388 | .llseek = no_llseek, |
| 5389 | }; |
| 5390 | |
| 5391 | /** |
| 5392 | * cpr3_regulator_debugfs_corner_add() - add debugfs files to expose |
| 5393 | * configuration data for the CPR corner |
| 5394 | * @vreg: Pointer to the CPR3 regulator |
| 5395 | * @corner_dir: Pointer to the parent corner dentry for the new files |
| 5396 | * @index: Pointer to the corner array index |
| 5397 | * |
| 5398 | * Return: none |
| 5399 | */ |
| 5400 | static void cpr3_regulator_debugfs_corner_add(struct cpr3_regulator *vreg, |
| 5401 | struct dentry *corner_dir, int *index) |
| 5402 | { |
| 5403 | struct cpr3_debug_corner_info *info; |
| 5404 | struct dentry *temp; |
| 5405 | |
| 5406 | temp = cpr3_debugfs_create_corner_int(vreg, "floor_volt", 0444, |
| 5407 | corner_dir, index, offsetof(struct cpr3_corner, floor_volt)); |
| 5408 | if (IS_ERR_OR_NULL(temp)) { |
| 5409 | cpr3_err(vreg, "floor_volt debugfs file creation failed\n"); |
| 5410 | return; |
| 5411 | } |
| 5412 | |
| 5413 | temp = cpr3_debugfs_create_corner_int(vreg, "ceiling_volt", 0444, |
| 5414 | corner_dir, index, offsetof(struct cpr3_corner, ceiling_volt)); |
| 5415 | if (IS_ERR_OR_NULL(temp)) { |
| 5416 | cpr3_err(vreg, "ceiling_volt debugfs file creation failed\n"); |
| 5417 | return; |
| 5418 | } |
| 5419 | |
| 5420 | temp = cpr3_debugfs_create_corner_int(vreg, "open_loop_volt", 0444, |
| 5421 | corner_dir, index, |
| 5422 | offsetof(struct cpr3_corner, open_loop_volt)); |
| 5423 | if (IS_ERR_OR_NULL(temp)) { |
| 5424 | cpr3_err(vreg, "open_loop_volt debugfs file creation failed\n"); |
| 5425 | return; |
| 5426 | } |
| 5427 | |
| 5428 | temp = cpr3_debugfs_create_corner_int(vreg, "last_volt", 0444, |
| 5429 | corner_dir, index, offsetof(struct cpr3_corner, last_volt)); |
| 5430 | if (IS_ERR_OR_NULL(temp)) { |
| 5431 | cpr3_err(vreg, "last_volt debugfs file creation failed\n"); |
| 5432 | return; |
| 5433 | } |
| 5434 | |
| 5435 | info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL); |
| 5436 | if (!info) |
| 5437 | return; |
| 5438 | |
| 5439 | info->vreg = vreg; |
| 5440 | info->index = index; |
| 5441 | info->corner = vreg->corner; |
| 5442 | |
| 5443 | temp = debugfs_create_file("target_quots", 0444, corner_dir, info, |
| 5444 | &cpr3_debug_quot_fops); |
| 5445 | if (IS_ERR_OR_NULL(temp)) { |
| 5446 | cpr3_err(vreg, "target_quots debugfs file creation failed\n"); |
| 5447 | return; |
| 5448 | } |
| 5449 | } |
| 5450 | |
| 5451 | /** |
| 5452 | * cpr3_debug_corner_index_set() - debugfs callback used to change the |
| 5453 | * value of the CPR3 regulator debug_corner index |
| 5454 | * @data: Pointer to private data which is equal to the CPR3 |
| 5455 | * regulator pointer |
| 5456 | * @val: New value for debug_corner |
| 5457 | * |
| 5458 | * Return: 0 on success, errno on failure |
| 5459 | */ |
| 5460 | static int cpr3_debug_corner_index_set(void *data, u64 val) |
| 5461 | { |
| 5462 | struct cpr3_regulator *vreg = data; |
| 5463 | |
| 5464 | if (val < CPR3_CORNER_OFFSET || val > vreg->corner_count) { |
| 5465 | cpr3_err(vreg, "invalid corner index %llu; allowed values: %d-%d\n", |
| 5466 | val, CPR3_CORNER_OFFSET, vreg->corner_count); |
| 5467 | return -EINVAL; |
| 5468 | } |
| 5469 | |
| 5470 | mutex_lock(&vreg->thread->ctrl->lock); |
| 5471 | vreg->debug_corner = val - CPR3_CORNER_OFFSET; |
| 5472 | mutex_unlock(&vreg->thread->ctrl->lock); |
| 5473 | |
| 5474 | return 0; |
| 5475 | } |
| 5476 | |
| 5477 | /** |
| 5478 | * cpr3_debug_corner_index_get() - debugfs callback used to retrieve |
| 5479 | * the value of the CPR3 regulator debug_corner index |
| 5480 | * @data: Pointer to private data which is equal to the CPR3 |
| 5481 | * regulator pointer |
| 5482 | * @val: Output parameter written with the value of |
| 5483 | * debug_corner |
| 5484 | * |
| 5485 | * Return: 0 on success, errno on failure |
| 5486 | */ |
| 5487 | static int cpr3_debug_corner_index_get(void *data, u64 *val) |
| 5488 | { |
| 5489 | struct cpr3_regulator *vreg = data; |
| 5490 | |
| 5491 | *val = vreg->debug_corner + CPR3_CORNER_OFFSET; |
| 5492 | |
| 5493 | return 0; |
| 5494 | } |
| 5495 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_index_fops, |
| 5496 | cpr3_debug_corner_index_get, |
| 5497 | cpr3_debug_corner_index_set, |
| 5498 | "%llu\n"); |
| 5499 | |
| 5500 | /** |
| 5501 | * cpr3_debug_current_corner_index_get() - debugfs callback used to retrieve |
| 5502 | * the value of the CPR3 regulator current_corner index |
| 5503 | * @data: Pointer to private data which is equal to the CPR3 |
| 5504 | * regulator pointer |
| 5505 | * @val: Output parameter written with the value of |
| 5506 | * current_corner |
| 5507 | * |
| 5508 | * Return: 0 on success, errno on failure |
| 5509 | */ |
| 5510 | static int cpr3_debug_current_corner_index_get(void *data, u64 *val) |
| 5511 | { |
| 5512 | struct cpr3_regulator *vreg = data; |
| 5513 | |
| 5514 | *val = vreg->current_corner + CPR3_CORNER_OFFSET; |
| 5515 | |
| 5516 | return 0; |
| 5517 | } |
| 5518 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_current_corner_index_fops, |
| 5519 | cpr3_debug_current_corner_index_get, |
| 5520 | NULL, "%llu\n"); |
| 5521 | |
| 5522 | /** |
| 5523 | * cpr3_regulator_debugfs_vreg_add() - add debugfs files to expose configuration |
| 5524 | * data for the CPR3 regulator |
| 5525 | * @vreg: Pointer to the CPR3 regulator |
| 5526 | * @thread_dir CPR3 thread debugfs directory handle |
| 5527 | * |
| 5528 | * Return: none |
| 5529 | */ |
| 5530 | static void cpr3_regulator_debugfs_vreg_add(struct cpr3_regulator *vreg, |
| 5531 | struct dentry *thread_dir) |
| 5532 | { |
| 5533 | struct dentry *temp, *corner_dir, *vreg_dir; |
| 5534 | |
| 5535 | vreg_dir = debugfs_create_dir(vreg->name, thread_dir); |
| 5536 | if (IS_ERR_OR_NULL(vreg_dir)) { |
| 5537 | cpr3_err(vreg, "%s debugfs directory creation failed\n", |
| 5538 | vreg->name); |
| 5539 | return; |
| 5540 | } |
| 5541 | |
| 5542 | temp = debugfs_create_int("speed_bin_fuse", 0444, vreg_dir, |
| 5543 | &vreg->speed_bin_fuse); |
| 5544 | if (IS_ERR_OR_NULL(temp)) { |
| 5545 | cpr3_err(vreg, "speed_bin_fuse debugfs file creation failed\n"); |
| 5546 | return; |
| 5547 | } |
| 5548 | |
| 5549 | temp = debugfs_create_int("cpr_rev_fuse", 0444, vreg_dir, |
| 5550 | &vreg->cpr_rev_fuse); |
| 5551 | if (IS_ERR_OR_NULL(temp)) { |
| 5552 | cpr3_err(vreg, "cpr_rev_fuse debugfs file creation failed\n"); |
| 5553 | return; |
| 5554 | } |
| 5555 | |
| 5556 | temp = debugfs_create_int("fuse_combo", 0444, vreg_dir, |
| 5557 | &vreg->fuse_combo); |
| 5558 | if (IS_ERR_OR_NULL(temp)) { |
| 5559 | cpr3_err(vreg, "fuse_combo debugfs file creation failed\n"); |
| 5560 | return; |
| 5561 | } |
| 5562 | |
| 5563 | if (vreg->ldo_regulator) { |
| 5564 | temp = debugfs_create_file("ldo_mode", 0444, vreg_dir, vreg, |
| 5565 | &cpr3_debug_ldo_mode_fops); |
| 5566 | if (IS_ERR_OR_NULL(temp)) { |
| 5567 | cpr3_err(vreg, "ldo_mode debugfs file creation failed\n"); |
| 5568 | return; |
| 5569 | } |
| 5570 | |
| 5571 | temp = debugfs_create_file("ldo_mode_allowed", |
| 5572 | 0644, vreg_dir, vreg, |
| 5573 | &cpr3_debug_ldo_mode_allowed_fops); |
| 5574 | if (IS_ERR_OR_NULL(temp)) { |
| 5575 | cpr3_err(vreg, "ldo_mode_allowed debugfs file creation failed\n"); |
| 5576 | return; |
| 5577 | } |
| 5578 | } |
| 5579 | |
| 5580 | temp = debugfs_create_int("corner_count", 0444, vreg_dir, |
| 5581 | &vreg->corner_count); |
| 5582 | if (IS_ERR_OR_NULL(temp)) { |
| 5583 | cpr3_err(vreg, "corner_count debugfs file creation failed\n"); |
| 5584 | return; |
| 5585 | } |
| 5586 | |
| 5587 | corner_dir = debugfs_create_dir("corner", vreg_dir); |
| 5588 | if (IS_ERR_OR_NULL(corner_dir)) { |
| 5589 | cpr3_err(vreg, "corner debugfs directory creation failed\n"); |
| 5590 | return; |
| 5591 | } |
| 5592 | |
| 5593 | temp = debugfs_create_file("index", 0644, corner_dir, vreg, |
| 5594 | &cpr3_debug_corner_index_fops); |
| 5595 | if (IS_ERR_OR_NULL(temp)) { |
| 5596 | cpr3_err(vreg, "index debugfs file creation failed\n"); |
| 5597 | return; |
| 5598 | } |
| 5599 | |
| 5600 | cpr3_regulator_debugfs_corner_add(vreg, corner_dir, |
| 5601 | &vreg->debug_corner); |
| 5602 | |
| 5603 | corner_dir = debugfs_create_dir("current_corner", vreg_dir); |
| 5604 | if (IS_ERR_OR_NULL(corner_dir)) { |
| 5605 | cpr3_err(vreg, "current_corner debugfs directory creation failed\n"); |
| 5606 | return; |
| 5607 | } |
| 5608 | |
| 5609 | temp = debugfs_create_file("index", 0444, corner_dir, vreg, |
| 5610 | &cpr3_debug_current_corner_index_fops); |
| 5611 | if (IS_ERR_OR_NULL(temp)) { |
| 5612 | cpr3_err(vreg, "index debugfs file creation failed\n"); |
| 5613 | return; |
| 5614 | } |
| 5615 | |
| 5616 | cpr3_regulator_debugfs_corner_add(vreg, corner_dir, |
| 5617 | &vreg->current_corner); |
| 5618 | } |
| 5619 | |
| 5620 | /** |
| 5621 | * cpr3_regulator_debugfs_thread_add() - add debugfs files to expose |
| 5622 | * configuration data for the CPR thread |
| 5623 | * @thread: Pointer to the CPR3 thread |
| 5624 | * |
| 5625 | * Return: none |
| 5626 | */ |
| 5627 | static void cpr3_regulator_debugfs_thread_add(struct cpr3_thread *thread) |
| 5628 | { |
| 5629 | struct cpr3_controller *ctrl = thread->ctrl; |
| 5630 | struct dentry *aggr_dir, *temp, *thread_dir; |
| 5631 | struct cpr3_debug_corner_info *info; |
| 5632 | char buf[20]; |
| 5633 | int *index; |
| 5634 | int i; |
| 5635 | |
| 5636 | scnprintf(buf, sizeof(buf), "thread%u", thread->thread_id); |
| 5637 | thread_dir = debugfs_create_dir(buf, thread->ctrl->debugfs); |
| 5638 | if (IS_ERR_OR_NULL(thread_dir)) { |
| 5639 | cpr3_err(ctrl, "thread %u %s debugfs directory creation failed\n", |
| 5640 | thread->thread_id, buf); |
| 5641 | return; |
| 5642 | } |
| 5643 | |
| 5644 | aggr_dir = debugfs_create_dir("max_aggregated_params", thread_dir); |
| 5645 | if (IS_ERR_OR_NULL(aggr_dir)) { |
| 5646 | cpr3_err(ctrl, "thread %u max_aggregated_params debugfs directory creation failed\n", |
| 5647 | thread->thread_id); |
| 5648 | return; |
| 5649 | } |
| 5650 | |
| 5651 | temp = debugfs_create_int("floor_volt", 0444, aggr_dir, |
| 5652 | &thread->aggr_corner.floor_volt); |
| 5653 | if (IS_ERR_OR_NULL(temp)) { |
| 5654 | cpr3_err(ctrl, "thread %u aggr floor_volt debugfs file creation failed\n", |
| 5655 | thread->thread_id); |
| 5656 | return; |
| 5657 | } |
| 5658 | |
| 5659 | temp = debugfs_create_int("ceiling_volt", 0444, aggr_dir, |
| 5660 | &thread->aggr_corner.ceiling_volt); |
| 5661 | if (IS_ERR_OR_NULL(temp)) { |
| 5662 | cpr3_err(ctrl, "thread %u aggr ceiling_volt debugfs file creation failed\n", |
| 5663 | thread->thread_id); |
| 5664 | return; |
| 5665 | } |
| 5666 | |
| 5667 | temp = debugfs_create_int("open_loop_volt", 0444, aggr_dir, |
| 5668 | &thread->aggr_corner.open_loop_volt); |
| 5669 | if (IS_ERR_OR_NULL(temp)) { |
| 5670 | cpr3_err(ctrl, "thread %u aggr open_loop_volt debugfs file creation failed\n", |
| 5671 | thread->thread_id); |
| 5672 | return; |
| 5673 | } |
| 5674 | |
| 5675 | temp = debugfs_create_int("last_volt", 0444, aggr_dir, |
| 5676 | &thread->aggr_corner.last_volt); |
| 5677 | if (IS_ERR_OR_NULL(temp)) { |
| 5678 | cpr3_err(ctrl, "thread %u aggr last_volt debugfs file creation failed\n", |
| 5679 | thread->thread_id); |
| 5680 | return; |
| 5681 | } |
| 5682 | |
| 5683 | info = devm_kzalloc(thread->ctrl->dev, sizeof(*info), GFP_KERNEL); |
| 5684 | index = devm_kzalloc(thread->ctrl->dev, sizeof(*index), GFP_KERNEL); |
| 5685 | if (!info || !index) |
| 5686 | return; |
| 5687 | *index = 0; |
| 5688 | info->vreg = &thread->vreg[0]; |
| 5689 | info->index = index; |
| 5690 | info->corner = &thread->aggr_corner; |
| 5691 | |
| 5692 | temp = debugfs_create_file("target_quots", 0444, aggr_dir, info, |
| 5693 | &cpr3_debug_quot_fops); |
| 5694 | if (IS_ERR_OR_NULL(temp)) { |
| 5695 | cpr3_err(ctrl, "thread %u target_quots debugfs file creation failed\n", |
| 5696 | thread->thread_id); |
| 5697 | return; |
| 5698 | } |
| 5699 | |
| 5700 | for (i = 0; i < thread->vreg_count; i++) |
| 5701 | cpr3_regulator_debugfs_vreg_add(&thread->vreg[i], thread_dir); |
| 5702 | } |
| 5703 | |
| 5704 | /** |
| 5705 | * cpr3_debug_closed_loop_enable_set() - debugfs callback used to change the |
| 5706 | * value of the CPR controller cpr_allowed_sw flag which enables or |
| 5707 | * disables closed-loop operation |
| 5708 | * @data: Pointer to private data which is equal to the CPR |
| 5709 | * controller pointer |
| 5710 | * @val: New value for cpr_allowed_sw |
| 5711 | * |
| 5712 | * Return: 0 on success, errno on failure |
| 5713 | */ |
| 5714 | static int cpr3_debug_closed_loop_enable_set(void *data, u64 val) |
| 5715 | { |
| 5716 | struct cpr3_controller *ctrl = data; |
| 5717 | bool enable = !!val; |
| 5718 | int rc; |
| 5719 | |
| 5720 | mutex_lock(&ctrl->lock); |
| 5721 | |
| 5722 | if (ctrl->cpr_allowed_sw == enable) |
| 5723 | goto done; |
| 5724 | |
| 5725 | if (enable && !ctrl->cpr_allowed_hw) { |
| 5726 | cpr3_err(ctrl, "CPR closed-loop operation is not allowed\n"); |
| 5727 | goto done; |
| 5728 | } |
| 5729 | |
| 5730 | ctrl->cpr_allowed_sw = enable; |
| 5731 | |
| 5732 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 5733 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 5734 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 5735 | ctrl->cpr_allowed_sw && ctrl->use_hw_closed_loop |
| 5736 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE |
| 5737 | : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); |
| 5738 | } else { |
| 5739 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 5740 | if (rc) { |
| 5741 | cpr3_err(ctrl, "could not change CPR enable state=%u, rc=%d\n", |
| 5742 | enable, rc); |
| 5743 | goto done; |
| 5744 | } |
| 5745 | |
| 5746 | if (ctrl->proc_clock_throttle && !ctrl->cpr_enabled) { |
| 5747 | rc = cpr3_clock_enable(ctrl); |
| 5748 | if (rc) { |
| 5749 | cpr3_err(ctrl, "clock enable failed, rc=%d\n", |
| 5750 | rc); |
| 5751 | goto done; |
| 5752 | } |
| 5753 | ctrl->cpr_enabled = true; |
| 5754 | |
| 5755 | cpr3_write(ctrl, CPR3_REG_PD_THROTTLE, |
| 5756 | CPR3_PD_THROTTLE_DISABLE); |
| 5757 | |
| 5758 | cpr3_clock_disable(ctrl); |
| 5759 | ctrl->cpr_enabled = false; |
| 5760 | } |
| 5761 | } |
| 5762 | |
| 5763 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 5764 | cpr3_debug(ctrl, "closed-loop=%s\n", enable ? |
| 5765 | "enabled" : "disabled"); |
| 5766 | } else { |
| 5767 | cpr3_debug(ctrl, "closed-loop=%s\n", enable && |
| 5768 | ctrl->use_hw_closed_loop ? "enabled" : "disabled"); |
| 5769 | } |
| 5770 | done: |
| 5771 | mutex_unlock(&ctrl->lock); |
| 5772 | return 0; |
| 5773 | } |
| 5774 | |
| 5775 | /** |
| 5776 | * cpr3_debug_closed_loop_enable_get() - debugfs callback used to retrieve |
| 5777 | * the value of the CPR controller cpr_allowed_sw flag which |
| 5778 | * indicates if closed-loop operation is enabled |
| 5779 | * @data: Pointer to private data which is equal to the CPR |
| 5780 | * controller pointer |
| 5781 | * @val: Output parameter written with the value of |
| 5782 | * cpr_allowed_sw |
| 5783 | * |
| 5784 | * Return: 0 on success, errno on failure |
| 5785 | */ |
| 5786 | static int cpr3_debug_closed_loop_enable_get(void *data, u64 *val) |
| 5787 | { |
| 5788 | struct cpr3_controller *ctrl = data; |
| 5789 | |
| 5790 | *val = ctrl->cpr_allowed_sw; |
| 5791 | |
| 5792 | return 0; |
| 5793 | } |
| 5794 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_closed_loop_enable_fops, |
| 5795 | cpr3_debug_closed_loop_enable_get, |
| 5796 | cpr3_debug_closed_loop_enable_set, |
| 5797 | "%llu\n"); |
| 5798 | |
| 5799 | /** |
| 5800 | * cpr3_debug_hw_closed_loop_enable_set() - debugfs callback used to change the |
| 5801 | * value of the CPR controller use_hw_closed_loop flag which |
| 5802 | * switches between software closed-loop and hardware closed-loop |
| 5803 | * operation for CPR3 and CPR4 controllers and between open-loop |
| 5804 | * and full hardware closed-loop operation for CPRh controllers. |
| 5805 | * @data: Pointer to private data which is equal to the CPR |
| 5806 | * controller pointer |
| 5807 | * @val: New value for use_hw_closed_loop |
| 5808 | * |
| 5809 | * Return: 0 on success, errno on failure |
| 5810 | */ |
| 5811 | static int cpr3_debug_hw_closed_loop_enable_set(void *data, u64 val) |
| 5812 | { |
| 5813 | struct cpr3_controller *ctrl = data; |
| 5814 | bool use_hw_closed_loop = !!val; |
| 5815 | struct cpr3_regulator *vreg; |
| 5816 | bool cpr_enabled; |
| 5817 | int i, j, k, rc; |
| 5818 | |
| 5819 | mutex_lock(&ctrl->lock); |
| 5820 | |
| 5821 | if (ctrl->use_hw_closed_loop == use_hw_closed_loop) |
| 5822 | goto done; |
| 5823 | |
| 5824 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 5825 | rc = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 5826 | if (rc) { |
| 5827 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 5828 | rc); |
| 5829 | goto done; |
| 5830 | } |
| 5831 | } |
| 5832 | |
| 5833 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) |
| 5834 | cpr3_ctrl_loop_disable(ctrl); |
| 5835 | |
| 5836 | ctrl->use_hw_closed_loop = use_hw_closed_loop; |
| 5837 | |
| 5838 | cpr_enabled = ctrl->cpr_enabled; |
| 5839 | |
| 5840 | /* Ensure that CPR clocks are enabled before writing to registers. */ |
| 5841 | if (!cpr_enabled) { |
| 5842 | rc = cpr3_clock_enable(ctrl); |
| 5843 | if (rc) { |
| 5844 | cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc); |
| 5845 | goto done; |
| 5846 | } |
| 5847 | ctrl->cpr_enabled = true; |
| 5848 | } |
| 5849 | |
| 5850 | if (ctrl->use_hw_closed_loop && ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) |
| 5851 | cpr3_write(ctrl, CPR3_REG_IRQ_EN, 0); |
| 5852 | |
| 5853 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 5854 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 5855 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 5856 | ctrl->use_hw_closed_loop |
| 5857 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE |
| 5858 | : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); |
| 5859 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPRH) { |
| 5860 | cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL, |
| 5861 | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, |
| 5862 | ctrl->cpr_allowed_sw && ctrl->use_hw_closed_loop |
| 5863 | ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE |
| 5864 | : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE); |
| 5865 | } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 5866 | cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP, |
| 5867 | ctrl->use_hw_closed_loop |
| 5868 | ? CPR3_HW_CLOSED_LOOP_ENABLE |
| 5869 | : CPR3_HW_CLOSED_LOOP_DISABLE); |
| 5870 | } |
| 5871 | |
| 5872 | /* Turn off CPR clocks if they were off before this function call. */ |
| 5873 | if (!cpr_enabled) { |
| 5874 | cpr3_clock_disable(ctrl); |
| 5875 | ctrl->cpr_enabled = false; |
| 5876 | } |
| 5877 | |
| 5878 | if (ctrl->use_hw_closed_loop && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 5879 | rc = regulator_enable(ctrl->vdd_limit_regulator); |
| 5880 | if (rc) { |
| 5881 | cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n", |
| 5882 | rc); |
| 5883 | goto done; |
| 5884 | } |
| 5885 | |
| 5886 | rc = msm_spm_avs_enable_irq(0, MSM_SPM_AVS_IRQ_MAX); |
| 5887 | if (rc) { |
| 5888 | cpr3_err(ctrl, "could not enable max IRQ, rc=%d\n", rc); |
| 5889 | goto done; |
| 5890 | } |
| 5891 | } else if (!ctrl->use_hw_closed_loop |
| 5892 | && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 5893 | rc = regulator_disable(ctrl->vdd_limit_regulator); |
| 5894 | if (rc) { |
| 5895 | cpr3_err(ctrl, "CPR limit regulator disable failed, rc=%d\n", |
| 5896 | rc); |
| 5897 | goto done; |
| 5898 | } |
| 5899 | |
| 5900 | rc = msm_spm_avs_disable_irq(0, MSM_SPM_AVS_IRQ_MAX); |
| 5901 | if (rc) { |
| 5902 | cpr3_err(ctrl, "could not disable max IRQ, rc=%d\n", |
| 5903 | rc); |
| 5904 | goto done; |
| 5905 | } |
| 5906 | } |
| 5907 | |
| 5908 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 5909 | /* |
| 5910 | * Due to APM and mem-acc floor restriction constraints, |
| 5911 | * the closed-loop voltage may be different when using |
| 5912 | * software closed-loop vs hardware closed-loop. Therefore, |
| 5913 | * reset the cached closed-loop voltage for all corners to the |
| 5914 | * corresponding open-loop voltage when switching between |
| 5915 | * SW and HW closed-loop mode. |
| 5916 | */ |
| 5917 | for (i = 0; i < ctrl->thread_count; i++) { |
| 5918 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 5919 | vreg = &ctrl->thread[i].vreg[j]; |
| 5920 | for (k = 0; k < vreg->corner_count; k++) |
| 5921 | vreg->corner[k].last_volt |
| 5922 | = vreg->corner[k].open_loop_volt; |
| 5923 | } |
| 5924 | } |
| 5925 | |
| 5926 | /* Skip last_volt caching */ |
| 5927 | ctrl->last_corner_was_closed_loop = false; |
| 5928 | |
| 5929 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 5930 | if (rc) { |
| 5931 | cpr3_err(ctrl, "could not change CPR HW closed-loop enable state=%u, rc=%d\n", |
| 5932 | use_hw_closed_loop, rc); |
| 5933 | goto done; |
| 5934 | } |
| 5935 | |
| 5936 | cpr3_debug(ctrl, "CPR mode=%s\n", |
| 5937 | use_hw_closed_loop ? |
| 5938 | "HW closed-loop" : "SW closed-loop"); |
| 5939 | } else { |
| 5940 | cpr3_debug(ctrl, "CPR mode=%s\n", |
| 5941 | ctrl->cpr_allowed_sw && use_hw_closed_loop ? |
| 5942 | "full HW closed-loop" : "open-loop"); |
| 5943 | } |
| 5944 | done: |
| 5945 | mutex_unlock(&ctrl->lock); |
| 5946 | return 0; |
| 5947 | } |
| 5948 | |
| 5949 | /** |
| 5950 | * cpr3_debug_hw_closed_loop_enable_get() - debugfs callback used to retrieve |
| 5951 | * the value of the CPR controller use_hw_closed_loop flag which |
| 5952 | * indicates if hardware closed-loop operation is being used in |
| 5953 | * place of software closed-loop operation |
| 5954 | * @data: Pointer to private data which is equal to the CPR |
| 5955 | * controller pointer |
| 5956 | * @val: Output parameter written with the value of |
| 5957 | * use_hw_closed_loop |
| 5958 | * |
| 5959 | * Return: 0 on success, errno on failure |
| 5960 | */ |
| 5961 | static int cpr3_debug_hw_closed_loop_enable_get(void *data, u64 *val) |
| 5962 | { |
| 5963 | struct cpr3_controller *ctrl = data; |
| 5964 | |
| 5965 | *val = ctrl->use_hw_closed_loop; |
| 5966 | |
| 5967 | return 0; |
| 5968 | } |
| 5969 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_hw_closed_loop_enable_fops, |
| 5970 | cpr3_debug_hw_closed_loop_enable_get, |
| 5971 | cpr3_debug_hw_closed_loop_enable_set, |
| 5972 | "%llu\n"); |
| 5973 | |
| 5974 | /** |
| 5975 | * cpr3_debug_trigger_aging_measurement_set() - debugfs callback used to trigger |
| 5976 | * another CPR measurement |
| 5977 | * @data: Pointer to private data which is equal to the CPR |
| 5978 | * controller pointer |
| 5979 | * @val: Unused |
| 5980 | * |
| 5981 | * Return: 0 on success, errno on failure |
| 5982 | */ |
| 5983 | static int cpr3_debug_trigger_aging_measurement_set(void *data, u64 val) |
| 5984 | { |
| 5985 | struct cpr3_controller *ctrl = data; |
| 5986 | int rc; |
| 5987 | |
| 5988 | mutex_lock(&ctrl->lock); |
| 5989 | |
| 5990 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 5991 | rc = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 5992 | if (rc) { |
| 5993 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 5994 | rc); |
| 5995 | goto done; |
| 5996 | } |
| 5997 | } |
| 5998 | |
| 5999 | cpr3_ctrl_loop_disable(ctrl); |
| 6000 | |
| 6001 | cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX); |
| 6002 | ctrl->aging_required = true; |
| 6003 | ctrl->aging_succeeded = false; |
| 6004 | ctrl->aging_failed = false; |
| 6005 | |
| 6006 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 6007 | if (rc) { |
| 6008 | cpr3_err(ctrl, "could not update the CPR controller state, rc=%d\n", |
| 6009 | rc); |
| 6010 | goto done; |
| 6011 | } |
| 6012 | |
| 6013 | done: |
| 6014 | mutex_unlock(&ctrl->lock); |
| 6015 | return 0; |
| 6016 | } |
| 6017 | DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_trigger_aging_measurement_fops, |
| 6018 | NULL, |
| 6019 | cpr3_debug_trigger_aging_measurement_set, |
| 6020 | "%llu\n"); |
| 6021 | |
| 6022 | /** |
| 6023 | * cpr3_regulator_debugfs_ctrl_add() - add debugfs files to expose configuration |
| 6024 | * data for the CPR controller |
| 6025 | * @ctrl: Pointer to the CPR3 controller |
| 6026 | * |
| 6027 | * Return: none |
| 6028 | */ |
| 6029 | static void cpr3_regulator_debugfs_ctrl_add(struct cpr3_controller *ctrl) |
| 6030 | { |
| 6031 | struct dentry *temp, *aggr_dir; |
| 6032 | int i; |
| 6033 | |
| 6034 | /* Add cpr3-regulator base directory if it isn't present already. */ |
| 6035 | if (cpr3_debugfs_base == NULL) { |
| 6036 | cpr3_debugfs_base = debugfs_create_dir("cpr3-regulator", NULL); |
| 6037 | if (IS_ERR_OR_NULL(cpr3_debugfs_base)) { |
| 6038 | cpr3_err(ctrl, "cpr3-regulator debugfs base directory creation failed\n"); |
| 6039 | cpr3_debugfs_base = NULL; |
| 6040 | return; |
| 6041 | } |
| 6042 | } |
| 6043 | |
| 6044 | ctrl->debugfs = debugfs_create_dir(ctrl->name, cpr3_debugfs_base); |
| 6045 | if (IS_ERR_OR_NULL(ctrl->debugfs)) { |
| 6046 | cpr3_err(ctrl, "cpr3-regulator controller debugfs directory creation failed\n"); |
| 6047 | return; |
| 6048 | } |
| 6049 | |
| 6050 | temp = debugfs_create_file("cpr_closed_loop_enable", 0644, |
| 6051 | ctrl->debugfs, ctrl, |
| 6052 | &cpr3_debug_closed_loop_enable_fops); |
| 6053 | if (IS_ERR_OR_NULL(temp)) { |
| 6054 | cpr3_err(ctrl, "cpr_closed_loop_enable debugfs file creation failed\n"); |
| 6055 | return; |
| 6056 | } |
| 6057 | |
| 6058 | if (ctrl->supports_hw_closed_loop) { |
| 6059 | temp = debugfs_create_file("use_hw_closed_loop", 0644, |
| 6060 | ctrl->debugfs, ctrl, |
| 6061 | &cpr3_debug_hw_closed_loop_enable_fops); |
| 6062 | if (IS_ERR_OR_NULL(temp)) { |
| 6063 | cpr3_err(ctrl, "use_hw_closed_loop debugfs file creation failed\n"); |
| 6064 | return; |
| 6065 | } |
| 6066 | } |
| 6067 | |
| 6068 | temp = debugfs_create_int("thread_count", 0444, ctrl->debugfs, |
| 6069 | &ctrl->thread_count); |
| 6070 | if (IS_ERR_OR_NULL(temp)) { |
| 6071 | cpr3_err(ctrl, "thread_count debugfs file creation failed\n"); |
| 6072 | return; |
| 6073 | } |
| 6074 | |
| 6075 | if (ctrl->apm) { |
| 6076 | temp = debugfs_create_int("apm_threshold_volt", 0444, |
| 6077 | ctrl->debugfs, &ctrl->apm_threshold_volt); |
| 6078 | if (IS_ERR_OR_NULL(temp)) { |
| 6079 | cpr3_err(ctrl, "apm_threshold_volt debugfs file creation failed\n"); |
| 6080 | return; |
| 6081 | } |
| 6082 | } |
| 6083 | |
| 6084 | if (ctrl->aging_required || ctrl->aging_succeeded |
| 6085 | || ctrl->aging_failed) { |
| 6086 | temp = debugfs_create_int("aging_adj_volt", 0444, |
| 6087 | ctrl->debugfs, &ctrl->aging_ref_adjust_volt); |
| 6088 | if (IS_ERR_OR_NULL(temp)) { |
| 6089 | cpr3_err(ctrl, "aging_adj_volt debugfs file creation failed\n"); |
| 6090 | return; |
| 6091 | } |
| 6092 | |
| 6093 | temp = debugfs_create_file("aging_succeeded", 0444, |
| 6094 | ctrl->debugfs, &ctrl->aging_succeeded, &fops_bool_ro); |
| 6095 | if (IS_ERR_OR_NULL(temp)) { |
| 6096 | cpr3_err(ctrl, "aging_succeeded debugfs file creation failed\n"); |
| 6097 | return; |
| 6098 | } |
| 6099 | |
| 6100 | temp = debugfs_create_file("aging_failed", 0444, |
| 6101 | ctrl->debugfs, &ctrl->aging_failed, &fops_bool_ro); |
| 6102 | if (IS_ERR_OR_NULL(temp)) { |
| 6103 | cpr3_err(ctrl, "aging_failed debugfs file creation failed\n"); |
| 6104 | return; |
| 6105 | } |
| 6106 | |
| 6107 | temp = debugfs_create_file("aging_trigger", 0200, |
| 6108 | ctrl->debugfs, ctrl, |
| 6109 | &cpr3_debug_trigger_aging_measurement_fops); |
| 6110 | if (IS_ERR_OR_NULL(temp)) { |
| 6111 | cpr3_err(ctrl, "aging_trigger debugfs file creation failed\n"); |
| 6112 | return; |
| 6113 | } |
| 6114 | } |
| 6115 | |
| 6116 | aggr_dir = debugfs_create_dir("max_aggregated_voltages", ctrl->debugfs); |
| 6117 | if (IS_ERR_OR_NULL(aggr_dir)) { |
| 6118 | cpr3_err(ctrl, "max_aggregated_voltages debugfs directory creation failed\n"); |
| 6119 | return; |
| 6120 | } |
| 6121 | |
| 6122 | temp = debugfs_create_int("floor_volt", 0444, aggr_dir, |
| 6123 | &ctrl->aggr_corner.floor_volt); |
| 6124 | if (IS_ERR_OR_NULL(temp)) { |
| 6125 | cpr3_err(ctrl, "aggr floor_volt debugfs file creation failed\n"); |
| 6126 | return; |
| 6127 | } |
| 6128 | |
| 6129 | temp = debugfs_create_int("ceiling_volt", 0444, aggr_dir, |
| 6130 | &ctrl->aggr_corner.ceiling_volt); |
| 6131 | if (IS_ERR_OR_NULL(temp)) { |
| 6132 | cpr3_err(ctrl, "aggr ceiling_volt debugfs file creation failed\n"); |
| 6133 | return; |
| 6134 | } |
| 6135 | |
| 6136 | temp = debugfs_create_int("open_loop_volt", 0444, aggr_dir, |
| 6137 | &ctrl->aggr_corner.open_loop_volt); |
| 6138 | if (IS_ERR_OR_NULL(temp)) { |
| 6139 | cpr3_err(ctrl, "aggr open_loop_volt debugfs file creation failed\n"); |
| 6140 | return; |
| 6141 | } |
| 6142 | |
| 6143 | temp = debugfs_create_int("last_volt", 0444, aggr_dir, |
| 6144 | &ctrl->aggr_corner.last_volt); |
| 6145 | if (IS_ERR_OR_NULL(temp)) { |
| 6146 | cpr3_err(ctrl, "aggr last_volt debugfs file creation failed\n"); |
| 6147 | return; |
| 6148 | } |
| 6149 | |
| 6150 | for (i = 0; i < ctrl->thread_count; i++) |
| 6151 | cpr3_regulator_debugfs_thread_add(&ctrl->thread[i]); |
| 6152 | } |
| 6153 | |
| 6154 | /** |
| 6155 | * cpr3_regulator_debugfs_ctrl_remove() - remove debugfs files for the CPR |
| 6156 | * controller |
| 6157 | * @ctrl: Pointer to the CPR3 controller |
| 6158 | * |
| 6159 | * Note, this function must be called after the controller has been removed from |
| 6160 | * cpr3_controller_list and while the cpr3_controller_list_mutex lock is held. |
| 6161 | * |
| 6162 | * Return: none |
| 6163 | */ |
| 6164 | static void cpr3_regulator_debugfs_ctrl_remove(struct cpr3_controller *ctrl) |
| 6165 | { |
| 6166 | if (list_empty(&cpr3_controller_list)) { |
| 6167 | debugfs_remove_recursive(cpr3_debugfs_base); |
| 6168 | cpr3_debugfs_base = NULL; |
| 6169 | } else { |
| 6170 | debugfs_remove_recursive(ctrl->debugfs); |
| 6171 | } |
| 6172 | } |
| 6173 | |
| 6174 | /** |
| 6175 | * cpr3_regulator_init_ctrl_data() - performs initialization of CPR controller |
| 6176 | * elements |
| 6177 | * @ctrl: Pointer to the CPR3 controller |
| 6178 | * |
| 6179 | * Return: 0 on success, errno on failure |
| 6180 | */ |
| 6181 | static int cpr3_regulator_init_ctrl_data(struct cpr3_controller *ctrl) |
| 6182 | { |
| 6183 | /* Read the initial vdd voltage from hardware. */ |
| 6184 | ctrl->aggr_corner.last_volt |
| 6185 | = regulator_get_voltage(ctrl->vdd_regulator); |
| 6186 | if (ctrl->aggr_corner.last_volt < 0) { |
| 6187 | cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n", |
| 6188 | ctrl->aggr_corner.last_volt); |
| 6189 | return ctrl->aggr_corner.last_volt; |
| 6190 | } |
| 6191 | ctrl->aggr_corner.open_loop_volt = ctrl->aggr_corner.last_volt; |
| 6192 | |
| 6193 | return 0; |
| 6194 | } |
| 6195 | |
| 6196 | /** |
| 6197 | * cpr3_regulator_init_vreg_data() - performs initialization of common CPR3 |
| 6198 | * regulator elements and validate aging configurations |
| 6199 | * @vreg: Pointer to the CPR3 regulator |
| 6200 | * |
| 6201 | * Return: 0 on success, errno on failure |
| 6202 | */ |
| 6203 | static int cpr3_regulator_init_vreg_data(struct cpr3_regulator *vreg) |
| 6204 | { |
| 6205 | int i, j; |
| 6206 | bool init_aging; |
| 6207 | |
| 6208 | vreg->current_corner = CPR3_REGULATOR_CORNER_INVALID; |
| 6209 | vreg->last_closed_loop_corner = CPR3_REGULATOR_CORNER_INVALID; |
| 6210 | |
| 6211 | init_aging = vreg->aging_allowed && vreg->thread->ctrl->aging_required; |
| 6212 | |
| 6213 | for (i = 0; i < vreg->corner_count; i++) { |
| 6214 | vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt; |
| 6215 | vreg->corner[i].irq_en = CPR3_IRQ_UP | CPR3_IRQ_DOWN; |
| 6216 | |
| 6217 | vreg->corner[i].ro_mask = 0; |
| 6218 | for (j = 0; j < CPR3_RO_COUNT; j++) { |
| 6219 | if (vreg->corner[i].target_quot[j] == 0) |
| 6220 | vreg->corner[i].ro_mask |= BIT(j); |
| 6221 | } |
| 6222 | |
| 6223 | if (init_aging) { |
| 6224 | vreg->corner[i].unaged_floor_volt |
| 6225 | = vreg->corner[i].floor_volt; |
| 6226 | vreg->corner[i].unaged_ceiling_volt |
| 6227 | = vreg->corner[i].ceiling_volt; |
| 6228 | vreg->corner[i].unaged_open_loop_volt |
| 6229 | = vreg->corner[i].open_loop_volt; |
| 6230 | } |
| 6231 | |
| 6232 | if (vreg->aging_allowed) { |
| 6233 | if (vreg->corner[i].unaged_floor_volt <= 0) { |
| 6234 | cpr3_err(vreg, "invalid unaged_floor_volt[%d] = %d\n", |
| 6235 | i, vreg->corner[i].unaged_floor_volt); |
| 6236 | return -EINVAL; |
| 6237 | } |
| 6238 | if (vreg->corner[i].unaged_ceiling_volt <= 0) { |
| 6239 | cpr3_err(vreg, "invalid unaged_ceiling_volt[%d] = %d\n", |
| 6240 | i, vreg->corner[i].unaged_ceiling_volt); |
| 6241 | return -EINVAL; |
| 6242 | } |
| 6243 | if (vreg->corner[i].unaged_open_loop_volt <= 0) { |
| 6244 | cpr3_err(vreg, "invalid unaged_open_loop_volt[%d] = %d\n", |
| 6245 | i, vreg->corner[i].unaged_open_loop_volt); |
| 6246 | return -EINVAL; |
| 6247 | } |
| 6248 | } |
| 6249 | } |
| 6250 | |
| 6251 | if (vreg->aging_allowed && vreg->corner[vreg->aging_corner].ceiling_volt |
| 6252 | > vreg->thread->ctrl->aging_ref_volt) { |
| 6253 | cpr3_err(vreg, "aging corner %d ceiling voltage = %d > aging ref voltage = %d uV\n", |
| 6254 | vreg->aging_corner, |
| 6255 | vreg->corner[vreg->aging_corner].ceiling_volt, |
| 6256 | vreg->thread->ctrl->aging_ref_volt); |
| 6257 | return -EINVAL; |
| 6258 | } |
| 6259 | |
| 6260 | return 0; |
| 6261 | } |
| 6262 | |
| 6263 | /** |
| 6264 | * cpr3_regulator_suspend() - perform common required CPR3 power down steps |
| 6265 | * before the system enters suspend |
| 6266 | * @ctrl: Pointer to the CPR3 controller |
| 6267 | * |
| 6268 | * Return: 0 on success, errno on failure |
| 6269 | */ |
| 6270 | int cpr3_regulator_suspend(struct cpr3_controller *ctrl) |
| 6271 | { |
| 6272 | int rc; |
| 6273 | |
| 6274 | mutex_lock(&ctrl->lock); |
| 6275 | |
| 6276 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
| 6277 | rc = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 6278 | if (rc) { |
| 6279 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 6280 | rc); |
| 6281 | mutex_unlock(&ctrl->lock); |
| 6282 | return rc; |
| 6283 | } |
| 6284 | } |
| 6285 | |
| 6286 | cpr3_ctrl_loop_disable(ctrl); |
| 6287 | |
| 6288 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 6289 | rc = cpr3_closed_loop_disable(ctrl); |
| 6290 | if (rc) |
| 6291 | cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc); |
| 6292 | |
| 6293 | ctrl->cpr_suspended = true; |
| 6294 | } |
| 6295 | |
| 6296 | mutex_unlock(&ctrl->lock); |
| 6297 | return 0; |
| 6298 | } |
| 6299 | |
| 6300 | /** |
| 6301 | * cpr3_regulator_resume() - perform common required CPR3 power up steps after |
| 6302 | * the system resumes from suspend |
| 6303 | * @ctrl: Pointer to the CPR3 controller |
| 6304 | * |
| 6305 | * Return: 0 on success, errno on failure |
| 6306 | */ |
| 6307 | int cpr3_regulator_resume(struct cpr3_controller *ctrl) |
| 6308 | { |
| 6309 | int rc; |
| 6310 | |
| 6311 | mutex_lock(&ctrl->lock); |
| 6312 | |
| 6313 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 6314 | ctrl->cpr_suspended = false; |
| 6315 | rc = cpr3_regulator_update_ctrl_state(ctrl); |
| 6316 | if (rc) |
| 6317 | cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc); |
| 6318 | } else { |
| 6319 | cpr3_ctrl_loop_enable(ctrl); |
| 6320 | } |
| 6321 | |
| 6322 | mutex_unlock(&ctrl->lock); |
| 6323 | return 0; |
| 6324 | } |
| 6325 | |
| 6326 | /** |
| 6327 | * cpr3_regulator_cpu_hotplug_callback() - reset CPR IRQ affinity when a CPU is |
| 6328 | * brought online via hotplug |
| 6329 | * @nb: Pointer to the notifier block |
| 6330 | * @action: hotplug action |
| 6331 | * @hcpu: long value corresponding to the CPU number |
| 6332 | * |
| 6333 | * Return: NOTIFY_OK |
| 6334 | */ |
| 6335 | static int cpr3_regulator_cpu_hotplug_callback(struct notifier_block *nb, |
| 6336 | unsigned long action, void *hcpu) |
| 6337 | { |
| 6338 | struct cpr3_controller *ctrl = container_of(nb, struct cpr3_controller, |
| 6339 | cpu_hotplug_notifier); |
| 6340 | int cpu = (long)hcpu; |
| 6341 | |
| 6342 | action &= ~CPU_TASKS_FROZEN; |
| 6343 | |
| 6344 | if (action == CPU_ONLINE |
| 6345 | && cpumask_test_cpu(cpu, &ctrl->irq_affinity_mask)) |
| 6346 | irq_set_affinity(ctrl->irq, &ctrl->irq_affinity_mask); |
| 6347 | |
| 6348 | return NOTIFY_OK; |
| 6349 | } |
| 6350 | |
| 6351 | /** |
| 6352 | * cpr3_regulator_validate_controller() - verify the data passed in via the |
| 6353 | * cpr3_controller data structure |
| 6354 | * @ctrl: Pointer to the CPR3 controller |
| 6355 | * |
| 6356 | * Return: 0 on success, errno on failure |
| 6357 | */ |
| 6358 | static int cpr3_regulator_validate_controller(struct cpr3_controller *ctrl) |
| 6359 | { |
| 6360 | struct cpr3_thread *thread; |
| 6361 | struct cpr3_regulator *vreg; |
| 6362 | int i, j, allow_boost_vreg_count = 0; |
| 6363 | |
| 6364 | if (!ctrl->vdd_regulator && ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 6365 | cpr3_err(ctrl, "vdd regulator missing\n"); |
| 6366 | return -EINVAL; |
| 6367 | } else if (ctrl->sensor_count <= 0 |
| 6368 | || ctrl->sensor_count > CPR3_MAX_SENSOR_COUNT) { |
| 6369 | cpr3_err(ctrl, "invalid CPR sensor count=%d\n", |
| 6370 | ctrl->sensor_count); |
| 6371 | return -EINVAL; |
| 6372 | } else if (!ctrl->sensor_owner) { |
| 6373 | cpr3_err(ctrl, "CPR sensor ownership table missing\n"); |
| 6374 | return -EINVAL; |
| 6375 | } |
| 6376 | |
| 6377 | if (ctrl->aging_required) { |
| 6378 | for (i = 0; i < ctrl->aging_sensor_count; i++) { |
| 6379 | if (ctrl->aging_sensor[i].sensor_id |
| 6380 | >= ctrl->sensor_count) { |
| 6381 | cpr3_err(ctrl, "aging_sensor[%d] id=%u is not in the value range 0-%d", |
| 6382 | i, ctrl->aging_sensor[i].sensor_id, |
| 6383 | ctrl->sensor_count - 1); |
| 6384 | return -EINVAL; |
| 6385 | } |
| 6386 | } |
| 6387 | } |
| 6388 | |
| 6389 | for (i = 0; i < ctrl->thread_count; i++) { |
| 6390 | thread = &ctrl->thread[i]; |
| 6391 | for (j = 0; j < thread->vreg_count; j++) { |
| 6392 | vreg = &thread->vreg[j]; |
| 6393 | if (vreg->allow_boost) |
| 6394 | allow_boost_vreg_count++; |
| 6395 | } |
| 6396 | } |
| 6397 | |
| 6398 | if (allow_boost_vreg_count > 1) { |
| 6399 | /* |
| 6400 | * Boost feature is not allowed to be used for more |
| 6401 | * than one CPR3 regulator of a CPR3 controller. |
| 6402 | */ |
| 6403 | cpr3_err(ctrl, "Boost feature is enabled for more than one regulator\n"); |
| 6404 | return -EINVAL; |
| 6405 | } |
| 6406 | |
| 6407 | return 0; |
| 6408 | } |
| 6409 | |
| 6410 | /** |
| 6411 | * cpr3_panic_callback() - panic notification callback function. This function |
| 6412 | * is invoked when a kernel panic occurs. |
| 6413 | * @nfb: Notifier block pointer of CPR3 controller |
| 6414 | * @event: Value passed unmodified to notifier function |
| 6415 | * @data: Pointer passed unmodified to notifier function |
| 6416 | * |
| 6417 | * Return: NOTIFY_OK |
| 6418 | */ |
| 6419 | static int cpr3_panic_callback(struct notifier_block *nfb, |
| 6420 | unsigned long event, void *data) |
| 6421 | { |
| 6422 | struct cpr3_controller *ctrl = container_of(nfb, |
| 6423 | struct cpr3_controller, panic_notifier); |
| 6424 | struct cpr3_panic_regs_info *regs_info = ctrl->panic_regs_info; |
| 6425 | struct cpr3_reg_info *reg; |
| 6426 | int i = 0; |
| 6427 | |
| 6428 | for (i = 0; i < regs_info->reg_count; i++) { |
| 6429 | reg = &(regs_info->regs[i]); |
| 6430 | reg->value = readl_relaxed(reg->virt_addr); |
| 6431 | pr_err("%s[0x%08x] = 0x%08x\n", reg->name, reg->addr, |
| 6432 | reg->value); |
| 6433 | } |
| 6434 | /* |
| 6435 | * Barrier to ensure that the information has been updated in the |
| 6436 | * structure. |
| 6437 | */ |
| 6438 | mb(); |
| 6439 | |
| 6440 | return NOTIFY_OK; |
| 6441 | } |
| 6442 | |
| 6443 | /** |
| 6444 | * cpr3_regulator_register() - register the regulators for a CPR3 controller and |
| 6445 | * perform CPR hardware initialization |
| 6446 | * @pdev: Platform device pointer for the CPR3 controller |
| 6447 | * @ctrl: Pointer to the CPR3 controller |
| 6448 | * |
| 6449 | * Return: 0 on success, errno on failure |
| 6450 | */ |
| 6451 | int cpr3_regulator_register(struct platform_device *pdev, |
| 6452 | struct cpr3_controller *ctrl) |
| 6453 | { |
| 6454 | struct device *dev = &pdev->dev; |
| 6455 | struct resource *res; |
| 6456 | int i, j, rc; |
| 6457 | |
| 6458 | if (!dev->of_node) { |
| 6459 | dev_err(dev, "%s: Device tree node is missing\n", __func__); |
| 6460 | return -EINVAL; |
| 6461 | } |
| 6462 | |
| 6463 | if (!ctrl || !ctrl->name) { |
| 6464 | dev_err(dev, "%s: CPR controller data is missing\n", __func__); |
| 6465 | return -EINVAL; |
| 6466 | } |
| 6467 | |
| 6468 | rc = cpr3_regulator_validate_controller(ctrl); |
| 6469 | if (rc) { |
| 6470 | cpr3_err(ctrl, "controller validation failed, rc=%d\n", rc); |
| 6471 | return rc; |
| 6472 | } |
| 6473 | |
| 6474 | mutex_init(&ctrl->lock); |
| 6475 | |
| 6476 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpr_ctrl"); |
| 6477 | if (!res || !res->start) { |
| 6478 | cpr3_err(ctrl, "CPR controller address is missing\n"); |
| 6479 | return -ENXIO; |
| 6480 | } |
| 6481 | ctrl->cpr_ctrl_base = devm_ioremap(dev, res->start, resource_size(res)); |
| 6482 | |
David Collins | ee80499 | 2017-07-21 15:20:19 -0700 | [diff] [blame] | 6483 | if (cpr3_regulator_cprh_initialized(ctrl)) { |
| 6484 | cpr3_err(ctrl, "CPRh controller already initialized by boot loader\n"); |
| 6485 | return -EPERM; |
| 6486 | } |
| 6487 | |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 6488 | if (ctrl->aging_possible_mask) { |
| 6489 | /* |
| 6490 | * Aging possible register address is required if an aging |
| 6491 | * possible mask has been specified. |
| 6492 | */ |
| 6493 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 6494 | "aging_allowed"); |
| 6495 | if (!res || !res->start) { |
| 6496 | cpr3_err(ctrl, "CPR aging allowed address is missing\n"); |
| 6497 | return -ENXIO; |
| 6498 | } |
| 6499 | ctrl->aging_possible_reg = devm_ioremap(dev, res->start, |
| 6500 | resource_size(res)); |
| 6501 | } |
| 6502 | |
| 6503 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 6504 | ctrl->irq = platform_get_irq_byname(pdev, "cpr"); |
| 6505 | if (ctrl->irq < 0) { |
| 6506 | cpr3_err(ctrl, "missing CPR interrupt\n"); |
| 6507 | return ctrl->irq; |
| 6508 | } |
| 6509 | } |
| 6510 | |
| 6511 | if (ctrl->supports_hw_closed_loop) { |
David Collins | 54f78b7 | 2017-02-24 11:18:57 -0800 | [diff] [blame] | 6512 | rc = cpr3_regulator_init_hw_closed_loop_dependencies(pdev, |
| 6513 | ctrl); |
| 6514 | if (rc) |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 6515 | return rc; |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 6516 | |
| 6517 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 6518 | ctrl->ceiling_irq = platform_get_irq_byname(pdev, |
| 6519 | "ceiling"); |
| 6520 | if (ctrl->ceiling_irq < 0) { |
| 6521 | cpr3_err(ctrl, "missing ceiling interrupt\n"); |
| 6522 | return ctrl->ceiling_irq; |
| 6523 | } |
| 6524 | } |
| 6525 | } |
| 6526 | |
| 6527 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 6528 | rc = cpr3_regulator_init_ctrl_data(ctrl); |
| 6529 | if (rc) { |
| 6530 | cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n", |
| 6531 | rc); |
| 6532 | return rc; |
| 6533 | } |
| 6534 | } |
| 6535 | |
| 6536 | for (i = 0; i < ctrl->thread_count; i++) { |
| 6537 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 6538 | rc = cpr3_regulator_init_vreg_data( |
| 6539 | &ctrl->thread[i].vreg[j]); |
| 6540 | if (rc) |
| 6541 | return rc; |
| 6542 | cpr3_print_quots(&ctrl->thread[i].vreg[j]); |
| 6543 | } |
| 6544 | } |
| 6545 | |
| 6546 | /* |
| 6547 | * Add the maximum possible aging voltage margin until it is possible |
| 6548 | * to perform an aging measurement. |
| 6549 | */ |
| 6550 | if (ctrl->aging_required) |
| 6551 | cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX); |
| 6552 | |
| 6553 | rc = cpr3_regulator_init_ctrl(ctrl); |
| 6554 | if (rc) { |
| 6555 | cpr3_err(ctrl, "CPR controller initialization failed, rc=%d\n", |
| 6556 | rc); |
| 6557 | return rc; |
| 6558 | } |
| 6559 | |
| 6560 | /* Register regulator devices for all threads. */ |
| 6561 | for (i = 0; i < ctrl->thread_count; i++) { |
| 6562 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) { |
| 6563 | rc = cpr3_regulator_vreg_register( |
| 6564 | &ctrl->thread[i].vreg[j]); |
| 6565 | if (rc) { |
| 6566 | cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n", |
| 6567 | rc); |
| 6568 | goto free_regulators; |
| 6569 | } |
| 6570 | } |
| 6571 | } |
| 6572 | |
| 6573 | if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPRH) { |
| 6574 | rc = devm_request_threaded_irq(dev, ctrl->irq, NULL, |
| 6575 | cpr3_irq_handler, |
| 6576 | IRQF_ONESHOT | |
| 6577 | IRQF_TRIGGER_RISING, |
| 6578 | "cpr3", ctrl); |
| 6579 | if (rc) { |
| 6580 | cpr3_err(ctrl, "could not request IRQ %d, rc=%d\n", |
| 6581 | ctrl->irq, rc); |
| 6582 | goto free_regulators; |
| 6583 | } |
| 6584 | } |
| 6585 | |
| 6586 | if (ctrl->supports_hw_closed_loop && |
| 6587 | ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) { |
| 6588 | rc = devm_request_threaded_irq(dev, ctrl->ceiling_irq, NULL, |
| 6589 | cpr3_ceiling_irq_handler, |
| 6590 | IRQF_ONESHOT | IRQF_TRIGGER_RISING, |
| 6591 | "cpr3_ceiling", ctrl); |
| 6592 | if (rc) { |
| 6593 | cpr3_err(ctrl, "could not request ceiling IRQ %d, rc=%d\n", |
| 6594 | ctrl->ceiling_irq, rc); |
| 6595 | goto free_regulators; |
| 6596 | } |
| 6597 | } |
| 6598 | |
| 6599 | if (ctrl->irq && !cpumask_empty(&ctrl->irq_affinity_mask)) { |
| 6600 | irq_set_affinity(ctrl->irq, &ctrl->irq_affinity_mask); |
| 6601 | |
| 6602 | ctrl->cpu_hotplug_notifier.notifier_call |
| 6603 | = cpr3_regulator_cpu_hotplug_callback; |
| 6604 | register_hotcpu_notifier(&ctrl->cpu_hotplug_notifier); |
| 6605 | } |
| 6606 | |
| 6607 | mutex_lock(&cpr3_controller_list_mutex); |
| 6608 | cpr3_regulator_debugfs_ctrl_add(ctrl); |
| 6609 | list_add(&ctrl->list, &cpr3_controller_list); |
| 6610 | mutex_unlock(&cpr3_controller_list_mutex); |
| 6611 | |
| 6612 | if (ctrl->panic_regs_info) { |
| 6613 | /* Register panic notification call back */ |
| 6614 | ctrl->panic_notifier.notifier_call = cpr3_panic_callback; |
| 6615 | atomic_notifier_chain_register(&panic_notifier_list, |
| 6616 | &ctrl->panic_notifier); |
| 6617 | } |
| 6618 | |
| 6619 | return 0; |
| 6620 | |
| 6621 | free_regulators: |
| 6622 | for (i = 0; i < ctrl->thread_count; i++) |
| 6623 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) |
| 6624 | if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev)) |
| 6625 | regulator_unregister( |
| 6626 | ctrl->thread[i].vreg[j].rdev); |
| 6627 | return rc; |
| 6628 | } |
| 6629 | |
| 6630 | /** |
| 6631 | * cpr3_regulator_unregister() - unregister the regulators for a CPR3 controller |
| 6632 | * and perform CPR hardware shutdown |
| 6633 | * @ctrl: Pointer to the CPR3 controller |
| 6634 | * |
| 6635 | * Return: 0 on success, errno on failure |
| 6636 | */ |
| 6637 | int cpr3_regulator_unregister(struct cpr3_controller *ctrl) |
| 6638 | { |
| 6639 | int i, j, rc = 0; |
| 6640 | |
| 6641 | mutex_lock(&cpr3_controller_list_mutex); |
| 6642 | list_del(&ctrl->list); |
| 6643 | cpr3_regulator_debugfs_ctrl_remove(ctrl); |
| 6644 | mutex_unlock(&cpr3_controller_list_mutex); |
| 6645 | |
| 6646 | if (ctrl->irq && !cpumask_empty(&ctrl->irq_affinity_mask)) |
| 6647 | unregister_hotcpu_notifier(&ctrl->cpu_hotplug_notifier); |
| 6648 | |
Stephen Boyd | 09e9be0 | 2017-03-16 15:34:52 -0700 | [diff] [blame] | 6649 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 6650 | rc = cpr3_ctrl_clear_cpr4_config(ctrl); |
| 6651 | if (rc) |
| 6652 | cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n", |
| 6653 | rc); |
Stephen Boyd | 09e9be0 | 2017-03-16 15:34:52 -0700 | [diff] [blame] | 6654 | } |
David Collins | 7370f1a | 2017-01-18 16:21:53 -0800 | [diff] [blame] | 6655 | |
| 6656 | cpr3_ctrl_loop_disable(ctrl); |
| 6657 | |
| 6658 | cpr3_closed_loop_disable(ctrl); |
| 6659 | |
| 6660 | if (ctrl->vdd_limit_regulator) { |
| 6661 | regulator_disable(ctrl->vdd_limit_regulator); |
| 6662 | |
| 6663 | if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) |
| 6664 | msm_spm_avs_disable_irq(0, MSM_SPM_AVS_IRQ_MAX); |
| 6665 | } |
| 6666 | |
| 6667 | for (i = 0; i < ctrl->thread_count; i++) |
| 6668 | for (j = 0; j < ctrl->thread[i].vreg_count; j++) |
| 6669 | regulator_unregister(ctrl->thread[i].vreg[j].rdev); |
| 6670 | |
| 6671 | if (ctrl->panic_notifier.notifier_call) |
| 6672 | atomic_notifier_chain_unregister(&panic_notifier_list, |
| 6673 | &ctrl->panic_notifier); |
| 6674 | |
| 6675 | return 0; |
| 6676 | } |