Kiran Gunda | 7e9e00a | 2017-10-16 16:10:08 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/arm-smccc.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/regmap.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/of_device.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/spmi.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/string.h> |
| 28 | #include <linux/regulator/driver.h> |
| 29 | #include <linux/regulator/machine.h> |
| 30 | #include <linux/regulator/of_regulator.h> |
| 31 | #include <linux/regulator/spm-regulator.h> |
| 32 | #include <soc/qcom/spm.h> |
| 33 | #include <linux/arm-smccc.h> |
| 34 | |
| 35 | #if defined(CONFIG_ARM64) || (defined(CONFIG_ARM) && defined(CONFIG_ARM_PSCI)) |
| 36 | #else |
| 37 | #define __invoke_psci_fn_smc(a, b, c, d) 0 |
| 38 | #endif |
| 39 | |
| 40 | #define SPM_REGULATOR_DRIVER_NAME "qcom,spm-regulator" |
| 41 | |
| 42 | struct voltage_range { |
| 43 | int min_uV; |
| 44 | int set_point_min_uV; |
| 45 | int max_uV; |
| 46 | int step_uV; |
| 47 | }; |
| 48 | |
| 49 | enum qpnp_regulator_uniq_type { |
| 50 | QPNP_TYPE_HF, |
| 51 | QPNP_TYPE_FTS2, |
| 52 | QPNP_TYPE_FTS2p5, |
| 53 | QPNP_TYPE_FTS426, |
| 54 | QPNP_TYPE_ULT_HF, |
| 55 | }; |
| 56 | |
| 57 | enum qpnp_regulator_type { |
| 58 | QPNP_HF_TYPE = 0x03, |
| 59 | QPNP_FTS2_TYPE = 0x1C, |
| 60 | QPNP_FTS2p5_TYPE = 0x1C, |
| 61 | QPNP_FTS426_TYPE = 0x1C, |
| 62 | QPNP_ULT_HF_TYPE = 0x22, |
| 63 | }; |
| 64 | |
| 65 | enum qpnp_regulator_subtype { |
| 66 | QPNP_FTS2_SUBTYPE = 0x08, |
| 67 | QPNP_HF_SUBTYPE = 0x08, |
| 68 | QPNP_FTS2p5_SUBTYPE = 0x09, |
| 69 | QPNP_FTS426_SUBTYPE = 0x0A, |
| 70 | QPNP_ULT_HF_SUBTYPE = 0x0D, |
| 71 | }; |
| 72 | |
| 73 | enum qpnp_logical_mode { |
| 74 | QPNP_LOGICAL_MODE_AUTO, |
| 75 | QPNP_LOGICAL_MODE_PWM, |
| 76 | }; |
| 77 | |
| 78 | static const struct voltage_range fts2_range0 = {0, 350000, 1275000, 5000}; |
| 79 | static const struct voltage_range fts2_range1 = {0, 700000, 2040000, 10000}; |
| 80 | static const struct voltage_range fts2p5_range0 |
| 81 | = { 80000, 350000, 1355000, 5000}; |
| 82 | static const struct voltage_range fts2p5_range1 |
| 83 | = {160000, 700000, 2200000, 10000}; |
| 84 | static const struct voltage_range fts426_range = {0, 320000, 1352000, 4000}; |
| 85 | static const struct voltage_range ult_hf_range0 = {375000, 375000, 1562500, |
| 86 | 12500}; |
| 87 | static const struct voltage_range ult_hf_range1 = {750000, 750000, 1525000, |
| 88 | 25000}; |
| 89 | static const struct voltage_range hf_range0 = {375000, 375000, 1562500, 12500}; |
| 90 | static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000, |
| 91 | 25000}; |
| 92 | |
| 93 | #define QPNP_SMPS_REG_TYPE 0x04 |
| 94 | #define QPNP_SMPS_REG_SUBTYPE 0x05 |
| 95 | #define QPNP_SMPS_REG_VOLTAGE_RANGE 0x40 |
| 96 | #define QPNP_SMPS_REG_VOLTAGE_SETPOINT 0x41 |
| 97 | #define QPNP_SMPS_REG_MODE 0x45 |
| 98 | #define QPNP_SMPS_REG_STEP_CTRL 0x61 |
| 99 | #define QPNP_SMPS_REG_UL_LL_CTRL 0x68 |
| 100 | |
| 101 | /* FTS426 voltage control registers */ |
| 102 | #define QPNP_FTS426_REG_VOLTAGE_LB 0x40 |
| 103 | #define QPNP_FTS426_REG_VOLTAGE_UB 0x41 |
| 104 | #define QPNP_FTS426_REG_VOLTAGE_VALID_LB 0x42 |
| 105 | #define QPNP_FTS426_REG_VOLTAGE_VALID_UB 0x43 |
| 106 | |
| 107 | /* HF voltage limit registers */ |
| 108 | #define QPNP_HF_REG_VOLTAGE_ULS 0x69 |
| 109 | #define QPNP_HF_REG_VOLTAGE_LLS 0x6B |
| 110 | |
| 111 | /* FTS voltage limit registers */ |
| 112 | #define QPNP_FTS_REG_VOLTAGE_ULS_VALID 0x6A |
| 113 | #define QPNP_FTS_REG_VOLTAGE_LLS_VALID 0x6C |
| 114 | |
| 115 | /* FTS426 voltage limit registers */ |
| 116 | #define QPNP_FTS426_REG_VOLTAGE_ULS_LB 0x68 |
| 117 | #define QPNP_FTS426_REG_VOLTAGE_ULS_UB 0x69 |
| 118 | |
| 119 | /* Common regulator UL & LL limits control register layout */ |
| 120 | #define QPNP_COMMON_UL_EN_MASK 0x80 |
| 121 | #define QPNP_COMMON_LL_EN_MASK 0x40 |
| 122 | |
| 123 | #define QPNP_SMPS_MODE_PWM 0x80 |
| 124 | #define QPNP_SMPS_MODE_AUTO 0x40 |
| 125 | #define QPNP_FTS426_MODE_PWM 0x07 |
| 126 | #define QPNP_FTS426_MODE_AUTO 0x06 |
| 127 | |
| 128 | #define QPNP_SMPS_STEP_CTRL_STEP_MASK 0x18 |
| 129 | #define QPNP_SMPS_STEP_CTRL_STEP_SHIFT 3 |
| 130 | #define QPNP_SMPS_STEP_CTRL_DELAY_MASK 0x07 |
| 131 | #define QPNP_SMPS_STEP_CTRL_DELAY_SHIFT 0 |
| 132 | #define QPNP_FTS426_STEP_CTRL_DELAY_MASK 0x03 |
| 133 | #define QPNP_FTS426_STEP_CTRL_DELAY_SHIFT 0 |
| 134 | |
| 135 | /* Clock rate in kHz of the FTS2 regulator reference clock. */ |
| 136 | #define QPNP_SMPS_CLOCK_RATE 19200 |
| 137 | #define QPNP_FTS426_CLOCK_RATE 4800 |
| 138 | |
| 139 | /* Time to delay in us to ensure that a mode change has completed. */ |
| 140 | #define QPNP_FTS2_MODE_CHANGE_DELAY 50 |
| 141 | |
| 142 | /* Minimum time in us that it takes to complete a single SPMI write. */ |
| 143 | #define QPNP_SPMI_WRITE_MIN_DELAY 8 |
| 144 | |
| 145 | /* Minimum voltage stepper delay for each step. */ |
| 146 | #define QPNP_FTS2_STEP_DELAY 8 |
| 147 | #define QPNP_HF_STEP_DELAY 20 |
| 148 | #define QPNP_FTS426_STEP_DELAY 2 |
| 149 | |
| 150 | /* Arbitrarily large max step size used to avoid possible numerical overflow */ |
| 151 | #define SPM_REGULATOR_MAX_STEP_UV 10000000 |
| 152 | |
| 153 | /* |
| 154 | * The ratio QPNP_FTS2_STEP_MARGIN_NUM/QPNP_FTS2_STEP_MARGIN_DEN is use to |
| 155 | * adjust the step rate in order to account for oscillator variance. |
| 156 | */ |
| 157 | #define QPNP_FTS2_STEP_MARGIN_NUM 4 |
| 158 | #define QPNP_FTS2_STEP_MARGIN_DEN 5 |
| 159 | #define QPNP_FTS426_STEP_MARGIN_NUM 10 |
| 160 | #define QPNP_FTS426_STEP_MARGIN_DEN 11 |
| 161 | |
| 162 | /* |
| 163 | * Settling delay for FTS2.5 |
| 164 | * Warm-up=20uS, 0-10% & 90-100% non-linear V-ramp delay = 50uS |
| 165 | */ |
| 166 | #define FTS2P5_SETTLING_DELAY_US 70 |
| 167 | |
| 168 | /* VSET value to decide the range of ULT SMPS */ |
| 169 | #define ULT_SMPS_RANGE_SPLIT 0x60 |
| 170 | |
| 171 | struct spm_vreg { |
| 172 | struct regulator_desc rdesc; |
| 173 | struct regulator_dev *rdev; |
| 174 | struct platform_device *pdev; |
| 175 | struct regmap *regmap; |
| 176 | const struct voltage_range *range; |
| 177 | int uV; |
| 178 | int last_set_uV; |
| 179 | unsigned vlevel; |
| 180 | unsigned last_set_vlevel; |
| 181 | u32 max_step_uV; |
| 182 | bool online; |
| 183 | u16 spmi_base_addr; |
| 184 | enum qpnp_logical_mode init_mode; |
| 185 | enum qpnp_logical_mode mode; |
| 186 | int step_rate; |
| 187 | enum qpnp_regulator_uniq_type regulator_type; |
| 188 | u32 cpu_num; |
| 189 | bool bypass_spm; |
| 190 | struct regulator_desc avs_rdesc; |
| 191 | struct regulator_dev *avs_rdev; |
| 192 | int avs_min_uV; |
| 193 | int avs_max_uV; |
| 194 | bool avs_enabled; |
| 195 | u32 recal_cluster_mask; |
| 196 | }; |
| 197 | |
| 198 | static inline bool spm_regulator_using_avs(struct spm_vreg *vreg) |
| 199 | { |
| 200 | return vreg->avs_rdev && !vreg->bypass_spm; |
| 201 | } |
| 202 | |
| 203 | static int spm_regulator_uv_to_vlevel(struct spm_vreg *vreg, int uV) |
| 204 | { |
| 205 | int vlevel; |
| 206 | |
| 207 | if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 208 | return roundup(uV, vreg->range->step_uV) / 1000; |
| 209 | |
| 210 | vlevel = DIV_ROUND_UP(uV - vreg->range->min_uV, vreg->range->step_uV); |
| 211 | |
| 212 | /* Fix VSET for ULT HF Buck */ |
| 213 | if (vreg->regulator_type == QPNP_TYPE_ULT_HF |
| 214 | && vreg->range == &ult_hf_range1) { |
| 215 | vlevel &= 0x1F; |
| 216 | vlevel |= ULT_SMPS_RANGE_SPLIT; |
| 217 | } |
| 218 | |
| 219 | return vlevel; |
| 220 | } |
| 221 | |
| 222 | static int spm_regulator_vlevel_to_uv(struct spm_vreg *vreg, int vlevel) |
| 223 | { |
| 224 | if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 225 | return vlevel * 1000; |
| 226 | /* |
| 227 | * Calculate ULT HF buck VSET based on range: |
| 228 | * In case of range 0: VSET is a 7 bit value. |
| 229 | * In case of range 1: VSET is a 5 bit value. |
| 230 | */ |
| 231 | if (vreg->regulator_type == QPNP_TYPE_ULT_HF |
| 232 | && vreg->range == &ult_hf_range1) |
| 233 | vlevel &= ~ULT_SMPS_RANGE_SPLIT; |
| 234 | |
| 235 | return vlevel * vreg->range->step_uV + vreg->range->min_uV; |
| 236 | } |
| 237 | |
| 238 | static unsigned spm_regulator_vlevel_to_selector(struct spm_vreg *vreg, |
| 239 | unsigned vlevel) |
| 240 | { |
| 241 | /* Fix VSET for ULT HF Buck */ |
| 242 | if (vreg->regulator_type == QPNP_TYPE_ULT_HF |
| 243 | && vreg->range == &ult_hf_range1) |
| 244 | vlevel &= ~ULT_SMPS_RANGE_SPLIT; |
| 245 | |
| 246 | return vlevel - (vreg->range->set_point_min_uV - vreg->range->min_uV) |
| 247 | / vreg->range->step_uV; |
| 248 | } |
| 249 | |
| 250 | static int qpnp_smps_read_voltage(struct spm_vreg *vreg) |
| 251 | { |
| 252 | int rc; |
| 253 | u8 val[2] = {0}; |
| 254 | |
| 255 | if (vreg->regulator_type == QPNP_TYPE_FTS426) { |
| 256 | rc = regmap_bulk_read(vreg->regmap, |
| 257 | vreg->spmi_base_addr + QPNP_FTS426_REG_VOLTAGE_VALID_LB, |
| 258 | val, 2); |
| 259 | if (rc) { |
| 260 | dev_err(&vreg->pdev->dev, "%s: could not read voltage setpoint registers, rc=%d\n", |
| 261 | __func__, rc); |
| 262 | return rc; |
| 263 | } |
| 264 | |
| 265 | vreg->last_set_vlevel = ((unsigned)val[1] << 8) | val[0]; |
| 266 | } else { |
| 267 | rc = regmap_bulk_read(vreg->regmap, |
| 268 | vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT, |
| 269 | val, 1); |
| 270 | if (rc) { |
| 271 | dev_err(&vreg->pdev->dev, "%s: could not read voltage setpoint register, rc=%d\n", |
| 272 | __func__, rc); |
| 273 | return rc; |
| 274 | } |
| 275 | vreg->last_set_vlevel = val[0]; |
| 276 | } |
| 277 | |
| 278 | vreg->last_set_uV = spm_regulator_vlevel_to_uv(vreg, |
| 279 | vreg->last_set_vlevel); |
| 280 | return rc; |
| 281 | } |
| 282 | |
| 283 | static int qpnp_smps_write_voltage(struct spm_vreg *vreg, unsigned vlevel) |
| 284 | { |
| 285 | int rc = 0; |
| 286 | u8 reg[2]; |
| 287 | |
| 288 | /* Set voltage control registers via SPMI. */ |
| 289 | reg[0] = vlevel & 0xFF; |
| 290 | reg[1] = (vlevel >> 8) & 0xFF; |
| 291 | |
| 292 | if (vreg->regulator_type == QPNP_TYPE_FTS426) { |
| 293 | rc = regmap_bulk_write(vreg->regmap, |
| 294 | vreg->spmi_base_addr + QPNP_FTS426_REG_VOLTAGE_LB, |
| 295 | reg, 2); |
| 296 | } else { |
| 297 | rc = regmap_write(vreg->regmap, |
| 298 | vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT, |
| 299 | reg[0]); |
| 300 | } |
| 301 | |
| 302 | if (rc) |
| 303 | pr_err("%s: regmap_write failed, rc=%d\n", |
| 304 | vreg->rdesc.name, rc); |
| 305 | |
| 306 | return rc; |
| 307 | } |
| 308 | |
| 309 | static inline enum qpnp_logical_mode qpnp_regval_to_mode(struct spm_vreg *vreg, |
| 310 | u8 regval) |
| 311 | { |
| 312 | if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 313 | return (regval == QPNP_FTS426_MODE_PWM) |
| 314 | ? QPNP_LOGICAL_MODE_PWM : QPNP_LOGICAL_MODE_AUTO; |
| 315 | else |
| 316 | return (regval & QPNP_SMPS_MODE_PWM) |
| 317 | ? QPNP_LOGICAL_MODE_PWM : QPNP_LOGICAL_MODE_AUTO; |
| 318 | } |
| 319 | |
| 320 | static inline u8 qpnp_mode_to_regval(struct spm_vreg *vreg, |
| 321 | enum qpnp_logical_mode mode) |
| 322 | { |
| 323 | if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 324 | return (mode == QPNP_LOGICAL_MODE_PWM) |
| 325 | ? QPNP_FTS426_MODE_PWM : QPNP_FTS426_MODE_AUTO; |
| 326 | else |
| 327 | return (mode == QPNP_LOGICAL_MODE_PWM) |
| 328 | ? QPNP_SMPS_MODE_PWM : QPNP_SMPS_MODE_AUTO; |
| 329 | } |
| 330 | |
| 331 | static int qpnp_smps_set_mode(struct spm_vreg *vreg, u8 mode) |
| 332 | { |
| 333 | int rc; |
| 334 | |
| 335 | rc = regmap_write(vreg->regmap, |
| 336 | vreg->spmi_base_addr + QPNP_SMPS_REG_MODE, |
| 337 | qpnp_mode_to_regval(vreg, mode)); |
| 338 | if (rc) |
| 339 | dev_err(&vreg->pdev->dev, |
| 340 | "%s: could not write to mode register, rc=%d\n", |
| 341 | __func__, rc); |
| 342 | |
| 343 | return rc; |
| 344 | } |
| 345 | |
| 346 | static int spm_regulator_get_voltage(struct regulator_dev *rdev) |
| 347 | { |
| 348 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 349 | int vlevel, rc; |
| 350 | |
| 351 | if (spm_regulator_using_avs(vreg)) { |
| 352 | vlevel = msm_spm_get_vdd(vreg->cpu_num); |
| 353 | |
| 354 | if (vlevel < 0) { |
| 355 | pr_debug("%s: msm_spm_get_vdd failed, rc=%d; falling back on SPMI read\n", |
| 356 | vreg->rdesc.name, vlevel); |
| 357 | |
| 358 | rc = qpnp_smps_read_voltage(vreg); |
| 359 | if (rc) { |
| 360 | pr_err("%s: voltage read failed, rc=%d\n", |
| 361 | vreg->rdesc.name, rc); |
| 362 | return rc; |
| 363 | } |
| 364 | |
| 365 | return vreg->last_set_uV; |
| 366 | } |
| 367 | |
| 368 | vreg->last_set_vlevel = vlevel; |
| 369 | vreg->last_set_uV = spm_regulator_vlevel_to_uv(vreg, vlevel); |
| 370 | |
| 371 | return vreg->last_set_uV; |
| 372 | } else { |
| 373 | return vreg->uV; |
| 374 | } |
| 375 | }; |
| 376 | |
| 377 | static int spm_regulator_write_voltage(struct spm_vreg *vreg, int uV) |
| 378 | { |
| 379 | unsigned vlevel = spm_regulator_uv_to_vlevel(vreg, uV); |
| 380 | bool spm_failed = false; |
| 381 | int rc = 0; |
| 382 | u32 slew_delay; |
| 383 | |
| 384 | if (likely(!vreg->bypass_spm)) { |
| 385 | /* Set voltage control register via SPM. */ |
| 386 | rc = msm_spm_set_vdd(vreg->cpu_num, vlevel); |
| 387 | if (rc) { |
| 388 | pr_debug("%s: msm_spm_set_vdd failed, rc=%d; falling back on SPMI write\n", |
| 389 | vreg->rdesc.name, rc); |
| 390 | spm_failed = true; |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | if (unlikely(vreg->bypass_spm || spm_failed)) { |
| 395 | rc = qpnp_smps_write_voltage(vreg, vlevel); |
| 396 | if (rc) { |
| 397 | pr_err("%s: voltage write failed, rc=%d\n", |
| 398 | vreg->rdesc.name, rc); |
| 399 | return rc; |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | if (uV > vreg->last_set_uV) { |
| 404 | /* Wait for voltage stepping to complete. */ |
| 405 | slew_delay = DIV_ROUND_UP(uV - vreg->last_set_uV, |
| 406 | vreg->step_rate); |
| 407 | if (vreg->regulator_type == QPNP_TYPE_FTS2p5) |
| 408 | slew_delay += FTS2P5_SETTLING_DELAY_US; |
| 409 | udelay(slew_delay); |
| 410 | } else if (vreg->regulator_type == QPNP_TYPE_FTS2p5) { |
| 411 | /* add the ramp-down delay */ |
| 412 | slew_delay = DIV_ROUND_UP(vreg->last_set_uV - uV, |
| 413 | vreg->step_rate) + FTS2P5_SETTLING_DELAY_US; |
| 414 | udelay(slew_delay); |
| 415 | } |
| 416 | |
| 417 | vreg->last_set_uV = uV; |
| 418 | vreg->last_set_vlevel = vlevel; |
| 419 | |
| 420 | return rc; |
| 421 | } |
| 422 | |
| 423 | static int spm_regulator_recalibrate(struct spm_vreg *vreg) |
| 424 | { |
| 425 | struct arm_smccc_res res; |
| 426 | |
| 427 | if (!vreg->recal_cluster_mask) |
| 428 | return 0; |
| 429 | |
| 430 | arm_smccc_smc(0xC4000020, vreg->recal_cluster_mask, 2, 0, 0, 0, 0, 0, &res); |
| 431 | if (res.a0) |
| 432 | pr_err("%s: recalibration failed, rc=%ld\n", vreg->rdesc.name, |
| 433 | res.a0); |
| 434 | |
| 435 | return res.a0; |
| 436 | } |
| 437 | |
| 438 | static int _spm_regulator_set_voltage(struct regulator_dev *rdev) |
| 439 | { |
| 440 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 441 | bool pwm_required; |
| 442 | int rc = 0; |
| 443 | int uV; |
| 444 | |
| 445 | rc = spm_regulator_get_voltage(rdev); |
| 446 | if (rc < 0) |
| 447 | return rc; |
| 448 | |
| 449 | if (vreg->vlevel == vreg->last_set_vlevel) |
| 450 | return 0; |
| 451 | |
| 452 | pwm_required = (vreg->regulator_type == QPNP_TYPE_FTS2) |
| 453 | && (vreg->init_mode != QPNP_LOGICAL_MODE_PWM) |
| 454 | && vreg->uV > vreg->last_set_uV; |
| 455 | |
| 456 | if (pwm_required) { |
| 457 | /* Switch to PWM mode so that voltage ramping is fast. */ |
| 458 | rc = qpnp_smps_set_mode(vreg, QPNP_LOGICAL_MODE_PWM); |
| 459 | if (rc) |
| 460 | return rc; |
| 461 | } |
| 462 | |
| 463 | do { |
| 464 | uV = vreg->uV > vreg->last_set_uV |
| 465 | ? min(vreg->uV, vreg->last_set_uV + (int)vreg->max_step_uV) |
| 466 | : max(vreg->uV, vreg->last_set_uV - (int)vreg->max_step_uV); |
| 467 | |
| 468 | rc = spm_regulator_write_voltage(vreg, uV); |
| 469 | if (rc) |
| 470 | return rc; |
| 471 | } while (vreg->last_set_uV != vreg->uV); |
| 472 | |
| 473 | if (pwm_required) { |
| 474 | /* Wait for mode transition to complete. */ |
| 475 | udelay(QPNP_FTS2_MODE_CHANGE_DELAY - QPNP_SPMI_WRITE_MIN_DELAY); |
| 476 | /* Switch to AUTO mode so that power consumption is lowered. */ |
| 477 | rc = qpnp_smps_set_mode(vreg, QPNP_LOGICAL_MODE_AUTO); |
| 478 | if (rc) |
| 479 | return rc; |
| 480 | } |
| 481 | |
| 482 | rc = spm_regulator_recalibrate(vreg); |
| 483 | |
| 484 | return rc; |
| 485 | } |
| 486 | |
| 487 | static int spm_regulator_set_voltage(struct regulator_dev *rdev, int min_uV, |
| 488 | int max_uV, unsigned *selector) |
| 489 | { |
| 490 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 491 | const struct voltage_range *range = vreg->range; |
| 492 | int uV = min_uV; |
| 493 | unsigned vlevel; |
| 494 | |
| 495 | if (uV < range->set_point_min_uV && max_uV >= range->set_point_min_uV) |
| 496 | uV = range->set_point_min_uV; |
| 497 | |
| 498 | if (uV < range->set_point_min_uV || uV > range->max_uV) { |
| 499 | pr_err("%s: request v=[%d, %d] is outside possible v=[%d, %d]\n", |
| 500 | vreg->rdesc.name, min_uV, max_uV, |
| 501 | range->set_point_min_uV, range->max_uV); |
| 502 | return -EINVAL; |
| 503 | } |
| 504 | |
| 505 | vlevel = spm_regulator_uv_to_vlevel(vreg, uV); |
| 506 | uV = spm_regulator_vlevel_to_uv(vreg, vlevel); |
| 507 | |
| 508 | if (uV > max_uV) { |
| 509 | pr_err("%s: request v=[%d, %d] cannot be met by any set point\n", |
| 510 | vreg->rdesc.name, min_uV, max_uV); |
| 511 | return -EINVAL; |
| 512 | } |
| 513 | |
| 514 | *selector = spm_regulator_vlevel_to_selector(vreg, vlevel); |
| 515 | vreg->vlevel = vlevel; |
| 516 | vreg->uV = uV; |
| 517 | |
| 518 | if (!vreg->online) |
| 519 | return 0; |
| 520 | |
| 521 | return _spm_regulator_set_voltage(rdev); |
| 522 | } |
| 523 | |
| 524 | static int spm_regulator_list_voltage(struct regulator_dev *rdev, |
| 525 | unsigned selector) |
| 526 | { |
| 527 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 528 | |
| 529 | if (selector >= vreg->rdesc.n_voltages) |
| 530 | return 0; |
| 531 | |
| 532 | return selector * vreg->range->step_uV + vreg->range->set_point_min_uV; |
| 533 | } |
| 534 | |
| 535 | static int spm_regulator_enable(struct regulator_dev *rdev) |
| 536 | { |
| 537 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 538 | int rc; |
| 539 | |
| 540 | rc = _spm_regulator_set_voltage(rdev); |
| 541 | |
| 542 | if (!rc) |
| 543 | vreg->online = true; |
| 544 | |
| 545 | return rc; |
| 546 | } |
| 547 | |
| 548 | static int spm_regulator_disable(struct regulator_dev *rdev) |
| 549 | { |
| 550 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 551 | |
| 552 | vreg->online = false; |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | static int spm_regulator_is_enabled(struct regulator_dev *rdev) |
| 558 | { |
| 559 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 560 | |
| 561 | return vreg->online; |
| 562 | } |
| 563 | |
| 564 | static unsigned int spm_regulator_get_mode(struct regulator_dev *rdev) |
| 565 | { |
| 566 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 567 | |
| 568 | return vreg->mode == QPNP_LOGICAL_MODE_PWM |
| 569 | ? REGULATOR_MODE_NORMAL : REGULATOR_MODE_IDLE; |
| 570 | } |
| 571 | |
| 572 | static int spm_regulator_set_mode(struct regulator_dev *rdev, unsigned int mode) |
| 573 | { |
| 574 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 575 | |
| 576 | /* |
| 577 | * Map REGULATOR_MODE_NORMAL to PWM mode and REGULATOR_MODE_IDLE to |
| 578 | * init_mode. This ensures that the regulator always stays in PWM mode |
| 579 | * in the case that qcom,mode has been specified as "pwm" in device |
| 580 | * tree. |
| 581 | */ |
| 582 | vreg->mode = (mode == REGULATOR_MODE_NORMAL) ? QPNP_LOGICAL_MODE_PWM |
| 583 | : vreg->init_mode; |
| 584 | |
| 585 | return qpnp_smps_set_mode(vreg, vreg->mode); |
| 586 | } |
| 587 | |
| 588 | static struct regulator_ops spm_regulator_ops = { |
| 589 | .get_voltage = spm_regulator_get_voltage, |
| 590 | .set_voltage = spm_regulator_set_voltage, |
| 591 | .list_voltage = spm_regulator_list_voltage, |
| 592 | .get_mode = spm_regulator_get_mode, |
| 593 | .set_mode = spm_regulator_set_mode, |
| 594 | .enable = spm_regulator_enable, |
| 595 | .disable = spm_regulator_disable, |
| 596 | .is_enabled = spm_regulator_is_enabled, |
| 597 | }; |
| 598 | |
| 599 | static int spm_regulator_avs_set_voltage(struct regulator_dev *rdev, int min_uV, |
| 600 | int max_uV, unsigned *selector) |
| 601 | { |
| 602 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 603 | const struct voltage_range *range = vreg->range; |
| 604 | unsigned vlevel_min, vlevel_max; |
| 605 | int uV, avs_min_uV, avs_max_uV, rc; |
| 606 | |
| 607 | uV = min_uV; |
| 608 | |
| 609 | if (uV < range->set_point_min_uV && max_uV >= range->set_point_min_uV) |
| 610 | uV = range->set_point_min_uV; |
| 611 | |
| 612 | if (uV < range->set_point_min_uV || uV > range->max_uV) { |
| 613 | pr_err("%s: request v=[%d, %d] is outside possible v=[%d, %d]\n", |
| 614 | vreg->avs_rdesc.name, min_uV, max_uV, |
| 615 | range->set_point_min_uV, range->max_uV); |
| 616 | return -EINVAL; |
| 617 | } |
| 618 | |
| 619 | vlevel_min = spm_regulator_uv_to_vlevel(vreg, uV); |
| 620 | avs_min_uV = spm_regulator_vlevel_to_uv(vreg, vlevel_min); |
| 621 | |
| 622 | if (avs_min_uV > max_uV) { |
| 623 | pr_err("%s: request v=[%d, %d] cannot be met by any set point\n", |
| 624 | vreg->avs_rdesc.name, min_uV, max_uV); |
| 625 | return -EINVAL; |
| 626 | } |
| 627 | |
| 628 | uV = max_uV; |
| 629 | |
| 630 | if (uV > range->max_uV && min_uV <= range->max_uV) |
| 631 | uV = range->max_uV; |
| 632 | |
| 633 | if (uV < range->set_point_min_uV || uV > range->max_uV) { |
| 634 | pr_err("%s: request v=[%d, %d] is outside possible v=[%d, %d]\n", |
| 635 | vreg->avs_rdesc.name, min_uV, max_uV, |
| 636 | range->set_point_min_uV, range->max_uV); |
| 637 | return -EINVAL; |
| 638 | } |
| 639 | |
| 640 | vlevel_max = spm_regulator_uv_to_vlevel(vreg, uV); |
| 641 | avs_max_uV = spm_regulator_vlevel_to_uv(vreg, vlevel_max); |
| 642 | |
| 643 | if (avs_max_uV < min_uV) { |
| 644 | pr_err("%s: request v=[%d, %d] cannot be met by any set point\n", |
| 645 | vreg->avs_rdesc.name, min_uV, max_uV); |
| 646 | return -EINVAL; |
| 647 | } |
| 648 | |
| 649 | if (likely(!vreg->bypass_spm)) { |
| 650 | rc = msm_spm_avs_set_limit(vreg->cpu_num, vlevel_min, |
| 651 | vlevel_max); |
| 652 | if (rc) { |
| 653 | pr_err("%s: AVS limit setting failed, rc=%d\n", |
| 654 | vreg->avs_rdesc.name, rc); |
| 655 | return rc; |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | *selector = spm_regulator_vlevel_to_selector(vreg, vlevel_min); |
| 660 | vreg->avs_min_uV = avs_min_uV; |
| 661 | vreg->avs_max_uV = avs_max_uV; |
| 662 | |
| 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | static int spm_regulator_avs_get_voltage(struct regulator_dev *rdev) |
| 667 | { |
| 668 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 669 | |
| 670 | return vreg->avs_min_uV; |
| 671 | } |
| 672 | |
| 673 | static int spm_regulator_avs_enable(struct regulator_dev *rdev) |
| 674 | { |
| 675 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 676 | int rc; |
| 677 | |
| 678 | if (likely(!vreg->bypass_spm)) { |
| 679 | rc = msm_spm_avs_enable(vreg->cpu_num); |
| 680 | if (rc) { |
| 681 | pr_err("%s: AVS enable failed, rc=%d\n", |
| 682 | vreg->avs_rdesc.name, rc); |
| 683 | return rc; |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | vreg->avs_enabled = true; |
| 688 | |
| 689 | return 0; |
| 690 | } |
| 691 | |
| 692 | static int spm_regulator_avs_disable(struct regulator_dev *rdev) |
| 693 | { |
| 694 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 695 | int rc; |
| 696 | |
| 697 | if (likely(!vreg->bypass_spm)) { |
| 698 | rc = msm_spm_avs_disable(vreg->cpu_num); |
| 699 | if (rc) { |
| 700 | pr_err("%s: AVS disable failed, rc=%d\n", |
| 701 | vreg->avs_rdesc.name, rc); |
| 702 | return rc; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | vreg->avs_enabled = false; |
| 707 | |
| 708 | return 0; |
| 709 | } |
| 710 | |
| 711 | static int spm_regulator_avs_is_enabled(struct regulator_dev *rdev) |
| 712 | { |
| 713 | struct spm_vreg *vreg = rdev_get_drvdata(rdev); |
| 714 | |
| 715 | return vreg->avs_enabled; |
| 716 | } |
| 717 | |
| 718 | static struct regulator_ops spm_regulator_avs_ops = { |
| 719 | .get_voltage = spm_regulator_avs_get_voltage, |
| 720 | .set_voltage = spm_regulator_avs_set_voltage, |
| 721 | .list_voltage = spm_regulator_list_voltage, |
| 722 | .enable = spm_regulator_avs_enable, |
| 723 | .disable = spm_regulator_avs_disable, |
| 724 | .is_enabled = spm_regulator_avs_is_enabled, |
| 725 | }; |
| 726 | |
| 727 | static int qpnp_smps_check_type(struct spm_vreg *vreg) |
| 728 | { |
| 729 | int rc; |
| 730 | u8 type[2]; |
| 731 | |
| 732 | rc = regmap_bulk_read(vreg->regmap, |
| 733 | vreg->spmi_base_addr + QPNP_SMPS_REG_TYPE, |
| 734 | type, |
| 735 | 2); |
| 736 | if (rc) { |
| 737 | dev_err(&vreg->pdev->dev, |
| 738 | "%s: could not read type register, rc=%d\n", |
| 739 | __func__, rc); |
| 740 | return rc; |
| 741 | } |
| 742 | |
| 743 | if (type[0] == QPNP_FTS2_TYPE && type[1] == QPNP_FTS2_SUBTYPE) { |
| 744 | vreg->regulator_type = QPNP_TYPE_FTS2; |
| 745 | } else if (type[0] == QPNP_FTS2p5_TYPE |
| 746 | && type[1] == QPNP_FTS2p5_SUBTYPE) { |
| 747 | vreg->regulator_type = QPNP_TYPE_FTS2p5; |
| 748 | } else if (type[0] == QPNP_FTS426_TYPE |
| 749 | && type[1] == QPNP_FTS426_SUBTYPE) { |
| 750 | vreg->regulator_type = QPNP_TYPE_FTS426; |
| 751 | } else if (type[0] == QPNP_ULT_HF_TYPE |
| 752 | && type[1] == QPNP_ULT_HF_SUBTYPE) { |
| 753 | vreg->regulator_type = QPNP_TYPE_ULT_HF; |
| 754 | } else if (type[0] == QPNP_HF_TYPE |
| 755 | && type[1] == QPNP_HF_SUBTYPE) { |
| 756 | vreg->regulator_type = QPNP_TYPE_HF; |
| 757 | } else { |
| 758 | dev_err(&vreg->pdev->dev, |
| 759 | "%s: invalid type=0x%02X, subtype=0x%02X register pair\n", |
| 760 | __func__, type[0], type[1]); |
| 761 | return -ENODEV; |
| 762 | }; |
| 763 | |
| 764 | return rc; |
| 765 | } |
| 766 | |
| 767 | static int qpnp_smps_init_range(struct spm_vreg *vreg, |
| 768 | const struct voltage_range *range0, const struct voltage_range *range1) |
| 769 | { |
| 770 | int rc; |
| 771 | u8 reg = 0; |
| 772 | uint val; |
| 773 | |
| 774 | rc = regmap_read(vreg->regmap, |
| 775 | vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_RANGE, |
| 776 | &val); |
| 777 | if (rc) { |
| 778 | dev_err(&vreg->pdev->dev, |
| 779 | "%s: could not read voltage range register, rc=%d\n", |
| 780 | __func__, rc); |
| 781 | return rc; |
| 782 | } |
| 783 | reg = (u8)val; |
| 784 | |
| 785 | if (reg == 0x00) { |
| 786 | vreg->range = range0; |
| 787 | } else if (reg == 0x01) { |
| 788 | vreg->range = range1; |
| 789 | } else { |
| 790 | dev_err(&vreg->pdev->dev, "%s: voltage range=%d is invalid\n", |
| 791 | __func__, reg); |
| 792 | rc = -EINVAL; |
| 793 | } |
| 794 | |
| 795 | return rc; |
| 796 | } |
| 797 | |
| 798 | static int qpnp_ult_hf_init_range(struct spm_vreg *vreg) |
| 799 | { |
| 800 | int rc; |
| 801 | u8 reg = 0; |
| 802 | uint val; |
| 803 | |
| 804 | rc = regmap_read(vreg->regmap, |
| 805 | vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT, |
| 806 | &val); |
| 807 | if (rc) { |
| 808 | dev_err(&vreg->pdev->dev, |
| 809 | "%s: could not read voltage range register, rc=%d\n", |
| 810 | __func__, rc); |
| 811 | return rc; |
| 812 | } |
| 813 | reg = (u8)val; |
| 814 | |
| 815 | vreg->range = (reg < ULT_SMPS_RANGE_SPLIT) ? &ult_hf_range0 : |
| 816 | &ult_hf_range1; |
| 817 | return rc; |
| 818 | } |
| 819 | |
| 820 | static int qpnp_smps_init_voltage(struct spm_vreg *vreg) |
| 821 | { |
| 822 | int rc; |
| 823 | |
| 824 | rc = qpnp_smps_read_voltage(vreg); |
| 825 | if (rc) { |
| 826 | pr_err("%s: voltage read failed, rc=%d\n", vreg->rdesc.name, |
| 827 | rc); |
| 828 | return rc; |
| 829 | } |
| 830 | |
| 831 | vreg->vlevel = vreg->last_set_vlevel; |
| 832 | vreg->uV = vreg->last_set_uV; |
| 833 | |
| 834 | /* Initialize SAW voltage control register */ |
| 835 | if (!vreg->bypass_spm) { |
| 836 | rc = msm_spm_set_vdd(vreg->cpu_num, vreg->vlevel); |
| 837 | if (rc) |
| 838 | pr_err("%s: msm_spm_set_vdd failed, rc=%d\n", |
| 839 | vreg->rdesc.name, rc); |
| 840 | } |
| 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static int qpnp_smps_init_mode(struct spm_vreg *vreg) |
| 846 | { |
| 847 | const char *mode_name; |
| 848 | int rc; |
| 849 | uint val; |
| 850 | |
| 851 | rc = of_property_read_string(vreg->pdev->dev.of_node, "qcom,mode", |
| 852 | &mode_name); |
| 853 | if (!rc) { |
| 854 | if (strcmp("pwm", mode_name) == 0) { |
| 855 | vreg->init_mode = QPNP_LOGICAL_MODE_PWM; |
| 856 | } else if ((strcmp("auto", mode_name) == 0) && |
| 857 | (vreg->regulator_type != QPNP_TYPE_ULT_HF)) { |
| 858 | vreg->init_mode = QPNP_LOGICAL_MODE_AUTO; |
| 859 | } else { |
| 860 | dev_err(&vreg->pdev->dev, |
| 861 | "%s: unknown regulator mode: %s\n", |
| 862 | __func__, mode_name); |
| 863 | return -EINVAL; |
| 864 | } |
| 865 | |
| 866 | rc = qpnp_smps_set_mode(vreg, vreg->init_mode); |
| 867 | if (rc) |
| 868 | return rc; |
| 869 | } else { |
| 870 | rc = regmap_read(vreg->regmap, |
| 871 | vreg->spmi_base_addr + QPNP_SMPS_REG_MODE, |
| 872 | &val); |
| 873 | if (rc) |
| 874 | dev_err(&vreg->pdev->dev, |
| 875 | "%s: could not read mode register, rc=%d\n", |
| 876 | __func__, rc); |
| 877 | vreg->init_mode = qpnp_regval_to_mode(vreg, val); |
| 878 | } |
| 879 | |
| 880 | vreg->mode = vreg->init_mode; |
| 881 | |
| 882 | return rc; |
| 883 | } |
| 884 | |
| 885 | static int qpnp_smps_init_step_rate(struct spm_vreg *vreg) |
| 886 | { |
| 887 | int rc; |
| 888 | u8 reg = 0; |
| 889 | int step = 0, delay; |
| 890 | uint val; |
| 891 | |
| 892 | rc = regmap_read(vreg->regmap, |
| 893 | vreg->spmi_base_addr + QPNP_SMPS_REG_STEP_CTRL, &val); |
| 894 | if (rc) { |
| 895 | dev_err(&vreg->pdev->dev, |
| 896 | "%s: could not read stepping control register, rc=%d\n", |
| 897 | __func__, rc); |
| 898 | return rc; |
| 899 | } |
| 900 | reg = (u8)val; |
| 901 | |
| 902 | /* ULT and FTS426 bucks do not support steps */ |
| 903 | if (vreg->regulator_type != QPNP_TYPE_ULT_HF && vreg->regulator_type != |
| 904 | QPNP_TYPE_FTS426) |
| 905 | step = (reg & QPNP_SMPS_STEP_CTRL_STEP_MASK) |
| 906 | >> QPNP_SMPS_STEP_CTRL_STEP_SHIFT; |
| 907 | |
| 908 | if (vreg->regulator_type == QPNP_TYPE_FTS426) { |
| 909 | delay = (reg & QPNP_FTS426_STEP_CTRL_DELAY_MASK) |
| 910 | >> QPNP_FTS426_STEP_CTRL_DELAY_SHIFT; |
| 911 | |
| 912 | /* step_rate has units of uV/us. */ |
| 913 | vreg->step_rate = QPNP_FTS426_CLOCK_RATE * vreg->range->step_uV; |
| 914 | } else { |
| 915 | delay = (reg & QPNP_SMPS_STEP_CTRL_DELAY_MASK) |
| 916 | >> QPNP_SMPS_STEP_CTRL_DELAY_SHIFT; |
| 917 | |
| 918 | /* step_rate has units of uV/us. */ |
| 919 | vreg->step_rate = QPNP_SMPS_CLOCK_RATE * vreg->range->step_uV |
| 920 | * (1 << step); |
| 921 | } |
| 922 | |
| 923 | if ((vreg->regulator_type == QPNP_TYPE_ULT_HF) |
| 924 | || (vreg->regulator_type == QPNP_TYPE_HF)) |
| 925 | vreg->step_rate /= 1000 * (QPNP_HF_STEP_DELAY << delay); |
| 926 | else if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 927 | vreg->step_rate /= 1000 * (QPNP_FTS426_STEP_DELAY << delay); |
| 928 | else |
| 929 | vreg->step_rate /= 1000 * (QPNP_FTS2_STEP_DELAY << delay); |
| 930 | |
| 931 | if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 932 | vreg->step_rate = vreg->step_rate * QPNP_FTS426_STEP_MARGIN_NUM |
| 933 | / QPNP_FTS426_STEP_MARGIN_DEN; |
| 934 | else |
| 935 | vreg->step_rate = vreg->step_rate * QPNP_FTS2_STEP_MARGIN_NUM |
| 936 | / QPNP_FTS2_STEP_MARGIN_DEN; |
| 937 | |
| 938 | /* Ensure that the stepping rate is greater than 0. */ |
| 939 | vreg->step_rate = max(vreg->step_rate, 1); |
| 940 | |
| 941 | return rc; |
| 942 | } |
| 943 | |
| 944 | static int qpnp_smps_check_constraints(struct spm_vreg *vreg, |
| 945 | struct regulator_init_data *init_data) |
| 946 | { |
| 947 | int rc = 0, limit_min_uV, limit_max_uV; |
| 948 | u16 ul_reg, ll_reg; |
| 949 | u8 reg[2]; |
| 950 | |
| 951 | limit_min_uV = 0; |
| 952 | limit_max_uV = INT_MAX; |
| 953 | |
| 954 | ul_reg = QPNP_FTS_REG_VOLTAGE_ULS_VALID; |
| 955 | ll_reg = QPNP_FTS_REG_VOLTAGE_LLS_VALID; |
| 956 | |
| 957 | switch (vreg->regulator_type) { |
| 958 | case QPNP_TYPE_HF: |
| 959 | ul_reg = QPNP_HF_REG_VOLTAGE_ULS; |
| 960 | ll_reg = QPNP_HF_REG_VOLTAGE_LLS; |
| 961 | case QPNP_TYPE_FTS2: |
| 962 | case QPNP_TYPE_FTS2p5: |
| 963 | rc = regmap_bulk_read(vreg->regmap, vreg->spmi_base_addr |
| 964 | + QPNP_SMPS_REG_UL_LL_CTRL, reg, 1); |
| 965 | if (rc) { |
| 966 | dev_err(&vreg->pdev->dev, "%s: UL_LL register read failed, rc=%d\n", |
| 967 | __func__, rc); |
| 968 | return rc; |
| 969 | } |
| 970 | |
| 971 | if (reg[0] & QPNP_COMMON_UL_EN_MASK) { |
| 972 | rc = regmap_bulk_read(vreg->regmap, vreg->spmi_base_addr |
| 973 | + ul_reg, ®[1], 1); |
| 974 | if (rc) { |
| 975 | dev_err(&vreg->pdev->dev, "%s: ULS register read failed, rc=%d\n", |
| 976 | __func__, rc); |
| 977 | return rc; |
| 978 | } |
| 979 | |
| 980 | limit_max_uV = spm_regulator_vlevel_to_uv(vreg, reg[1]); |
| 981 | } |
| 982 | |
| 983 | if (reg[0] & QPNP_COMMON_LL_EN_MASK) { |
| 984 | rc = regmap_bulk_read(vreg->regmap, vreg->spmi_base_addr |
| 985 | + ll_reg, ®[1], 1); |
| 986 | if (rc) { |
| 987 | dev_err(&vreg->pdev->dev, "%s: LLS register read failed, rc=%d\n", |
| 988 | __func__, rc); |
| 989 | return rc; |
| 990 | } |
| 991 | |
| 992 | limit_min_uV = spm_regulator_vlevel_to_uv(vreg, reg[1]); |
| 993 | } |
| 994 | |
| 995 | break; |
| 996 | case QPNP_TYPE_FTS426: |
| 997 | rc = regmap_bulk_read(vreg->regmap, vreg->spmi_base_addr |
| 998 | + QPNP_FTS426_REG_VOLTAGE_ULS_LB, |
| 999 | reg, 2); |
| 1000 | if (rc) { |
| 1001 | dev_err(&vreg->pdev->dev, "%s: could not read voltage limit registers, rc=%d\n", |
| 1002 | __func__, rc); |
| 1003 | return rc; |
| 1004 | } |
| 1005 | |
| 1006 | limit_max_uV = spm_regulator_vlevel_to_uv(vreg, |
| 1007 | ((unsigned)reg[1] << 8) | reg[0]); |
| 1008 | break; |
| 1009 | case QPNP_TYPE_ULT_HF: |
| 1010 | /* no HW voltage limit configuration */ |
| 1011 | break; |
| 1012 | } |
| 1013 | |
| 1014 | if (init_data->constraints.min_uV < limit_min_uV |
| 1015 | || init_data->constraints.max_uV > limit_max_uV) { |
| 1016 | dev_err(&vreg->pdev->dev, "regulator min/max(%d/%d) constraints do not fit within HW configured min/max(%d/%d) constraints\n", |
| 1017 | init_data->constraints.min_uV, |
| 1018 | init_data->constraints.max_uV, limit_min_uV, |
| 1019 | limit_max_uV); |
| 1020 | return -EINVAL; |
| 1021 | } |
| 1022 | |
| 1023 | return rc; |
| 1024 | } |
| 1025 | |
| 1026 | static bool spm_regulator_using_range0(struct spm_vreg *vreg) |
| 1027 | { |
| 1028 | return vreg->range == &fts2_range0 || vreg->range == &fts2p5_range0 |
| 1029 | || vreg->range == &ult_hf_range0 || vreg->range == &hf_range0 |
| 1030 | || vreg->range == &fts426_range; |
| 1031 | } |
| 1032 | |
| 1033 | /* Register a regulator to enable/disable AVS and set AVS min/max limits. */ |
| 1034 | static int spm_regulator_avs_register(struct spm_vreg *vreg, |
| 1035 | struct device *dev, struct device_node *node) |
| 1036 | { |
| 1037 | struct regulator_config reg_config = {}; |
| 1038 | struct device_node *avs_node = NULL; |
| 1039 | struct device_node *child_node; |
| 1040 | struct regulator_init_data *init_data; |
| 1041 | int rc; |
| 1042 | |
| 1043 | /* |
| 1044 | * Find the first available child node (if any). It corresponds to an |
| 1045 | * AVS limits regulator. |
| 1046 | */ |
| 1047 | for_each_available_child_of_node(node, child_node) { |
| 1048 | avs_node = child_node; |
| 1049 | break; |
| 1050 | } |
| 1051 | |
| 1052 | if (!avs_node) |
| 1053 | return 0; |
| 1054 | |
| 1055 | init_data = of_get_regulator_init_data(dev, avs_node, &vreg->avs_rdesc); |
| 1056 | if (!init_data) { |
| 1057 | dev_err(dev, "%s: unable to allocate memory\n", __func__); |
| 1058 | return -ENOMEM; |
| 1059 | } |
| 1060 | init_data->constraints.input_uV = init_data->constraints.max_uV; |
| 1061 | init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS |
| 1062 | | REGULATOR_CHANGE_VOLTAGE; |
| 1063 | |
| 1064 | if (!init_data->constraints.name) { |
| 1065 | dev_err(dev, "%s: AVS node is missing regulator name\n", |
| 1066 | __func__); |
| 1067 | return -EINVAL; |
| 1068 | } |
| 1069 | |
| 1070 | vreg->avs_rdesc.name = init_data->constraints.name; |
| 1071 | vreg->avs_rdesc.type = REGULATOR_VOLTAGE; |
| 1072 | vreg->avs_rdesc.owner = THIS_MODULE; |
| 1073 | vreg->avs_rdesc.ops = &spm_regulator_avs_ops; |
| 1074 | vreg->avs_rdesc.n_voltages |
| 1075 | = (vreg->range->max_uV - vreg->range->set_point_min_uV) |
| 1076 | / vreg->range->step_uV + 1; |
| 1077 | |
| 1078 | reg_config.dev = dev; |
| 1079 | reg_config.init_data = init_data; |
| 1080 | reg_config.driver_data = vreg; |
| 1081 | reg_config.of_node = avs_node; |
| 1082 | |
| 1083 | vreg->avs_rdev = regulator_register(&vreg->avs_rdesc, ®_config); |
| 1084 | if (IS_ERR(vreg->avs_rdev)) { |
| 1085 | rc = PTR_ERR(vreg->avs_rdev); |
| 1086 | dev_err(dev, "%s: AVS regulator_register failed, rc=%d\n", |
| 1087 | __func__, rc); |
| 1088 | return rc; |
| 1089 | } |
| 1090 | |
| 1091 | if (vreg->bypass_spm) |
| 1092 | pr_debug("%s: SPM bypassed so AVS regulator calls are no-ops\n", |
| 1093 | vreg->avs_rdesc.name); |
| 1094 | |
| 1095 | return 0; |
| 1096 | } |
| 1097 | |
| 1098 | static int spm_regulator_probe(struct platform_device *pdev) |
| 1099 | { |
| 1100 | struct regulator_config reg_config = {}; |
| 1101 | struct device_node *node = pdev->dev.of_node; |
| 1102 | struct regulator_init_data *init_data; |
| 1103 | struct spm_vreg *vreg; |
| 1104 | unsigned int base; |
| 1105 | bool bypass_spm; |
| 1106 | int rc; |
| 1107 | |
| 1108 | if (!node) { |
| 1109 | dev_err(&pdev->dev, "%s: device node missing\n", __func__); |
| 1110 | return -ENODEV; |
| 1111 | } |
| 1112 | |
| 1113 | bypass_spm = of_property_read_bool(node, "qcom,bypass-spm"); |
| 1114 | if (!bypass_spm) { |
| 1115 | rc = msm_spm_probe_done(); |
| 1116 | if (rc) { |
| 1117 | if (rc != -EPROBE_DEFER) |
| 1118 | dev_err(&pdev->dev, |
| 1119 | "%s: spm unavailable, rc=%d\n", |
| 1120 | __func__, rc); |
| 1121 | return rc; |
| 1122 | } |
| 1123 | } |
| 1124 | |
| 1125 | vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL); |
| 1126 | if (!vreg) { |
| 1127 | pr_err("allocation failed.\n"); |
| 1128 | return -ENOMEM; |
| 1129 | } |
| 1130 | vreg->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 1131 | if (!vreg->regmap) { |
| 1132 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 1133 | return -EINVAL; |
| 1134 | } |
| 1135 | vreg->pdev = pdev; |
| 1136 | vreg->bypass_spm = bypass_spm; |
| 1137 | |
| 1138 | rc = of_property_read_u32(pdev->dev.of_node, "reg", &base); |
| 1139 | if (rc < 0) { |
| 1140 | dev_err(&pdev->dev, |
| 1141 | "Couldn't find reg in node = %s rc = %d\n", |
| 1142 | pdev->dev.of_node->full_name, rc); |
| 1143 | return rc; |
| 1144 | } |
| 1145 | vreg->spmi_base_addr = base; |
| 1146 | |
| 1147 | rc = qpnp_smps_check_type(vreg); |
| 1148 | if (rc) |
| 1149 | return rc; |
| 1150 | |
| 1151 | /* Specify CPU 0 as default in order to handle shared regulator case. */ |
| 1152 | vreg->cpu_num = 0; |
| 1153 | of_property_read_u32(vreg->pdev->dev.of_node, "qcom,cpu-num", |
| 1154 | &vreg->cpu_num); |
| 1155 | |
| 1156 | of_property_read_u32(vreg->pdev->dev.of_node, "qcom,recal-mask", |
| 1157 | &vreg->recal_cluster_mask); |
| 1158 | |
| 1159 | /* |
| 1160 | * The regulator must be initialized to range 0 or range 1 during |
| 1161 | * PMIC power on sequence. Once it is set, it cannot be changed |
| 1162 | * dynamically. |
| 1163 | */ |
| 1164 | if (vreg->regulator_type == QPNP_TYPE_FTS2) |
| 1165 | rc = qpnp_smps_init_range(vreg, &fts2_range0, &fts2_range1); |
| 1166 | else if (vreg->regulator_type == QPNP_TYPE_FTS2p5) |
| 1167 | rc = qpnp_smps_init_range(vreg, &fts2p5_range0, &fts2p5_range1); |
| 1168 | else if (vreg->regulator_type == QPNP_TYPE_FTS426) |
| 1169 | vreg->range = &fts426_range; |
| 1170 | else if (vreg->regulator_type == QPNP_TYPE_HF) |
| 1171 | rc = qpnp_smps_init_range(vreg, &hf_range0, &hf_range1); |
| 1172 | else if (vreg->regulator_type == QPNP_TYPE_ULT_HF) |
| 1173 | rc = qpnp_ult_hf_init_range(vreg); |
| 1174 | if (rc) |
| 1175 | return rc; |
| 1176 | |
| 1177 | rc = qpnp_smps_init_voltage(vreg); |
| 1178 | if (rc) |
| 1179 | return rc; |
| 1180 | |
| 1181 | rc = qpnp_smps_init_mode(vreg); |
| 1182 | if (rc) |
| 1183 | return rc; |
| 1184 | |
| 1185 | rc = qpnp_smps_init_step_rate(vreg); |
| 1186 | if (rc) |
| 1187 | return rc; |
| 1188 | |
| 1189 | init_data = of_get_regulator_init_data(&pdev->dev, node, &vreg->rdesc); |
| 1190 | if (!init_data) { |
| 1191 | dev_err(&pdev->dev, "%s: unable to allocate memory\n", |
| 1192 | __func__); |
| 1193 | return -ENOMEM; |
| 1194 | } |
| 1195 | init_data->constraints.input_uV = init_data->constraints.max_uV; |
| 1196 | init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS |
| 1197 | | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE; |
| 1198 | init_data->constraints.valid_modes_mask |
| 1199 | = REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE; |
| 1200 | |
| 1201 | if (!init_data->constraints.name) { |
| 1202 | dev_err(&pdev->dev, "%s: node is missing regulator name\n", |
| 1203 | __func__); |
| 1204 | return -EINVAL; |
| 1205 | } |
| 1206 | |
| 1207 | rc = qpnp_smps_check_constraints(vreg, init_data); |
| 1208 | if (rc) { |
| 1209 | dev_err(&pdev->dev, "%s: regulator constraints check failed, rc=%d\n", |
| 1210 | __func__, rc); |
| 1211 | return rc; |
| 1212 | } |
| 1213 | |
| 1214 | vreg->rdesc.name = init_data->constraints.name; |
| 1215 | vreg->rdesc.type = REGULATOR_VOLTAGE; |
| 1216 | vreg->rdesc.owner = THIS_MODULE; |
| 1217 | vreg->rdesc.ops = &spm_regulator_ops; |
| 1218 | vreg->rdesc.n_voltages |
| 1219 | = (vreg->range->max_uV - vreg->range->set_point_min_uV) |
| 1220 | / vreg->range->step_uV + 1; |
| 1221 | |
| 1222 | vreg->max_step_uV = SPM_REGULATOR_MAX_STEP_UV; |
| 1223 | of_property_read_u32(vreg->pdev->dev.of_node, |
| 1224 | "qcom,max-voltage-step", &vreg->max_step_uV); |
| 1225 | |
| 1226 | if (vreg->max_step_uV > SPM_REGULATOR_MAX_STEP_UV) |
| 1227 | vreg->max_step_uV = SPM_REGULATOR_MAX_STEP_UV; |
| 1228 | |
| 1229 | vreg->max_step_uV = rounddown(vreg->max_step_uV, vreg->range->step_uV); |
| 1230 | pr_debug("%s: max single voltage step size=%u uV\n", |
| 1231 | vreg->rdesc.name, vreg->max_step_uV); |
| 1232 | |
| 1233 | reg_config.dev = &pdev->dev; |
| 1234 | reg_config.init_data = init_data; |
| 1235 | reg_config.driver_data = vreg; |
| 1236 | reg_config.of_node = node; |
| 1237 | vreg->rdev = regulator_register(&vreg->rdesc, ®_config); |
| 1238 | |
| 1239 | if (IS_ERR(vreg->rdev)) { |
| 1240 | rc = PTR_ERR(vreg->rdev); |
| 1241 | dev_err(&pdev->dev, "%s: regulator_register failed, rc=%d\n", |
| 1242 | __func__, rc); |
| 1243 | return rc; |
| 1244 | } |
| 1245 | |
| 1246 | rc = spm_regulator_avs_register(vreg, &pdev->dev, node); |
| 1247 | if (rc) { |
| 1248 | regulator_unregister(vreg->rdev); |
| 1249 | return rc; |
| 1250 | } |
| 1251 | |
| 1252 | dev_set_drvdata(&pdev->dev, vreg); |
| 1253 | |
| 1254 | pr_info("name=%s, range=%s, voltage=%d uV, mode=%s, step rate=%d uV/us\n", |
| 1255 | vreg->rdesc.name, |
| 1256 | spm_regulator_using_range0(vreg) ? "LV" : "MV", |
| 1257 | vreg->uV, |
| 1258 | vreg->init_mode == QPNP_LOGICAL_MODE_PWM ? "PWM" : |
| 1259 | (vreg->init_mode == QPNP_LOGICAL_MODE_AUTO ? "AUTO" : "PFM"), |
| 1260 | vreg->step_rate); |
| 1261 | |
| 1262 | return rc; |
| 1263 | } |
| 1264 | |
| 1265 | static int spm_regulator_remove(struct platform_device *pdev) |
| 1266 | { |
| 1267 | struct spm_vreg *vreg = dev_get_drvdata(&pdev->dev); |
| 1268 | |
| 1269 | if (vreg->avs_rdev) |
| 1270 | regulator_unregister(vreg->avs_rdev); |
| 1271 | regulator_unregister(vreg->rdev); |
| 1272 | |
| 1273 | return 0; |
| 1274 | } |
| 1275 | |
| 1276 | static struct of_device_id spm_regulator_match_table[] = { |
| 1277 | { .compatible = SPM_REGULATOR_DRIVER_NAME, }, |
| 1278 | {} |
| 1279 | }; |
| 1280 | |
| 1281 | static const struct platform_device_id spm_regulator_id[] = { |
| 1282 | { SPM_REGULATOR_DRIVER_NAME, 0 }, |
| 1283 | {} |
| 1284 | }; |
| 1285 | MODULE_DEVICE_TABLE(spmi, spm_regulator_id); |
| 1286 | |
| 1287 | static struct platform_driver spm_regulator_driver = { |
| 1288 | .driver = { |
| 1289 | .name = SPM_REGULATOR_DRIVER_NAME, |
| 1290 | .of_match_table = spm_regulator_match_table, |
| 1291 | .owner = THIS_MODULE, |
| 1292 | }, |
| 1293 | .probe = spm_regulator_probe, |
| 1294 | .remove = spm_regulator_remove, |
| 1295 | .id_table = spm_regulator_id, |
| 1296 | }; |
| 1297 | |
| 1298 | /** |
| 1299 | * spm_regulator_init() - register spmi driver for spm-regulator |
| 1300 | * |
| 1301 | * This initialization function should be called in systems in which driver |
| 1302 | * registration ordering must be controlled precisely. |
| 1303 | * |
| 1304 | * Returns 0 on success or errno on failure. |
| 1305 | */ |
| 1306 | int __init spm_regulator_init(void) |
| 1307 | { |
| 1308 | static bool has_registered; |
| 1309 | |
| 1310 | if (has_registered) |
| 1311 | return 0; |
| 1312 | else |
| 1313 | has_registered = true; |
| 1314 | |
| 1315 | return platform_driver_register(&spm_regulator_driver); |
| 1316 | } |
| 1317 | EXPORT_SYMBOL(spm_regulator_init); |
| 1318 | |
| 1319 | static void __exit spm_regulator_exit(void) |
| 1320 | { |
| 1321 | platform_driver_unregister(&spm_regulator_driver); |
| 1322 | } |
| 1323 | |
| 1324 | arch_initcall(spm_regulator_init); |
| 1325 | module_exit(spm_regulator_exit); |
| 1326 | |
| 1327 | MODULE_LICENSE("GPL v2"); |
| 1328 | MODULE_DESCRIPTION("SPM regulator driver"); |
| 1329 | MODULE_ALIAS("platform:spm-regulator"); |