Vivek Mahajan | a2b31dd | 2009-12-08 13:01:15 +0530 | [diff] [blame] | 1 | * Freescale PQ3 and QorIQ based Cache SRAM |
| 2 | |
| 3 | Freescale's mpc85xx and some QorIQ platforms provide an |
| 4 | option of configuring a part of (or full) cache memory |
| 5 | as SRAM. This cache SRAM representation in the device |
| 6 | tree should be done as under:- |
| 7 | |
| 8 | Required properties: |
| 9 | |
| 10 | - compatible : should be "fsl,p2020-cache-sram" |
| 11 | - fsl,cache-sram-ctlr-handle : points to the L2 controller |
| 12 | - reg : offset and length of the cache-sram. |
| 13 | |
| 14 | Example: |
| 15 | |
| 16 | cache-sram@fff00000 { |
| 17 | fsl,cache-sram-ctlr-handle = <&L2>; |
| 18 | reg = <0 0xfff00000 0 0x10000>; |
| 19 | compatible = "fsl,p2020-cache-sram"; |
| 20 | }; |