Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 1 | * Freescale DMA Controllers |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 2 | |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 3 | ** Freescale Elo DMA Controller |
| 4 | This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx |
| 5 | series chips such as mpc8315, mpc8349, mpc8379 etc. |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 6 | |
| 7 | Required properties: |
| 8 | |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 9 | - compatible : must include "fsl,elo-dma" |
| 10 | - reg : DMA General Status Register, i.e. DGSR which contains |
| 11 | status for all the 4 DMA channels |
| 12 | - ranges : describes the mapping between the address space of the |
| 13 | DMA channels and the address space of the DMA controller |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 14 | - cell-index : controller index. 0 for controller @ 0x8100 |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 15 | - interrupts : interrupt specifier for DMA IRQ |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 16 | - interrupt-parent : optional, if needed for interrupt mapping |
| 17 | |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 18 | - DMA channel nodes: |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 19 | - compatible : must include "fsl,elo-dma-channel" |
| 20 | However, see note below. |
| 21 | - reg : DMA channel specific registers |
| 22 | - cell-index : DMA channel index starts at 0. |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 23 | |
| 24 | Optional properties: |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 25 | - interrupts : interrupt specifier for DMA channel IRQ |
| 26 | (on 83xx this is expected to be identical to |
| 27 | the interrupts property of the parent node) |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 28 | - interrupt-parent : optional, if needed for interrupt mapping |
| 29 | |
| 30 | Example: |
| 31 | dma@82a8 { |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <1>; |
| 34 | compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 35 | reg = <0x82a8 4>; |
| 36 | ranges = <0 0x8100 0x1a4>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 37 | interrupt-parent = <&ipic>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 38 | interrupts = <71 8>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 39 | cell-index = <0>; |
| 40 | dma-channel@0 { |
| 41 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 42 | cell-index = <0>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 43 | reg = <0 0x80>; |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 44 | interrupt-parent = <&ipic>; |
| 45 | interrupts = <71 8>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 46 | }; |
| 47 | dma-channel@80 { |
| 48 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 49 | cell-index = <1>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 50 | reg = <0x80 0x80>; |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 51 | interrupt-parent = <&ipic>; |
| 52 | interrupts = <71 8>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 53 | }; |
| 54 | dma-channel@100 { |
| 55 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 56 | cell-index = <2>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 57 | reg = <0x100 0x80>; |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 58 | interrupt-parent = <&ipic>; |
| 59 | interrupts = <71 8>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 60 | }; |
| 61 | dma-channel@180 { |
| 62 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 63 | cell-index = <3>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 64 | reg = <0x180 0x80>; |
Ira Snyder | d3f620b | 2010-01-06 13:34:04 +0000 | [diff] [blame] | 65 | interrupt-parent = <&ipic>; |
| 66 | interrupts = <71 8>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 67 | }; |
| 68 | }; |
| 69 | |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 70 | ** Freescale EloPlus DMA Controller |
| 71 | This is a 4-channel DMA controller with extended addresses and chaining, |
| 72 | mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as |
| 73 | mpc8540, mpc8641 p4080, bsc9131 etc. |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 74 | |
| 75 | Required properties: |
| 76 | |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 77 | - compatible : must include "fsl,eloplus-dma" |
| 78 | - reg : DMA General Status Register, i.e. DGSR which contains |
| 79 | status for all the 4 DMA channels |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 80 | - cell-index : controller index. 0 for controller @ 0x21000, |
| 81 | 1 for controller @ 0xc000 |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 82 | - ranges : describes the mapping between the address space of the |
| 83 | DMA channels and the address space of the DMA controller |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 84 | |
| 85 | - DMA channel nodes: |
Hongbo Zhang | c3d68d8 | 2013-09-26 17:33:41 +0800 | [diff] [blame] | 86 | - compatible : must include "fsl,eloplus-dma-channel" |
| 87 | However, see note below. |
| 88 | - cell-index : DMA channel index starts at 0. |
| 89 | - reg : DMA channel specific registers |
| 90 | - interrupts : interrupt specifier for DMA channel IRQ |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 91 | - interrupt-parent : optional, if needed for interrupt mapping |
| 92 | |
| 93 | Example: |
| 94 | dma@21300 { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <1>; |
| 97 | compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 98 | reg = <0x21300 4>; |
| 99 | ranges = <0 0x21100 0x200>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 100 | cell-index = <0>; |
| 101 | dma-channel@0 { |
| 102 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 103 | reg = <0 0x80>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 104 | cell-index = <0>; |
| 105 | interrupt-parent = <&mpic>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 106 | interrupts = <20 2>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 107 | }; |
| 108 | dma-channel@80 { |
| 109 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 110 | reg = <0x80 0x80>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 111 | cell-index = <1>; |
| 112 | interrupt-parent = <&mpic>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 113 | interrupts = <21 2>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 114 | }; |
| 115 | dma-channel@100 { |
| 116 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 117 | reg = <0x100 0x80>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 118 | cell-index = <2>; |
| 119 | interrupt-parent = <&mpic>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 120 | interrupts = <22 2>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 121 | }; |
| 122 | dma-channel@180 { |
| 123 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 124 | reg = <0x180 0x80>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 125 | cell-index = <3>; |
| 126 | interrupt-parent = <&mpic>; |
Peter Korsgaard | b4f7ec4 | 2009-01-14 15:52:41 +0100 | [diff] [blame] | 127 | interrupts = <23 2>; |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 128 | }; |
| 129 | }; |
Timur Tabi | b56c276 | 2008-10-10 11:52:31 -0500 | [diff] [blame] | 130 | |
Hongbo Zhang | 03aa254 | 2013-09-26 17:33:42 +0800 | [diff] [blame] | 131 | ** Freescale Elo3 DMA Controller |
| 132 | DMA controller which has same function as EloPlus except that Elo3 has 8 |
| 133 | channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx |
| 134 | series chips, such as t1040, t4240, b4860. |
| 135 | |
| 136 | Required properties: |
| 137 | |
| 138 | - compatible : must include "fsl,elo3-dma" |
| 139 | - reg : contains two entries for DMA General Status Registers, |
| 140 | i.e. DGSR0 which includes status for channel 1~4, and |
| 141 | DGSR1 for channel 5~8 |
| 142 | - ranges : describes the mapping between the address space of the |
| 143 | DMA channels and the address space of the DMA controller |
| 144 | |
| 145 | - DMA channel nodes: |
| 146 | - compatible : must include "fsl,eloplus-dma-channel" |
| 147 | - reg : DMA channel specific registers |
| 148 | - interrupts : interrupt specifier for DMA channel IRQ |
| 149 | - interrupt-parent : optional, if needed for interrupt mapping |
| 150 | |
| 151 | Example: |
| 152 | dma@100300 { |
| 153 | #address-cells = <1>; |
| 154 | #size-cells = <1>; |
| 155 | compatible = "fsl,elo3-dma"; |
| 156 | reg = <0x100300 0x4>, |
| 157 | <0x100600 0x4>; |
| 158 | ranges = <0x0 0x100100 0x500>; |
| 159 | dma-channel@0 { |
| 160 | compatible = "fsl,eloplus-dma-channel"; |
| 161 | reg = <0x0 0x80>; |
| 162 | interrupts = <28 2 0 0>; |
| 163 | }; |
| 164 | dma-channel@80 { |
| 165 | compatible = "fsl,eloplus-dma-channel"; |
| 166 | reg = <0x80 0x80>; |
| 167 | interrupts = <29 2 0 0>; |
| 168 | }; |
| 169 | dma-channel@100 { |
| 170 | compatible = "fsl,eloplus-dma-channel"; |
| 171 | reg = <0x100 0x80>; |
| 172 | interrupts = <30 2 0 0>; |
| 173 | }; |
| 174 | dma-channel@180 { |
| 175 | compatible = "fsl,eloplus-dma-channel"; |
| 176 | reg = <0x180 0x80>; |
| 177 | interrupts = <31 2 0 0>; |
| 178 | }; |
| 179 | dma-channel@300 { |
| 180 | compatible = "fsl,eloplus-dma-channel"; |
| 181 | reg = <0x300 0x80>; |
| 182 | interrupts = <76 2 0 0>; |
| 183 | }; |
| 184 | dma-channel@380 { |
| 185 | compatible = "fsl,eloplus-dma-channel"; |
| 186 | reg = <0x380 0x80>; |
| 187 | interrupts = <77 2 0 0>; |
| 188 | }; |
| 189 | dma-channel@400 { |
| 190 | compatible = "fsl,eloplus-dma-channel"; |
| 191 | reg = <0x400 0x80>; |
| 192 | interrupts = <78 2 0 0>; |
| 193 | }; |
| 194 | dma-channel@480 { |
| 195 | compatible = "fsl,eloplus-dma-channel"; |
| 196 | reg = <0x480 0x80>; |
| 197 | interrupts = <79 2 0 0>; |
| 198 | }; |
| 199 | }; |
| 200 | |
Timur Tabi | b56c276 | 2008-10-10 11:52:31 -0500 | [diff] [blame] | 201 | Note on DMA channel compatible properties: The compatible property must say |
| 202 | "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA |
| 203 | driver (fsldma). Any DMA channel used by fsldma cannot be used by another |
| 204 | DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA |
| 205 | channel that should be used for another driver should not use |
| 206 | "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for |
| 207 | example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt |
| 208 | for more information. |