| harninder rai | c70a974 | 2014-02-19 18:11:26 +0530 | [diff] [blame] | 1 | Freescale L2 Cache Controller |
| 2 | |
| 3 | L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. |
| 4 | The cache bindings explained below are ePAPR compliant |
| 5 | |
| 6 | Required Properties: |
| 7 | |
| 8 | - compatible : Should include "fsl,chip-l2-cache-controller" and "cache" |
| 9 | where chip is the processor (bsc9132, npc8572 etc.) |
| 10 | - reg : Address and size of L2 cache controller registers |
| 11 | - cache-size : Size of the entire L2 cache |
| 12 | - interrupts : Error interrupt of L2 controller |
| 13 | - cache-line-size : Size of L2 cache lines |
| 14 | |
| 15 | Example: |
| 16 | |
| 17 | L2: l2-cache-controller@20000 { |
| 18 | compatible = "fsl,bsc9132-l2-cache-controller", "cache"; |
| 19 | reg = <0x20000 0x1000>; |
| 20 | cache-line-size = <32>; // 32 bytes |
| 21 | cache-size = <0x40000>; // L2,256K |
| 22 | interrupts = <16 2 1 0>; |
| 23 | }; |