Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 1 | * Freescale MSI interrupt controller |
| 2 | |
Matt LaPlante | 19f5946 | 2009-04-27 15:06:31 +0200 | [diff] [blame] | 3 | Required properties: |
Minghuan Lian | 03daa99 | 2013-06-21 18:59:12 +0800 | [diff] [blame] | 4 | - compatible : compatible list, may contain one or two entries |
| 5 | The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, |
| 6 | etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or |
| 7 | "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic |
| 8 | version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is |
| 9 | provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" |
| 10 | should be used. The first entry is optional; the second entry is |
| 11 | required. |
Scott Wood | 6820fea | 2011-01-17 14:25:28 -0600 | [diff] [blame] | 12 | |
Diana CRACIUN | da3b6c0 | 2012-02-01 17:50:34 +0200 | [diff] [blame] | 13 | - reg : It may contain one or two regions. The first region should contain |
| 14 | the address and the length of the shared message interrupt register set. |
Minghuan Lian | 03daa99 | 2013-06-21 18:59:12 +0800 | [diff] [blame] | 15 | The second region should contain the address of aliased MSIIR or MSIIR1 |
| 16 | register for platforms that have such an alias, if using MSIIR1, the second |
| 17 | region must be added because different MSI group has different MSIIR1 offset. |
Scott Wood | 6820fea | 2011-01-17 14:25:28 -0600 | [diff] [blame] | 18 | |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 19 | - interrupts : each one of the interrupts here is one entry per 32 MSIs, |
| 20 | and routed to the host interrupt controller. the interrupts should |
Scott Wood | 6820fea | 2011-01-17 14:25:28 -0600 | [diff] [blame] | 21 | be set as edge sensitive. If msi-available-ranges is present, only |
| 22 | the interrupts that correspond to available ranges shall be present. |
| 23 | |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 24 | - interrupt-parent: the phandle for the interrupt controller |
| 25 | that services interrupts for this device. for 83xx cpu, the interrupts |
| 26 | are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed |
| 27 | to MPIC. |
| 28 | |
Timur Tabi | 2bcd1c0 | 2011-09-23 12:41:35 -0500 | [diff] [blame] | 29 | Optional properties: |
Minghuan Lian | 03daa99 | 2013-06-21 18:59:12 +0800 | [diff] [blame] | 30 | - msi-available-ranges: use <start count> style section to define which |
| 31 | msi interrupt can be used in the 256 msi interrupts. This property is |
| 32 | optional, without this, all the MSI interrupts can be used. |
| 33 | Each available range must begin and end on a multiple of 32 (i.e. |
| 34 | no splitting an individual MSI register or the associated PIC interrupt). |
| 35 | MPIC v4.3 does not support this property because the 32 interrupts of an |
| 36 | individual register are not continuous when using MSIIR1. |
| 37 | |
Timur Tabi | 2bcd1c0 | 2011-09-23 12:41:35 -0500 | [diff] [blame] | 38 | - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register |
| 39 | is used for MSI messaging. The address of MSIIR in PCI address space is |
| 40 | the MSI message address. |
| 41 | |
| 42 | This property may be used in virtualized environments where the hypervisor |
| 43 | has created an alternate mapping for the MSIR block. See below for an |
| 44 | explanation. |
| 45 | |
| 46 | |
Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame] | 47 | Example: |
| 48 | msi@41600 { |
| 49 | compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; |
| 50 | reg = <0x41600 0x80>; |
| 51 | msi-available-ranges = <0 0x100>; |
| 52 | interrupts = < |
| 53 | 0xe0 0 |
| 54 | 0xe1 0 |
| 55 | 0xe2 0 |
| 56 | 0xe3 0 |
| 57 | 0xe4 0 |
| 58 | 0xe5 0 |
| 59 | 0xe6 0 |
| 60 | 0xe7 0>; |
| 61 | interrupt-parent = <&mpic>; |
| 62 | }; |
Timur Tabi | 2bcd1c0 | 2011-09-23 12:41:35 -0500 | [diff] [blame] | 63 | |
Minghuan Lian | 03daa99 | 2013-06-21 18:59:12 +0800 | [diff] [blame] | 64 | msi@41600 { |
| 65 | compatible = "fsl,mpic-msi-v4.3"; |
| 66 | reg = <0x41600 0x200 0x44148 4>; |
| 67 | interrupts = < |
| 68 | 0xe0 0 0 0 |
| 69 | 0xe1 0 0 0 |
| 70 | 0xe2 0 0 0 |
| 71 | 0xe3 0 0 0 |
| 72 | 0xe4 0 0 0 |
| 73 | 0xe5 0 0 0 |
| 74 | 0xe6 0 0 0 |
| 75 | 0xe7 0 0 0 |
| 76 | 0x100 0 0 0 |
| 77 | 0x101 0 0 0 |
| 78 | 0x102 0 0 0 |
| 79 | 0x103 0 0 0 |
| 80 | 0x104 0 0 0 |
| 81 | 0x105 0 0 0 |
| 82 | 0x106 0 0 0 |
| 83 | 0x107 0 0 0>; |
| 84 | }; |
| 85 | |
Timur Tabi | 2bcd1c0 | 2011-09-23 12:41:35 -0500 | [diff] [blame] | 86 | The Freescale hypervisor and msi-address-64 |
| 87 | ------------------------------------------- |
| 88 | Normally, PCI devices have access to all of CCSR via an ATMU mapping. The |
| 89 | Freescale MSI driver calculates the address of MSIIR (in the MSI register |
| 90 | block) and sets that address as the MSI message address. |
| 91 | |
| 92 | In a virtualized environment, the hypervisor may need to create an IOMMU |
| 93 | mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement |
| 94 | because of hardware limitations of the Peripheral Access Management Unit |
| 95 | (PAMU), which is currently the only IOMMU that the hypervisor supports. |
| 96 | The ATMU is programmed with the guest physical address, and the PAMU |
| 97 | intercepts transactions and reroutes them to the true physical address. |
| 98 | |
| 99 | In the PAMU, each PCI controller is given only one primary window. The |
| 100 | PAMU restricts DMA operations so that they can only occur within a window. |
| 101 | Because PCI devices must be able to DMA to memory, the primary window must |
| 102 | be used to cover all of the guest's memory space. |
| 103 | |
| 104 | PAMU primary windows can be divided into 256 subwindows, and each |
| 105 | subwindow can have its own address mapping ("guest physical" to "true |
| 106 | physical"). However, each subwindow has to have the same alignment, which |
| 107 | means they cannot be located at just any address. Because of these |
| 108 | restrictions, it is usually impossible to create a 4KB subwindow that |
| 109 | covers MSIIR where it's normally located. |
| 110 | |
| 111 | Therefore, the hypervisor has to create a subwindow inside the same |
| 112 | primary window used for memory, but mapped to the MSIR block (where MSIIR |
| 113 | lives). The first subwindow after the end of guest memory is used for |
| 114 | this. The address specified in the msi-address-64 property is the PCI |
| 115 | address of MSIIR. The hypervisor configures the PAMU to map that address to |
| 116 | the true physical address of MSIIR. |