| Christophe Ricard | 92a2c6b | 2015-03-08 11:17:16 +0100 | [diff] [blame] | 1 | * STMicroelectronics SAS. ST33ZP24 TPM SoC |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: Should be "st,st33zp24-spi". |
| 5 | - spi-max-frequency: Maximum SPI frequency (<= 10000000). |
| 6 | |
| 7 | Optional ST33ZP24 Properties: |
| 8 | - interrupt-parent: phandle for the interrupt gpio controller |
| 9 | - interrupts: GPIO interrupt to which the chip is connected |
| 10 | - lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state. |
| 11 | If set, power must be present when the platform is going into sleep/hibernate mode. |
| 12 | |
| 13 | Optional SoC Specific Properties: |
| 14 | - pinctrl-names: Contains only one value - "default". |
| 15 | - pintctrl-0: Specifies the pin control groups used for this controller. |
| 16 | |
| 17 | Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4): |
| 18 | |
| 19 | &mcspi4 { |
| 20 | |
| 21 | status = "okay"; |
| 22 | |
| 23 | st33zp24@0 { |
| 24 | |
| 25 | compatible = "st,st33zp24-spi"; |
| 26 | |
| 27 | spi-max-frequency = <10000000>; |
| 28 | |
| 29 | interrupt-parent = <&gpio5>; |
| 30 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
| 31 | |
| 32 | lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; |
| 33 | }; |
| 34 | }; |