| Qipan Li | 1ef3980 | 2013-08-15 06:52:16 +0800 | [diff] [blame] | 1 | * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * |
| 2 | |
| 3 | Required properties: |
| Qipan Li | 52bec4e | 2014-11-11 20:44:58 +0800 | [diff] [blame] | 4 | - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", |
| Qipan Li | 4b8038d | 2015-04-20 08:10:22 +0000 | [diff] [blame] | 5 | "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". |
| Qipan Li | 1ef3980 | 2013-08-15 06:52:16 +0800 | [diff] [blame] | 6 | - reg : Offset and length of the register set for the device |
| 7 | - interrupts : Should contain uart interrupt |
| 8 | - fifosize : Should define hardware rx/tx fifo size |
| 9 | - clocks : Should contain uart clock number |
| 10 | |
| 11 | Optional properties: |
| Geert Uytterhoeven | 7f60830 | 2016-04-22 17:22:24 +0200 | [diff] [blame] | 12 | - uart-has-rtscts: we have hardware flow controller pins in hardware |
| 13 | - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true |
| 14 | - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true |
| Qipan Li | 1ef3980 | 2013-08-15 06:52:16 +0800 | [diff] [blame] | 15 | |
| 16 | Example: |
| 17 | |
| 18 | uart0: uart@b0050000 { |
| 19 | cell-index = <0>; |
| 20 | compatible = "sirf,prima2-uart"; |
| 21 | reg = <0xb0050000 0x1000>; |
| 22 | interrupts = <17>; |
| 23 | fifosize = <128>; |
| 24 | clocks = <&clks 13>; |
| 25 | }; |
| 26 | |
| 27 | On the board-specific dts, we can put rts-gpios and cts-gpios like |
| 28 | |
| 29 | usp@b0090000 { |
| 30 | compatible = "sirf,prima2-usp-uart"; |
| Geert Uytterhoeven | 7f60830 | 2016-04-22 17:22:24 +0200 | [diff] [blame] | 31 | uart-has-rtscts; |
| Qipan Li | 1ef3980 | 2013-08-15 06:52:16 +0800 | [diff] [blame] | 32 | rts-gpios = <&gpio 15 0>; |
| 33 | cts-gpios = <&gpio 46 0>; |
| 34 | }; |