Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1999,2000 Arm Limited |
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| 4 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 5 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 6 | * - add MX31 specific definitions |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/mm.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/err.h> |
| 22 | |
| 23 | #include <asm/pgtable.h> |
Shawn Guo | ddd5f51 | 2011-09-28 17:16:05 +0800 | [diff] [blame] | 24 | #include <asm/hardware/cache-l2x0.h> |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 25 | #include <asm/mach/map.h> |
| 26 | |
| 27 | #include <mach/common.h> |
Shawn Guo | 3622360 | 2011-06-22 22:41:30 +0800 | [diff] [blame] | 28 | #include <mach/devices-common.h> |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 29 | #include <mach/hardware.h> |
| 30 | #include <mach/iomux-v3.h> |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 31 | #include <mach/irqs.h> |
| 32 | |
Shawn Guo | 41e7daf | 2011-09-28 17:16:06 +0800 | [diff] [blame] | 33 | static void imx3_idle(void) |
| 34 | { |
| 35 | unsigned long reg = 0; |
Shawn Guo | 8c6d831 | 2011-11-11 13:09:18 +0800 | [diff] [blame] | 36 | |
| 37 | if (!need_resched()) |
| 38 | __asm__ __volatile__( |
| 39 | /* disable I and D cache */ |
| 40 | "mrc p15, 0, %0, c1, c0, 0\n" |
| 41 | "bic %0, %0, #0x00001000\n" |
| 42 | "bic %0, %0, #0x00000004\n" |
| 43 | "mcr p15, 0, %0, c1, c0, 0\n" |
| 44 | /* invalidate I cache */ |
| 45 | "mov %0, #0\n" |
| 46 | "mcr p15, 0, %0, c7, c5, 0\n" |
| 47 | /* clear and invalidate D cache */ |
| 48 | "mov %0, #0\n" |
| 49 | "mcr p15, 0, %0, c7, c14, 0\n" |
| 50 | /* WFI */ |
| 51 | "mov %0, #0\n" |
| 52 | "mcr p15, 0, %0, c7, c0, 4\n" |
| 53 | "nop\n" "nop\n" "nop\n" "nop\n" |
| 54 | "nop\n" "nop\n" "nop\n" |
| 55 | /* enable I and D cache */ |
| 56 | "mrc p15, 0, %0, c1, c0, 0\n" |
| 57 | "orr %0, %0, #0x00001000\n" |
| 58 | "orr %0, %0, #0x00000004\n" |
| 59 | "mcr p15, 0, %0, c1, c0, 0\n" |
| 60 | : "=r" (reg)); |
| 61 | local_irq_enable(); |
Shawn Guo | 41e7daf | 2011-09-28 17:16:06 +0800 | [diff] [blame] | 62 | } |
| 63 | |
Shawn Guo | f548897 | 2011-09-28 17:16:07 +0800 | [diff] [blame] | 64 | static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, |
| 65 | unsigned int mtype) |
| 66 | { |
| 67 | if (mtype == MT_DEVICE) { |
| 68 | /* |
| 69 | * Access all peripherals below 0x80000000 as nonshared device |
| 70 | * on mx3, but leave l2cc alone. Otherwise cache corruptions |
| 71 | * can occur. |
| 72 | */ |
| 73 | if (phys_addr < 0x80000000 && |
| 74 | !addr_in_module(phys_addr, MX3x_L2CC)) |
| 75 | mtype = MT_DEVICE_NONSHARED; |
| 76 | } |
| 77 | |
| 78 | return __arm_ioremap(phys_addr, size, mtype); |
| 79 | } |
| 80 | |
Shawn Guo | ddd5f51 | 2011-09-28 17:16:05 +0800 | [diff] [blame] | 81 | void imx3_init_l2x0(void) |
| 82 | { |
| 83 | void __iomem *l2x0_base; |
| 84 | void __iomem *clkctl_base; |
| 85 | |
| 86 | /* |
| 87 | * First of all, we must repair broken chip settings. There are some |
| 88 | * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These |
| 89 | * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. |
| 90 | * Workaraound is to setup the correct register setting prior enabling the |
| 91 | * L2 cache. This should not hurt already working CPUs, as they are using the |
| 92 | * same value. |
| 93 | */ |
| 94 | #define L2_MEM_VAL 0x10 |
| 95 | |
| 96 | clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); |
| 97 | if (clkctl_base != NULL) { |
| 98 | writel(0x00000515, clkctl_base + L2_MEM_VAL); |
| 99 | iounmap(clkctl_base); |
| 100 | } else { |
| 101 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); |
| 102 | } |
| 103 | |
| 104 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); |
| 105 | if (IS_ERR(l2x0_base)) { |
| 106 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", |
| 107 | PTR_ERR(l2x0_base)); |
| 108 | return; |
| 109 | } |
| 110 | |
| 111 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); |
| 112 | } |
| 113 | |
Uwe Kleine-König | 87514fc | 2011-11-22 10:07:26 +0100 | [diff] [blame] | 114 | #ifdef CONFIG_SOC_IMX31 |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 115 | static struct map_desc mx31_io_desc[] __initdata = { |
| 116 | imx_map_entry(MX31, X_MEMC, MT_DEVICE), |
| 117 | imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), |
| 118 | imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), |
| 119 | imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), |
| 120 | imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), |
| 121 | }; |
| 122 | |
| 123 | /* |
| 124 | * This function initializes the memory map. It is called during the |
| 125 | * system startup to create static physical to virtual memory mappings |
| 126 | * for the IO modules. |
| 127 | */ |
| 128 | void __init mx31_map_io(void) |
| 129 | { |
| 130 | iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); |
| 131 | } |
| 132 | |
| 133 | void __init imx31_init_early(void) |
| 134 | { |
| 135 | mxc_set_cpu_type(MXC_CPU_MX31); |
| 136 | mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); |
Shawn Guo | 8c6d831 | 2011-11-11 13:09:18 +0800 | [diff] [blame] | 137 | pm_idle = imx3_idle; |
Shawn Guo | f548897 | 2011-09-28 17:16:07 +0800 | [diff] [blame] | 138 | imx_ioremap = imx3_ioremap; |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 139 | } |
| 140 | |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 141 | void __init mx31_init_irq(void) |
| 142 | { |
| 143 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 144 | } |
| 145 | |
Shawn Guo | 3622360 | 2011-06-22 22:41:30 +0800 | [diff] [blame] | 146 | static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { |
| 147 | .per_2_per_addr = 1677, |
| 148 | }; |
| 149 | |
| 150 | static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { |
| 151 | .ap_2_ap_addr = 423, |
| 152 | .ap_2_bp_addr = 829, |
| 153 | .bp_2_ap_addr = 1029, |
| 154 | }; |
| 155 | |
| 156 | static struct sdma_platform_data imx31_sdma_pdata __initdata = { |
Shawn Guo | 2e534b2 | 2011-06-22 22:41:31 +0800 | [diff] [blame] | 157 | .fw_name = "sdma-imx31-to2.bin", |
Shawn Guo | 3622360 | 2011-06-22 22:41:30 +0800 | [diff] [blame] | 158 | .script_addrs = &imx31_to2_sdma_script, |
| 159 | }; |
| 160 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 161 | void __init imx31_soc_init(void) |
| 162 | { |
Shawn Guo | 3622360 | 2011-06-22 22:41:30 +0800 | [diff] [blame] | 163 | int to_version = mx31_revision() >> 4; |
| 164 | |
Shawn Guo | ddd5f51 | 2011-09-28 17:16:05 +0800 | [diff] [blame] | 165 | imx3_init_l2x0(); |
| 166 | |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 167 | mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); |
| 168 | mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); |
| 169 | mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); |
Shawn Guo | 3622360 | 2011-06-22 22:41:30 +0800 | [diff] [blame] | 170 | |
Shawn Guo | 2e534b2 | 2011-06-22 22:41:31 +0800 | [diff] [blame] | 171 | if (to_version == 1) { |
| 172 | strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", |
| 173 | strlen(imx31_sdma_pdata.fw_name)); |
Shawn Guo | 3622360 | 2011-06-22 22:41:30 +0800 | [diff] [blame] | 174 | imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; |
Shawn Guo | 2e534b2 | 2011-06-22 22:41:31 +0800 | [diff] [blame] | 175 | } |
| 176 | |
Shawn Guo | 62550cd | 2011-07-13 21:33:17 +0800 | [diff] [blame] | 177 | imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); |
Uwe Kleine-König | 27ad4bf | 2011-03-17 09:40:29 +0100 | [diff] [blame] | 178 | } |
Uwe Kleine-König | 87514fc | 2011-11-22 10:07:26 +0100 | [diff] [blame] | 179 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 180 | |
| 181 | #ifdef CONFIG_SOC_IMX35 |
| 182 | static struct map_desc mx35_io_desc[] __initdata = { |
| 183 | imx_map_entry(MX35, X_MEMC, MT_DEVICE), |
| 184 | imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), |
| 185 | imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), |
| 186 | imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), |
| 187 | imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), |
| 188 | }; |
| 189 | |
| 190 | void __init mx35_map_io(void) |
| 191 | { |
| 192 | iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); |
| 193 | } |
| 194 | |
| 195 | void __init imx35_init_early(void) |
| 196 | { |
| 197 | mxc_set_cpu_type(MXC_CPU_MX35); |
| 198 | mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); |
| 199 | mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); |
Sascha Hauer | 9a2ee71 | 2011-11-22 11:32:39 +0100 | [diff] [blame] | 200 | pm_idle = imx3_idle; |
Uwe Kleine-König | 87514fc | 2011-11-22 10:07:26 +0100 | [diff] [blame] | 201 | imx_ioremap = imx3_ioremap; |
| 202 | } |
| 203 | |
| 204 | void __init mx35_init_irq(void) |
| 205 | { |
| 206 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); |
| 207 | } |
Shawn Guo | f1263de | 2011-09-28 17:16:03 +0800 | [diff] [blame] | 208 | |
| 209 | static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { |
| 210 | .ap_2_ap_addr = 642, |
| 211 | .uart_2_mcu_addr = 817, |
| 212 | .mcu_2_app_addr = 747, |
| 213 | .uartsh_2_mcu_addr = 1183, |
| 214 | .per_2_shp_addr = 1033, |
| 215 | .mcu_2_shp_addr = 961, |
| 216 | .ata_2_mcu_addr = 1333, |
| 217 | .mcu_2_ata_addr = 1252, |
| 218 | .app_2_mcu_addr = 683, |
| 219 | .shp_2_per_addr = 1111, |
| 220 | .shp_2_mcu_addr = 892, |
| 221 | }; |
| 222 | |
| 223 | static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { |
| 224 | .ap_2_ap_addr = 729, |
| 225 | .uart_2_mcu_addr = 904, |
| 226 | .per_2_app_addr = 1597, |
| 227 | .mcu_2_app_addr = 834, |
| 228 | .uartsh_2_mcu_addr = 1270, |
| 229 | .per_2_shp_addr = 1120, |
| 230 | .mcu_2_shp_addr = 1048, |
| 231 | .ata_2_mcu_addr = 1429, |
| 232 | .mcu_2_ata_addr = 1339, |
| 233 | .app_2_per_addr = 1531, |
| 234 | .app_2_mcu_addr = 770, |
| 235 | .shp_2_per_addr = 1198, |
| 236 | .shp_2_mcu_addr = 979, |
| 237 | }; |
| 238 | |
| 239 | static struct sdma_platform_data imx35_sdma_pdata __initdata = { |
| 240 | .fw_name = "sdma-imx35-to2.bin", |
| 241 | .script_addrs = &imx35_to2_sdma_script, |
| 242 | }; |
| 243 | |
| 244 | void __init imx35_soc_init(void) |
| 245 | { |
| 246 | int to_version = mx35_revision() >> 4; |
| 247 | |
Shawn Guo | ddd5f51 | 2011-09-28 17:16:05 +0800 | [diff] [blame] | 248 | imx3_init_l2x0(); |
| 249 | |
Shawn Guo | f1263de | 2011-09-28 17:16:03 +0800 | [diff] [blame] | 250 | /* i.mx35 has the i.mx31 type gpio */ |
| 251 | mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); |
| 252 | mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); |
| 253 | mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); |
| 254 | |
| 255 | if (to_version == 1) { |
| 256 | strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", |
| 257 | strlen(imx35_sdma_pdata.fw_name)); |
| 258 | imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; |
| 259 | } |
| 260 | |
| 261 | imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); |
| 262 | } |
Uwe Kleine-König | 87514fc | 2011-11-22 10:07:26 +0100 | [diff] [blame] | 263 | #endif /* ifdef CONFIG_SOC_IMX35 */ |