Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include "hw.h" |
Luis R. Rodriguez | b622a72 | 2010-04-15 17:39:28 -0400 | [diff] [blame] | 18 | #include "ar9003_mac.h" |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 19 | #include "ar9003_2p2_initvals.h" |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 20 | #include "ar9485_initvals.h" |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 21 | #include "ar9340_initvals.h" |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 22 | #include "ar9330_1p1_initvals.h" |
| 23 | #include "ar9330_1p2_initvals.h" |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 24 | #include "ar9580_1p0_initvals.h" |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 25 | |
| 26 | /* General hardware code for the AR9003 hadware family */ |
| 27 | |
Luis R. Rodriguez | 886b42b | 2010-10-14 11:44:27 -0700 | [diff] [blame] | 28 | /* |
| 29 | * The AR9003 family uses a new INI format (pre, core, post |
| 30 | * arrays per subsystem). This provides support for the |
| 31 | * AR9003 2.2 chipsets. |
| 32 | */ |
| 33 | static void ar9003_hw_init_mode_regs(struct ath_hw *ah) |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 34 | { |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 35 | if (AR_SREV_9330_11(ah)) { |
| 36 | /* mac */ |
| 37 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| 38 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 39 | ar9331_1p1_mac_core, |
| 40 | ARRAY_SIZE(ar9331_1p1_mac_core), 2); |
| 41 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 42 | ar9331_1p1_mac_postamble, |
| 43 | ARRAY_SIZE(ar9331_1p1_mac_postamble), 5); |
| 44 | |
| 45 | /* bb */ |
| 46 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); |
| 47 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 48 | ar9331_1p1_baseband_core, |
| 49 | ARRAY_SIZE(ar9331_1p1_baseband_core), 2); |
| 50 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 51 | ar9331_1p1_baseband_postamble, |
| 52 | ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5); |
| 53 | |
| 54 | /* radio */ |
| 55 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); |
| 56 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 57 | ar9331_1p1_radio_core, |
| 58 | ARRAY_SIZE(ar9331_1p1_radio_core), 2); |
| 59 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0); |
| 60 | |
| 61 | /* soc */ |
| 62 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 63 | ar9331_1p1_soc_preamble, |
| 64 | ARRAY_SIZE(ar9331_1p1_soc_preamble), 2); |
| 65 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); |
| 66 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 67 | ar9331_1p1_soc_postamble, |
| 68 | ARRAY_SIZE(ar9331_1p1_soc_postamble), 2); |
| 69 | |
| 70 | /* rx/tx gain */ |
| 71 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 72 | ar9331_common_rx_gain_1p1, |
| 73 | ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2); |
| 74 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 75 | ar9331_modes_lowest_ob_db_tx_gain_1p1, |
| 76 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1), |
| 77 | 5); |
| 78 | |
| 79 | /* additional clock settings */ |
| 80 | if (ah->is_clk_25mhz) |
| 81 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 82 | ar9331_1p1_xtal_25M, |
| 83 | ARRAY_SIZE(ar9331_1p1_xtal_25M), 2); |
| 84 | else |
| 85 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 86 | ar9331_1p1_xtal_40M, |
| 87 | ARRAY_SIZE(ar9331_1p1_xtal_40M), 2); |
| 88 | } else if (AR_SREV_9330_12(ah)) { |
| 89 | /* mac */ |
| 90 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| 91 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 92 | ar9331_1p2_mac_core, |
| 93 | ARRAY_SIZE(ar9331_1p2_mac_core), 2); |
| 94 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 95 | ar9331_1p2_mac_postamble, |
| 96 | ARRAY_SIZE(ar9331_1p2_mac_postamble), 5); |
| 97 | |
| 98 | /* bb */ |
| 99 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); |
| 100 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 101 | ar9331_1p2_baseband_core, |
| 102 | ARRAY_SIZE(ar9331_1p2_baseband_core), 2); |
| 103 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 104 | ar9331_1p2_baseband_postamble, |
| 105 | ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5); |
| 106 | |
| 107 | /* radio */ |
| 108 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); |
| 109 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 110 | ar9331_1p2_radio_core, |
| 111 | ARRAY_SIZE(ar9331_1p2_radio_core), 2); |
| 112 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0); |
| 113 | |
| 114 | /* soc */ |
| 115 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 116 | ar9331_1p2_soc_preamble, |
| 117 | ARRAY_SIZE(ar9331_1p2_soc_preamble), 2); |
| 118 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); |
| 119 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 120 | ar9331_1p2_soc_postamble, |
| 121 | ARRAY_SIZE(ar9331_1p2_soc_postamble), 2); |
| 122 | |
| 123 | /* rx/tx gain */ |
| 124 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 125 | ar9331_common_rx_gain_1p2, |
| 126 | ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2); |
| 127 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 128 | ar9331_modes_lowest_ob_db_tx_gain_1p2, |
| 129 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2), |
| 130 | 5); |
| 131 | |
| 132 | /* additional clock settings */ |
| 133 | if (ah->is_clk_25mhz) |
| 134 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 135 | ar9331_1p2_xtal_25M, |
| 136 | ARRAY_SIZE(ar9331_1p2_xtal_25M), 2); |
| 137 | else |
| 138 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 139 | ar9331_1p2_xtal_40M, |
| 140 | ARRAY_SIZE(ar9331_1p2_xtal_40M), 2); |
| 141 | } else if (AR_SREV_9340(ah)) { |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 142 | /* mac */ |
| 143 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| 144 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 145 | ar9340_1p0_mac_core, |
| 146 | ARRAY_SIZE(ar9340_1p0_mac_core), 2); |
| 147 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 148 | ar9340_1p0_mac_postamble, |
| 149 | ARRAY_SIZE(ar9340_1p0_mac_postamble), 5); |
| 150 | |
| 151 | /* bb */ |
| 152 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); |
| 153 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 154 | ar9340_1p0_baseband_core, |
| 155 | ARRAY_SIZE(ar9340_1p0_baseband_core), 2); |
| 156 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 157 | ar9340_1p0_baseband_postamble, |
| 158 | ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5); |
| 159 | |
| 160 | /* radio */ |
| 161 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); |
| 162 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 163 | ar9340_1p0_radio_core, |
| 164 | ARRAY_SIZE(ar9340_1p0_radio_core), 2); |
| 165 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 166 | ar9340_1p0_radio_postamble, |
| 167 | ARRAY_SIZE(ar9340_1p0_radio_postamble), 5); |
| 168 | |
| 169 | /* soc */ |
| 170 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 171 | ar9340_1p0_soc_preamble, |
| 172 | ARRAY_SIZE(ar9340_1p0_soc_preamble), 2); |
| 173 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); |
| 174 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 175 | ar9340_1p0_soc_postamble, |
| 176 | ARRAY_SIZE(ar9340_1p0_soc_postamble), 5); |
| 177 | |
| 178 | /* rx/tx gain */ |
| 179 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 180 | ar9340Common_wo_xlna_rx_gain_table_1p0, |
| 181 | ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), |
| 182 | 5); |
| 183 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 184 | ar9340Modes_high_ob_db_tx_gain_table_1p0, |
| 185 | ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0), |
| 186 | 5); |
| 187 | |
| 188 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 189 | ar9340Modes_fast_clock_1p0, |
| 190 | ARRAY_SIZE(ar9340Modes_fast_clock_1p0), |
| 191 | 3); |
| 192 | |
| 193 | INIT_INI_ARRAY(&ah->iniModesAdditional_40M, |
| 194 | ar9340_1p0_radio_core_40M, |
| 195 | ARRAY_SIZE(ar9340_1p0_radio_core_40M), |
| 196 | 2); |
| 197 | } else if (AR_SREV_9485_11(ah)) { |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 198 | /* mac */ |
| 199 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| 200 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 201 | ar9485_1_1_mac_core, |
| 202 | ARRAY_SIZE(ar9485_1_1_mac_core), 2); |
| 203 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 204 | ar9485_1_1_mac_postamble, |
| 205 | ARRAY_SIZE(ar9485_1_1_mac_postamble), 5); |
| 206 | |
| 207 | /* bb */ |
| 208 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1, |
| 209 | ARRAY_SIZE(ar9485_1_1), 2); |
| 210 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 211 | ar9485_1_1_baseband_core, |
| 212 | ARRAY_SIZE(ar9485_1_1_baseband_core), 2); |
| 213 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 214 | ar9485_1_1_baseband_postamble, |
| 215 | ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5); |
| 216 | |
| 217 | /* radio */ |
| 218 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); |
| 219 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 220 | ar9485_1_1_radio_core, |
| 221 | ARRAY_SIZE(ar9485_1_1_radio_core), 2); |
| 222 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 223 | ar9485_1_1_radio_postamble, |
| 224 | ARRAY_SIZE(ar9485_1_1_radio_postamble), 2); |
| 225 | |
| 226 | /* soc */ |
| 227 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 228 | ar9485_1_1_soc_preamble, |
| 229 | ARRAY_SIZE(ar9485_1_1_soc_preamble), 2); |
| 230 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); |
| 231 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0); |
| 232 | |
| 233 | /* rx/tx gain */ |
| 234 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Vasanthakumar Thiagarajan | 832fd35 | 2011-04-01 15:32:16 +0530 | [diff] [blame] | 235 | ar9485Common_wo_xlna_rx_gain_1_1, |
| 236 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 237 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 238 | ar9485_modes_lowest_ob_db_tx_gain_1_1, |
| 239 | ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), |
| 240 | 5); |
| 241 | |
| 242 | /* Load PCIE SERDES settings from INI */ |
| 243 | |
| 244 | /* Awake Setting */ |
| 245 | |
| 246 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Vivek Natarajan | 06fed57 | 2011-02-25 17:31:01 +0530 | [diff] [blame] | 247 | ar9485_1_1_pcie_phy_clkreq_disable_L1, |
| 248 | ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 249 | 2); |
| 250 | |
| 251 | /* Sleep Setting */ |
| 252 | |
| 253 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Vivek Natarajan | 06fed57 | 2011-02-25 17:31:01 +0530 | [diff] [blame] | 254 | ar9485_1_1_pcie_phy_clkreq_disable_L1, |
| 255 | ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 256 | 2); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 257 | } else if (AR_SREV_9580(ah)) { |
| 258 | /* mac */ |
| 259 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| 260 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 261 | ar9580_1p0_mac_core, |
| 262 | ARRAY_SIZE(ar9580_1p0_mac_core), 2); |
| 263 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 264 | ar9580_1p0_mac_postamble, |
| 265 | ARRAY_SIZE(ar9580_1p0_mac_postamble), 5); |
| 266 | |
| 267 | /* bb */ |
| 268 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); |
| 269 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 270 | ar9580_1p0_baseband_core, |
| 271 | ARRAY_SIZE(ar9580_1p0_baseband_core), 2); |
| 272 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 273 | ar9580_1p0_baseband_postamble, |
| 274 | ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5); |
| 275 | |
| 276 | /* radio */ |
| 277 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); |
| 278 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 279 | ar9580_1p0_radio_core, |
| 280 | ARRAY_SIZE(ar9580_1p0_radio_core), 2); |
| 281 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 282 | ar9580_1p0_radio_postamble, |
| 283 | ARRAY_SIZE(ar9580_1p0_radio_postamble), 5); |
| 284 | |
| 285 | /* soc */ |
| 286 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 287 | ar9580_1p0_soc_preamble, |
| 288 | ARRAY_SIZE(ar9580_1p0_soc_preamble), 2); |
| 289 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); |
| 290 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 291 | ar9580_1p0_soc_postamble, |
| 292 | ARRAY_SIZE(ar9580_1p0_soc_postamble), 5); |
| 293 | |
| 294 | /* rx/tx gain */ |
| 295 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 296 | ar9580_1p0_rx_gain_table, |
| 297 | ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2); |
| 298 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 299 | ar9580_1p0_low_ob_db_tx_gain_table, |
| 300 | ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table), |
| 301 | 5); |
| 302 | |
| 303 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 304 | ar9580_1p0_modes_fast_clock, |
| 305 | ARRAY_SIZE(ar9580_1p0_modes_fast_clock), |
| 306 | 3); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 307 | } else { |
| 308 | /* mac */ |
| 309 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); |
| 310 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 311 | ar9300_2p2_mac_core, |
| 312 | ARRAY_SIZE(ar9300_2p2_mac_core), 2); |
| 313 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 314 | ar9300_2p2_mac_postamble, |
| 315 | ARRAY_SIZE(ar9300_2p2_mac_postamble), 5); |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 316 | |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 317 | /* bb */ |
| 318 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); |
| 319 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 320 | ar9300_2p2_baseband_core, |
| 321 | ARRAY_SIZE(ar9300_2p2_baseband_core), 2); |
| 322 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 323 | ar9300_2p2_baseband_postamble, |
| 324 | ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5); |
| 325 | |
| 326 | /* radio */ |
| 327 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); |
| 328 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 329 | ar9300_2p2_radio_core, |
| 330 | ARRAY_SIZE(ar9300_2p2_radio_core), 2); |
| 331 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 332 | ar9300_2p2_radio_postamble, |
| 333 | ARRAY_SIZE(ar9300_2p2_radio_postamble), 5); |
| 334 | |
| 335 | /* soc */ |
| 336 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 337 | ar9300_2p2_soc_preamble, |
| 338 | ARRAY_SIZE(ar9300_2p2_soc_preamble), 2); |
| 339 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); |
| 340 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 341 | ar9300_2p2_soc_postamble, |
| 342 | ARRAY_SIZE(ar9300_2p2_soc_postamble), 5); |
| 343 | |
| 344 | /* rx/tx gain */ |
| 345 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 346 | ar9300Common_rx_gain_table_2p2, |
| 347 | ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2); |
| 348 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 349 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2, |
| 350 | ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), |
| 351 | 5); |
| 352 | |
| 353 | /* Load PCIE SERDES settings from INI */ |
| 354 | |
| 355 | /* Awake Setting */ |
| 356 | |
| 357 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 358 | ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, |
| 359 | ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), |
| 360 | 2); |
| 361 | |
| 362 | /* Sleep Setting */ |
| 363 | |
| 364 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Luis R. Rodriguez | 58c5296 | 2011-01-13 18:19:29 -0800 | [diff] [blame] | 365 | ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, |
| 366 | ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 367 | 2); |
| 368 | |
| 369 | /* Fast clock modal settings */ |
| 370 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
| 371 | ar9300Modes_fast_clock_2p2, |
| 372 | ARRAY_SIZE(ar9300Modes_fast_clock_2p2), |
| 373 | 3); |
| 374 | } |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 375 | } |
| 376 | |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 377 | static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) |
| 378 | { |
| 379 | if (AR_SREV_9330_12(ah)) |
| 380 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 381 | ar9331_modes_lowest_ob_db_tx_gain_1p2, |
| 382 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2), |
| 383 | 5); |
| 384 | else if (AR_SREV_9330_11(ah)) |
| 385 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 386 | ar9331_modes_lowest_ob_db_tx_gain_1p1, |
| 387 | ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1), |
| 388 | 5); |
| 389 | else if (AR_SREV_9340(ah)) |
| 390 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 391 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, |
| 392 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), |
| 393 | 5); |
| 394 | else if (AR_SREV_9485_11(ah)) |
| 395 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 396 | ar9485_modes_lowest_ob_db_tx_gain_1_1, |
| 397 | ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), |
| 398 | 5); |
| 399 | else if (AR_SREV_9580(ah)) |
| 400 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 401 | ar9580_1p0_lowest_ob_db_tx_gain_table, |
| 402 | ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table), |
| 403 | 5); |
| 404 | else |
| 405 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 406 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2, |
| 407 | ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), |
| 408 | 5); |
| 409 | } |
| 410 | |
| 411 | static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) |
| 412 | { |
| 413 | if (AR_SREV_9330_12(ah)) |
| 414 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 415 | ar9331_modes_high_ob_db_tx_gain_1p2, |
| 416 | ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2), |
| 417 | 5); |
| 418 | else if (AR_SREV_9330_11(ah)) |
| 419 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 420 | ar9331_modes_high_ob_db_tx_gain_1p1, |
| 421 | ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1), |
| 422 | 5); |
| 423 | else if (AR_SREV_9340(ah)) |
| 424 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 425 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, |
| 426 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), |
| 427 | 5); |
| 428 | else if (AR_SREV_9485_11(ah)) |
| 429 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 430 | ar9485Modes_high_ob_db_tx_gain_1_1, |
| 431 | ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1), |
| 432 | 5); |
| 433 | else if (AR_SREV_9580(ah)) |
| 434 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 435 | ar9580_1p0_high_ob_db_tx_gain_table, |
| 436 | ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), |
| 437 | 5); |
| 438 | else |
| 439 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 440 | ar9300Modes_high_ob_db_tx_gain_table_2p2, |
| 441 | ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2), |
| 442 | 5); |
| 443 | } |
| 444 | |
| 445 | static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) |
| 446 | { |
| 447 | if (AR_SREV_9330_12(ah)) |
| 448 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 449 | ar9331_modes_low_ob_db_tx_gain_1p2, |
| 450 | ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2), |
| 451 | 5); |
| 452 | else if (AR_SREV_9330_11(ah)) |
| 453 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 454 | ar9331_modes_low_ob_db_tx_gain_1p1, |
| 455 | ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1), |
| 456 | 5); |
| 457 | else if (AR_SREV_9340(ah)) |
| 458 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 459 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, |
| 460 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), |
| 461 | 5); |
| 462 | else if (AR_SREV_9485_11(ah)) |
| 463 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 464 | ar9485Modes_low_ob_db_tx_gain_1_1, |
| 465 | ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1), |
| 466 | 5); |
| 467 | else if (AR_SREV_9580(ah)) |
| 468 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 469 | ar9580_1p0_low_ob_db_tx_gain_table, |
| 470 | ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table), |
| 471 | 5); |
| 472 | else |
| 473 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 474 | ar9300Modes_low_ob_db_tx_gain_table_2p2, |
| 475 | ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2), |
| 476 | 5); |
| 477 | } |
| 478 | |
| 479 | static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) |
| 480 | { |
| 481 | if (AR_SREV_9330_12(ah)) |
| 482 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 483 | ar9331_modes_high_power_tx_gain_1p2, |
| 484 | ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2), |
| 485 | 5); |
| 486 | else if (AR_SREV_9330_11(ah)) |
| 487 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 488 | ar9331_modes_high_power_tx_gain_1p1, |
| 489 | ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1), |
| 490 | 5); |
| 491 | else if (AR_SREV_9340(ah)) |
| 492 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 493 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0, |
| 494 | ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), |
| 495 | 5); |
| 496 | else if (AR_SREV_9485_11(ah)) |
| 497 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 498 | ar9485Modes_high_power_tx_gain_1_1, |
| 499 | ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1), |
| 500 | 5); |
| 501 | else if (AR_SREV_9580(ah)) |
| 502 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 503 | ar9580_1p0_high_power_tx_gain_table, |
| 504 | ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table), |
| 505 | 5); |
| 506 | else |
| 507 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 508 | ar9300Modes_high_power_tx_gain_table_2p2, |
| 509 | ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2), |
| 510 | 5); |
| 511 | } |
| 512 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 513 | static void ar9003_tx_gain_table_apply(struct ath_hw *ah) |
| 514 | { |
| 515 | switch (ar9003_hw_get_tx_gain_idx(ah)) { |
| 516 | case 0: |
| 517 | default: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 518 | ar9003_tx_gain_table_mode0(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 519 | break; |
| 520 | case 1: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 521 | ar9003_tx_gain_table_mode1(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 522 | break; |
| 523 | case 2: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 524 | ar9003_tx_gain_table_mode2(ah); |
Vasanthakumar Thiagarajan | ff48ba4 | 2010-12-06 04:27:38 -0800 | [diff] [blame] | 525 | break; |
| 526 | case 3: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 527 | ar9003_tx_gain_table_mode3(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 528 | break; |
| 529 | } |
| 530 | } |
| 531 | |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 532 | static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) |
| 533 | { |
| 534 | if (AR_SREV_9330_12(ah)) |
| 535 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 536 | ar9331_common_rx_gain_1p2, |
| 537 | ARRAY_SIZE(ar9331_common_rx_gain_1p2), |
| 538 | 2); |
| 539 | else if (AR_SREV_9330_11(ah)) |
| 540 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 541 | ar9331_common_rx_gain_1p1, |
| 542 | ARRAY_SIZE(ar9331_common_rx_gain_1p1), |
| 543 | 2); |
| 544 | else if (AR_SREV_9340(ah)) |
| 545 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 546 | ar9340Common_rx_gain_table_1p0, |
| 547 | ARRAY_SIZE(ar9340Common_rx_gain_table_1p0), |
| 548 | 2); |
| 549 | else if (AR_SREV_9485_11(ah)) |
| 550 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 551 | ar9485Common_wo_xlna_rx_gain_1_1, |
| 552 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), |
| 553 | 2); |
| 554 | else if (AR_SREV_9580(ah)) |
| 555 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 556 | ar9580_1p0_rx_gain_table, |
| 557 | ARRAY_SIZE(ar9580_1p0_rx_gain_table), |
| 558 | 2); |
| 559 | else |
| 560 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 561 | ar9300Common_rx_gain_table_2p2, |
| 562 | ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), |
| 563 | 2); |
| 564 | } |
| 565 | |
| 566 | static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) |
| 567 | { |
| 568 | if (AR_SREV_9330_12(ah)) |
| 569 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 570 | ar9331_common_wo_xlna_rx_gain_1p2, |
| 571 | ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2), |
| 572 | 2); |
| 573 | else if (AR_SREV_9330_11(ah)) |
| 574 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 575 | ar9331_common_wo_xlna_rx_gain_1p1, |
| 576 | ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1), |
| 577 | 2); |
| 578 | else if (AR_SREV_9340(ah)) |
| 579 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 580 | ar9340Common_wo_xlna_rx_gain_table_1p0, |
| 581 | ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), |
| 582 | 2); |
| 583 | else if (AR_SREV_9485_11(ah)) |
| 584 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 585 | ar9485Common_wo_xlna_rx_gain_1_1, |
| 586 | ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), |
| 587 | 2); |
| 588 | else if (AR_SREV_9580(ah)) |
| 589 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 590 | ar9580_1p0_wo_xlna_rx_gain_table, |
| 591 | ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table), |
| 592 | 2); |
| 593 | else |
| 594 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 595 | ar9300Common_wo_xlna_rx_gain_table_2p2, |
| 596 | ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2), |
| 597 | 2); |
| 598 | } |
| 599 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 600 | static void ar9003_rx_gain_table_apply(struct ath_hw *ah) |
| 601 | { |
| 602 | switch (ar9003_hw_get_rx_gain_idx(ah)) { |
| 603 | case 0: |
| 604 | default: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 605 | ar9003_rx_gain_table_mode0(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 606 | break; |
| 607 | case 1: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame^] | 608 | ar9003_rx_gain_table_mode1(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 609 | break; |
| 610 | } |
| 611 | } |
| 612 | |
| 613 | /* set gain table pointers according to values read from the eeprom */ |
| 614 | static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 615 | { |
| 616 | ar9003_tx_gain_table_apply(ah); |
| 617 | ar9003_rx_gain_table_apply(ah); |
| 618 | } |
| 619 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 620 | /* |
| 621 | * Helper for ASPM support. |
| 622 | * |
| 623 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 624 | * This power saving option must be enabled through the SerDes. |
| 625 | * |
| 626 | * Programming the SerDes must go through the same 288 bit serial shift |
| 627 | * register as the other analog registers. Hence the 9 writes. |
| 628 | */ |
| 629 | static void ar9003_hw_configpcipowersave(struct ath_hw *ah, |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 630 | bool power_off) |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 631 | { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 632 | /* Nothing to do on restore for 11N */ |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 633 | if (!power_off /* !restore */) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 634 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 635 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
| 636 | |
| 637 | /* Several PCIe massages to ensure proper behaviour */ |
| 638 | if (ah->config.pcie_waen) |
| 639 | REG_WRITE(ah, AR_WA, ah->config.pcie_waen); |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 640 | else |
| 641 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 642 | } |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 643 | |
| 644 | /* |
| 645 | * Configire PCIE after Ini init. SERDES values now come from ini file |
| 646 | * This enables PCIe low power mode. |
| 647 | */ |
Luis R. Rodriguez | 6a0ec30 | 2010-06-21 18:38:49 -0400 | [diff] [blame] | 648 | if (ah->config.pcieSerDesWrite) { |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 649 | unsigned int i; |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 650 | struct ar5416IniArray *array; |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 651 | |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 652 | array = power_off ? &ah->iniPcieSerdes : |
| 653 | &ah->iniPcieSerdesLowPower; |
| 654 | |
| 655 | for (i = 0; i < array->ia_rows; i++) { |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 656 | REG_WRITE(ah, |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 657 | INI_RA(array, i, 0), |
| 658 | INI_RA(array, i, 1)); |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 659 | } |
| 660 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | /* Sets up the AR9003 hardware familiy callbacks */ |
| 664 | void ar9003_hw_attach_ops(struct ath_hw *ah) |
| 665 | { |
| 666 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 667 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 668 | |
| 669 | priv_ops->init_mode_regs = ar9003_hw_init_mode_regs; |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 670 | priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 671 | |
| 672 | ops->config_pci_powersave = ar9003_hw_configpcipowersave; |
| 673 | |
| 674 | ar9003_hw_attach_phy_ops(ah); |
| 675 | ar9003_hw_attach_calib_ops(ah); |
| 676 | ar9003_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 677 | } |