blob: cfb5f44b2d43d895c2a16b99775f88d77231a486 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 *
4 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5 * Pilo Chambert <pilo.c@wanadoo.fr>
6 *
7 * Thanks to : Anders Torger <torger@ludd.luth.se>,
8 * Henk Hesselink <henk@anda.nl>
9 * for writing the digi96-driver
10 * and RME for all informations.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * ****************************************************************************
28 *
29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
30 *
31 * Identical soundcards by Sek'd were labeled:
32 * RME Digi 32 = Sek'd Prodif 32
33 * RME Digi 32 Pro = Sek'd Prodif 96
34 * RME Digi 32/8 = Sek'd Prodif Gold
35 *
36 * ****************************************************************************
37 *
38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
39 *
40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41 * in this mode. Rec data and play data are using the same buffer therefore. At
42 * first you have got the playing bits in the buffer and then (after playing
43 * them) they were overwitten by the captured sound of the CS8412/14. Both
44 * modes (play/record) are running harmonically hand in hand in the same buffer
45 * and you have only one start bit plus one interrupt bit to control this
46 * paired action.
47 * This is opposite to the latter rme96 where playing and capturing is totally
48 * separated and so their full duplex mode is supported by alsa (using two
49 * start bits and two interrupts for two different buffers).
50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
52 * able to solve it. Are you motivated enough to solve this problem now? Your
53 * patch would be welcome!
54 *
55 * ****************************************************************************
56 *
57 * "The story after the long seeking" -- tiwai
58 *
59 * Ok, the situation regarding the full duplex is now improved a bit.
60 * In the fullduplex mode (given by the module parameter), the hardware buffer
61 * is split to halves for read and write directions at the DMA pointer.
62 * That is, the half above the current DMA pointer is used for write, and
63 * the half below is used for read. To mangle this strange behavior, an
64 * software intermediate buffer is introduced. This is, of course, not good
65 * from the viewpoint of the data transfer efficiency. However, this allows
66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67 *
68 * ****************************************************************************
69 */
70
71
72#include <sound/driver.h>
73#include <linux/delay.h>
74#include <linux/init.h>
75#include <linux/interrupt.h>
76#include <linux/pci.h>
77#include <linux/slab.h>
78#include <linux/moduleparam.h>
79
80#include <sound/core.h>
81#include <sound/info.h>
82#include <sound/control.h>
83#include <sound/pcm.h>
84#include <sound/pcm_params.h>
85#include <sound/pcm-indirect.h>
86#include <sound/asoundef.h>
87#include <sound/initval.h>
88
89#include <asm/io.h>
90
91static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
92static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
93static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
94static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
95
96module_param_array(index, int, NULL, 0444);
97MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
98module_param_array(id, charp, NULL, 0444);
99MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
100module_param_array(enable, bool, NULL, 0444);
101MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
102module_param_array(fullduplex, bool, NULL, 0444);
103MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
104MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
105MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
106MODULE_LICENSE("GPL");
107MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
108
109/* Defines for RME Digi32 series */
110#define RME32_SPDIF_NCHANNELS 2
111
112/* Playback and capture buffer size */
113#define RME32_BUFFER_SIZE 0x20000
114
115/* IO area size */
116#define RME32_IO_SIZE 0x30000
117
118/* IO area offsets */
119#define RME32_IO_DATA_BUFFER 0x0
120#define RME32_IO_CONTROL_REGISTER 0x20000
121#define RME32_IO_GET_POS 0x20000
122#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
123#define RME32_IO_RESET_POS 0x20100
124
125/* Write control register bits */
126#define RME32_WCR_START (1 << 0) /* startbit */
127#define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
128 Setting the whole card to mono
129 doesn't seem to be very useful.
130 A software-solution can handle
131 full-duplex with one direction in
132 stereo and the other way in mono.
133 So, the hardware should work all
134 the time in stereo! */
135#define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
136#define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
137#define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
138#define RME32_WCR_FREQ_1 (1 << 5)
139#define RME32_WCR_INP_0 (1 << 6) /* input switch */
140#define RME32_WCR_INP_1 (1 << 7)
141#define RME32_WCR_RESET (1 << 8) /* Reset address */
142#define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
143#define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
144#define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
145#define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
146#define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
147#define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
148#define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
149
150#define RME32_WCR_BITPOS_FREQ_0 4
151#define RME32_WCR_BITPOS_FREQ_1 5
152#define RME32_WCR_BITPOS_INP_0 6
153#define RME32_WCR_BITPOS_INP_1 7
154
155/* Read control register bits */
156#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
157#define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
158#define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
159#define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
160#define RME32_RCR_FREQ_1 (1 << 28)
161#define RME32_RCR_FREQ_2 (1 << 29)
162#define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
163#define RME32_RCR_IRQ (1 << 31) /* interrupt */
164
165#define RME32_RCR_BITPOS_F0 27
166#define RME32_RCR_BITPOS_F1 28
167#define RME32_RCR_BITPOS_F2 29
168
169/* Input types */
170#define RME32_INPUT_OPTICAL 0
171#define RME32_INPUT_COAXIAL 1
172#define RME32_INPUT_INTERNAL 2
173#define RME32_INPUT_XLR 3
174
175/* Clock modes */
176#define RME32_CLOCKMODE_SLAVE 0
177#define RME32_CLOCKMODE_MASTER_32 1
178#define RME32_CLOCKMODE_MASTER_44 2
179#define RME32_CLOCKMODE_MASTER_48 3
180
181/* Block sizes in bytes */
182#define RME32_BLOCK_SIZE 8192
183
184/* Software intermediate buffer (max) size */
185#define RME32_MID_BUFFER_SIZE (1024*1024)
186
187/* Hardware revisions */
188#define RME32_32_REVISION 192
189#define RME32_328_REVISION_OLD 100
190#define RME32_328_REVISION_NEW 101
191#define RME32_PRO_REVISION_WITH_8412 192
192#define RME32_PRO_REVISION_WITH_8414 150
193
194
195/* PCI vendor/device ID's */
196#ifndef PCI_VENDOR_ID_XILINX_RME
197# define PCI_VENDOR_ID_XILINX_RME 0xea60
198#endif
199#ifndef PCI_DEVICE_ID_DIGI32
200# define PCI_DEVICE_ID_DIGI32 0x9896
201#endif
202#ifndef PCI_DEVICE_ID_DIGI32_PRO
203# define PCI_DEVICE_ID_DIGI32_PRO 0x9897
204#endif
205#ifndef PCI_DEVICE_ID_DIGI32_8
206# define PCI_DEVICE_ID_DIGI32_8 0x9898
207#endif
208
209typedef struct snd_rme32 {
210 spinlock_t lock;
211 int irq;
212 unsigned long port;
213 void __iomem *iobase;
214
215 u32 wcreg; /* cached write control register value */
216 u32 wcreg_spdif; /* S/PDIF setup */
217 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
218 u32 rcreg; /* cached read control register value */
219
220 u8 rev; /* card revision number */
221
222 snd_pcm_substream_t *playback_substream;
223 snd_pcm_substream_t *capture_substream;
224
225 int playback_frlog; /* log2 of framesize */
226 int capture_frlog;
227
228 size_t playback_periodsize; /* in bytes, zero if not used */
229 size_t capture_periodsize; /* in bytes, zero if not used */
230
231 unsigned int fullduplex_mode;
232 int running;
233
234 snd_pcm_indirect_t playback_pcm;
235 snd_pcm_indirect_t capture_pcm;
236
237 snd_card_t *card;
238 snd_pcm_t *spdif_pcm;
239 snd_pcm_t *adat_pcm;
240 struct pci_dev *pci;
241 snd_kcontrol_t *spdif_ctl;
242} rme32_t;
243
244static struct pci_device_id snd_rme32_ids[] = {
245 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
247 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_8,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
249 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_PRO,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
251 {0,}
252};
253
254MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
255
256#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
257#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
258
259static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream);
260
261static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream);
262
263static int snd_rme32_pcm_trigger(snd_pcm_substream_t * substream, int cmd);
264
265static void snd_rme32_proc_init(rme32_t * rme32);
266
267static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32);
268
269static inline unsigned int snd_rme32_pcm_byteptr(rme32_t * rme32)
270{
271 return (readl(rme32->iobase + RME32_IO_GET_POS)
272 & RME32_RCR_AUDIO_ADDR_MASK);
273}
274
275static int snd_rme32_ratecode(int rate)
276{
277 switch (rate) {
278 case 32000: return SNDRV_PCM_RATE_32000;
279 case 44100: return SNDRV_PCM_RATE_44100;
280 case 48000: return SNDRV_PCM_RATE_48000;
281 case 64000: return SNDRV_PCM_RATE_64000;
282 case 88200: return SNDRV_PCM_RATE_88200;
283 case 96000: return SNDRV_PCM_RATE_96000;
284 }
285 return 0;
286}
287
288/* silence callback for halfduplex mode */
289static int snd_rme32_playback_silence(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
290 snd_pcm_uframes_t pos,
291 snd_pcm_uframes_t count)
292{
293 rme32_t *rme32 = snd_pcm_substream_chip(substream);
294 count <<= rme32->playback_frlog;
295 pos <<= rme32->playback_frlog;
296 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
297 return 0;
298}
299
300/* copy callback for halfduplex mode */
301static int snd_rme32_playback_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
302 snd_pcm_uframes_t pos,
303 void __user *src, snd_pcm_uframes_t count)
304{
305 rme32_t *rme32 = snd_pcm_substream_chip(substream);
306 count <<= rme32->playback_frlog;
307 pos <<= rme32->playback_frlog;
308 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
309 src, count))
310 return -EFAULT;
311 return 0;
312}
313
314/* copy callback for halfduplex mode */
315static int snd_rme32_capture_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
316 snd_pcm_uframes_t pos,
317 void __user *dst, snd_pcm_uframes_t count)
318{
319 rme32_t *rme32 = snd_pcm_substream_chip(substream);
320 count <<= rme32->capture_frlog;
321 pos <<= rme32->capture_frlog;
322 if (copy_to_user_fromio(dst,
323 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
324 count))
325 return -EFAULT;
326 return 0;
327}
328
329/*
330 * SPDIF I/O capabilites (half-duplex mode)
331 */
332static snd_pcm_hardware_t snd_rme32_spdif_info = {
333 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
334 SNDRV_PCM_INFO_MMAP_VALID |
335 SNDRV_PCM_INFO_INTERLEAVED |
336 SNDRV_PCM_INFO_PAUSE |
337 SNDRV_PCM_INFO_SYNC_START),
338 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
339 SNDRV_PCM_FMTBIT_S32_LE),
340 .rates = (SNDRV_PCM_RATE_32000 |
341 SNDRV_PCM_RATE_44100 |
342 SNDRV_PCM_RATE_48000),
343 .rate_min = 32000,
344 .rate_max = 48000,
345 .channels_min = 2,
346 .channels_max = 2,
347 .buffer_bytes_max = RME32_BUFFER_SIZE,
348 .period_bytes_min = RME32_BLOCK_SIZE,
349 .period_bytes_max = RME32_BLOCK_SIZE,
350 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
351 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
352 .fifo_size = 0,
353};
354
355/*
356 * ADAT I/O capabilites (half-duplex mode)
357 */
358static snd_pcm_hardware_t snd_rme32_adat_info =
359{
360 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
361 SNDRV_PCM_INFO_MMAP_VALID |
362 SNDRV_PCM_INFO_INTERLEAVED |
363 SNDRV_PCM_INFO_PAUSE |
364 SNDRV_PCM_INFO_SYNC_START),
365 .formats= SNDRV_PCM_FMTBIT_S16_LE,
366 .rates = (SNDRV_PCM_RATE_44100 |
367 SNDRV_PCM_RATE_48000),
368 .rate_min = 44100,
369 .rate_max = 48000,
370 .channels_min = 8,
371 .channels_max = 8,
372 .buffer_bytes_max = RME32_BUFFER_SIZE,
373 .period_bytes_min = RME32_BLOCK_SIZE,
374 .period_bytes_max = RME32_BLOCK_SIZE,
375 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
376 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
377 .fifo_size = 0,
378};
379
380/*
381 * SPDIF I/O capabilites (full-duplex mode)
382 */
383static snd_pcm_hardware_t snd_rme32_spdif_fd_info = {
384 .info = (SNDRV_PCM_INFO_MMAP |
385 SNDRV_PCM_INFO_MMAP_VALID |
386 SNDRV_PCM_INFO_INTERLEAVED |
387 SNDRV_PCM_INFO_PAUSE |
388 SNDRV_PCM_INFO_SYNC_START),
389 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
390 SNDRV_PCM_FMTBIT_S32_LE),
391 .rates = (SNDRV_PCM_RATE_32000 |
392 SNDRV_PCM_RATE_44100 |
393 SNDRV_PCM_RATE_48000),
394 .rate_min = 32000,
395 .rate_max = 48000,
396 .channels_min = 2,
397 .channels_max = 2,
398 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
399 .period_bytes_min = RME32_BLOCK_SIZE,
400 .period_bytes_max = RME32_BLOCK_SIZE,
401 .periods_min = 2,
402 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
403 .fifo_size = 0,
404};
405
406/*
407 * ADAT I/O capabilites (full-duplex mode)
408 */
409static snd_pcm_hardware_t snd_rme32_adat_fd_info =
410{
411 .info = (SNDRV_PCM_INFO_MMAP |
412 SNDRV_PCM_INFO_MMAP_VALID |
413 SNDRV_PCM_INFO_INTERLEAVED |
414 SNDRV_PCM_INFO_PAUSE |
415 SNDRV_PCM_INFO_SYNC_START),
416 .formats= SNDRV_PCM_FMTBIT_S16_LE,
417 .rates = (SNDRV_PCM_RATE_44100 |
418 SNDRV_PCM_RATE_48000),
419 .rate_min = 44100,
420 .rate_max = 48000,
421 .channels_min = 8,
422 .channels_max = 8,
423 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
424 .period_bytes_min = RME32_BLOCK_SIZE,
425 .period_bytes_max = RME32_BLOCK_SIZE,
426 .periods_min = 2,
427 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
428 .fifo_size = 0,
429};
430
431static void snd_rme32_reset_dac(rme32_t *rme32)
432{
433 writel(rme32->wcreg | RME32_WCR_PD,
434 rme32->iobase + RME32_IO_CONTROL_REGISTER);
435 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
436}
437
438static int snd_rme32_playback_getrate(rme32_t * rme32)
439{
440 int rate;
441
442 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
443 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
444 switch (rate) {
445 case 1:
446 rate = 32000;
447 break;
448 case 2:
449 rate = 44100;
450 break;
451 case 3:
452 rate = 48000;
453 break;
454 default:
455 return -1;
456 }
457 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
458}
459
460static int snd_rme32_capture_getrate(rme32_t * rme32, int *is_adat)
461{
462 int n;
463
464 *is_adat = 0;
465 if (rme32->rcreg & RME32_RCR_LOCK) {
466 /* ADAT rate */
467 *is_adat = 1;
468 }
469 if (rme32->rcreg & RME32_RCR_ERF) {
470 return -1;
471 }
472
473 /* S/PDIF rate */
474 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
475 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
476 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
477
478 if (RME32_PRO_WITH_8414(rme32))
479 switch (n) { /* supporting the CS8414 */
480 case 0:
481 case 1:
482 case 2:
483 return -1;
484 case 3:
485 return 96000;
486 case 4:
487 return 88200;
488 case 5:
489 return 48000;
490 case 6:
491 return 44100;
492 case 7:
493 return 32000;
494 default:
495 return -1;
496 break;
497 }
498 else
499 switch (n) { /* supporting the CS8412 */
500 case 0:
501 return -1;
502 case 1:
503 return 48000;
504 case 2:
505 return 44100;
506 case 3:
507 return 32000;
508 case 4:
509 return 48000;
510 case 5:
511 return 44100;
512 case 6:
513 return 44056;
514 case 7:
515 return 32000;
516 default:
517 break;
518 }
519 return -1;
520}
521
522static int snd_rme32_playback_setrate(rme32_t * rme32, int rate)
523{
524 int ds;
525
526 ds = rme32->wcreg & RME32_WCR_DS_BM;
527 switch (rate) {
528 case 32000:
529 rme32->wcreg &= ~RME32_WCR_DS_BM;
530 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
531 ~RME32_WCR_FREQ_1;
532 break;
533 case 44100:
534 rme32->wcreg &= ~RME32_WCR_DS_BM;
535 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
536 ~RME32_WCR_FREQ_0;
537 break;
538 case 48000:
539 rme32->wcreg &= ~RME32_WCR_DS_BM;
540 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
541 RME32_WCR_FREQ_1;
542 break;
543 case 64000:
544 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
545 return -EINVAL;
546 rme32->wcreg |= RME32_WCR_DS_BM;
547 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
548 ~RME32_WCR_FREQ_1;
549 break;
550 case 88200:
551 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
552 return -EINVAL;
553 rme32->wcreg |= RME32_WCR_DS_BM;
554 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
555 ~RME32_WCR_FREQ_0;
556 break;
557 case 96000:
558 if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
559 return -EINVAL;
560 rme32->wcreg |= RME32_WCR_DS_BM;
561 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
562 RME32_WCR_FREQ_1;
563 break;
564 default:
565 return -EINVAL;
566 }
567 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
568 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
569 {
570 /* change to/from double-speed: reset the DAC (if available) */
571 snd_rme32_reset_dac(rme32);
572 } else {
573 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
574 }
575 return 0;
576}
577
578static int snd_rme32_setclockmode(rme32_t * rme32, int mode)
579{
580 switch (mode) {
581 case RME32_CLOCKMODE_SLAVE:
582 /* AutoSync */
583 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
584 ~RME32_WCR_FREQ_1;
585 break;
586 case RME32_CLOCKMODE_MASTER_32:
587 /* Internal 32.0kHz */
588 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
589 ~RME32_WCR_FREQ_1;
590 break;
591 case RME32_CLOCKMODE_MASTER_44:
592 /* Internal 44.1kHz */
593 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
594 RME32_WCR_FREQ_1;
595 break;
596 case RME32_CLOCKMODE_MASTER_48:
597 /* Internal 48.0kHz */
598 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
599 RME32_WCR_FREQ_1;
600 break;
601 default:
602 return -EINVAL;
603 }
604 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
605 return 0;
606}
607
608static int snd_rme32_getclockmode(rme32_t * rme32)
609{
610 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
611 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
612}
613
614static int snd_rme32_setinputtype(rme32_t * rme32, int type)
615{
616 switch (type) {
617 case RME32_INPUT_OPTICAL:
618 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
619 ~RME32_WCR_INP_1;
620 break;
621 case RME32_INPUT_COAXIAL:
622 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
623 ~RME32_WCR_INP_1;
624 break;
625 case RME32_INPUT_INTERNAL:
626 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
627 RME32_WCR_INP_1;
628 break;
629 case RME32_INPUT_XLR:
630 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
631 RME32_WCR_INP_1;
632 break;
633 default:
634 return -EINVAL;
635 }
636 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
637 return 0;
638}
639
640static int snd_rme32_getinputtype(rme32_t * rme32)
641{
642 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
643 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
644}
645
646static void
647snd_rme32_setframelog(rme32_t * rme32, int n_channels, int is_playback)
648{
649 int frlog;
650
651 if (n_channels == 2) {
652 frlog = 1;
653 } else {
654 /* assume 8 channels */
655 frlog = 3;
656 }
657 if (is_playback) {
658 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
659 rme32->playback_frlog = frlog;
660 } else {
661 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
662 rme32->capture_frlog = frlog;
663 }
664}
665
666static int snd_rme32_setformat(rme32_t * rme32, int format)
667{
668 switch (format) {
669 case SNDRV_PCM_FORMAT_S16_LE:
670 rme32->wcreg &= ~RME32_WCR_MODE24;
671 break;
672 case SNDRV_PCM_FORMAT_S32_LE:
673 rme32->wcreg |= RME32_WCR_MODE24;
674 break;
675 default:
676 return -EINVAL;
677 }
678 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
679 return 0;
680}
681
682static int
683snd_rme32_playback_hw_params(snd_pcm_substream_t * substream,
684 snd_pcm_hw_params_t * params)
685{
686 int err, rate, dummy;
687 rme32_t *rme32 = snd_pcm_substream_chip(substream);
688 snd_pcm_runtime_t *runtime = substream->runtime;
689
690 if (rme32->fullduplex_mode) {
691 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
692 if (err < 0)
693 return err;
694 } else {
Clemens Ladisch4d233592005-09-05 10:35:20 +0200695 runtime->dma_area = (void __force *)(rme32->iobase +
696 RME32_IO_DATA_BUFFER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
698 runtime->dma_bytes = RME32_BUFFER_SIZE;
699 }
700
701 spin_lock_irq(&rme32->lock);
702 if ((rme32->rcreg & RME32_RCR_KMODE) &&
703 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
704 /* AutoSync */
705 if ((int)params_rate(params) != rate) {
706 spin_unlock_irq(&rme32->lock);
707 return -EIO;
708 }
709 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
710 spin_unlock_irq(&rme32->lock);
711 return err;
712 }
713 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
714 spin_unlock_irq(&rme32->lock);
715 return err;
716 }
717
718 snd_rme32_setframelog(rme32, params_channels(params), 1);
719 if (rme32->capture_periodsize != 0) {
720 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
721 spin_unlock_irq(&rme32->lock);
722 return -EBUSY;
723 }
724 }
725 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
726 /* S/PDIF setup */
727 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
728 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
729 rme32->wcreg |= rme32->wcreg_spdif_stream;
730 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
731 }
732 spin_unlock_irq(&rme32->lock);
733
734 return 0;
735}
736
737static int
738snd_rme32_capture_hw_params(snd_pcm_substream_t * substream,
739 snd_pcm_hw_params_t * params)
740{
741 int err, isadat, rate;
742 rme32_t *rme32 = snd_pcm_substream_chip(substream);
743 snd_pcm_runtime_t *runtime = substream->runtime;
744
745 if (rme32->fullduplex_mode) {
746 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
747 if (err < 0)
748 return err;
749 } else {
Clemens Ladisch4d233592005-09-05 10:35:20 +0200750 runtime->dma_area = (void __force *)rme32->iobase +
751 RME32_IO_DATA_BUFFER;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
753 runtime->dma_bytes = RME32_BUFFER_SIZE;
754 }
755
756 spin_lock_irq(&rme32->lock);
757 /* enable AutoSync for record-preparing */
758 rme32->wcreg |= RME32_WCR_AUTOSYNC;
759 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
760
761 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
762 spin_unlock_irq(&rme32->lock);
763 return err;
764 }
765 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
766 spin_unlock_irq(&rme32->lock);
767 return err;
768 }
769 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
770 if ((int)params_rate(params) != rate) {
771 spin_unlock_irq(&rme32->lock);
772 return -EIO;
773 }
774 if ((isadat && runtime->hw.channels_min == 2) ||
775 (!isadat && runtime->hw.channels_min == 8)) {
776 spin_unlock_irq(&rme32->lock);
777 return -EIO;
778 }
779 }
780 /* AutoSync off for recording */
781 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
782 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
783
784 snd_rme32_setframelog(rme32, params_channels(params), 0);
785 if (rme32->playback_periodsize != 0) {
786 if (params_period_size(params) << rme32->capture_frlog !=
787 rme32->playback_periodsize) {
788 spin_unlock_irq(&rme32->lock);
789 return -EBUSY;
790 }
791 }
792 rme32->capture_periodsize =
793 params_period_size(params) << rme32->capture_frlog;
794 spin_unlock_irq(&rme32->lock);
795
796 return 0;
797}
798
799static int snd_rme32_pcm_hw_free(snd_pcm_substream_t * substream)
800{
801 rme32_t *rme32 = snd_pcm_substream_chip(substream);
802 if (! rme32->fullduplex_mode)
803 return 0;
804 return snd_pcm_lib_free_pages(substream);
805}
806
807static void snd_rme32_pcm_start(rme32_t * rme32, int from_pause)
808{
809 if (!from_pause) {
810 writel(0, rme32->iobase + RME32_IO_RESET_POS);
811 }
812
813 rme32->wcreg |= RME32_WCR_START;
814 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
815}
816
817static void snd_rme32_pcm_stop(rme32_t * rme32, int to_pause)
818{
819 /*
820 * Check if there is an unconfirmed IRQ, if so confirm it, or else
821 * the hardware will not stop generating interrupts
822 */
823 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
824 if (rme32->rcreg & RME32_RCR_IRQ) {
825 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
826 }
827 rme32->wcreg &= ~RME32_WCR_START;
828 if (rme32->wcreg & RME32_WCR_SEL)
829 rme32->wcreg |= RME32_WCR_MUTE;
830 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
831 if (! to_pause)
832 writel(0, rme32->iobase + RME32_IO_RESET_POS);
833}
834
835static irqreturn_t
836snd_rme32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
837{
838 rme32_t *rme32 = (rme32_t *) dev_id;
839
840 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
841 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
842 return IRQ_NONE;
843 } else {
844 if (rme32->capture_substream) {
845 snd_pcm_period_elapsed(rme32->capture_substream);
846 }
847 if (rme32->playback_substream) {
848 snd_pcm_period_elapsed(rme32->playback_substream);
849 }
850 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
851 }
852 return IRQ_HANDLED;
853}
854
855static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
856
857
858static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
859 .count = ARRAY_SIZE(period_bytes),
860 .list = period_bytes,
861 .mask = 0
862};
863
864static void snd_rme32_set_buffer_constraint(rme32_t *rme32, snd_pcm_runtime_t *runtime)
865{
866 if (! rme32->fullduplex_mode) {
867 snd_pcm_hw_constraint_minmax(runtime,
868 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
869 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
870 snd_pcm_hw_constraint_list(runtime, 0,
871 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
872 &hw_constraints_period_bytes);
873 }
874}
875
876static int snd_rme32_playback_spdif_open(snd_pcm_substream_t * substream)
877{
878 int rate, dummy;
879 rme32_t *rme32 = snd_pcm_substream_chip(substream);
880 snd_pcm_runtime_t *runtime = substream->runtime;
881
882 snd_pcm_set_sync(substream);
883
884 spin_lock_irq(&rme32->lock);
885 if (rme32->playback_substream != NULL) {
886 spin_unlock_irq(&rme32->lock);
887 return -EBUSY;
888 }
889 rme32->wcreg &= ~RME32_WCR_ADAT;
890 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
891 rme32->playback_substream = substream;
892 spin_unlock_irq(&rme32->lock);
893
894 if (rme32->fullduplex_mode)
895 runtime->hw = snd_rme32_spdif_fd_info;
896 else
897 runtime->hw = snd_rme32_spdif_info;
898 if (rme32->pci->device == PCI_DEVICE_ID_DIGI32_PRO) {
899 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
900 runtime->hw.rate_max = 96000;
901 }
902 if ((rme32->rcreg & RME32_RCR_KMODE) &&
903 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
904 /* AutoSync */
905 runtime->hw.rates = snd_rme32_ratecode(rate);
906 runtime->hw.rate_min = rate;
907 runtime->hw.rate_max = rate;
908 }
909
910 snd_rme32_set_buffer_constraint(rme32, runtime);
911
912 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
913 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
914 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
915 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
916 return 0;
917}
918
919static int snd_rme32_capture_spdif_open(snd_pcm_substream_t * substream)
920{
921 int isadat, rate;
922 rme32_t *rme32 = snd_pcm_substream_chip(substream);
923 snd_pcm_runtime_t *runtime = substream->runtime;
924
925 snd_pcm_set_sync(substream);
926
927 spin_lock_irq(&rme32->lock);
928 if (rme32->capture_substream != NULL) {
929 spin_unlock_irq(&rme32->lock);
930 return -EBUSY;
931 }
932 rme32->capture_substream = substream;
933 spin_unlock_irq(&rme32->lock);
934
935 if (rme32->fullduplex_mode)
936 runtime->hw = snd_rme32_spdif_fd_info;
937 else
938 runtime->hw = snd_rme32_spdif_info;
939 if (RME32_PRO_WITH_8414(rme32)) {
940 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
941 runtime->hw.rate_max = 96000;
942 }
943 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
944 if (isadat) {
945 return -EIO;
946 }
947 runtime->hw.rates = snd_rme32_ratecode(rate);
948 runtime->hw.rate_min = rate;
949 runtime->hw.rate_max = rate;
950 }
951
952 snd_rme32_set_buffer_constraint(rme32, runtime);
953
954 return 0;
955}
956
957static int
958snd_rme32_playback_adat_open(snd_pcm_substream_t *substream)
959{
960 int rate, dummy;
961 rme32_t *rme32 = snd_pcm_substream_chip(substream);
962 snd_pcm_runtime_t *runtime = substream->runtime;
963
964 snd_pcm_set_sync(substream);
965
966 spin_lock_irq(&rme32->lock);
967 if (rme32->playback_substream != NULL) {
968 spin_unlock_irq(&rme32->lock);
969 return -EBUSY;
970 }
971 rme32->wcreg |= RME32_WCR_ADAT;
972 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
973 rme32->playback_substream = substream;
974 spin_unlock_irq(&rme32->lock);
975
976 if (rme32->fullduplex_mode)
977 runtime->hw = snd_rme32_adat_fd_info;
978 else
979 runtime->hw = snd_rme32_adat_info;
980 if ((rme32->rcreg & RME32_RCR_KMODE) &&
981 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
982 /* AutoSync */
983 runtime->hw.rates = snd_rme32_ratecode(rate);
984 runtime->hw.rate_min = rate;
985 runtime->hw.rate_max = rate;
986 }
987
988 snd_rme32_set_buffer_constraint(rme32, runtime);
989 return 0;
990}
991
992static int
993snd_rme32_capture_adat_open(snd_pcm_substream_t *substream)
994{
995 int isadat, rate;
996 rme32_t *rme32 = snd_pcm_substream_chip(substream);
997 snd_pcm_runtime_t *runtime = substream->runtime;
998
999 if (rme32->fullduplex_mode)
1000 runtime->hw = snd_rme32_adat_fd_info;
1001 else
1002 runtime->hw = snd_rme32_adat_info;
1003 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
1004 if (!isadat) {
1005 return -EIO;
1006 }
1007 runtime->hw.rates = snd_rme32_ratecode(rate);
1008 runtime->hw.rate_min = rate;
1009 runtime->hw.rate_max = rate;
1010 }
1011
1012 snd_pcm_set_sync(substream);
1013
1014 spin_lock_irq(&rme32->lock);
1015 if (rme32->capture_substream != NULL) {
1016 spin_unlock_irq(&rme32->lock);
1017 return -EBUSY;
1018 }
1019 rme32->capture_substream = substream;
1020 spin_unlock_irq(&rme32->lock);
1021
1022 snd_rme32_set_buffer_constraint(rme32, runtime);
1023 return 0;
1024}
1025
1026static int snd_rme32_playback_close(snd_pcm_substream_t * substream)
1027{
1028 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1029 int spdif = 0;
1030
1031 spin_lock_irq(&rme32->lock);
1032 rme32->playback_substream = NULL;
1033 rme32->playback_periodsize = 0;
1034 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1035 spin_unlock_irq(&rme32->lock);
1036 if (spdif) {
1037 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1038 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1039 SNDRV_CTL_EVENT_MASK_INFO,
1040 &rme32->spdif_ctl->id);
1041 }
1042 return 0;
1043}
1044
1045static int snd_rme32_capture_close(snd_pcm_substream_t * substream)
1046{
1047 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1048
1049 spin_lock_irq(&rme32->lock);
1050 rme32->capture_substream = NULL;
1051 rme32->capture_periodsize = 0;
1052 spin_unlock(&rme32->lock);
1053 return 0;
1054}
1055
1056static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream)
1057{
1058 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1059
1060 spin_lock_irq(&rme32->lock);
1061 if (rme32->fullduplex_mode) {
1062 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1063 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1064 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1065 } else {
1066 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1067 }
1068 if (rme32->wcreg & RME32_WCR_SEL)
1069 rme32->wcreg &= ~RME32_WCR_MUTE;
1070 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1071 spin_unlock_irq(&rme32->lock);
1072 return 0;
1073}
1074
1075static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream)
1076{
1077 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1078
1079 spin_lock_irq(&rme32->lock);
1080 if (rme32->fullduplex_mode) {
1081 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1082 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1083 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1084 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1085 } else {
1086 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1087 }
1088 spin_unlock_irq(&rme32->lock);
1089 return 0;
1090}
1091
1092static int
1093snd_rme32_pcm_trigger(snd_pcm_substream_t * substream, int cmd)
1094{
1095 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1096 struct list_head *pos;
1097 snd_pcm_substream_t *s;
1098
1099 spin_lock(&rme32->lock);
1100 snd_pcm_group_for_each(pos, substream) {
1101 s = snd_pcm_group_substream_entry(pos);
1102 if (s != rme32->playback_substream &&
1103 s != rme32->capture_substream)
1104 continue;
1105 switch (cmd) {
1106 case SNDRV_PCM_TRIGGER_START:
1107 rme32->running |= (1 << s->stream);
1108 if (rme32->fullduplex_mode) {
1109 /* remember the current DMA position */
1110 if (s == rme32->playback_substream) {
1111 rme32->playback_pcm.hw_io =
1112 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1113 } else {
1114 rme32->capture_pcm.hw_io =
1115 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1116 }
1117 }
1118 break;
1119 case SNDRV_PCM_TRIGGER_STOP:
1120 rme32->running &= ~(1 << s->stream);
1121 break;
1122 }
1123 snd_pcm_trigger_done(s, substream);
1124 }
1125
1126 /* prefill playback buffer */
1127 if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1128 snd_pcm_group_for_each(pos, substream) {
1129 s = snd_pcm_group_substream_entry(pos);
1130 if (s == rme32->playback_substream) {
1131 s->ops->ack(s);
1132 break;
1133 }
1134 }
1135 }
1136
1137 switch (cmd) {
1138 case SNDRV_PCM_TRIGGER_START:
1139 if (rme32->running && ! RME32_ISWORKING(rme32))
1140 snd_rme32_pcm_start(rme32, 0);
1141 break;
1142 case SNDRV_PCM_TRIGGER_STOP:
1143 if (! rme32->running && RME32_ISWORKING(rme32))
1144 snd_rme32_pcm_stop(rme32, 0);
1145 break;
1146 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1147 if (rme32->running && RME32_ISWORKING(rme32))
1148 snd_rme32_pcm_stop(rme32, 1);
1149 break;
1150 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1151 if (rme32->running && ! RME32_ISWORKING(rme32))
1152 snd_rme32_pcm_start(rme32, 1);
1153 break;
1154 }
1155 spin_unlock(&rme32->lock);
1156 return 0;
1157}
1158
1159/* pointer callback for halfduplex mode */
1160static snd_pcm_uframes_t
1161snd_rme32_playback_pointer(snd_pcm_substream_t * substream)
1162{
1163 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1164 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1165}
1166
1167static snd_pcm_uframes_t
1168snd_rme32_capture_pointer(snd_pcm_substream_t * substream)
1169{
1170 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1171 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1172}
1173
1174
1175/* ack and pointer callbacks for fullduplex mode */
1176static void snd_rme32_pb_trans_copy(snd_pcm_substream_t *substream,
1177 snd_pcm_indirect_t *rec, size_t bytes)
1178{
1179 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1180 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1181 substream->runtime->dma_area + rec->sw_data, bytes);
1182}
1183
1184static int snd_rme32_playback_fd_ack(snd_pcm_substream_t *substream)
1185{
1186 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1187 snd_pcm_indirect_t *rec, *cprec;
1188
1189 rec = &rme32->playback_pcm;
1190 cprec = &rme32->capture_pcm;
1191 spin_lock(&rme32->lock);
1192 rec->hw_queue_size = RME32_BUFFER_SIZE;
1193 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1194 rec->hw_queue_size -= cprec->hw_ready;
1195 spin_unlock(&rme32->lock);
1196 snd_pcm_indirect_playback_transfer(substream, rec,
1197 snd_rme32_pb_trans_copy);
1198 return 0;
1199}
1200
1201static void snd_rme32_cp_trans_copy(snd_pcm_substream_t *substream,
1202 snd_pcm_indirect_t *rec, size_t bytes)
1203{
1204 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1205 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1206 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1207 bytes);
1208}
1209
1210static int snd_rme32_capture_fd_ack(snd_pcm_substream_t *substream)
1211{
1212 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1213 snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1214 snd_rme32_cp_trans_copy);
1215 return 0;
1216}
1217
1218static snd_pcm_uframes_t
1219snd_rme32_playback_fd_pointer(snd_pcm_substream_t * substream)
1220{
1221 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1222 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1223 snd_rme32_pcm_byteptr(rme32));
1224}
1225
1226static snd_pcm_uframes_t
1227snd_rme32_capture_fd_pointer(snd_pcm_substream_t * substream)
1228{
1229 rme32_t *rme32 = snd_pcm_substream_chip(substream);
1230 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1231 snd_rme32_pcm_byteptr(rme32));
1232}
1233
1234/* for halfduplex mode */
1235static snd_pcm_ops_t snd_rme32_playback_spdif_ops = {
1236 .open = snd_rme32_playback_spdif_open,
1237 .close = snd_rme32_playback_close,
1238 .ioctl = snd_pcm_lib_ioctl,
1239 .hw_params = snd_rme32_playback_hw_params,
1240 .hw_free = snd_rme32_pcm_hw_free,
1241 .prepare = snd_rme32_playback_prepare,
1242 .trigger = snd_rme32_pcm_trigger,
1243 .pointer = snd_rme32_playback_pointer,
1244 .copy = snd_rme32_playback_copy,
1245 .silence = snd_rme32_playback_silence,
1246 .mmap = snd_pcm_lib_mmap_iomem,
1247};
1248
1249static snd_pcm_ops_t snd_rme32_capture_spdif_ops = {
1250 .open = snd_rme32_capture_spdif_open,
1251 .close = snd_rme32_capture_close,
1252 .ioctl = snd_pcm_lib_ioctl,
1253 .hw_params = snd_rme32_capture_hw_params,
1254 .hw_free = snd_rme32_pcm_hw_free,
1255 .prepare = snd_rme32_capture_prepare,
1256 .trigger = snd_rme32_pcm_trigger,
1257 .pointer = snd_rme32_capture_pointer,
1258 .copy = snd_rme32_capture_copy,
1259 .mmap = snd_pcm_lib_mmap_iomem,
1260};
1261
1262static snd_pcm_ops_t snd_rme32_playback_adat_ops = {
1263 .open = snd_rme32_playback_adat_open,
1264 .close = snd_rme32_playback_close,
1265 .ioctl = snd_pcm_lib_ioctl,
1266 .hw_params = snd_rme32_playback_hw_params,
1267 .prepare = snd_rme32_playback_prepare,
1268 .trigger = snd_rme32_pcm_trigger,
1269 .pointer = snd_rme32_playback_pointer,
1270 .copy = snd_rme32_playback_copy,
1271 .silence = snd_rme32_playback_silence,
1272 .mmap = snd_pcm_lib_mmap_iomem,
1273};
1274
1275static snd_pcm_ops_t snd_rme32_capture_adat_ops = {
1276 .open = snd_rme32_capture_adat_open,
1277 .close = snd_rme32_capture_close,
1278 .ioctl = snd_pcm_lib_ioctl,
1279 .hw_params = snd_rme32_capture_hw_params,
1280 .prepare = snd_rme32_capture_prepare,
1281 .trigger = snd_rme32_pcm_trigger,
1282 .pointer = snd_rme32_capture_pointer,
1283 .copy = snd_rme32_capture_copy,
1284 .mmap = snd_pcm_lib_mmap_iomem,
1285};
1286
1287/* for fullduplex mode */
1288static snd_pcm_ops_t snd_rme32_playback_spdif_fd_ops = {
1289 .open = snd_rme32_playback_spdif_open,
1290 .close = snd_rme32_playback_close,
1291 .ioctl = snd_pcm_lib_ioctl,
1292 .hw_params = snd_rme32_playback_hw_params,
1293 .hw_free = snd_rme32_pcm_hw_free,
1294 .prepare = snd_rme32_playback_prepare,
1295 .trigger = snd_rme32_pcm_trigger,
1296 .pointer = snd_rme32_playback_fd_pointer,
1297 .ack = snd_rme32_playback_fd_ack,
1298};
1299
1300static snd_pcm_ops_t snd_rme32_capture_spdif_fd_ops = {
1301 .open = snd_rme32_capture_spdif_open,
1302 .close = snd_rme32_capture_close,
1303 .ioctl = snd_pcm_lib_ioctl,
1304 .hw_params = snd_rme32_capture_hw_params,
1305 .hw_free = snd_rme32_pcm_hw_free,
1306 .prepare = snd_rme32_capture_prepare,
1307 .trigger = snd_rme32_pcm_trigger,
1308 .pointer = snd_rme32_capture_fd_pointer,
1309 .ack = snd_rme32_capture_fd_ack,
1310};
1311
1312static snd_pcm_ops_t snd_rme32_playback_adat_fd_ops = {
1313 .open = snd_rme32_playback_adat_open,
1314 .close = snd_rme32_playback_close,
1315 .ioctl = snd_pcm_lib_ioctl,
1316 .hw_params = snd_rme32_playback_hw_params,
1317 .prepare = snd_rme32_playback_prepare,
1318 .trigger = snd_rme32_pcm_trigger,
1319 .pointer = snd_rme32_playback_fd_pointer,
1320 .ack = snd_rme32_playback_fd_ack,
1321};
1322
1323static snd_pcm_ops_t snd_rme32_capture_adat_fd_ops = {
1324 .open = snd_rme32_capture_adat_open,
1325 .close = snd_rme32_capture_close,
1326 .ioctl = snd_pcm_lib_ioctl,
1327 .hw_params = snd_rme32_capture_hw_params,
1328 .prepare = snd_rme32_capture_prepare,
1329 .trigger = snd_rme32_pcm_trigger,
1330 .pointer = snd_rme32_capture_fd_pointer,
1331 .ack = snd_rme32_capture_fd_ack,
1332};
1333
1334static void snd_rme32_free(void *private_data)
1335{
1336 rme32_t *rme32 = (rme32_t *) private_data;
1337
1338 if (rme32 == NULL) {
1339 return;
1340 }
1341 if (rme32->irq >= 0) {
1342 snd_rme32_pcm_stop(rme32, 0);
1343 free_irq(rme32->irq, (void *) rme32);
1344 rme32->irq = -1;
1345 }
1346 if (rme32->iobase) {
1347 iounmap(rme32->iobase);
1348 rme32->iobase = NULL;
1349 }
1350 if (rme32->port) {
1351 pci_release_regions(rme32->pci);
1352 rme32->port = 0;
1353 }
1354 pci_disable_device(rme32->pci);
1355}
1356
1357static void snd_rme32_free_spdif_pcm(snd_pcm_t * pcm)
1358{
1359 rme32_t *rme32 = (rme32_t *) pcm->private_data;
1360 rme32->spdif_pcm = NULL;
1361}
1362
1363static void
1364snd_rme32_free_adat_pcm(snd_pcm_t *pcm)
1365{
1366 rme32_t *rme32 = (rme32_t *) pcm->private_data;
1367 rme32->adat_pcm = NULL;
1368}
1369
1370static int __devinit snd_rme32_create(rme32_t * rme32)
1371{
1372 struct pci_dev *pci = rme32->pci;
1373 int err;
1374
1375 rme32->irq = -1;
1376 spin_lock_init(&rme32->lock);
1377
1378 if ((err = pci_enable_device(pci)) < 0)
1379 return err;
1380
1381 if ((err = pci_request_regions(pci, "RME32")) < 0)
1382 return err;
1383 rme32->port = pci_resource_start(rme32->pci, 0);
1384
1385 if (request_irq(pci->irq, snd_rme32_interrupt, SA_INTERRUPT | SA_SHIRQ, "RME32", (void *) rme32)) {
1386 snd_printk("unable to grab IRQ %d\n", pci->irq);
1387 return -EBUSY;
1388 }
1389 rme32->irq = pci->irq;
1390
1391 if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
1392 snd_printk("unable to remap memory region 0x%lx-0x%lx\n",
1393 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1394 return -ENOMEM;
1395 }
1396
1397 /* read the card's revision number */
1398 pci_read_config_byte(pci, 8, &rme32->rev);
1399
1400 /* set up ALSA pcm device for S/PDIF */
1401 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1402 return err;
1403 }
1404 rme32->spdif_pcm->private_data = rme32;
1405 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1406 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1407 if (rme32->fullduplex_mode) {
1408 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1409 &snd_rme32_playback_spdif_fd_ops);
1410 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1411 &snd_rme32_capture_spdif_fd_ops);
1412 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1413 snd_dma_continuous_data(GFP_KERNEL),
1414 0, RME32_MID_BUFFER_SIZE);
1415 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1416 } else {
1417 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1418 &snd_rme32_playback_spdif_ops);
1419 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1420 &snd_rme32_capture_spdif_ops);
1421 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1422 }
1423
1424 /* set up ALSA pcm device for ADAT */
1425 if ((pci->device == PCI_DEVICE_ID_DIGI32) ||
1426 (pci->device == PCI_DEVICE_ID_DIGI32_PRO)) {
1427 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1428 rme32->adat_pcm = NULL;
1429 }
1430 else {
1431 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1432 1, 1, &rme32->adat_pcm)) < 0)
1433 {
1434 return err;
1435 }
1436 rme32->adat_pcm->private_data = rme32;
1437 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1438 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1439 if (rme32->fullduplex_mode) {
1440 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1441 &snd_rme32_playback_adat_fd_ops);
1442 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1443 &snd_rme32_capture_adat_fd_ops);
1444 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1445 snd_dma_continuous_data(GFP_KERNEL),
1446 0, RME32_MID_BUFFER_SIZE);
1447 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1448 } else {
1449 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1450 &snd_rme32_playback_adat_ops);
1451 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1452 &snd_rme32_capture_adat_ops);
1453 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1454 }
1455 }
1456
1457
1458 rme32->playback_periodsize = 0;
1459 rme32->capture_periodsize = 0;
1460
1461 /* make sure playback/capture is stopped, if by some reason active */
1462 snd_rme32_pcm_stop(rme32, 0);
1463
1464 /* reset DAC */
1465 snd_rme32_reset_dac(rme32);
1466
1467 /* reset buffer pointer */
1468 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1469
1470 /* set default values in registers */
1471 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1472 RME32_WCR_INP_0 | /* input select */
1473 RME32_WCR_MUTE; /* muting on */
1474 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1475
1476
1477 /* init switch interface */
1478 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1479 return err;
1480 }
1481
1482 /* init proc interface */
1483 snd_rme32_proc_init(rme32);
1484
1485 rme32->capture_substream = NULL;
1486 rme32->playback_substream = NULL;
1487
1488 return 0;
1489}
1490
1491/*
1492 * proc interface
1493 */
1494
1495static void
1496snd_rme32_proc_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer)
1497{
1498 int n;
1499 rme32_t *rme32 = (rme32_t *) entry->private_data;
1500
1501 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1502
1503 snd_iprintf(buffer, rme32->card->longname);
1504 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1505
1506 snd_iprintf(buffer, "\nGeneral settings\n");
1507 if (rme32->fullduplex_mode)
1508 snd_iprintf(buffer, " Full-duplex mode\n");
1509 else
1510 snd_iprintf(buffer, " Half-duplex mode\n");
1511 if (RME32_PRO_WITH_8414(rme32)) {
1512 snd_iprintf(buffer, " receiver: CS8414\n");
1513 } else {
1514 snd_iprintf(buffer, " receiver: CS8412\n");
1515 }
1516 if (rme32->wcreg & RME32_WCR_MODE24) {
1517 snd_iprintf(buffer, " format: 24 bit");
1518 } else {
1519 snd_iprintf(buffer, " format: 16 bit");
1520 }
1521 if (rme32->wcreg & RME32_WCR_MONO) {
1522 snd_iprintf(buffer, ", Mono\n");
1523 } else {
1524 snd_iprintf(buffer, ", Stereo\n");
1525 }
1526
1527 snd_iprintf(buffer, "\nInput settings\n");
1528 switch (snd_rme32_getinputtype(rme32)) {
1529 case RME32_INPUT_OPTICAL:
1530 snd_iprintf(buffer, " input: optical");
1531 break;
1532 case RME32_INPUT_COAXIAL:
1533 snd_iprintf(buffer, " input: coaxial");
1534 break;
1535 case RME32_INPUT_INTERNAL:
1536 snd_iprintf(buffer, " input: internal");
1537 break;
1538 case RME32_INPUT_XLR:
1539 snd_iprintf(buffer, " input: XLR");
1540 break;
1541 }
1542 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1543 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1544 } else {
1545 if (n) {
1546 snd_iprintf(buffer, " (8 channels)\n");
1547 } else {
1548 snd_iprintf(buffer, " (2 channels)\n");
1549 }
1550 snd_iprintf(buffer, " sample rate: %d Hz\n",
1551 snd_rme32_capture_getrate(rme32, &n));
1552 }
1553
1554 snd_iprintf(buffer, "\nOutput settings\n");
1555 if (rme32->wcreg & RME32_WCR_SEL) {
1556 snd_iprintf(buffer, " output signal: normal playback");
1557 } else {
1558 snd_iprintf(buffer, " output signal: same as input");
1559 }
1560 if (rme32->wcreg & RME32_WCR_MUTE) {
1561 snd_iprintf(buffer, " (muted)\n");
1562 } else {
1563 snd_iprintf(buffer, "\n");
1564 }
1565
1566 /* master output frequency */
1567 if (!
1568 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1569 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1570 snd_iprintf(buffer, " sample rate: %d Hz\n",
1571 snd_rme32_playback_getrate(rme32));
1572 }
1573 if (rme32->rcreg & RME32_RCR_KMODE) {
1574 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1575 } else {
1576 snd_iprintf(buffer, " sample clock source: Internal\n");
1577 }
1578 if (rme32->wcreg & RME32_WCR_PRO) {
1579 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1580 } else {
1581 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1582 }
1583 if (rme32->wcreg & RME32_WCR_EMP) {
1584 snd_iprintf(buffer, " emphasis: on\n");
1585 } else {
1586 snd_iprintf(buffer, " emphasis: off\n");
1587 }
1588}
1589
1590static void __devinit snd_rme32_proc_init(rme32_t * rme32)
1591{
1592 snd_info_entry_t *entry;
1593
1594 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1595 snd_info_set_text_ops(entry, rme32, 1024, snd_rme32_proc_read);
1596}
1597
1598/*
1599 * control interface
1600 */
1601
1602static int
1603snd_rme32_info_loopback_control(snd_kcontrol_t * kcontrol,
1604 snd_ctl_elem_info_t * uinfo)
1605{
1606 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1607 uinfo->count = 1;
1608 uinfo->value.integer.min = 0;
1609 uinfo->value.integer.max = 1;
1610 return 0;
1611}
1612static int
1613snd_rme32_get_loopback_control(snd_kcontrol_t * kcontrol,
1614 snd_ctl_elem_value_t * ucontrol)
1615{
1616 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1617
1618 spin_lock_irq(&rme32->lock);
1619 ucontrol->value.integer.value[0] =
1620 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1621 spin_unlock_irq(&rme32->lock);
1622 return 0;
1623}
1624static int
1625snd_rme32_put_loopback_control(snd_kcontrol_t * kcontrol,
1626 snd_ctl_elem_value_t * ucontrol)
1627{
1628 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1629 unsigned int val;
1630 int change;
1631
1632 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1633 spin_lock_irq(&rme32->lock);
1634 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1635 change = val != rme32->wcreg;
1636 if (ucontrol->value.integer.value[0])
1637 val &= ~RME32_WCR_MUTE;
1638 else
1639 val |= RME32_WCR_MUTE;
1640 rme32->wcreg = val;
1641 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1642 spin_unlock_irq(&rme32->lock);
1643 return change;
1644}
1645
1646static int
1647snd_rme32_info_inputtype_control(snd_kcontrol_t * kcontrol,
1648 snd_ctl_elem_info_t * uinfo)
1649{
1650 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1651 static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1652
1653 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1654 uinfo->count = 1;
1655 switch (rme32->pci->device) {
1656 case PCI_DEVICE_ID_DIGI32:
1657 case PCI_DEVICE_ID_DIGI32_8:
1658 uinfo->value.enumerated.items = 3;
1659 break;
1660 case PCI_DEVICE_ID_DIGI32_PRO:
1661 uinfo->value.enumerated.items = 4;
1662 break;
1663 default:
1664 snd_BUG();
1665 break;
1666 }
1667 if (uinfo->value.enumerated.item >
1668 uinfo->value.enumerated.items - 1) {
1669 uinfo->value.enumerated.item =
1670 uinfo->value.enumerated.items - 1;
1671 }
1672 strcpy(uinfo->value.enumerated.name,
1673 texts[uinfo->value.enumerated.item]);
1674 return 0;
1675}
1676static int
1677snd_rme32_get_inputtype_control(snd_kcontrol_t * kcontrol,
1678 snd_ctl_elem_value_t * ucontrol)
1679{
1680 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1681 unsigned int items = 3;
1682
1683 spin_lock_irq(&rme32->lock);
1684 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1685
1686 switch (rme32->pci->device) {
1687 case PCI_DEVICE_ID_DIGI32:
1688 case PCI_DEVICE_ID_DIGI32_8:
1689 items = 3;
1690 break;
1691 case PCI_DEVICE_ID_DIGI32_PRO:
1692 items = 4;
1693 break;
1694 default:
1695 snd_BUG();
1696 break;
1697 }
1698 if (ucontrol->value.enumerated.item[0] >= items) {
1699 ucontrol->value.enumerated.item[0] = items - 1;
1700 }
1701
1702 spin_unlock_irq(&rme32->lock);
1703 return 0;
1704}
1705static int
1706snd_rme32_put_inputtype_control(snd_kcontrol_t * kcontrol,
1707 snd_ctl_elem_value_t * ucontrol)
1708{
1709 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1710 unsigned int val;
1711 int change, items = 3;
1712
1713 switch (rme32->pci->device) {
1714 case PCI_DEVICE_ID_DIGI32:
1715 case PCI_DEVICE_ID_DIGI32_8:
1716 items = 3;
1717 break;
1718 case PCI_DEVICE_ID_DIGI32_PRO:
1719 items = 4;
1720 break;
1721 default:
1722 snd_BUG();
1723 break;
1724 }
1725 val = ucontrol->value.enumerated.item[0] % items;
1726
1727 spin_lock_irq(&rme32->lock);
1728 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1729 snd_rme32_setinputtype(rme32, val);
1730 spin_unlock_irq(&rme32->lock);
1731 return change;
1732}
1733
1734static int
1735snd_rme32_info_clockmode_control(snd_kcontrol_t * kcontrol,
1736 snd_ctl_elem_info_t * uinfo)
1737{
1738 static char *texts[4] = { "AutoSync",
1739 "Internal 32.0kHz",
1740 "Internal 44.1kHz",
1741 "Internal 48.0kHz" };
1742
1743 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1744 uinfo->count = 1;
1745 uinfo->value.enumerated.items = 4;
1746 if (uinfo->value.enumerated.item > 3) {
1747 uinfo->value.enumerated.item = 3;
1748 }
1749 strcpy(uinfo->value.enumerated.name,
1750 texts[uinfo->value.enumerated.item]);
1751 return 0;
1752}
1753static int
1754snd_rme32_get_clockmode_control(snd_kcontrol_t * kcontrol,
1755 snd_ctl_elem_value_t * ucontrol)
1756{
1757 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1758
1759 spin_lock_irq(&rme32->lock);
1760 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1761 spin_unlock_irq(&rme32->lock);
1762 return 0;
1763}
1764static int
1765snd_rme32_put_clockmode_control(snd_kcontrol_t * kcontrol,
1766 snd_ctl_elem_value_t * ucontrol)
1767{
1768 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1769 unsigned int val;
1770 int change;
1771
1772 val = ucontrol->value.enumerated.item[0] % 3;
1773 spin_lock_irq(&rme32->lock);
1774 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1775 snd_rme32_setclockmode(rme32, val);
1776 spin_unlock_irq(&rme32->lock);
1777 return change;
1778}
1779
1780static u32 snd_rme32_convert_from_aes(snd_aes_iec958_t * aes)
1781{
1782 u32 val = 0;
1783 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1784 if (val & RME32_WCR_PRO)
1785 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1786 else
1787 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1788 return val;
1789}
1790
1791static void snd_rme32_convert_to_aes(snd_aes_iec958_t * aes, u32 val)
1792{
1793 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1794 if (val & RME32_WCR_PRO)
1795 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1796 else
1797 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1798}
1799
1800static int snd_rme32_control_spdif_info(snd_kcontrol_t * kcontrol,
1801 snd_ctl_elem_info_t * uinfo)
1802{
1803 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1804 uinfo->count = 1;
1805 return 0;
1806}
1807
1808static int snd_rme32_control_spdif_get(snd_kcontrol_t * kcontrol,
1809 snd_ctl_elem_value_t * ucontrol)
1810{
1811 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1812
1813 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1814 rme32->wcreg_spdif);
1815 return 0;
1816}
1817
1818static int snd_rme32_control_spdif_put(snd_kcontrol_t * kcontrol,
1819 snd_ctl_elem_value_t * ucontrol)
1820{
1821 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1822 int change;
1823 u32 val;
1824
1825 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1826 spin_lock_irq(&rme32->lock);
1827 change = val != rme32->wcreg_spdif;
1828 rme32->wcreg_spdif = val;
1829 spin_unlock_irq(&rme32->lock);
1830 return change;
1831}
1832
1833static int snd_rme32_control_spdif_stream_info(snd_kcontrol_t * kcontrol,
1834 snd_ctl_elem_info_t * uinfo)
1835{
1836 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1837 uinfo->count = 1;
1838 return 0;
1839}
1840
1841static int snd_rme32_control_spdif_stream_get(snd_kcontrol_t * kcontrol,
1842 snd_ctl_elem_value_t *
1843 ucontrol)
1844{
1845 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1846
1847 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1848 rme32->wcreg_spdif_stream);
1849 return 0;
1850}
1851
1852static int snd_rme32_control_spdif_stream_put(snd_kcontrol_t * kcontrol,
1853 snd_ctl_elem_value_t *
1854 ucontrol)
1855{
1856 rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
1857 int change;
1858 u32 val;
1859
1860 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1861 spin_lock_irq(&rme32->lock);
1862 change = val != rme32->wcreg_spdif_stream;
1863 rme32->wcreg_spdif_stream = val;
1864 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1865 rme32->wcreg |= val;
1866 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1867 spin_unlock_irq(&rme32->lock);
1868 return change;
1869}
1870
1871static int snd_rme32_control_spdif_mask_info(snd_kcontrol_t * kcontrol,
1872 snd_ctl_elem_info_t * uinfo)
1873{
1874 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1875 uinfo->count = 1;
1876 return 0;
1877}
1878
1879static int snd_rme32_control_spdif_mask_get(snd_kcontrol_t * kcontrol,
1880 snd_ctl_elem_value_t *
1881 ucontrol)
1882{
1883 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1884 return 0;
1885}
1886
1887static snd_kcontrol_new_t snd_rme32_controls[] = {
1888 {
1889 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1890 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1891 .info = snd_rme32_control_spdif_info,
1892 .get = snd_rme32_control_spdif_get,
1893 .put = snd_rme32_control_spdif_put
1894 },
1895 {
1896 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1897 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1898 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1899 .info = snd_rme32_control_spdif_stream_info,
1900 .get = snd_rme32_control_spdif_stream_get,
1901 .put = snd_rme32_control_spdif_stream_put
1902 },
1903 {
1904 .access = SNDRV_CTL_ELEM_ACCESS_READ,
Clemens Ladisch67ed4162005-07-29 15:32:58 +02001905 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1907 .info = snd_rme32_control_spdif_mask_info,
1908 .get = snd_rme32_control_spdif_mask_get,
1909 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1910 },
1911 {
1912 .access = SNDRV_CTL_ELEM_ACCESS_READ,
Clemens Ladisch67ed4162005-07-29 15:32:58 +02001913 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001914 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1915 .info = snd_rme32_control_spdif_mask_info,
1916 .get = snd_rme32_control_spdif_mask_get,
1917 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1918 },
1919 {
1920 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1921 .name = "Input Connector",
1922 .info = snd_rme32_info_inputtype_control,
1923 .get = snd_rme32_get_inputtype_control,
1924 .put = snd_rme32_put_inputtype_control
1925 },
1926 {
1927 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1928 .name = "Loopback Input",
1929 .info = snd_rme32_info_loopback_control,
1930 .get = snd_rme32_get_loopback_control,
1931 .put = snd_rme32_put_loopback_control
1932 },
1933 {
1934 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1935 .name = "Sample Clock Source",
1936 .info = snd_rme32_info_clockmode_control,
1937 .get = snd_rme32_get_clockmode_control,
1938 .put = snd_rme32_put_clockmode_control
1939 }
1940};
1941
1942static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32)
1943{
1944 int idx, err;
1945 snd_kcontrol_t *kctl;
1946
1947 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1948 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1949 return err;
1950 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1951 rme32->spdif_ctl = kctl;
1952 }
1953
1954 return 0;
1955}
1956
1957/*
1958 * Card initialisation
1959 */
1960
1961static void snd_rme32_card_free(snd_card_t * card)
1962{
1963 snd_rme32_free(card->private_data);
1964}
1965
1966static int __devinit
1967snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1968{
1969 static int dev;
1970 rme32_t *rme32;
1971 snd_card_t *card;
1972 int err;
1973
1974 if (dev >= SNDRV_CARDS) {
1975 return -ENODEV;
1976 }
1977 if (!enable[dev]) {
1978 dev++;
1979 return -ENOENT;
1980 }
1981
1982 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
1983 sizeof(rme32_t))) == NULL)
1984 return -ENOMEM;
1985 card->private_free = snd_rme32_card_free;
1986 rme32 = (rme32_t *) card->private_data;
1987 rme32->card = card;
1988 rme32->pci = pci;
1989 snd_card_set_dev(card, &pci->dev);
1990 if (fullduplex[dev])
1991 rme32->fullduplex_mode = 1;
1992 if ((err = snd_rme32_create(rme32)) < 0) {
1993 snd_card_free(card);
1994 return err;
1995 }
1996
1997 strcpy(card->driver, "Digi32");
1998 switch (rme32->pci->device) {
1999 case PCI_DEVICE_ID_DIGI32:
2000 strcpy(card->shortname, "RME Digi32");
2001 break;
2002 case PCI_DEVICE_ID_DIGI32_8:
2003 strcpy(card->shortname, "RME Digi32/8");
2004 break;
2005 case PCI_DEVICE_ID_DIGI32_PRO:
2006 strcpy(card->shortname, "RME Digi32 PRO");
2007 break;
2008 }
2009 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
2010 card->shortname, rme32->rev, rme32->port, rme32->irq);
2011
2012 if ((err = snd_card_register(card)) < 0) {
2013 snd_card_free(card);
2014 return err;
2015 }
2016 pci_set_drvdata(pci, card);
2017 dev++;
2018 return 0;
2019}
2020
2021static void __devexit snd_rme32_remove(struct pci_dev *pci)
2022{
2023 snd_card_free(pci_get_drvdata(pci));
2024 pci_set_drvdata(pci, NULL);
2025}
2026
2027static struct pci_driver driver = {
2028 .name = "RME Digi32",
2029 .id_table = snd_rme32_ids,
2030 .probe = snd_rme32_probe,
2031 .remove = __devexit_p(snd_rme32_remove),
2032};
2033
2034static int __init alsa_card_rme32_init(void)
2035{
Takashi Iwai01d25d42005-04-11 16:58:24 +02002036 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002037}
2038
2039static void __exit alsa_card_rme32_exit(void)
2040{
2041 pci_unregister_driver(&driver);
2042}
2043
2044module_init(alsa_card_rme32_init)
2045module_exit(alsa_card_rme32_exit)