Paul Mundt | de9186c | 2010-10-18 21:32:58 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Helper routines for SuperH Clock Pulse Generator blocks (CPG). |
| 3 | * |
| 4 | * Copyright (C) 2010 Magnus Damm |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 5 | * Copyright (C) 2010 - 2012 Paul Mundt |
Paul Mundt | de9186c | 2010-10-18 21:32:58 +0900 | [diff] [blame] | 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 11 | #include <linux/clk.h> |
| 12 | #include <linux/compiler.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/sh_clk.h> |
| 16 | |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 17 | static int sh_clk_mstp_enable(struct clk *clk) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 18 | { |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 19 | if (clk->flags & CLK_ENABLE_REG_8BIT) |
| 20 | iowrite8(ioread8(clk->mapped_reg) & ~(1 << clk->enable_bit), |
| 21 | clk->mapped_reg); |
| 22 | else if (clk->flags & CLK_ENABLE_REG_16BIT) |
| 23 | iowrite16(ioread16(clk->mapped_reg) & ~(1 << clk->enable_bit), |
| 24 | clk->mapped_reg); |
| 25 | else |
| 26 | iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit), |
| 27 | clk->mapped_reg); |
| 28 | |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 29 | return 0; |
| 30 | } |
| 31 | |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 32 | static void sh_clk_mstp_disable(struct clk *clk) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 33 | { |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 34 | if (clk->flags & CLK_ENABLE_REG_8BIT) |
| 35 | iowrite8(ioread8(clk->mapped_reg) | (1 << clk->enable_bit), |
| 36 | clk->mapped_reg); |
| 37 | else if (clk->flags & CLK_ENABLE_REG_16BIT) |
| 38 | iowrite16(ioread16(clk->mapped_reg) | (1 << clk->enable_bit), |
| 39 | clk->mapped_reg); |
| 40 | else |
| 41 | iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit), |
| 42 | clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 43 | } |
| 44 | |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 45 | static struct sh_clk_ops sh_clk_mstp_clk_ops = { |
| 46 | .enable = sh_clk_mstp_enable, |
| 47 | .disable = sh_clk_mstp_disable, |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 48 | .recalc = followparent_recalc, |
| 49 | }; |
| 50 | |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 51 | int __init sh_clk_mstp_register(struct clk *clks, int nr) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 52 | { |
| 53 | struct clk *clkp; |
| 54 | int ret = 0; |
| 55 | int k; |
| 56 | |
| 57 | for (k = 0; !ret && (k < nr); k++) { |
| 58 | clkp = clks + k; |
Paul Mundt | 4d6ddb0 | 2012-04-11 12:05:50 +0900 | [diff] [blame^] | 59 | clkp->ops = &sh_clk_mstp_clk_ops; |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 60 | ret |= clk_register(clkp); |
| 61 | } |
| 62 | |
| 63 | return ret; |
| 64 | } |
| 65 | |
| 66 | static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) |
| 67 | { |
| 68 | return clk_rate_table_round(clk, clk->freq_table, rate); |
| 69 | } |
| 70 | |
| 71 | static int sh_clk_div6_divisors[64] = { |
| 72 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, |
| 73 | 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, |
| 74 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, |
| 75 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 |
| 76 | }; |
| 77 | |
| 78 | static struct clk_div_mult_table sh_clk_div6_table = { |
| 79 | .divisors = sh_clk_div6_divisors, |
| 80 | .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors), |
| 81 | }; |
| 82 | |
| 83 | static unsigned long sh_clk_div6_recalc(struct clk *clk) |
| 84 | { |
| 85 | struct clk_div_mult_table *table = &sh_clk_div6_table; |
| 86 | unsigned int idx; |
| 87 | |
| 88 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, |
| 89 | table, NULL); |
| 90 | |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 91 | idx = ioread32(clk->mapped_reg) & 0x003f; |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 92 | |
| 93 | return clk->freq_table[idx].frequency; |
| 94 | } |
| 95 | |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 96 | static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) |
| 97 | { |
| 98 | struct clk_div_mult_table *table = &sh_clk_div6_table; |
| 99 | u32 value; |
| 100 | int ret, i; |
| 101 | |
| 102 | if (!clk->parent_table || !clk->parent_num) |
| 103 | return -EINVAL; |
| 104 | |
| 105 | /* Search the parent */ |
| 106 | for (i = 0; i < clk->parent_num; i++) |
| 107 | if (clk->parent_table[i] == parent) |
| 108 | break; |
| 109 | |
| 110 | if (i == clk->parent_num) |
| 111 | return -ENODEV; |
| 112 | |
| 113 | ret = clk_reparent(clk, parent); |
| 114 | if (ret < 0) |
| 115 | return ret; |
| 116 | |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 117 | value = ioread32(clk->mapped_reg) & |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 118 | ~(((1 << clk->src_width) - 1) << clk->src_shift); |
| 119 | |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 120 | iowrite32(value | (i << clk->src_shift), clk->mapped_reg); |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 121 | |
| 122 | /* Rebuild the frequency table */ |
| 123 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, |
Kuninori Morimoto | 52c10ad | 2011-04-14 17:13:53 +0900 | [diff] [blame] | 124 | table, NULL); |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 125 | |
| 126 | return 0; |
| 127 | } |
| 128 | |
Paul Mundt | 35a96c7 | 2010-11-15 18:18:32 +0900 | [diff] [blame] | 129 | static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 130 | { |
| 131 | unsigned long value; |
| 132 | int idx; |
| 133 | |
| 134 | idx = clk_rate_table_find(clk, clk->freq_table, rate); |
| 135 | if (idx < 0) |
| 136 | return idx; |
| 137 | |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 138 | value = ioread32(clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 139 | value &= ~0x3f; |
| 140 | value |= idx; |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 141 | iowrite32(value, clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | static int sh_clk_div6_enable(struct clk *clk) |
| 146 | { |
| 147 | unsigned long value; |
| 148 | int ret; |
| 149 | |
Paul Mundt | f278ea8 | 2010-11-19 16:40:35 +0900 | [diff] [blame] | 150 | ret = sh_clk_div6_set_rate(clk, clk->rate); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 151 | if (ret == 0) { |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 152 | value = ioread32(clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 153 | value &= ~0x100; /* clear stop bit to enable clock */ |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 154 | iowrite32(value, clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 155 | } |
| 156 | return ret; |
| 157 | } |
| 158 | |
| 159 | static void sh_clk_div6_disable(struct clk *clk) |
| 160 | { |
| 161 | unsigned long value; |
| 162 | |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 163 | value = ioread32(clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 164 | value |= 0x100; /* stop clock */ |
| 165 | value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 166 | iowrite32(value, clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 167 | } |
| 168 | |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 169 | static struct sh_clk_ops sh_clk_div6_clk_ops = { |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 170 | .recalc = sh_clk_div6_recalc, |
| 171 | .round_rate = sh_clk_div_round_rate, |
| 172 | .set_rate = sh_clk_div6_set_rate, |
| 173 | .enable = sh_clk_div6_enable, |
| 174 | .disable = sh_clk_div6_disable, |
| 175 | }; |
| 176 | |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 177 | static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 178 | .recalc = sh_clk_div6_recalc, |
| 179 | .round_rate = sh_clk_div_round_rate, |
| 180 | .set_rate = sh_clk_div6_set_rate, |
| 181 | .enable = sh_clk_div6_enable, |
| 182 | .disable = sh_clk_div6_disable, |
| 183 | .set_parent = sh_clk_div6_set_parent, |
| 184 | }; |
| 185 | |
Kuninori Morimoto | 56242a1 | 2011-11-21 21:33:18 -0800 | [diff] [blame] | 186 | static int __init sh_clk_init_parent(struct clk *clk) |
| 187 | { |
| 188 | u32 val; |
| 189 | |
| 190 | if (clk->parent) |
| 191 | return 0; |
| 192 | |
| 193 | if (!clk->parent_table || !clk->parent_num) |
| 194 | return 0; |
| 195 | |
| 196 | if (!clk->src_width) { |
| 197 | pr_err("sh_clk_init_parent: cannot select parent clock\n"); |
| 198 | return -EINVAL; |
| 199 | } |
| 200 | |
Magnus Damm | 2dacb97 | 2011-12-08 22:59:22 +0900 | [diff] [blame] | 201 | val = (ioread32(clk->mapped_reg) >> clk->src_shift); |
Kuninori Morimoto | 56242a1 | 2011-11-21 21:33:18 -0800 | [diff] [blame] | 202 | val &= (1 << clk->src_width) - 1; |
| 203 | |
| 204 | if (val >= clk->parent_num) { |
| 205 | pr_err("sh_clk_init_parent: parent table size failed\n"); |
| 206 | return -EINVAL; |
| 207 | } |
| 208 | |
Kuninori Morimoto | 64dea57 | 2012-01-19 01:00:40 -0800 | [diff] [blame] | 209 | clk_reparent(clk, clk->parent_table[val]); |
Kuninori Morimoto | 56242a1 | 2011-11-21 21:33:18 -0800 | [diff] [blame] | 210 | if (!clk->parent) { |
| 211 | pr_err("sh_clk_init_parent: unable to set parent"); |
| 212 | return -EINVAL; |
| 213 | } |
| 214 | |
| 215 | return 0; |
| 216 | } |
| 217 | |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 218 | static int __init sh_clk_div6_register_ops(struct clk *clks, int nr, |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 219 | struct sh_clk_ops *ops) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 220 | { |
| 221 | struct clk *clkp; |
| 222 | void *freq_table; |
| 223 | int nr_divs = sh_clk_div6_table.nr_divisors; |
| 224 | int freq_table_size = sizeof(struct cpufreq_frequency_table); |
| 225 | int ret = 0; |
| 226 | int k; |
| 227 | |
| 228 | freq_table_size *= (nr_divs + 1); |
| 229 | freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL); |
| 230 | if (!freq_table) { |
| 231 | pr_err("sh_clk_div6_register: unable to alloc memory\n"); |
| 232 | return -ENOMEM; |
| 233 | } |
| 234 | |
| 235 | for (k = 0; !ret && (k < nr); k++) { |
| 236 | clkp = clks + k; |
| 237 | |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 238 | clkp->ops = ops; |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 239 | clkp->freq_table = freq_table + (k * freq_table_size); |
| 240 | clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; |
Kuninori Morimoto | 7784f4d | 2011-12-11 19:02:09 -0800 | [diff] [blame] | 241 | ret = clk_register(clkp); |
Kuninori Morimoto | 56242a1 | 2011-11-21 21:33:18 -0800 | [diff] [blame] | 242 | if (ret < 0) |
| 243 | break; |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 244 | |
Kuninori Morimoto | 7784f4d | 2011-12-11 19:02:09 -0800 | [diff] [blame] | 245 | ret = sh_clk_init_parent(clkp); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 246 | } |
| 247 | |
| 248 | return ret; |
| 249 | } |
| 250 | |
Guennadi Liakhovetski | b3dd51a | 2010-07-21 10:13:10 +0000 | [diff] [blame] | 251 | int __init sh_clk_div6_register(struct clk *clks, int nr) |
| 252 | { |
| 253 | return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops); |
| 254 | } |
| 255 | |
| 256 | int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) |
| 257 | { |
| 258 | return sh_clk_div6_register_ops(clks, nr, |
| 259 | &sh_clk_div6_reparent_clk_ops); |
| 260 | } |
| 261 | |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 262 | static unsigned long sh_clk_div4_recalc(struct clk *clk) |
| 263 | { |
| 264 | struct clk_div4_table *d4t = clk->priv; |
| 265 | struct clk_div_mult_table *table = d4t->div_mult_table; |
| 266 | unsigned int idx; |
| 267 | |
| 268 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, |
| 269 | table, &clk->arch_flags); |
| 270 | |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 271 | idx = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0x000f; |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 272 | |
| 273 | return clk->freq_table[idx].frequency; |
| 274 | } |
| 275 | |
| 276 | static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) |
| 277 | { |
| 278 | struct clk_div4_table *d4t = clk->priv; |
| 279 | struct clk_div_mult_table *table = d4t->div_mult_table; |
| 280 | u32 value; |
| 281 | int ret; |
| 282 | |
| 283 | /* we really need a better way to determine parent index, but for |
| 284 | * now assume internal parent comes with CLK_ENABLE_ON_INIT set, |
| 285 | * no CLK_ENABLE_ON_INIT means external clock... |
| 286 | */ |
| 287 | |
| 288 | if (parent->flags & CLK_ENABLE_ON_INIT) |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 289 | value = ioread32(clk->mapped_reg) & ~(1 << 7); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 290 | else |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 291 | value = ioread32(clk->mapped_reg) | (1 << 7); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 292 | |
| 293 | ret = clk_reparent(clk, parent); |
| 294 | if (ret < 0) |
| 295 | return ret; |
| 296 | |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 297 | iowrite32(value, clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 298 | |
| 299 | /* Rebiuld the frequency table */ |
| 300 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, |
| 301 | table, &clk->arch_flags); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
Paul Mundt | 35a96c7 | 2010-11-15 18:18:32 +0900 | [diff] [blame] | 306 | static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 307 | { |
| 308 | struct clk_div4_table *d4t = clk->priv; |
| 309 | unsigned long value; |
| 310 | int idx = clk_rate_table_find(clk, clk->freq_table, rate); |
| 311 | if (idx < 0) |
| 312 | return idx; |
| 313 | |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 314 | value = ioread32(clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 315 | value &= ~(0xf << clk->enable_bit); |
| 316 | value |= (idx << clk->enable_bit); |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 317 | iowrite32(value, clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 318 | |
| 319 | if (d4t->kick) |
| 320 | d4t->kick(clk); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static int sh_clk_div4_enable(struct clk *clk) |
| 326 | { |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 327 | iowrite32(ioread32(clk->mapped_reg) & ~(1 << 8), clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static void sh_clk_div4_disable(struct clk *clk) |
| 332 | { |
Magnus Damm | 0e02737 | 2011-12-08 22:59:13 +0900 | [diff] [blame] | 333 | iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg); |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 334 | } |
| 335 | |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 336 | static struct sh_clk_ops sh_clk_div4_clk_ops = { |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 337 | .recalc = sh_clk_div4_recalc, |
| 338 | .set_rate = sh_clk_div4_set_rate, |
| 339 | .round_rate = sh_clk_div_round_rate, |
| 340 | }; |
| 341 | |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 342 | static struct sh_clk_ops sh_clk_div4_enable_clk_ops = { |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 343 | .recalc = sh_clk_div4_recalc, |
| 344 | .set_rate = sh_clk_div4_set_rate, |
| 345 | .round_rate = sh_clk_div_round_rate, |
| 346 | .enable = sh_clk_div4_enable, |
| 347 | .disable = sh_clk_div4_disable, |
| 348 | }; |
| 349 | |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 350 | static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 351 | .recalc = sh_clk_div4_recalc, |
| 352 | .set_rate = sh_clk_div4_set_rate, |
| 353 | .round_rate = sh_clk_div_round_rate, |
| 354 | .enable = sh_clk_div4_enable, |
| 355 | .disable = sh_clk_div4_disable, |
| 356 | .set_parent = sh_clk_div4_set_parent, |
| 357 | }; |
| 358 | |
| 359 | static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, |
Magnus Damm | a0ec360 | 2012-02-29 22:16:21 +0900 | [diff] [blame] | 360 | struct clk_div4_table *table, struct sh_clk_ops *ops) |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 361 | { |
| 362 | struct clk *clkp; |
| 363 | void *freq_table; |
| 364 | int nr_divs = table->div_mult_table->nr_divisors; |
| 365 | int freq_table_size = sizeof(struct cpufreq_frequency_table); |
| 366 | int ret = 0; |
| 367 | int k; |
| 368 | |
| 369 | freq_table_size *= (nr_divs + 1); |
| 370 | freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL); |
| 371 | if (!freq_table) { |
| 372 | pr_err("sh_clk_div4_register: unable to alloc memory\n"); |
| 373 | return -ENOMEM; |
| 374 | } |
| 375 | |
| 376 | for (k = 0; !ret && (k < nr); k++) { |
| 377 | clkp = clks + k; |
| 378 | |
| 379 | clkp->ops = ops; |
Magnus Damm | fa676ca | 2010-05-11 13:29:34 +0000 | [diff] [blame] | 380 | clkp->priv = table; |
| 381 | |
| 382 | clkp->freq_table = freq_table + (k * freq_table_size); |
| 383 | clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; |
| 384 | |
| 385 | ret = clk_register(clkp); |
| 386 | } |
| 387 | |
| 388 | return ret; |
| 389 | } |
| 390 | |
| 391 | int __init sh_clk_div4_register(struct clk *clks, int nr, |
| 392 | struct clk_div4_table *table) |
| 393 | { |
| 394 | return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops); |
| 395 | } |
| 396 | |
| 397 | int __init sh_clk_div4_enable_register(struct clk *clks, int nr, |
| 398 | struct clk_div4_table *table) |
| 399 | { |
| 400 | return sh_clk_div4_register_ops(clks, nr, table, |
| 401 | &sh_clk_div4_enable_clk_ops); |
| 402 | } |
| 403 | |
| 404 | int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, |
| 405 | struct clk_div4_table *table) |
| 406 | { |
| 407 | return sh_clk_div4_register_ops(clks, nr, table, |
| 408 | &sh_clk_div4_reparent_clk_ops); |
| 409 | } |