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gerrit-public.fairphone.software / kernel / msm-4.9 / 4dc3bd254c5dffbdf52caa78e7f8ac3dfae3f263 / . / drivers / gpu / drm / msm / sde_dbg.c
blob: dc16ab13ad6ba277421e80288f7025733b6e8705 [file] [log] [blame]
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]1/* Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
15#include <linux/delay.h>
16#include <linux/spinlock.h>
17#include <linux/ktime.h>
18#include <linux/debugfs.h>
19#include <linux/uaccess.h>
20#include <linux/dma-buf.h>
21#include <linux/slab.h>
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]22#include <linux/list_sort.h>
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]23
24#include "sde_dbg.h"
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]25#include "sde/sde_hw_catalog.h"
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]26
27#define SDE_DBG_BASE_MAX 10
28
29#define DEFAULT_PANIC 1
30#define DEFAULT_REGDUMP SDE_DBG_DUMP_IN_MEM
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]31#define DEFAULT_DBGBUS_SDE SDE_DBG_DUMP_IN_MEM
32#define DEFAULT_DBGBUS_VBIFRT SDE_DBG_DUMP_IN_MEM
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]33#define DEFAULT_BASE_REG_CNT 0x100
34#define GROUP_BYTES 4
35#define ROW_BYTES 16
36#define RANGE_NAME_LEN 40
37#define REG_BASE_NAME_LEN 80
38
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]39#define DBGBUS_FLAGS_DSPP BIT(0)
40#define DBGBUS_DSPP_STATUS 0x34C
41
42#define DBGBUS_NAME_SDE "sde"
43#define DBGBUS_NAME_VBIF_RT "vbif_rt"
44
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]45/* offsets from sde top address for the debug buses */
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]46#define DBGBUS_SSPP0 0x188
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]47#define DBGBUS_AXI_INTF 0x194
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]48#define DBGBUS_SSPP1 0x298
49#define DBGBUS_DSPP 0x348
50#define DBGBUS_PERIPH 0x418
51
52#define TEST_MASK(id, tp) ((id << 4) | (tp << 1) | BIT(0))
53
54/* following offsets are with respect to MDP VBIF base for DBG BUS access */
55#define MMSS_VBIF_CLKON 0x4
56#define MMSS_VBIF_TEST_BUS_OUT_CTRL 0x210
57#define MMSS_VBIF_TEST_BUS_OUT 0x230
58
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]59/* Vbif error info */
Clarence Ip5b730b42017-07-31 18:04:06 -0400[diff] [blame]60#define MMSS_VBIF_PND_ERR 0x190
61#define MMSS_VBIF_SRC_ERR 0x194
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]62#define MMSS_VBIF_XIN_HALT_CTRL1 0x204
63#define MMSS_VBIF_ERR_INFO 0X1a0
64#define MMSS_VBIF_ERR_INFO_1 0x1a4
65#define MMSS_VBIF_CLIENT_NUM 14
66
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]67/* print debug ranges in groups of 4 u32s */
68#define REG_DUMP_ALIGN 16
69
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]70#define RSC_DEBUG_MUX_SEL_SDM845 9
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]71/**
72 * struct sde_dbg_reg_offset - tracking for start and end of region
73 * @start: start offset
74 * @start: end offset
75 */
76struct sde_dbg_reg_offset {
77 u32 start;
78 u32 end;
79};
80
81/**
82 * struct sde_dbg_reg_range - register dumping named sub-range
83 * @head: head of this node
84 * @reg_dump: address for the mem dump
85 * @range_name: name of this range
86 * @offset: offsets for range to dump
87 * @xin_id: client xin id
88 */
89struct sde_dbg_reg_range {
90 struct list_head head;
91 u32 *reg_dump;
92 char range_name[RANGE_NAME_LEN];
93 struct sde_dbg_reg_offset offset;
94 uint32_t xin_id;
95};
96
97/**
98 * struct sde_dbg_reg_base - register region base.
99 * may sub-ranges: sub-ranges are used for dumping
100 * or may not have sub-ranges: dumping is base -> max_offset
101 * @reg_base_head: head of this node
102 * @sub_range_list: head to the list with dump ranges
103 * @name: register base name
104 * @base: base pointer
105 * @off: cached offset of region for manual register dumping
106 * @cnt: cached range of region for manual register dumping
107 * @max_offset: length of region
108 * @buf: buffer used for manual register dumping
109 * @buf_len: buffer length used for manual register dumping
110 * @reg_dump: address for the mem dump if no ranges used
Alan Kwongaa53e682017-07-31 18:21:15 -0400[diff] [blame]111 * @cb: callback for external dump function, null if not defined
112 * @cb_ptr: private pointer to callback function
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]113 */
114struct sde_dbg_reg_base {
115 struct list_head reg_base_head;
116 struct list_head sub_range_list;
117 char name[REG_BASE_NAME_LEN];
118 void __iomem *base;
119 size_t off;
120 size_t cnt;
121 size_t max_offset;
122 char *buf;
123 size_t buf_len;
124 u32 *reg_dump;
Alan Kwongaa53e682017-07-31 18:21:15 -0400[diff] [blame]125 void (*cb)(void *ptr);
126 void *cb_ptr;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]127};
128
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]129struct sde_debug_bus_entry {
130 u32 wr_addr;
131 u32 block_id;
132 u32 test_id;
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]133 void (*analyzer)(void __iomem *mem_base,
134 struct sde_debug_bus_entry *entry, u32 val);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]135};
136
137struct vbif_debug_bus_entry {
138 u32 disable_bus_addr;
139 u32 block_bus_addr;
140 u32 bit_offset;
141 u32 block_cnt;
142 u32 test_pnt_start;
143 u32 test_pnt_cnt;
144};
145
146struct sde_dbg_debug_bus_common {
147 char *name;
148 u32 enable_mask;
149 bool include_in_deferred_work;
150 u32 flags;
151 u32 entries_size;
152 u32 *dumped_content;
153};
154
155struct sde_dbg_sde_debug_bus {
156 struct sde_dbg_debug_bus_common cmn;
157 struct sde_debug_bus_entry *entries;
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]158 u32 top_blk_off;
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]159};
160
161struct sde_dbg_vbif_debug_bus {
162 struct sde_dbg_debug_bus_common cmn;
163 struct vbif_debug_bus_entry *entries;
164};
165
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]166/**
167 * struct sde_dbg_base - global sde debug base structure
168 * @evtlog: event log instance
169 * @reg_base_list: list of register dumping regions
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]170 * @dev: device pointer
171 * @power_ctrl: callback structure for enabling power for reading hw registers
172 * @req_dump_blks: list of blocks requested for dumping
173 * @panic_on_err: whether to kernel panic after triggering dump via debugfs
174 * @dump_work: work struct for deferring register dump work to separate thread
175 * @work_panic: panic after dump if internal user passed "panic" special region
176 * @enable_reg_dump: whether to dump registers into memory, kernel log, or both
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]177 * @dbgbus_sde: debug bus structure for the sde
178 * @dbgbus_vbif_rt: debug bus structure for the realtime vbif
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]179 * @dump_all: dump all entries in register dump
Dhaval Patelf9f3ffe2017-08-16 16:03:10 -0700[diff] [blame]180 * @dsi_dbg_bus: dump dsi debug bus register
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]181 */
182static struct sde_dbg_base {
183 struct sde_dbg_evtlog *evtlog;
184 struct list_head reg_base_list;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]185 struct device *dev;
186 struct sde_dbg_power_ctrl power_ctrl;
187
188 struct sde_dbg_reg_base *req_dump_blks[SDE_DBG_BASE_MAX];
189
190 u32 panic_on_err;
191 struct work_struct dump_work;
192 bool work_panic;
193 u32 enable_reg_dump;
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]194
195 struct sde_dbg_sde_debug_bus dbgbus_sde;
196 struct sde_dbg_vbif_debug_bus dbgbus_vbif_rt;
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]197 bool dump_all;
Dhaval Patelf9f3ffe2017-08-16 16:03:10 -0700[diff] [blame]198 bool dsi_dbg_bus;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]199} sde_dbg_base;
200
201/* sde_dbg_base_evtlog - global pointer to main sde event log for macro use */
202struct sde_dbg_evtlog *sde_dbg_base_evtlog;
203
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]204static void _sde_debug_bus_xbar_dump(void __iomem *mem_base,
205 struct sde_debug_bus_entry *entry, u32 val)
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]206{
207 dev_err(sde_dbg_base.dev, "xbar 0x%x %d %d 0x%x\n",
208 entry->wr_addr, entry->block_id, entry->test_id, val);
209}
210
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]211static void _sde_debug_bus_lm_dump(void __iomem *mem_base,
212 struct sde_debug_bus_entry *entry, u32 val)
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]213{
214 if (!(val & 0xFFF000))
215 return;
216
217 dev_err(sde_dbg_base.dev, "lm 0x%x %d %d 0x%x\n",
218 entry->wr_addr, entry->block_id, entry->test_id, val);
219}
220
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]221static void _sde_debug_bus_ppb0_dump(void __iomem *mem_base,
222 struct sde_debug_bus_entry *entry, u32 val)
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]223{
224 if (!(val & BIT(15)))
225 return;
226
227 dev_err(sde_dbg_base.dev, "ppb0 0x%x %d %d 0x%x\n",
228 entry->wr_addr, entry->block_id, entry->test_id, val);
229}
230
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]231static void _sde_debug_bus_ppb1_dump(void __iomem *mem_base,
232 struct sde_debug_bus_entry *entry, u32 val)
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]233{
234 if (!(val & BIT(15)))
235 return;
236
237 dev_err(sde_dbg_base.dev, "ppb1 0x%x %d %d 0x%x\n",
238 entry->wr_addr, entry->block_id, entry->test_id, val);
239}
240
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]241static void _sde_debug_bus_axi_dump_sdm845(void __iomem *mem_base,
242 struct sde_debug_bus_entry *entry, u32 val)
243{
244 u32 status, i;
245
246 if (!mem_base || !entry)
247 return;
248
249 for (i = 0; i <= RSC_DEBUG_MUX_SEL_SDM845; i++) {
250 sde_rsc_debug_dump(i);
251
252 /* make sure that mux_sel updated */
253 wmb();
254
255 /* read status again after rsc routes the debug bus */
256 status = readl_relaxed(mem_base + DBGBUS_DSPP_STATUS);
257
258 dev_err(sde_dbg_base.dev, "rsc mux_sel:%d 0x%x %d %d 0x%x\n",
259 i, entry->wr_addr, entry->block_id,
260 entry->test_id, status);
261 }
262}
263
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]264static struct sde_debug_bus_entry dbg_bus_sde_8998[] = {
265
266 /* Unpack 0 sspp 0*/
267 { DBGBUS_SSPP0, 50, 2 },
268 { DBGBUS_SSPP0, 60, 2 },
269 { DBGBUS_SSPP0, 70, 2 },
270 { DBGBUS_SSPP0, 85, 2 },
271
272 /* Upack 0 sspp 1*/
273 { DBGBUS_SSPP1, 50, 2 },
274 { DBGBUS_SSPP1, 60, 2 },
275 { DBGBUS_SSPP1, 70, 2 },
276 { DBGBUS_SSPP1, 85, 2 },
277
278 /* scheduler */
279 { DBGBUS_DSPP, 130, 0 },
280 { DBGBUS_DSPP, 130, 1 },
281 { DBGBUS_DSPP, 130, 2 },
282 { DBGBUS_DSPP, 130, 3 },
283 { DBGBUS_DSPP, 130, 4 },
284 { DBGBUS_DSPP, 130, 5 },
285
286 /* qseed */
287 { DBGBUS_SSPP0, 6, 0},
288 { DBGBUS_SSPP0, 6, 1},
289 { DBGBUS_SSPP0, 26, 0},
290 { DBGBUS_SSPP0, 26, 1},
291 { DBGBUS_SSPP1, 6, 0},
292 { DBGBUS_SSPP1, 6, 1},
293 { DBGBUS_SSPP1, 26, 0},
294 { DBGBUS_SSPP1, 26, 1},
295
296 /* scale */
297 { DBGBUS_SSPP0, 16, 0},
298 { DBGBUS_SSPP0, 16, 1},
299 { DBGBUS_SSPP0, 36, 0},
300 { DBGBUS_SSPP0, 36, 1},
301 { DBGBUS_SSPP1, 16, 0},
302 { DBGBUS_SSPP1, 16, 1},
303 { DBGBUS_SSPP1, 36, 0},
304 { DBGBUS_SSPP1, 36, 1},
305
306 /* fetch sspp0 */
307
308 /* vig 0 */
309 { DBGBUS_SSPP0, 0, 0 },
310 { DBGBUS_SSPP0, 0, 1 },
311 { DBGBUS_SSPP0, 0, 2 },
312 { DBGBUS_SSPP0, 0, 3 },
313 { DBGBUS_SSPP0, 0, 4 },
314 { DBGBUS_SSPP0, 0, 5 },
315 { DBGBUS_SSPP0, 0, 6 },
316 { DBGBUS_SSPP0, 0, 7 },
317
318 { DBGBUS_SSPP0, 1, 0 },
319 { DBGBUS_SSPP0, 1, 1 },
320 { DBGBUS_SSPP0, 1, 2 },
321 { DBGBUS_SSPP0, 1, 3 },
322 { DBGBUS_SSPP0, 1, 4 },
323 { DBGBUS_SSPP0, 1, 5 },
324 { DBGBUS_SSPP0, 1, 6 },
325 { DBGBUS_SSPP0, 1, 7 },
326
327 { DBGBUS_SSPP0, 2, 0 },
328 { DBGBUS_SSPP0, 2, 1 },
329 { DBGBUS_SSPP0, 2, 2 },
330 { DBGBUS_SSPP0, 2, 3 },
331 { DBGBUS_SSPP0, 2, 4 },
332 { DBGBUS_SSPP0, 2, 5 },
333 { DBGBUS_SSPP0, 2, 6 },
334 { DBGBUS_SSPP0, 2, 7 },
335
336 { DBGBUS_SSPP0, 4, 0 },
337 { DBGBUS_SSPP0, 4, 1 },
338 { DBGBUS_SSPP0, 4, 2 },
339 { DBGBUS_SSPP0, 4, 3 },
340 { DBGBUS_SSPP0, 4, 4 },
341 { DBGBUS_SSPP0, 4, 5 },
342 { DBGBUS_SSPP0, 4, 6 },
343 { DBGBUS_SSPP0, 4, 7 },
344
345 { DBGBUS_SSPP0, 5, 0 },
346 { DBGBUS_SSPP0, 5, 1 },
347 { DBGBUS_SSPP0, 5, 2 },
348 { DBGBUS_SSPP0, 5, 3 },
349 { DBGBUS_SSPP0, 5, 4 },
350 { DBGBUS_SSPP0, 5, 5 },
351 { DBGBUS_SSPP0, 5, 6 },
352 { DBGBUS_SSPP0, 5, 7 },
353
354 /* vig 2 */
355 { DBGBUS_SSPP0, 20, 0 },
356 { DBGBUS_SSPP0, 20, 1 },
357 { DBGBUS_SSPP0, 20, 2 },
358 { DBGBUS_SSPP0, 20, 3 },
359 { DBGBUS_SSPP0, 20, 4 },
360 { DBGBUS_SSPP0, 20, 5 },
361 { DBGBUS_SSPP0, 20, 6 },
362 { DBGBUS_SSPP0, 20, 7 },
363
364 { DBGBUS_SSPP0, 21, 0 },
365 { DBGBUS_SSPP0, 21, 1 },
366 { DBGBUS_SSPP0, 21, 2 },
367 { DBGBUS_SSPP0, 21, 3 },
368 { DBGBUS_SSPP0, 21, 4 },
369 { DBGBUS_SSPP0, 21, 5 },
370 { DBGBUS_SSPP0, 21, 6 },
371 { DBGBUS_SSPP0, 21, 7 },
372
373 { DBGBUS_SSPP0, 22, 0 },
374 { DBGBUS_SSPP0, 22, 1 },
375 { DBGBUS_SSPP0, 22, 2 },
376 { DBGBUS_SSPP0, 22, 3 },
377 { DBGBUS_SSPP0, 22, 4 },
378 { DBGBUS_SSPP0, 22, 5 },
379 { DBGBUS_SSPP0, 22, 6 },
380 { DBGBUS_SSPP0, 22, 7 },
381
382 { DBGBUS_SSPP0, 24, 0 },
383 { DBGBUS_SSPP0, 24, 1 },
384 { DBGBUS_SSPP0, 24, 2 },
385 { DBGBUS_SSPP0, 24, 3 },
386 { DBGBUS_SSPP0, 24, 4 },
387 { DBGBUS_SSPP0, 24, 5 },
388 { DBGBUS_SSPP0, 24, 6 },
389 { DBGBUS_SSPP0, 24, 7 },
390
391 { DBGBUS_SSPP0, 25, 0 },
392 { DBGBUS_SSPP0, 25, 1 },
393 { DBGBUS_SSPP0, 25, 2 },
394 { DBGBUS_SSPP0, 25, 3 },
395 { DBGBUS_SSPP0, 25, 4 },
396 { DBGBUS_SSPP0, 25, 5 },
397 { DBGBUS_SSPP0, 25, 6 },
398 { DBGBUS_SSPP0, 25, 7 },
399
400 /* dma 2 */
401 { DBGBUS_SSPP0, 30, 0 },
402 { DBGBUS_SSPP0, 30, 1 },
403 { DBGBUS_SSPP0, 30, 2 },
404 { DBGBUS_SSPP0, 30, 3 },
405 { DBGBUS_SSPP0, 30, 4 },
406 { DBGBUS_SSPP0, 30, 5 },
407 { DBGBUS_SSPP0, 30, 6 },
408 { DBGBUS_SSPP0, 30, 7 },
409
410 { DBGBUS_SSPP0, 31, 0 },
411 { DBGBUS_SSPP0, 31, 1 },
412 { DBGBUS_SSPP0, 31, 2 },
413 { DBGBUS_SSPP0, 31, 3 },
414 { DBGBUS_SSPP0, 31, 4 },
415 { DBGBUS_SSPP0, 31, 5 },
416 { DBGBUS_SSPP0, 31, 6 },
417 { DBGBUS_SSPP0, 31, 7 },
418
419 { DBGBUS_SSPP0, 32, 0 },
420 { DBGBUS_SSPP0, 32, 1 },
421 { DBGBUS_SSPP0, 32, 2 },
422 { DBGBUS_SSPP0, 32, 3 },
423 { DBGBUS_SSPP0, 32, 4 },
424 { DBGBUS_SSPP0, 32, 5 },
425 { DBGBUS_SSPP0, 32, 6 },
426 { DBGBUS_SSPP0, 32, 7 },
427
428 { DBGBUS_SSPP0, 33, 0 },
429 { DBGBUS_SSPP0, 33, 1 },
430 { DBGBUS_SSPP0, 33, 2 },
431 { DBGBUS_SSPP0, 33, 3 },
432 { DBGBUS_SSPP0, 33, 4 },
433 { DBGBUS_SSPP0, 33, 5 },
434 { DBGBUS_SSPP0, 33, 6 },
435 { DBGBUS_SSPP0, 33, 7 },
436
437 { DBGBUS_SSPP0, 34, 0 },
438 { DBGBUS_SSPP0, 34, 1 },
439 { DBGBUS_SSPP0, 34, 2 },
440 { DBGBUS_SSPP0, 34, 3 },
441 { DBGBUS_SSPP0, 34, 4 },
442 { DBGBUS_SSPP0, 34, 5 },
443 { DBGBUS_SSPP0, 34, 6 },
444 { DBGBUS_SSPP0, 34, 7 },
445
446 { DBGBUS_SSPP0, 35, 0 },
447 { DBGBUS_SSPP0, 35, 1 },
448 { DBGBUS_SSPP0, 35, 2 },
449 { DBGBUS_SSPP0, 35, 3 },
450
451 /* dma 0 */
452 { DBGBUS_SSPP0, 40, 0 },
453 { DBGBUS_SSPP0, 40, 1 },
454 { DBGBUS_SSPP0, 40, 2 },
455 { DBGBUS_SSPP0, 40, 3 },
456 { DBGBUS_SSPP0, 40, 4 },
457 { DBGBUS_SSPP0, 40, 5 },
458 { DBGBUS_SSPP0, 40, 6 },
459 { DBGBUS_SSPP0, 40, 7 },
460
461 { DBGBUS_SSPP0, 41, 0 },
462 { DBGBUS_SSPP0, 41, 1 },
463 { DBGBUS_SSPP0, 41, 2 },
464 { DBGBUS_SSPP0, 41, 3 },
465 { DBGBUS_SSPP0, 41, 4 },
466 { DBGBUS_SSPP0, 41, 5 },
467 { DBGBUS_SSPP0, 41, 6 },
468 { DBGBUS_SSPP0, 41, 7 },
469
470 { DBGBUS_SSPP0, 42, 0 },
471 { DBGBUS_SSPP0, 42, 1 },
472 { DBGBUS_SSPP0, 42, 2 },
473 { DBGBUS_SSPP0, 42, 3 },
474 { DBGBUS_SSPP0, 42, 4 },
475 { DBGBUS_SSPP0, 42, 5 },
476 { DBGBUS_SSPP0, 42, 6 },
477 { DBGBUS_SSPP0, 42, 7 },
478
479 { DBGBUS_SSPP0, 44, 0 },
480 { DBGBUS_SSPP0, 44, 1 },
481 { DBGBUS_SSPP0, 44, 2 },
482 { DBGBUS_SSPP0, 44, 3 },
483 { DBGBUS_SSPP0, 44, 4 },
484 { DBGBUS_SSPP0, 44, 5 },
485 { DBGBUS_SSPP0, 44, 6 },
486 { DBGBUS_SSPP0, 44, 7 },
487
488 { DBGBUS_SSPP0, 45, 0 },
489 { DBGBUS_SSPP0, 45, 1 },
490 { DBGBUS_SSPP0, 45, 2 },
491 { DBGBUS_SSPP0, 45, 3 },
492 { DBGBUS_SSPP0, 45, 4 },
493 { DBGBUS_SSPP0, 45, 5 },
494 { DBGBUS_SSPP0, 45, 6 },
495 { DBGBUS_SSPP0, 45, 7 },
496
497 /* fetch sspp1 */
498 /* vig 1 */
499 { DBGBUS_SSPP1, 0, 0 },
500 { DBGBUS_SSPP1, 0, 1 },
501 { DBGBUS_SSPP1, 0, 2 },
502 { DBGBUS_SSPP1, 0, 3 },
503 { DBGBUS_SSPP1, 0, 4 },
504 { DBGBUS_SSPP1, 0, 5 },
505 { DBGBUS_SSPP1, 0, 6 },
506 { DBGBUS_SSPP1, 0, 7 },
507
508 { DBGBUS_SSPP1, 1, 0 },
509 { DBGBUS_SSPP1, 1, 1 },
510 { DBGBUS_SSPP1, 1, 2 },
511 { DBGBUS_SSPP1, 1, 3 },
512 { DBGBUS_SSPP1, 1, 4 },
513 { DBGBUS_SSPP1, 1, 5 },
514 { DBGBUS_SSPP1, 1, 6 },
515 { DBGBUS_SSPP1, 1, 7 },
516
517 { DBGBUS_SSPP1, 2, 0 },
518 { DBGBUS_SSPP1, 2, 1 },
519 { DBGBUS_SSPP1, 2, 2 },
520 { DBGBUS_SSPP1, 2, 3 },
521 { DBGBUS_SSPP1, 2, 4 },
522 { DBGBUS_SSPP1, 2, 5 },
523 { DBGBUS_SSPP1, 2, 6 },
524 { DBGBUS_SSPP1, 2, 7 },
525
526 { DBGBUS_SSPP1, 4, 0 },
527 { DBGBUS_SSPP1, 4, 1 },
528 { DBGBUS_SSPP1, 4, 2 },
529 { DBGBUS_SSPP1, 4, 3 },
530 { DBGBUS_SSPP1, 4, 4 },
531 { DBGBUS_SSPP1, 4, 5 },
532 { DBGBUS_SSPP1, 4, 6 },
533 { DBGBUS_SSPP1, 4, 7 },
534
535 { DBGBUS_SSPP1, 5, 0 },
536 { DBGBUS_SSPP1, 5, 1 },
537 { DBGBUS_SSPP1, 5, 2 },
538 { DBGBUS_SSPP1, 5, 3 },
539 { DBGBUS_SSPP1, 5, 4 },
540 { DBGBUS_SSPP1, 5, 5 },
541 { DBGBUS_SSPP1, 5, 6 },
542 { DBGBUS_SSPP1, 5, 7 },
543
544 /* vig 3 */
545 { DBGBUS_SSPP1, 20, 0 },
546 { DBGBUS_SSPP1, 20, 1 },
547 { DBGBUS_SSPP1, 20, 2 },
548 { DBGBUS_SSPP1, 20, 3 },
549 { DBGBUS_SSPP1, 20, 4 },
550 { DBGBUS_SSPP1, 20, 5 },
551 { DBGBUS_SSPP1, 20, 6 },
552 { DBGBUS_SSPP1, 20, 7 },
553
554 { DBGBUS_SSPP1, 21, 0 },
555 { DBGBUS_SSPP1, 21, 1 },
556 { DBGBUS_SSPP1, 21, 2 },
557 { DBGBUS_SSPP1, 21, 3 },
558 { DBGBUS_SSPP1, 21, 4 },
559 { DBGBUS_SSPP1, 21, 5 },
560 { DBGBUS_SSPP1, 21, 6 },
561 { DBGBUS_SSPP1, 21, 7 },
562
563 { DBGBUS_SSPP1, 22, 0 },
564 { DBGBUS_SSPP1, 22, 1 },
565 { DBGBUS_SSPP1, 22, 2 },
566 { DBGBUS_SSPP1, 22, 3 },
567 { DBGBUS_SSPP1, 22, 4 },
568 { DBGBUS_SSPP1, 22, 5 },
569 { DBGBUS_SSPP1, 22, 6 },
570 { DBGBUS_SSPP1, 22, 7 },
571
572 { DBGBUS_SSPP1, 24, 0 },
573 { DBGBUS_SSPP1, 24, 1 },
574 { DBGBUS_SSPP1, 24, 2 },
575 { DBGBUS_SSPP1, 24, 3 },
576 { DBGBUS_SSPP1, 24, 4 },
577 { DBGBUS_SSPP1, 24, 5 },
578 { DBGBUS_SSPP1, 24, 6 },
579 { DBGBUS_SSPP1, 24, 7 },
580
581 { DBGBUS_SSPP1, 25, 0 },
582 { DBGBUS_SSPP1, 25, 1 },
583 { DBGBUS_SSPP1, 25, 2 },
584 { DBGBUS_SSPP1, 25, 3 },
585 { DBGBUS_SSPP1, 25, 4 },
586 { DBGBUS_SSPP1, 25, 5 },
587 { DBGBUS_SSPP1, 25, 6 },
588 { DBGBUS_SSPP1, 25, 7 },
589
590 /* dma 3 */
591 { DBGBUS_SSPP1, 30, 0 },
592 { DBGBUS_SSPP1, 30, 1 },
593 { DBGBUS_SSPP1, 30, 2 },
594 { DBGBUS_SSPP1, 30, 3 },
595 { DBGBUS_SSPP1, 30, 4 },
596 { DBGBUS_SSPP1, 30, 5 },
597 { DBGBUS_SSPP1, 30, 6 },
598 { DBGBUS_SSPP1, 30, 7 },
599
600 { DBGBUS_SSPP1, 31, 0 },
601 { DBGBUS_SSPP1, 31, 1 },
602 { DBGBUS_SSPP1, 31, 2 },
603 { DBGBUS_SSPP1, 31, 3 },
604 { DBGBUS_SSPP1, 31, 4 },
605 { DBGBUS_SSPP1, 31, 5 },
606 { DBGBUS_SSPP1, 31, 6 },
607 { DBGBUS_SSPP1, 31, 7 },
608
609 { DBGBUS_SSPP1, 32, 0 },
610 { DBGBUS_SSPP1, 32, 1 },
611 { DBGBUS_SSPP1, 32, 2 },
612 { DBGBUS_SSPP1, 32, 3 },
613 { DBGBUS_SSPP1, 32, 4 },
614 { DBGBUS_SSPP1, 32, 5 },
615 { DBGBUS_SSPP1, 32, 6 },
616 { DBGBUS_SSPP1, 32, 7 },
617
618 { DBGBUS_SSPP1, 33, 0 },
619 { DBGBUS_SSPP1, 33, 1 },
620 { DBGBUS_SSPP1, 33, 2 },
621 { DBGBUS_SSPP1, 33, 3 },
622 { DBGBUS_SSPP1, 33, 4 },
623 { DBGBUS_SSPP1, 33, 5 },
624 { DBGBUS_SSPP1, 33, 6 },
625 { DBGBUS_SSPP1, 33, 7 },
626
627 { DBGBUS_SSPP1, 34, 0 },
628 { DBGBUS_SSPP1, 34, 1 },
629 { DBGBUS_SSPP1, 34, 2 },
630 { DBGBUS_SSPP1, 34, 3 },
631 { DBGBUS_SSPP1, 34, 4 },
632 { DBGBUS_SSPP1, 34, 5 },
633 { DBGBUS_SSPP1, 34, 6 },
634 { DBGBUS_SSPP1, 34, 7 },
635
636 { DBGBUS_SSPP1, 35, 0 },
637 { DBGBUS_SSPP1, 35, 1 },
638 { DBGBUS_SSPP1, 35, 2 },
639
640 /* dma 1 */
641 { DBGBUS_SSPP1, 40, 0 },
642 { DBGBUS_SSPP1, 40, 1 },
643 { DBGBUS_SSPP1, 40, 2 },
644 { DBGBUS_SSPP1, 40, 3 },
645 { DBGBUS_SSPP1, 40, 4 },
646 { DBGBUS_SSPP1, 40, 5 },
647 { DBGBUS_SSPP1, 40, 6 },
648 { DBGBUS_SSPP1, 40, 7 },
649
650 { DBGBUS_SSPP1, 41, 0 },
651 { DBGBUS_SSPP1, 41, 1 },
652 { DBGBUS_SSPP1, 41, 2 },
653 { DBGBUS_SSPP1, 41, 3 },
654 { DBGBUS_SSPP1, 41, 4 },
655 { DBGBUS_SSPP1, 41, 5 },
656 { DBGBUS_SSPP1, 41, 6 },
657 { DBGBUS_SSPP1, 41, 7 },
658
659 { DBGBUS_SSPP1, 42, 0 },
660 { DBGBUS_SSPP1, 42, 1 },
661 { DBGBUS_SSPP1, 42, 2 },
662 { DBGBUS_SSPP1, 42, 3 },
663 { DBGBUS_SSPP1, 42, 4 },
664 { DBGBUS_SSPP1, 42, 5 },
665 { DBGBUS_SSPP1, 42, 6 },
666 { DBGBUS_SSPP1, 42, 7 },
667
668 { DBGBUS_SSPP1, 44, 0 },
669 { DBGBUS_SSPP1, 44, 1 },
670 { DBGBUS_SSPP1, 44, 2 },
671 { DBGBUS_SSPP1, 44, 3 },
672 { DBGBUS_SSPP1, 44, 4 },
673 { DBGBUS_SSPP1, 44, 5 },
674 { DBGBUS_SSPP1, 44, 6 },
675 { DBGBUS_SSPP1, 44, 7 },
676
677 { DBGBUS_SSPP1, 45, 0 },
678 { DBGBUS_SSPP1, 45, 1 },
679 { DBGBUS_SSPP1, 45, 2 },
680 { DBGBUS_SSPP1, 45, 3 },
681 { DBGBUS_SSPP1, 45, 4 },
682 { DBGBUS_SSPP1, 45, 5 },
683 { DBGBUS_SSPP1, 45, 6 },
684 { DBGBUS_SSPP1, 45, 7 },
685
686 /* cursor 1 */
687 { DBGBUS_SSPP1, 80, 0 },
688 { DBGBUS_SSPP1, 80, 1 },
689 { DBGBUS_SSPP1, 80, 2 },
690 { DBGBUS_SSPP1, 80, 3 },
691 { DBGBUS_SSPP1, 80, 4 },
692 { DBGBUS_SSPP1, 80, 5 },
693 { DBGBUS_SSPP1, 80, 6 },
694 { DBGBUS_SSPP1, 80, 7 },
695
696 { DBGBUS_SSPP1, 81, 0 },
697 { DBGBUS_SSPP1, 81, 1 },
698 { DBGBUS_SSPP1, 81, 2 },
699 { DBGBUS_SSPP1, 81, 3 },
700 { DBGBUS_SSPP1, 81, 4 },
701 { DBGBUS_SSPP1, 81, 5 },
702 { DBGBUS_SSPP1, 81, 6 },
703 { DBGBUS_SSPP1, 81, 7 },
704
705 { DBGBUS_SSPP1, 82, 0 },
706 { DBGBUS_SSPP1, 82, 1 },
707 { DBGBUS_SSPP1, 82, 2 },
708 { DBGBUS_SSPP1, 82, 3 },
709 { DBGBUS_SSPP1, 82, 4 },
710 { DBGBUS_SSPP1, 82, 5 },
711 { DBGBUS_SSPP1, 82, 6 },
712 { DBGBUS_SSPP1, 82, 7 },
713
714 { DBGBUS_SSPP1, 83, 0 },
715 { DBGBUS_SSPP1, 83, 1 },
716 { DBGBUS_SSPP1, 83, 2 },
717 { DBGBUS_SSPP1, 83, 3 },
718 { DBGBUS_SSPP1, 83, 4 },
719 { DBGBUS_SSPP1, 83, 5 },
720 { DBGBUS_SSPP1, 83, 6 },
721 { DBGBUS_SSPP1, 83, 7 },
722
723 { DBGBUS_SSPP1, 84, 0 },
724 { DBGBUS_SSPP1, 84, 1 },
725 { DBGBUS_SSPP1, 84, 2 },
726 { DBGBUS_SSPP1, 84, 3 },
727 { DBGBUS_SSPP1, 84, 4 },
728 { DBGBUS_SSPP1, 84, 5 },
729 { DBGBUS_SSPP1, 84, 6 },
730 { DBGBUS_SSPP1, 84, 7 },
731
732 /* dspp */
733 { DBGBUS_DSPP, 13, 0 },
734 { DBGBUS_DSPP, 19, 0 },
735 { DBGBUS_DSPP, 14, 0 },
736 { DBGBUS_DSPP, 14, 1 },
737 { DBGBUS_DSPP, 14, 3 },
738 { DBGBUS_DSPP, 20, 0 },
739 { DBGBUS_DSPP, 20, 1 },
740 { DBGBUS_DSPP, 20, 3 },
741
742 /* ppb_0 */
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]743 { DBGBUS_DSPP, 31, 0, _sde_debug_bus_ppb0_dump },
744 { DBGBUS_DSPP, 33, 0, _sde_debug_bus_ppb0_dump },
745 { DBGBUS_DSPP, 35, 0, _sde_debug_bus_ppb0_dump },
746 { DBGBUS_DSPP, 42, 0, _sde_debug_bus_ppb0_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]747
748 /* ppb_1 */
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]749 { DBGBUS_DSPP, 32, 0, _sde_debug_bus_ppb1_dump },
750 { DBGBUS_DSPP, 34, 0, _sde_debug_bus_ppb1_dump },
751 { DBGBUS_DSPP, 36, 0, _sde_debug_bus_ppb1_dump },
752 { DBGBUS_DSPP, 43, 0, _sde_debug_bus_ppb1_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]753
754 /* lm_lut */
755 { DBGBUS_DSPP, 109, 0 },
756 { DBGBUS_DSPP, 105, 0 },
757 { DBGBUS_DSPP, 103, 0 },
758
759 /* tear-check */
760 { DBGBUS_PERIPH, 63, 0 },
761 { DBGBUS_PERIPH, 64, 0 },
762 { DBGBUS_PERIPH, 65, 0 },
763 { DBGBUS_PERIPH, 73, 0 },
764 { DBGBUS_PERIPH, 74, 0 },
765
766 /* crossbar */
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]767 { DBGBUS_DSPP, 0, 0, _sde_debug_bus_xbar_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]768
769 /* rotator */
770 { DBGBUS_DSPP, 9, 0},
771
772 /* blend */
773 /* LM0 */
774 { DBGBUS_DSPP, 63, 0},
775 { DBGBUS_DSPP, 63, 1},
776 { DBGBUS_DSPP, 63, 2},
777 { DBGBUS_DSPP, 63, 3},
778 { DBGBUS_DSPP, 63, 4},
779 { DBGBUS_DSPP, 63, 5},
780 { DBGBUS_DSPP, 63, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]781 { DBGBUS_DSPP, 63, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]782
783 { DBGBUS_DSPP, 64, 0},
784 { DBGBUS_DSPP, 64, 1},
785 { DBGBUS_DSPP, 64, 2},
786 { DBGBUS_DSPP, 64, 3},
787 { DBGBUS_DSPP, 64, 4},
788 { DBGBUS_DSPP, 64, 5},
789 { DBGBUS_DSPP, 64, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]790 { DBGBUS_DSPP, 64, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]791
792 { DBGBUS_DSPP, 65, 0},
793 { DBGBUS_DSPP, 65, 1},
794 { DBGBUS_DSPP, 65, 2},
795 { DBGBUS_DSPP, 65, 3},
796 { DBGBUS_DSPP, 65, 4},
797 { DBGBUS_DSPP, 65, 5},
798 { DBGBUS_DSPP, 65, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]799 { DBGBUS_DSPP, 65, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]800
801 { DBGBUS_DSPP, 66, 0},
802 { DBGBUS_DSPP, 66, 1},
803 { DBGBUS_DSPP, 66, 2},
804 { DBGBUS_DSPP, 66, 3},
805 { DBGBUS_DSPP, 66, 4},
806 { DBGBUS_DSPP, 66, 5},
807 { DBGBUS_DSPP, 66, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]808 { DBGBUS_DSPP, 66, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]809
810 { DBGBUS_DSPP, 67, 0},
811 { DBGBUS_DSPP, 67, 1},
812 { DBGBUS_DSPP, 67, 2},
813 { DBGBUS_DSPP, 67, 3},
814 { DBGBUS_DSPP, 67, 4},
815 { DBGBUS_DSPP, 67, 5},
816 { DBGBUS_DSPP, 67, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]817 { DBGBUS_DSPP, 67, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]818
819 { DBGBUS_DSPP, 68, 0},
820 { DBGBUS_DSPP, 68, 1},
821 { DBGBUS_DSPP, 68, 2},
822 { DBGBUS_DSPP, 68, 3},
823 { DBGBUS_DSPP, 68, 4},
824 { DBGBUS_DSPP, 68, 5},
825 { DBGBUS_DSPP, 68, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]826 { DBGBUS_DSPP, 68, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]827
828 { DBGBUS_DSPP, 69, 0},
829 { DBGBUS_DSPP, 69, 1},
830 { DBGBUS_DSPP, 69, 2},
831 { DBGBUS_DSPP, 69, 3},
832 { DBGBUS_DSPP, 69, 4},
833 { DBGBUS_DSPP, 69, 5},
834 { DBGBUS_DSPP, 69, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]835 { DBGBUS_DSPP, 69, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]836
837 /* LM1 */
838 { DBGBUS_DSPP, 70, 0},
839 { DBGBUS_DSPP, 70, 1},
840 { DBGBUS_DSPP, 70, 2},
841 { DBGBUS_DSPP, 70, 3},
842 { DBGBUS_DSPP, 70, 4},
843 { DBGBUS_DSPP, 70, 5},
844 { DBGBUS_DSPP, 70, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]845 { DBGBUS_DSPP, 70, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]846
847 { DBGBUS_DSPP, 71, 0},
848 { DBGBUS_DSPP, 71, 1},
849 { DBGBUS_DSPP, 71, 2},
850 { DBGBUS_DSPP, 71, 3},
851 { DBGBUS_DSPP, 71, 4},
852 { DBGBUS_DSPP, 71, 5},
853 { DBGBUS_DSPP, 71, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]854 { DBGBUS_DSPP, 71, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]855
856 { DBGBUS_DSPP, 72, 0},
857 { DBGBUS_DSPP, 72, 1},
858 { DBGBUS_DSPP, 72, 2},
859 { DBGBUS_DSPP, 72, 3},
860 { DBGBUS_DSPP, 72, 4},
861 { DBGBUS_DSPP, 72, 5},
862 { DBGBUS_DSPP, 72, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]863 { DBGBUS_DSPP, 72, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]864
865 { DBGBUS_DSPP, 73, 0},
866 { DBGBUS_DSPP, 73, 1},
867 { DBGBUS_DSPP, 73, 2},
868 { DBGBUS_DSPP, 73, 3},
869 { DBGBUS_DSPP, 73, 4},
870 { DBGBUS_DSPP, 73, 5},
871 { DBGBUS_DSPP, 73, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]872 { DBGBUS_DSPP, 73, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]873
874 { DBGBUS_DSPP, 74, 0},
875 { DBGBUS_DSPP, 74, 1},
876 { DBGBUS_DSPP, 74, 2},
877 { DBGBUS_DSPP, 74, 3},
878 { DBGBUS_DSPP, 74, 4},
879 { DBGBUS_DSPP, 74, 5},
880 { DBGBUS_DSPP, 74, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]881 { DBGBUS_DSPP, 74, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]882
883 { DBGBUS_DSPP, 75, 0},
884 { DBGBUS_DSPP, 75, 1},
885 { DBGBUS_DSPP, 75, 2},
886 { DBGBUS_DSPP, 75, 3},
887 { DBGBUS_DSPP, 75, 4},
888 { DBGBUS_DSPP, 75, 5},
889 { DBGBUS_DSPP, 75, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]890 { DBGBUS_DSPP, 75, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]891
892 { DBGBUS_DSPP, 76, 0},
893 { DBGBUS_DSPP, 76, 1},
894 { DBGBUS_DSPP, 76, 2},
895 { DBGBUS_DSPP, 76, 3},
896 { DBGBUS_DSPP, 76, 4},
897 { DBGBUS_DSPP, 76, 5},
898 { DBGBUS_DSPP, 76, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]899 { DBGBUS_DSPP, 76, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]900
901 /* LM2 */
902 { DBGBUS_DSPP, 77, 0},
903 { DBGBUS_DSPP, 77, 1},
904 { DBGBUS_DSPP, 77, 2},
905 { DBGBUS_DSPP, 77, 3},
906 { DBGBUS_DSPP, 77, 4},
907 { DBGBUS_DSPP, 77, 5},
908 { DBGBUS_DSPP, 77, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]909 { DBGBUS_DSPP, 77, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]910
911 { DBGBUS_DSPP, 78, 0},
912 { DBGBUS_DSPP, 78, 1},
913 { DBGBUS_DSPP, 78, 2},
914 { DBGBUS_DSPP, 78, 3},
915 { DBGBUS_DSPP, 78, 4},
916 { DBGBUS_DSPP, 78, 5},
917 { DBGBUS_DSPP, 78, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]918 { DBGBUS_DSPP, 78, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]919
920 { DBGBUS_DSPP, 79, 0},
921 { DBGBUS_DSPP, 79, 1},
922 { DBGBUS_DSPP, 79, 2},
923 { DBGBUS_DSPP, 79, 3},
924 { DBGBUS_DSPP, 79, 4},
925 { DBGBUS_DSPP, 79, 5},
926 { DBGBUS_DSPP, 79, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]927 { DBGBUS_DSPP, 79, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]928
929 { DBGBUS_DSPP, 80, 0},
930 { DBGBUS_DSPP, 80, 1},
931 { DBGBUS_DSPP, 80, 2},
932 { DBGBUS_DSPP, 80, 3},
933 { DBGBUS_DSPP, 80, 4},
934 { DBGBUS_DSPP, 80, 5},
935 { DBGBUS_DSPP, 80, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]936 { DBGBUS_DSPP, 80, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]937
938 { DBGBUS_DSPP, 81, 0},
939 { DBGBUS_DSPP, 81, 1},
940 { DBGBUS_DSPP, 81, 2},
941 { DBGBUS_DSPP, 81, 3},
942 { DBGBUS_DSPP, 81, 4},
943 { DBGBUS_DSPP, 81, 5},
944 { DBGBUS_DSPP, 81, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]945 { DBGBUS_DSPP, 81, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]946
947 { DBGBUS_DSPP, 82, 0},
948 { DBGBUS_DSPP, 82, 1},
949 { DBGBUS_DSPP, 82, 2},
950 { DBGBUS_DSPP, 82, 3},
951 { DBGBUS_DSPP, 82, 4},
952 { DBGBUS_DSPP, 82, 5},
953 { DBGBUS_DSPP, 82, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]954 { DBGBUS_DSPP, 82, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]955
956 { DBGBUS_DSPP, 83, 0},
957 { DBGBUS_DSPP, 83, 1},
958 { DBGBUS_DSPP, 83, 2},
959 { DBGBUS_DSPP, 83, 3},
960 { DBGBUS_DSPP, 83, 4},
961 { DBGBUS_DSPP, 83, 5},
962 { DBGBUS_DSPP, 83, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]963 { DBGBUS_DSPP, 83, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]964
965 /* csc */
966 { DBGBUS_SSPP0, 7, 0},
967 { DBGBUS_SSPP0, 7, 1},
968 { DBGBUS_SSPP0, 27, 0},
969 { DBGBUS_SSPP0, 27, 1},
970 { DBGBUS_SSPP1, 7, 0},
971 { DBGBUS_SSPP1, 7, 1},
972 { DBGBUS_SSPP1, 27, 0},
973 { DBGBUS_SSPP1, 27, 1},
974
975 /* pcc */
976 { DBGBUS_SSPP0, 3, 3},
977 { DBGBUS_SSPP0, 23, 3},
978 { DBGBUS_SSPP0, 33, 3},
979 { DBGBUS_SSPP0, 43, 3},
980 { DBGBUS_SSPP1, 3, 3},
981 { DBGBUS_SSPP1, 23, 3},
982 { DBGBUS_SSPP1, 33, 3},
983 { DBGBUS_SSPP1, 43, 3},
984
985 /* spa */
986 { DBGBUS_SSPP0, 8, 0},
987 { DBGBUS_SSPP0, 28, 0},
988 { DBGBUS_SSPP1, 8, 0},
989 { DBGBUS_SSPP1, 28, 0},
990 { DBGBUS_DSPP, 13, 0},
991 { DBGBUS_DSPP, 19, 0},
992
993 /* igc */
994 { DBGBUS_SSPP0, 9, 0},
995 { DBGBUS_SSPP0, 9, 1},
996 { DBGBUS_SSPP0, 9, 3},
997 { DBGBUS_SSPP0, 29, 0},
998 { DBGBUS_SSPP0, 29, 1},
999 { DBGBUS_SSPP0, 29, 3},
1000 { DBGBUS_SSPP0, 17, 0},
1001 { DBGBUS_SSPP0, 17, 1},
1002 { DBGBUS_SSPP0, 17, 3},
1003 { DBGBUS_SSPP0, 37, 0},
1004 { DBGBUS_SSPP0, 37, 1},
1005 { DBGBUS_SSPP0, 37, 3},
1006 { DBGBUS_SSPP0, 46, 0},
1007 { DBGBUS_SSPP0, 46, 1},
1008 { DBGBUS_SSPP0, 46, 3},
1009
1010 { DBGBUS_SSPP1, 9, 0},
1011 { DBGBUS_SSPP1, 9, 1},
1012 { DBGBUS_SSPP1, 9, 3},
1013 { DBGBUS_SSPP1, 29, 0},
1014 { DBGBUS_SSPP1, 29, 1},
1015 { DBGBUS_SSPP1, 29, 3},
1016 { DBGBUS_SSPP1, 17, 0},
1017 { DBGBUS_SSPP1, 17, 1},
1018 { DBGBUS_SSPP1, 17, 3},
1019 { DBGBUS_SSPP1, 37, 0},
1020 { DBGBUS_SSPP1, 37, 1},
1021 { DBGBUS_SSPP1, 37, 3},
1022 { DBGBUS_SSPP1, 46, 0},
1023 { DBGBUS_SSPP1, 46, 1},
1024 { DBGBUS_SSPP1, 46, 3},
1025
1026 { DBGBUS_DSPP, 14, 0},
1027 { DBGBUS_DSPP, 14, 1},
1028 { DBGBUS_DSPP, 14, 3},
1029 { DBGBUS_DSPP, 20, 0},
1030 { DBGBUS_DSPP, 20, 1},
1031 { DBGBUS_DSPP, 20, 3},
1032
1033 { DBGBUS_PERIPH, 60, 0},
1034};
1035
1036static struct sde_debug_bus_entry dbg_bus_sde_sdm845[] = {
1037
1038 /* Unpack 0 sspp 0*/
1039 { DBGBUS_SSPP0, 50, 2 },
1040 { DBGBUS_SSPP0, 60, 2 },
1041 { DBGBUS_SSPP0, 70, 2 },
1042
1043 /* Upack 0 sspp 1*/
1044 { DBGBUS_SSPP1, 50, 2 },
1045 { DBGBUS_SSPP1, 60, 2 },
1046 { DBGBUS_SSPP1, 70, 2 },
1047
1048 /* scheduler */
1049 { DBGBUS_DSPP, 130, 0 },
1050 { DBGBUS_DSPP, 130, 1 },
1051 { DBGBUS_DSPP, 130, 2 },
1052 { DBGBUS_DSPP, 130, 3 },
1053 { DBGBUS_DSPP, 130, 4 },
1054 { DBGBUS_DSPP, 130, 5 },
1055
1056 /* qseed */
1057 { DBGBUS_SSPP0, 6, 0},
1058 { DBGBUS_SSPP0, 6, 1},
1059 { DBGBUS_SSPP0, 26, 0},
1060 { DBGBUS_SSPP0, 26, 1},
1061 { DBGBUS_SSPP1, 6, 0},
1062 { DBGBUS_SSPP1, 6, 1},
1063 { DBGBUS_SSPP1, 26, 0},
1064 { DBGBUS_SSPP1, 26, 1},
1065
1066 /* scale */
1067 { DBGBUS_SSPP0, 16, 0},
1068 { DBGBUS_SSPP0, 16, 1},
1069 { DBGBUS_SSPP0, 36, 0},
1070 { DBGBUS_SSPP0, 36, 1},
1071 { DBGBUS_SSPP1, 16, 0},
1072 { DBGBUS_SSPP1, 16, 1},
1073 { DBGBUS_SSPP1, 36, 0},
1074 { DBGBUS_SSPP1, 36, 1},
1075
1076 /* fetch sspp0 */
1077
1078 /* vig 0 */
1079 { DBGBUS_SSPP0, 0, 0 },
1080 { DBGBUS_SSPP0, 0, 1 },
1081 { DBGBUS_SSPP0, 0, 2 },
1082 { DBGBUS_SSPP0, 0, 3 },
1083 { DBGBUS_SSPP0, 0, 4 },
1084 { DBGBUS_SSPP0, 0, 5 },
1085 { DBGBUS_SSPP0, 0, 6 },
1086 { DBGBUS_SSPP0, 0, 7 },
1087
1088 { DBGBUS_SSPP0, 1, 0 },
1089 { DBGBUS_SSPP0, 1, 1 },
1090 { DBGBUS_SSPP0, 1, 2 },
1091 { DBGBUS_SSPP0, 1, 3 },
1092 { DBGBUS_SSPP0, 1, 4 },
1093 { DBGBUS_SSPP0, 1, 5 },
1094 { DBGBUS_SSPP0, 1, 6 },
1095 { DBGBUS_SSPP0, 1, 7 },
1096
1097 { DBGBUS_SSPP0, 2, 0 },
1098 { DBGBUS_SSPP0, 2, 1 },
1099 { DBGBUS_SSPP0, 2, 2 },
1100 { DBGBUS_SSPP0, 2, 3 },
1101 { DBGBUS_SSPP0, 2, 4 },
1102 { DBGBUS_SSPP0, 2, 5 },
1103 { DBGBUS_SSPP0, 2, 6 },
1104 { DBGBUS_SSPP0, 2, 7 },
1105
1106 { DBGBUS_SSPP0, 4, 0 },
1107 { DBGBUS_SSPP0, 4, 1 },
1108 { DBGBUS_SSPP0, 4, 2 },
1109 { DBGBUS_SSPP0, 4, 3 },
1110 { DBGBUS_SSPP0, 4, 4 },
1111 { DBGBUS_SSPP0, 4, 5 },
1112 { DBGBUS_SSPP0, 4, 6 },
1113 { DBGBUS_SSPP0, 4, 7 },
1114
1115 { DBGBUS_SSPP0, 5, 0 },
1116 { DBGBUS_SSPP0, 5, 1 },
1117 { DBGBUS_SSPP0, 5, 2 },
1118 { DBGBUS_SSPP0, 5, 3 },
1119 { DBGBUS_SSPP0, 5, 4 },
1120 { DBGBUS_SSPP0, 5, 5 },
1121 { DBGBUS_SSPP0, 5, 6 },
1122 { DBGBUS_SSPP0, 5, 7 },
1123
1124 /* vig 2 */
1125 { DBGBUS_SSPP0, 20, 0 },
1126 { DBGBUS_SSPP0, 20, 1 },
1127 { DBGBUS_SSPP0, 20, 2 },
1128 { DBGBUS_SSPP0, 20, 3 },
1129 { DBGBUS_SSPP0, 20, 4 },
1130 { DBGBUS_SSPP0, 20, 5 },
1131 { DBGBUS_SSPP0, 20, 6 },
1132 { DBGBUS_SSPP0, 20, 7 },
1133
1134 { DBGBUS_SSPP0, 21, 0 },
1135 { DBGBUS_SSPP0, 21, 1 },
1136 { DBGBUS_SSPP0, 21, 2 },
1137 { DBGBUS_SSPP0, 21, 3 },
1138 { DBGBUS_SSPP0, 21, 4 },
1139 { DBGBUS_SSPP0, 21, 5 },
1140 { DBGBUS_SSPP0, 21, 6 },
1141 { DBGBUS_SSPP0, 21, 7 },
1142
1143 { DBGBUS_SSPP0, 22, 0 },
1144 { DBGBUS_SSPP0, 22, 1 },
1145 { DBGBUS_SSPP0, 22, 2 },
1146 { DBGBUS_SSPP0, 22, 3 },
1147 { DBGBUS_SSPP0, 22, 4 },
1148 { DBGBUS_SSPP0, 22, 5 },
1149 { DBGBUS_SSPP0, 22, 6 },
1150 { DBGBUS_SSPP0, 22, 7 },
1151
1152 { DBGBUS_SSPP0, 24, 0 },
1153 { DBGBUS_SSPP0, 24, 1 },
1154 { DBGBUS_SSPP0, 24, 2 },
1155 { DBGBUS_SSPP0, 24, 3 },
1156 { DBGBUS_SSPP0, 24, 4 },
1157 { DBGBUS_SSPP0, 24, 5 },
1158 { DBGBUS_SSPP0, 24, 6 },
1159 { DBGBUS_SSPP0, 24, 7 },
1160
1161 { DBGBUS_SSPP0, 25, 0 },
1162 { DBGBUS_SSPP0, 25, 1 },
1163 { DBGBUS_SSPP0, 25, 2 },
1164 { DBGBUS_SSPP0, 25, 3 },
1165 { DBGBUS_SSPP0, 25, 4 },
1166 { DBGBUS_SSPP0, 25, 5 },
1167 { DBGBUS_SSPP0, 25, 6 },
1168 { DBGBUS_SSPP0, 25, 7 },
1169
1170 /* dma 2 */
1171 { DBGBUS_SSPP0, 30, 0 },
1172 { DBGBUS_SSPP0, 30, 1 },
1173 { DBGBUS_SSPP0, 30, 2 },
1174 { DBGBUS_SSPP0, 30, 3 },
1175 { DBGBUS_SSPP0, 30, 4 },
1176 { DBGBUS_SSPP0, 30, 5 },
1177 { DBGBUS_SSPP0, 30, 6 },
1178 { DBGBUS_SSPP0, 30, 7 },
1179
1180 { DBGBUS_SSPP0, 31, 0 },
1181 { DBGBUS_SSPP0, 31, 1 },
1182 { DBGBUS_SSPP0, 31, 2 },
1183 { DBGBUS_SSPP0, 31, 3 },
1184 { DBGBUS_SSPP0, 31, 4 },
1185 { DBGBUS_SSPP0, 31, 5 },
1186 { DBGBUS_SSPP0, 31, 6 },
1187 { DBGBUS_SSPP0, 31, 7 },
1188
1189 { DBGBUS_SSPP0, 32, 0 },
1190 { DBGBUS_SSPP0, 32, 1 },
1191 { DBGBUS_SSPP0, 32, 2 },
1192 { DBGBUS_SSPP0, 32, 3 },
1193 { DBGBUS_SSPP0, 32, 4 },
1194 { DBGBUS_SSPP0, 32, 5 },
1195 { DBGBUS_SSPP0, 32, 6 },
1196 { DBGBUS_SSPP0, 32, 7 },
1197
1198 { DBGBUS_SSPP0, 33, 0 },
1199 { DBGBUS_SSPP0, 33, 1 },
1200 { DBGBUS_SSPP0, 33, 2 },
1201 { DBGBUS_SSPP0, 33, 3 },
1202 { DBGBUS_SSPP0, 33, 4 },
1203 { DBGBUS_SSPP0, 33, 5 },
1204 { DBGBUS_SSPP0, 33, 6 },
1205 { DBGBUS_SSPP0, 33, 7 },
1206
1207 { DBGBUS_SSPP0, 34, 0 },
1208 { DBGBUS_SSPP0, 34, 1 },
1209 { DBGBUS_SSPP0, 34, 2 },
1210 { DBGBUS_SSPP0, 34, 3 },
1211 { DBGBUS_SSPP0, 34, 4 },
1212 { DBGBUS_SSPP0, 34, 5 },
1213 { DBGBUS_SSPP0, 34, 6 },
1214 { DBGBUS_SSPP0, 34, 7 },
1215
1216 { DBGBUS_SSPP0, 35, 0 },
1217 { DBGBUS_SSPP0, 35, 1 },
1218 { DBGBUS_SSPP0, 35, 2 },
1219 { DBGBUS_SSPP0, 35, 3 },
1220
1221 /* dma 0 */
1222 { DBGBUS_SSPP0, 40, 0 },
1223 { DBGBUS_SSPP0, 40, 1 },
1224 { DBGBUS_SSPP0, 40, 2 },
1225 { DBGBUS_SSPP0, 40, 3 },
1226 { DBGBUS_SSPP0, 40, 4 },
1227 { DBGBUS_SSPP0, 40, 5 },
1228 { DBGBUS_SSPP0, 40, 6 },
1229 { DBGBUS_SSPP0, 40, 7 },
1230
1231 { DBGBUS_SSPP0, 41, 0 },
1232 { DBGBUS_SSPP0, 41, 1 },
1233 { DBGBUS_SSPP0, 41, 2 },
1234 { DBGBUS_SSPP0, 41, 3 },
1235 { DBGBUS_SSPP0, 41, 4 },
1236 { DBGBUS_SSPP0, 41, 5 },
1237 { DBGBUS_SSPP0, 41, 6 },
1238 { DBGBUS_SSPP0, 41, 7 },
1239
1240 { DBGBUS_SSPP0, 42, 0 },
1241 { DBGBUS_SSPP0, 42, 1 },
1242 { DBGBUS_SSPP0, 42, 2 },
1243 { DBGBUS_SSPP0, 42, 3 },
1244 { DBGBUS_SSPP0, 42, 4 },
1245 { DBGBUS_SSPP0, 42, 5 },
1246 { DBGBUS_SSPP0, 42, 6 },
1247 { DBGBUS_SSPP0, 42, 7 },
1248
1249 { DBGBUS_SSPP0, 44, 0 },
1250 { DBGBUS_SSPP0, 44, 1 },
1251 { DBGBUS_SSPP0, 44, 2 },
1252 { DBGBUS_SSPP0, 44, 3 },
1253 { DBGBUS_SSPP0, 44, 4 },
1254 { DBGBUS_SSPP0, 44, 5 },
1255 { DBGBUS_SSPP0, 44, 6 },
1256 { DBGBUS_SSPP0, 44, 7 },
1257
1258 { DBGBUS_SSPP0, 45, 0 },
1259 { DBGBUS_SSPP0, 45, 1 },
1260 { DBGBUS_SSPP0, 45, 2 },
1261 { DBGBUS_SSPP0, 45, 3 },
1262 { DBGBUS_SSPP0, 45, 4 },
1263 { DBGBUS_SSPP0, 45, 5 },
1264 { DBGBUS_SSPP0, 45, 6 },
1265 { DBGBUS_SSPP0, 45, 7 },
1266
1267 /* fetch sspp1 */
1268 /* vig 1 */
1269 { DBGBUS_SSPP1, 0, 0 },
1270 { DBGBUS_SSPP1, 0, 1 },
1271 { DBGBUS_SSPP1, 0, 2 },
1272 { DBGBUS_SSPP1, 0, 3 },
1273 { DBGBUS_SSPP1, 0, 4 },
1274 { DBGBUS_SSPP1, 0, 5 },
1275 { DBGBUS_SSPP1, 0, 6 },
1276 { DBGBUS_SSPP1, 0, 7 },
1277
1278 { DBGBUS_SSPP1, 1, 0 },
1279 { DBGBUS_SSPP1, 1, 1 },
1280 { DBGBUS_SSPP1, 1, 2 },
1281 { DBGBUS_SSPP1, 1, 3 },
1282 { DBGBUS_SSPP1, 1, 4 },
1283 { DBGBUS_SSPP1, 1, 5 },
1284 { DBGBUS_SSPP1, 1, 6 },
1285 { DBGBUS_SSPP1, 1, 7 },
1286
1287 { DBGBUS_SSPP1, 2, 0 },
1288 { DBGBUS_SSPP1, 2, 1 },
1289 { DBGBUS_SSPP1, 2, 2 },
1290 { DBGBUS_SSPP1, 2, 3 },
1291 { DBGBUS_SSPP1, 2, 4 },
1292 { DBGBUS_SSPP1, 2, 5 },
1293 { DBGBUS_SSPP1, 2, 6 },
1294 { DBGBUS_SSPP1, 2, 7 },
1295
1296 { DBGBUS_SSPP1, 4, 0 },
1297 { DBGBUS_SSPP1, 4, 1 },
1298 { DBGBUS_SSPP1, 4, 2 },
1299 { DBGBUS_SSPP1, 4, 3 },
1300 { DBGBUS_SSPP1, 4, 4 },
1301 { DBGBUS_SSPP1, 4, 5 },
1302 { DBGBUS_SSPP1, 4, 6 },
1303 { DBGBUS_SSPP1, 4, 7 },
1304
1305 { DBGBUS_SSPP1, 5, 0 },
1306 { DBGBUS_SSPP1, 5, 1 },
1307 { DBGBUS_SSPP1, 5, 2 },
1308 { DBGBUS_SSPP1, 5, 3 },
1309 { DBGBUS_SSPP1, 5, 4 },
1310 { DBGBUS_SSPP1, 5, 5 },
1311 { DBGBUS_SSPP1, 5, 6 },
1312 { DBGBUS_SSPP1, 5, 7 },
1313
1314 /* vig 3 */
1315 { DBGBUS_SSPP1, 20, 0 },
1316 { DBGBUS_SSPP1, 20, 1 },
1317 { DBGBUS_SSPP1, 20, 2 },
1318 { DBGBUS_SSPP1, 20, 3 },
1319 { DBGBUS_SSPP1, 20, 4 },
1320 { DBGBUS_SSPP1, 20, 5 },
1321 { DBGBUS_SSPP1, 20, 6 },
1322 { DBGBUS_SSPP1, 20, 7 },
1323
1324 { DBGBUS_SSPP1, 21, 0 },
1325 { DBGBUS_SSPP1, 21, 1 },
1326 { DBGBUS_SSPP1, 21, 2 },
1327 { DBGBUS_SSPP1, 21, 3 },
1328 { DBGBUS_SSPP1, 21, 4 },
1329 { DBGBUS_SSPP1, 21, 5 },
1330 { DBGBUS_SSPP1, 21, 6 },
1331 { DBGBUS_SSPP1, 21, 7 },
1332
1333 { DBGBUS_SSPP1, 22, 0 },
1334 { DBGBUS_SSPP1, 22, 1 },
1335 { DBGBUS_SSPP1, 22, 2 },
1336 { DBGBUS_SSPP1, 22, 3 },
1337 { DBGBUS_SSPP1, 22, 4 },
1338 { DBGBUS_SSPP1, 22, 5 },
1339 { DBGBUS_SSPP1, 22, 6 },
1340 { DBGBUS_SSPP1, 22, 7 },
1341
1342 { DBGBUS_SSPP1, 24, 0 },
1343 { DBGBUS_SSPP1, 24, 1 },
1344 { DBGBUS_SSPP1, 24, 2 },
1345 { DBGBUS_SSPP1, 24, 3 },
1346 { DBGBUS_SSPP1, 24, 4 },
1347 { DBGBUS_SSPP1, 24, 5 },
1348 { DBGBUS_SSPP1, 24, 6 },
1349 { DBGBUS_SSPP1, 24, 7 },
1350
1351 { DBGBUS_SSPP1, 25, 0 },
1352 { DBGBUS_SSPP1, 25, 1 },
1353 { DBGBUS_SSPP1, 25, 2 },
1354 { DBGBUS_SSPP1, 25, 3 },
1355 { DBGBUS_SSPP1, 25, 4 },
1356 { DBGBUS_SSPP1, 25, 5 },
1357 { DBGBUS_SSPP1, 25, 6 },
1358 { DBGBUS_SSPP1, 25, 7 },
1359
1360 /* dma 3 */
1361 { DBGBUS_SSPP1, 30, 0 },
1362 { DBGBUS_SSPP1, 30, 1 },
1363 { DBGBUS_SSPP1, 30, 2 },
1364 { DBGBUS_SSPP1, 30, 3 },
1365 { DBGBUS_SSPP1, 30, 4 },
1366 { DBGBUS_SSPP1, 30, 5 },
1367 { DBGBUS_SSPP1, 30, 6 },
1368 { DBGBUS_SSPP1, 30, 7 },
1369
1370 { DBGBUS_SSPP1, 31, 0 },
1371 { DBGBUS_SSPP1, 31, 1 },
1372 { DBGBUS_SSPP1, 31, 2 },
1373 { DBGBUS_SSPP1, 31, 3 },
1374 { DBGBUS_SSPP1, 31, 4 },
1375 { DBGBUS_SSPP1, 31, 5 },
1376 { DBGBUS_SSPP1, 31, 6 },
1377 { DBGBUS_SSPP1, 31, 7 },
1378
1379 { DBGBUS_SSPP1, 32, 0 },
1380 { DBGBUS_SSPP1, 32, 1 },
1381 { DBGBUS_SSPP1, 32, 2 },
1382 { DBGBUS_SSPP1, 32, 3 },
1383 { DBGBUS_SSPP1, 32, 4 },
1384 { DBGBUS_SSPP1, 32, 5 },
1385 { DBGBUS_SSPP1, 32, 6 },
1386 { DBGBUS_SSPP1, 32, 7 },
1387
1388 { DBGBUS_SSPP1, 33, 0 },
1389 { DBGBUS_SSPP1, 33, 1 },
1390 { DBGBUS_SSPP1, 33, 2 },
1391 { DBGBUS_SSPP1, 33, 3 },
1392 { DBGBUS_SSPP1, 33, 4 },
1393 { DBGBUS_SSPP1, 33, 5 },
1394 { DBGBUS_SSPP1, 33, 6 },
1395 { DBGBUS_SSPP1, 33, 7 },
1396
1397 { DBGBUS_SSPP1, 34, 0 },
1398 { DBGBUS_SSPP1, 34, 1 },
1399 { DBGBUS_SSPP1, 34, 2 },
1400 { DBGBUS_SSPP1, 34, 3 },
1401 { DBGBUS_SSPP1, 34, 4 },
1402 { DBGBUS_SSPP1, 34, 5 },
1403 { DBGBUS_SSPP1, 34, 6 },
1404 { DBGBUS_SSPP1, 34, 7 },
1405
1406 { DBGBUS_SSPP1, 35, 0 },
1407 { DBGBUS_SSPP1, 35, 1 },
1408 { DBGBUS_SSPP1, 35, 2 },
1409
1410 /* dma 1 */
1411 { DBGBUS_SSPP1, 40, 0 },
1412 { DBGBUS_SSPP1, 40, 1 },
1413 { DBGBUS_SSPP1, 40, 2 },
1414 { DBGBUS_SSPP1, 40, 3 },
1415 { DBGBUS_SSPP1, 40, 4 },
1416 { DBGBUS_SSPP1, 40, 5 },
1417 { DBGBUS_SSPP1, 40, 6 },
1418 { DBGBUS_SSPP1, 40, 7 },
1419
1420 { DBGBUS_SSPP1, 41, 0 },
1421 { DBGBUS_SSPP1, 41, 1 },
1422 { DBGBUS_SSPP1, 41, 2 },
1423 { DBGBUS_SSPP1, 41, 3 },
1424 { DBGBUS_SSPP1, 41, 4 },
1425 { DBGBUS_SSPP1, 41, 5 },
1426 { DBGBUS_SSPP1, 41, 6 },
1427 { DBGBUS_SSPP1, 41, 7 },
1428
1429 { DBGBUS_SSPP1, 42, 0 },
1430 { DBGBUS_SSPP1, 42, 1 },
1431 { DBGBUS_SSPP1, 42, 2 },
1432 { DBGBUS_SSPP1, 42, 3 },
1433 { DBGBUS_SSPP1, 42, 4 },
1434 { DBGBUS_SSPP1, 42, 5 },
1435 { DBGBUS_SSPP1, 42, 6 },
1436 { DBGBUS_SSPP1, 42, 7 },
1437
1438 { DBGBUS_SSPP1, 44, 0 },
1439 { DBGBUS_SSPP1, 44, 1 },
1440 { DBGBUS_SSPP1, 44, 2 },
1441 { DBGBUS_SSPP1, 44, 3 },
1442 { DBGBUS_SSPP1, 44, 4 },
1443 { DBGBUS_SSPP1, 44, 5 },
1444 { DBGBUS_SSPP1, 44, 6 },
1445 { DBGBUS_SSPP1, 44, 7 },
1446
1447 { DBGBUS_SSPP1, 45, 0 },
1448 { DBGBUS_SSPP1, 45, 1 },
1449 { DBGBUS_SSPP1, 45, 2 },
1450 { DBGBUS_SSPP1, 45, 3 },
1451 { DBGBUS_SSPP1, 45, 4 },
1452 { DBGBUS_SSPP1, 45, 5 },
1453 { DBGBUS_SSPP1, 45, 6 },
1454 { DBGBUS_SSPP1, 45, 7 },
1455
1456 /* dspp */
1457 { DBGBUS_DSPP, 13, 0 },
1458 { DBGBUS_DSPP, 19, 0 },
1459 { DBGBUS_DSPP, 14, 0 },
1460 { DBGBUS_DSPP, 14, 1 },
1461 { DBGBUS_DSPP, 14, 3 },
1462 { DBGBUS_DSPP, 20, 0 },
1463 { DBGBUS_DSPP, 20, 1 },
1464 { DBGBUS_DSPP, 20, 3 },
1465
1466 /* ppb_0 */
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1467 { DBGBUS_DSPP, 31, 0, _sde_debug_bus_ppb0_dump },
1468 { DBGBUS_DSPP, 33, 0, _sde_debug_bus_ppb0_dump },
1469 { DBGBUS_DSPP, 35, 0, _sde_debug_bus_ppb0_dump },
1470 { DBGBUS_DSPP, 42, 0, _sde_debug_bus_ppb0_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1471
1472 /* ppb_1 */
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1473 { DBGBUS_DSPP, 32, 0, _sde_debug_bus_ppb1_dump },
1474 { DBGBUS_DSPP, 34, 0, _sde_debug_bus_ppb1_dump },
1475 { DBGBUS_DSPP, 36, 0, _sde_debug_bus_ppb1_dump },
1476 { DBGBUS_DSPP, 43, 0, _sde_debug_bus_ppb1_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1477
1478 /* lm_lut */
1479 { DBGBUS_DSPP, 109, 0 },
1480 { DBGBUS_DSPP, 105, 0 },
1481 { DBGBUS_DSPP, 103, 0 },
1482
1483 /* crossbar */
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1484 { DBGBUS_DSPP, 0, 0, _sde_debug_bus_xbar_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1485
1486 /* rotator */
1487 { DBGBUS_DSPP, 9, 0},
1488
1489 /* blend */
1490 /* LM0 */
1491 { DBGBUS_DSPP, 63, 1},
1492 { DBGBUS_DSPP, 63, 2},
1493 { DBGBUS_DSPP, 63, 3},
1494 { DBGBUS_DSPP, 63, 4},
1495 { DBGBUS_DSPP, 63, 5},
1496 { DBGBUS_DSPP, 63, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1497 { DBGBUS_DSPP, 63, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1498
1499 { DBGBUS_DSPP, 64, 1},
1500 { DBGBUS_DSPP, 64, 2},
1501 { DBGBUS_DSPP, 64, 3},
1502 { DBGBUS_DSPP, 64, 4},
1503 { DBGBUS_DSPP, 64, 5},
1504 { DBGBUS_DSPP, 64, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1505 { DBGBUS_DSPP, 64, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1506
1507 { DBGBUS_DSPP, 65, 1},
1508 { DBGBUS_DSPP, 65, 2},
1509 { DBGBUS_DSPP, 65, 3},
1510 { DBGBUS_DSPP, 65, 4},
1511 { DBGBUS_DSPP, 65, 5},
1512 { DBGBUS_DSPP, 65, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1513 { DBGBUS_DSPP, 65, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1514
1515 { DBGBUS_DSPP, 66, 1},
1516 { DBGBUS_DSPP, 66, 2},
1517 { DBGBUS_DSPP, 66, 3},
1518 { DBGBUS_DSPP, 66, 4},
1519 { DBGBUS_DSPP, 66, 5},
1520 { DBGBUS_DSPP, 66, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1521 { DBGBUS_DSPP, 66, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1522
1523 { DBGBUS_DSPP, 67, 1},
1524 { DBGBUS_DSPP, 67, 2},
1525 { DBGBUS_DSPP, 67, 3},
1526 { DBGBUS_DSPP, 67, 4},
1527 { DBGBUS_DSPP, 67, 5},
1528 { DBGBUS_DSPP, 67, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1529 { DBGBUS_DSPP, 67, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1530
1531 { DBGBUS_DSPP, 68, 1},
1532 { DBGBUS_DSPP, 68, 2},
1533 { DBGBUS_DSPP, 68, 3},
1534 { DBGBUS_DSPP, 68, 4},
1535 { DBGBUS_DSPP, 68, 5},
1536 { DBGBUS_DSPP, 68, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1537 { DBGBUS_DSPP, 68, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1538
1539 { DBGBUS_DSPP, 69, 1},
1540 { DBGBUS_DSPP, 69, 2},
1541 { DBGBUS_DSPP, 69, 3},
1542 { DBGBUS_DSPP, 69, 4},
1543 { DBGBUS_DSPP, 69, 5},
1544 { DBGBUS_DSPP, 69, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1545 { DBGBUS_DSPP, 69, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1546
1547 { DBGBUS_DSPP, 84, 1},
1548 { DBGBUS_DSPP, 84, 2},
1549 { DBGBUS_DSPP, 84, 3},
1550 { DBGBUS_DSPP, 84, 4},
1551 { DBGBUS_DSPP, 84, 5},
1552 { DBGBUS_DSPP, 84, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1553 { DBGBUS_DSPP, 84, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1554
1555
1556 { DBGBUS_DSPP, 85, 1},
1557 { DBGBUS_DSPP, 85, 2},
1558 { DBGBUS_DSPP, 85, 3},
1559 { DBGBUS_DSPP, 85, 4},
1560 { DBGBUS_DSPP, 85, 5},
1561 { DBGBUS_DSPP, 85, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1562 { DBGBUS_DSPP, 85, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1563
1564
1565 { DBGBUS_DSPP, 86, 1},
1566 { DBGBUS_DSPP, 86, 2},
1567 { DBGBUS_DSPP, 86, 3},
1568 { DBGBUS_DSPP, 86, 4},
1569 { DBGBUS_DSPP, 86, 5},
1570 { DBGBUS_DSPP, 86, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1571 { DBGBUS_DSPP, 86, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1572
1573
1574 { DBGBUS_DSPP, 87, 1},
1575 { DBGBUS_DSPP, 87, 2},
1576 { DBGBUS_DSPP, 87, 3},
1577 { DBGBUS_DSPP, 87, 4},
1578 { DBGBUS_DSPP, 87, 5},
1579 { DBGBUS_DSPP, 87, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1580 { DBGBUS_DSPP, 87, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1581
1582 /* LM1 */
1583 { DBGBUS_DSPP, 70, 1},
1584 { DBGBUS_DSPP, 70, 2},
1585 { DBGBUS_DSPP, 70, 3},
1586 { DBGBUS_DSPP, 70, 4},
1587 { DBGBUS_DSPP, 70, 5},
1588 { DBGBUS_DSPP, 70, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1589 { DBGBUS_DSPP, 70, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1590
1591 { DBGBUS_DSPP, 71, 1},
1592 { DBGBUS_DSPP, 71, 2},
1593 { DBGBUS_DSPP, 71, 3},
1594 { DBGBUS_DSPP, 71, 4},
1595 { DBGBUS_DSPP, 71, 5},
1596 { DBGBUS_DSPP, 71, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1597 { DBGBUS_DSPP, 71, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1598
1599 { DBGBUS_DSPP, 72, 1},
1600 { DBGBUS_DSPP, 72, 2},
1601 { DBGBUS_DSPP, 72, 3},
1602 { DBGBUS_DSPP, 72, 4},
1603 { DBGBUS_DSPP, 72, 5},
1604 { DBGBUS_DSPP, 72, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1605 { DBGBUS_DSPP, 72, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1606
1607 { DBGBUS_DSPP, 73, 1},
1608 { DBGBUS_DSPP, 73, 2},
1609 { DBGBUS_DSPP, 73, 3},
1610 { DBGBUS_DSPP, 73, 4},
1611 { DBGBUS_DSPP, 73, 5},
1612 { DBGBUS_DSPP, 73, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1613 { DBGBUS_DSPP, 73, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1614
1615 { DBGBUS_DSPP, 74, 1},
1616 { DBGBUS_DSPP, 74, 2},
1617 { DBGBUS_DSPP, 74, 3},
1618 { DBGBUS_DSPP, 74, 4},
1619 { DBGBUS_DSPP, 74, 5},
1620 { DBGBUS_DSPP, 74, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1621 { DBGBUS_DSPP, 74, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1622
1623 { DBGBUS_DSPP, 75, 1},
1624 { DBGBUS_DSPP, 75, 2},
1625 { DBGBUS_DSPP, 75, 3},
1626 { DBGBUS_DSPP, 75, 4},
1627 { DBGBUS_DSPP, 75, 5},
1628 { DBGBUS_DSPP, 75, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1629 { DBGBUS_DSPP, 75, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1630
1631 { DBGBUS_DSPP, 76, 1},
1632 { DBGBUS_DSPP, 76, 2},
1633 { DBGBUS_DSPP, 76, 3},
1634 { DBGBUS_DSPP, 76, 4},
1635 { DBGBUS_DSPP, 76, 5},
1636 { DBGBUS_DSPP, 76, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1637 { DBGBUS_DSPP, 76, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1638
1639 { DBGBUS_DSPP, 88, 1},
1640 { DBGBUS_DSPP, 88, 2},
1641 { DBGBUS_DSPP, 88, 3},
1642 { DBGBUS_DSPP, 88, 4},
1643 { DBGBUS_DSPP, 88, 5},
1644 { DBGBUS_DSPP, 88, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1645 { DBGBUS_DSPP, 88, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1646
1647 { DBGBUS_DSPP, 89, 1},
1648 { DBGBUS_DSPP, 89, 2},
1649 { DBGBUS_DSPP, 89, 3},
1650 { DBGBUS_DSPP, 89, 4},
1651 { DBGBUS_DSPP, 89, 5},
1652 { DBGBUS_DSPP, 89, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1653 { DBGBUS_DSPP, 89, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1654
1655 { DBGBUS_DSPP, 90, 1},
1656 { DBGBUS_DSPP, 90, 2},
1657 { DBGBUS_DSPP, 90, 3},
1658 { DBGBUS_DSPP, 90, 4},
1659 { DBGBUS_DSPP, 90, 5},
1660 { DBGBUS_DSPP, 90, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1661 { DBGBUS_DSPP, 90, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1662
1663 { DBGBUS_DSPP, 91, 1},
1664 { DBGBUS_DSPP, 91, 2},
1665 { DBGBUS_DSPP, 91, 3},
1666 { DBGBUS_DSPP, 91, 4},
1667 { DBGBUS_DSPP, 91, 5},
1668 { DBGBUS_DSPP, 91, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1669 { DBGBUS_DSPP, 91, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1670
1671 /* LM2 */
1672 { DBGBUS_DSPP, 77, 0},
1673 { DBGBUS_DSPP, 77, 1},
1674 { DBGBUS_DSPP, 77, 2},
1675 { DBGBUS_DSPP, 77, 3},
1676 { DBGBUS_DSPP, 77, 4},
1677 { DBGBUS_DSPP, 77, 5},
1678 { DBGBUS_DSPP, 77, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1679 { DBGBUS_DSPP, 77, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1680
1681 { DBGBUS_DSPP, 78, 0},
1682 { DBGBUS_DSPP, 78, 1},
1683 { DBGBUS_DSPP, 78, 2},
1684 { DBGBUS_DSPP, 78, 3},
1685 { DBGBUS_DSPP, 78, 4},
1686 { DBGBUS_DSPP, 78, 5},
1687 { DBGBUS_DSPP, 78, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1688 { DBGBUS_DSPP, 78, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1689
1690 { DBGBUS_DSPP, 79, 0},
1691 { DBGBUS_DSPP, 79, 1},
1692 { DBGBUS_DSPP, 79, 2},
1693 { DBGBUS_DSPP, 79, 3},
1694 { DBGBUS_DSPP, 79, 4},
1695 { DBGBUS_DSPP, 79, 5},
1696 { DBGBUS_DSPP, 79, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1697 { DBGBUS_DSPP, 79, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1698
1699 { DBGBUS_DSPP, 80, 0},
1700 { DBGBUS_DSPP, 80, 1},
1701 { DBGBUS_DSPP, 80, 2},
1702 { DBGBUS_DSPP, 80, 3},
1703 { DBGBUS_DSPP, 80, 4},
1704 { DBGBUS_DSPP, 80, 5},
1705 { DBGBUS_DSPP, 80, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1706 { DBGBUS_DSPP, 80, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1707
1708 { DBGBUS_DSPP, 81, 0},
1709 { DBGBUS_DSPP, 81, 1},
1710 { DBGBUS_DSPP, 81, 2},
1711 { DBGBUS_DSPP, 81, 3},
1712 { DBGBUS_DSPP, 81, 4},
1713 { DBGBUS_DSPP, 81, 5},
1714 { DBGBUS_DSPP, 81, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1715 { DBGBUS_DSPP, 81, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1716
1717 { DBGBUS_DSPP, 82, 0},
1718 { DBGBUS_DSPP, 82, 1},
1719 { DBGBUS_DSPP, 82, 2},
1720 { DBGBUS_DSPP, 82, 3},
1721 { DBGBUS_DSPP, 82, 4},
1722 { DBGBUS_DSPP, 82, 5},
1723 { DBGBUS_DSPP, 82, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1724 { DBGBUS_DSPP, 82, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1725
1726 { DBGBUS_DSPP, 83, 0},
1727 { DBGBUS_DSPP, 83, 1},
1728 { DBGBUS_DSPP, 83, 2},
1729 { DBGBUS_DSPP, 83, 3},
1730 { DBGBUS_DSPP, 83, 4},
1731 { DBGBUS_DSPP, 83, 5},
1732 { DBGBUS_DSPP, 83, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1733 { DBGBUS_DSPP, 83, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1734
1735 { DBGBUS_DSPP, 92, 1},
1736 { DBGBUS_DSPP, 92, 2},
1737 { DBGBUS_DSPP, 92, 3},
1738 { DBGBUS_DSPP, 92, 4},
1739 { DBGBUS_DSPP, 92, 5},
1740 { DBGBUS_DSPP, 92, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1741 { DBGBUS_DSPP, 92, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1742
1743 { DBGBUS_DSPP, 93, 1},
1744 { DBGBUS_DSPP, 93, 2},
1745 { DBGBUS_DSPP, 93, 3},
1746 { DBGBUS_DSPP, 93, 4},
1747 { DBGBUS_DSPP, 93, 5},
1748 { DBGBUS_DSPP, 93, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1749 { DBGBUS_DSPP, 93, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1750
1751 { DBGBUS_DSPP, 94, 1},
1752 { DBGBUS_DSPP, 94, 2},
1753 { DBGBUS_DSPP, 94, 3},
1754 { DBGBUS_DSPP, 94, 4},
1755 { DBGBUS_DSPP, 94, 5},
1756 { DBGBUS_DSPP, 94, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1757 { DBGBUS_DSPP, 94, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1758
1759 { DBGBUS_DSPP, 95, 1},
1760 { DBGBUS_DSPP, 95, 2},
1761 { DBGBUS_DSPP, 95, 3},
1762 { DBGBUS_DSPP, 95, 4},
1763 { DBGBUS_DSPP, 95, 5},
1764 { DBGBUS_DSPP, 95, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1765 { DBGBUS_DSPP, 95, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1766
1767 /* LM5 */
1768 { DBGBUS_DSPP, 110, 1},
1769 { DBGBUS_DSPP, 110, 2},
1770 { DBGBUS_DSPP, 110, 3},
1771 { DBGBUS_DSPP, 110, 4},
1772 { DBGBUS_DSPP, 110, 5},
1773 { DBGBUS_DSPP, 110, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1774 { DBGBUS_DSPP, 110, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1775
1776 { DBGBUS_DSPP, 111, 1},
1777 { DBGBUS_DSPP, 111, 2},
1778 { DBGBUS_DSPP, 111, 3},
1779 { DBGBUS_DSPP, 111, 4},
1780 { DBGBUS_DSPP, 111, 5},
1781 { DBGBUS_DSPP, 111, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1782 { DBGBUS_DSPP, 111, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1783
1784 { DBGBUS_DSPP, 112, 1},
1785 { DBGBUS_DSPP, 112, 2},
1786 { DBGBUS_DSPP, 112, 3},
1787 { DBGBUS_DSPP, 112, 4},
1788 { DBGBUS_DSPP, 112, 5},
1789 { DBGBUS_DSPP, 112, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1790 { DBGBUS_DSPP, 112, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1791
1792 { DBGBUS_DSPP, 113, 1},
1793 { DBGBUS_DSPP, 113, 2},
1794 { DBGBUS_DSPP, 113, 3},
1795 { DBGBUS_DSPP, 113, 4},
1796 { DBGBUS_DSPP, 113, 5},
1797 { DBGBUS_DSPP, 113, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1798 { DBGBUS_DSPP, 113, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1799
1800 { DBGBUS_DSPP, 114, 1},
1801 { DBGBUS_DSPP, 114, 2},
1802 { DBGBUS_DSPP, 114, 3},
1803 { DBGBUS_DSPP, 114, 4},
1804 { DBGBUS_DSPP, 114, 5},
1805 { DBGBUS_DSPP, 114, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1806 { DBGBUS_DSPP, 114, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1807
1808 { DBGBUS_DSPP, 115, 1},
1809 { DBGBUS_DSPP, 115, 2},
1810 { DBGBUS_DSPP, 115, 3},
1811 { DBGBUS_DSPP, 115, 4},
1812 { DBGBUS_DSPP, 115, 5},
1813 { DBGBUS_DSPP, 115, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1814 { DBGBUS_DSPP, 115, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1815
1816 { DBGBUS_DSPP, 116, 1},
1817 { DBGBUS_DSPP, 116, 2},
1818 { DBGBUS_DSPP, 116, 3},
1819 { DBGBUS_DSPP, 116, 4},
1820 { DBGBUS_DSPP, 116, 5},
1821 { DBGBUS_DSPP, 116, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1822 { DBGBUS_DSPP, 116, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1823
1824 { DBGBUS_DSPP, 117, 1},
1825 { DBGBUS_DSPP, 117, 2},
1826 { DBGBUS_DSPP, 117, 3},
1827 { DBGBUS_DSPP, 117, 4},
1828 { DBGBUS_DSPP, 117, 5},
1829 { DBGBUS_DSPP, 117, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1830 { DBGBUS_DSPP, 117, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1831
1832 { DBGBUS_DSPP, 118, 1},
1833 { DBGBUS_DSPP, 118, 2},
1834 { DBGBUS_DSPP, 118, 3},
1835 { DBGBUS_DSPP, 118, 4},
1836 { DBGBUS_DSPP, 118, 5},
1837 { DBGBUS_DSPP, 118, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1838 { DBGBUS_DSPP, 118, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1839
1840 { DBGBUS_DSPP, 119, 1},
1841 { DBGBUS_DSPP, 119, 2},
1842 { DBGBUS_DSPP, 119, 3},
1843 { DBGBUS_DSPP, 119, 4},
1844 { DBGBUS_DSPP, 119, 5},
1845 { DBGBUS_DSPP, 119, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1846 { DBGBUS_DSPP, 119, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1847
1848 { DBGBUS_DSPP, 120, 1},
1849 { DBGBUS_DSPP, 120, 2},
1850 { DBGBUS_DSPP, 120, 3},
1851 { DBGBUS_DSPP, 120, 4},
1852 { DBGBUS_DSPP, 120, 5},
1853 { DBGBUS_DSPP, 120, 6},
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]1854 { DBGBUS_DSPP, 120, 7, _sde_debug_bus_lm_dump },
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]1855
1856 /* csc */
1857 { DBGBUS_SSPP0, 7, 0},
1858 { DBGBUS_SSPP0, 7, 1},
1859 { DBGBUS_SSPP0, 27, 0},
1860 { DBGBUS_SSPP0, 27, 1},
1861 { DBGBUS_SSPP1, 7, 0},
1862 { DBGBUS_SSPP1, 7, 1},
1863 { DBGBUS_SSPP1, 27, 0},
1864 { DBGBUS_SSPP1, 27, 1},
1865
1866 /* pcc */
1867 { DBGBUS_SSPP0, 3, 3},
1868 { DBGBUS_SSPP0, 23, 3},
1869 { DBGBUS_SSPP0, 33, 3},
1870 { DBGBUS_SSPP0, 43, 3},
1871 { DBGBUS_SSPP1, 3, 3},
1872 { DBGBUS_SSPP1, 23, 3},
1873 { DBGBUS_SSPP1, 33, 3},
1874 { DBGBUS_SSPP1, 43, 3},
1875
1876 /* spa */
1877 { DBGBUS_SSPP0, 8, 0},
1878 { DBGBUS_SSPP0, 28, 0},
1879 { DBGBUS_SSPP1, 8, 0},
1880 { DBGBUS_SSPP1, 28, 0},
1881 { DBGBUS_DSPP, 13, 0},
1882 { DBGBUS_DSPP, 19, 0},
1883
1884 /* igc */
1885 { DBGBUS_SSPP0, 17, 0},
1886 { DBGBUS_SSPP0, 17, 1},
1887 { DBGBUS_SSPP0, 17, 3},
1888 { DBGBUS_SSPP0, 37, 0},
1889 { DBGBUS_SSPP0, 37, 1},
1890 { DBGBUS_SSPP0, 37, 3},
1891 { DBGBUS_SSPP0, 46, 0},
1892 { DBGBUS_SSPP0, 46, 1},
1893 { DBGBUS_SSPP0, 46, 3},
1894
1895 { DBGBUS_SSPP1, 17, 0},
1896 { DBGBUS_SSPP1, 17, 1},
1897 { DBGBUS_SSPP1, 17, 3},
1898 { DBGBUS_SSPP1, 37, 0},
1899 { DBGBUS_SSPP1, 37, 1},
1900 { DBGBUS_SSPP1, 37, 3},
1901 { DBGBUS_SSPP1, 46, 0},
1902 { DBGBUS_SSPP1, 46, 1},
1903 { DBGBUS_SSPP1, 46, 3},
1904
1905 { DBGBUS_DSPP, 14, 0},
1906 { DBGBUS_DSPP, 14, 1},
1907 { DBGBUS_DSPP, 14, 3},
1908 { DBGBUS_DSPP, 20, 0},
1909 { DBGBUS_DSPP, 20, 1},
1910 { DBGBUS_DSPP, 20, 3},
1911
1912 /* intf0-3 */
1913 { DBGBUS_PERIPH, 0, 0},
1914 { DBGBUS_PERIPH, 1, 0},
1915 { DBGBUS_PERIPH, 2, 0},
1916 { DBGBUS_PERIPH, 3, 0},
1917
1918 /* te counter wrapper */
1919 { DBGBUS_PERIPH, 60, 0},
1920
1921 /* dsc0 */
1922 { DBGBUS_PERIPH, 47, 0},
1923 { DBGBUS_PERIPH, 47, 1},
1924 { DBGBUS_PERIPH, 47, 2},
1925 { DBGBUS_PERIPH, 47, 3},
1926 { DBGBUS_PERIPH, 47, 4},
1927 { DBGBUS_PERIPH, 47, 5},
1928 { DBGBUS_PERIPH, 47, 6},
1929 { DBGBUS_PERIPH, 47, 7},
1930
1931 /* dsc1 */
1932 { DBGBUS_PERIPH, 48, 0},
1933 { DBGBUS_PERIPH, 48, 1},
1934 { DBGBUS_PERIPH, 48, 2},
1935 { DBGBUS_PERIPH, 48, 3},
1936 { DBGBUS_PERIPH, 48, 4},
1937 { DBGBUS_PERIPH, 48, 5},
1938 { DBGBUS_PERIPH, 48, 6},
1939 { DBGBUS_PERIPH, 48, 7},
1940
1941 /* dsc2 */
1942 { DBGBUS_PERIPH, 51, 0},
1943 { DBGBUS_PERIPH, 51, 1},
1944 { DBGBUS_PERIPH, 51, 2},
1945 { DBGBUS_PERIPH, 51, 3},
1946 { DBGBUS_PERIPH, 51, 4},
1947 { DBGBUS_PERIPH, 51, 5},
1948 { DBGBUS_PERIPH, 51, 6},
1949 { DBGBUS_PERIPH, 51, 7},
1950
1951 /* dsc3 */
1952 { DBGBUS_PERIPH, 52, 0},
1953 { DBGBUS_PERIPH, 52, 1},
1954 { DBGBUS_PERIPH, 52, 2},
1955 { DBGBUS_PERIPH, 52, 3},
1956 { DBGBUS_PERIPH, 52, 4},
1957 { DBGBUS_PERIPH, 52, 5},
1958 { DBGBUS_PERIPH, 52, 6},
1959 { DBGBUS_PERIPH, 52, 7},
1960
1961 /* tear-check */
1962 { DBGBUS_PERIPH, 63, 0 },
1963 { DBGBUS_PERIPH, 64, 0 },
1964 { DBGBUS_PERIPH, 65, 0 },
1965 { DBGBUS_PERIPH, 73, 0 },
1966 { DBGBUS_PERIPH, 74, 0 },
1967
1968 /* cdwn */
1969 { DBGBUS_PERIPH, 80, 0},
1970 { DBGBUS_PERIPH, 80, 1},
1971 { DBGBUS_PERIPH, 80, 2},
1972
1973 { DBGBUS_PERIPH, 81, 0},
1974 { DBGBUS_PERIPH, 81, 1},
1975 { DBGBUS_PERIPH, 81, 2},
1976
1977 { DBGBUS_PERIPH, 82, 0},
1978 { DBGBUS_PERIPH, 82, 1},
1979 { DBGBUS_PERIPH, 82, 2},
1980 { DBGBUS_PERIPH, 82, 3},
1981 { DBGBUS_PERIPH, 82, 4},
1982 { DBGBUS_PERIPH, 82, 5},
1983 { DBGBUS_PERIPH, 82, 6},
1984 { DBGBUS_PERIPH, 82, 7},
1985
1986 /* hdmi */
1987 { DBGBUS_PERIPH, 68, 0},
1988 { DBGBUS_PERIPH, 68, 1},
1989 { DBGBUS_PERIPH, 68, 2},
1990 { DBGBUS_PERIPH, 68, 3},
1991 { DBGBUS_PERIPH, 68, 4},
1992 { DBGBUS_PERIPH, 68, 5},
1993
1994 /* edp */
1995 { DBGBUS_PERIPH, 69, 0},
1996 { DBGBUS_PERIPH, 69, 1},
1997 { DBGBUS_PERIPH, 69, 2},
1998 { DBGBUS_PERIPH, 69, 3},
1999 { DBGBUS_PERIPH, 69, 4},
2000 { DBGBUS_PERIPH, 69, 5},
2001
2002 /* dsi0 */
2003 { DBGBUS_PERIPH, 70, 0},
2004 { DBGBUS_PERIPH, 70, 1},
2005 { DBGBUS_PERIPH, 70, 2},
2006 { DBGBUS_PERIPH, 70, 3},
2007 { DBGBUS_PERIPH, 70, 4},
2008 { DBGBUS_PERIPH, 70, 5},
2009
2010 /* dsi1 */
2011 { DBGBUS_PERIPH, 71, 0},
2012 { DBGBUS_PERIPH, 71, 1},
2013 { DBGBUS_PERIPH, 71, 2},
2014 { DBGBUS_PERIPH, 71, 3},
2015 { DBGBUS_PERIPH, 71, 4},
2016 { DBGBUS_PERIPH, 71, 5},
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]2017
2018 /* axi - should be last entry */
2019 { DBGBUS_AXI_INTF, 62, 0, _sde_debug_bus_axi_dump_sdm845},
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2020};
2021
2022static struct vbif_debug_bus_entry vbif_dbg_bus_msm8998[] = {
2023 {0x214, 0x21c, 16, 2, 0x0, 0xd}, /* arb clients */
2024 {0x214, 0x21c, 16, 2, 0x80, 0xc0}, /* arb clients */
2025 {0x214, 0x21c, 16, 2, 0x100, 0x140}, /* arb clients */
2026 {0x214, 0x21c, 0, 16, 0x0, 0xf}, /* xin blocks - axi side */
2027 {0x214, 0x21c, 0, 16, 0x80, 0xa4}, /* xin blocks - axi side */
2028 {0x214, 0x21c, 0, 15, 0x100, 0x124}, /* xin blocks - axi side */
2029 {0x21c, 0x214, 0, 14, 0, 0xc}, /* xin blocks - clock side */
2030};
2031
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2032/**
2033 * _sde_dbg_enable_power - use callback to turn power on for hw register access
2034 * @enable: whether to turn power on or off
2035 */
2036static inline void _sde_dbg_enable_power(int enable)
2037{
2038 if (!sde_dbg_base.power_ctrl.enable_fn)
2039 return;
2040 sde_dbg_base.power_ctrl.enable_fn(
2041 sde_dbg_base.power_ctrl.handle,
2042 sde_dbg_base.power_ctrl.client,
2043 enable);
2044}
2045
2046/**
2047 * _sde_dump_reg - helper function for dumping rotator register set content
2048 * @dump_name: register set name
2049 * @reg_dump_flag: dumping flag controlling in-log/memory dump location
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2050 * @base_addr: starting address of io region for calculating offsets to print
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2051 * @addr: starting address offset for dumping
2052 * @len_bytes: range of the register set
2053 * @dump_mem: output buffer for memory dump location option
2054 * @from_isr: whether being called from isr context
2055 */
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2056static void _sde_dump_reg(const char *dump_name, u32 reg_dump_flag,
2057 char *base_addr, char *addr, size_t len_bytes, u32 **dump_mem,
2058 bool from_isr)
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2059{
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2060 u32 in_log, in_mem, len_align, len_padded;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2061 u32 *dump_addr = NULL;
2062 char *end_addr;
2063 int i;
2064
Lloyd Atkinsonf3e8ef32017-03-22 18:49:49 -0400[diff] [blame]2065 if (!len_bytes)
2066 return;
2067
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2068 in_log = (reg_dump_flag & SDE_DBG_DUMP_IN_LOG);
2069 in_mem = (reg_dump_flag & SDE_DBG_DUMP_IN_MEM);
2070
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2071 pr_debug("%s: reg_dump_flag=%d in_log=%d in_mem=%d\n",
2072 dump_name, reg_dump_flag, in_log, in_mem);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2073
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2074 if (!in_log && !in_mem)
2075 return;
2076
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2077 if (in_log)
2078 dev_info(sde_dbg_base.dev, "%s: start_offset 0x%lx len 0x%zx\n",
2079 dump_name, addr - base_addr, len_bytes);
2080
2081 len_align = (len_bytes + REG_DUMP_ALIGN - 1) / REG_DUMP_ALIGN;
2082 len_padded = len_align * REG_DUMP_ALIGN;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2083 end_addr = addr + len_bytes;
2084
2085 if (in_mem) {
2086 if (dump_mem && !(*dump_mem)) {
2087 phys_addr_t phys = 0;
2088 *dump_mem = dma_alloc_coherent(sde_dbg_base.dev,
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2089 len_padded, &phys, GFP_KERNEL);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2090 }
2091
2092 if (dump_mem && *dump_mem) {
2093 dump_addr = *dump_mem;
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2094 dev_info(sde_dbg_base.dev,
2095 "%s: start_addr:0x%pK len:0x%x reg_offset=0x%lx\n",
2096 dump_name, dump_addr, len_padded,
2097 addr - base_addr);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2098 } else {
2099 in_mem = 0;
2100 pr_err("dump_mem: kzalloc fails!\n");
2101 }
2102 }
2103
2104 if (!from_isr)
2105 _sde_dbg_enable_power(true);
2106
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2107 for (i = 0; i < len_align; i++) {
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2108 u32 x0, x4, x8, xc;
2109
2110 x0 = (addr < end_addr) ? readl_relaxed(addr + 0x0) : 0;
2111 x4 = (addr + 0x4 < end_addr) ? readl_relaxed(addr + 0x4) : 0;
2112 x8 = (addr + 0x8 < end_addr) ? readl_relaxed(addr + 0x8) : 0;
2113 xc = (addr + 0xc < end_addr) ? readl_relaxed(addr + 0xc) : 0;
2114
2115 if (in_log)
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2116 dev_info(sde_dbg_base.dev,
2117 "0x%lx : %08x %08x %08x %08x\n",
2118 addr - base_addr, x0, x4, x8, xc);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2119
2120 if (dump_addr) {
2121 dump_addr[i * 4] = x0;
2122 dump_addr[i * 4 + 1] = x4;
2123 dump_addr[i * 4 + 2] = x8;
2124 dump_addr[i * 4 + 3] = xc;
2125 }
2126
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2127 addr += REG_DUMP_ALIGN;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2128 }
2129
2130 if (!from_isr)
2131 _sde_dbg_enable_power(false);
2132}
2133
2134/**
2135 * _sde_dbg_get_dump_range - helper to retrieve dump length for a range node
2136 * @range_node: range node to dump
2137 * @max_offset: max offset of the register base
2138 * @Return: length
2139 */
2140static u32 _sde_dbg_get_dump_range(struct sde_dbg_reg_offset *range_node,
2141 size_t max_offset)
2142{
2143 u32 length = 0;
2144
2145 if ((range_node->start > range_node->end) ||
2146 (range_node->end > max_offset) || (range_node->start == 0
2147 && range_node->end == 0)) {
2148 length = max_offset;
2149 } else {
2150 length = range_node->end - range_node->start;
2151 }
2152
2153 return length;
2154}
2155
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2156static int _sde_dump_reg_range_cmp(void *priv, struct list_head *a,
2157 struct list_head *b)
2158{
2159 struct sde_dbg_reg_range *ar, *br;
2160
2161 if (!a || !b)
2162 return 0;
2163
2164 ar = container_of(a, struct sde_dbg_reg_range, head);
2165 br = container_of(b, struct sde_dbg_reg_range, head);
2166
2167 return ar->offset.start - br->offset.start;
2168}
2169
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2170/**
2171 * _sde_dump_reg_by_ranges - dump ranges or full range of the register blk base
2172 * @dbg: register blk base structure
2173 * @reg_dump_flag: dump target, memory, kernel log, or both
2174 */
2175static void _sde_dump_reg_by_ranges(struct sde_dbg_reg_base *dbg,
2176 u32 reg_dump_flag)
2177{
2178 char *addr;
2179 size_t len;
2180 struct sde_dbg_reg_range *range_node;
2181
Alan Kwongaa53e682017-07-31 18:21:15 -0400[diff] [blame]2182 if (!dbg || !(dbg->base || dbg->cb)) {
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2183 pr_err("dbg base is null!\n");
2184 return;
2185 }
2186
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2187 dev_info(sde_dbg_base.dev, "%s:=========%s DUMP=========\n", __func__,
2188 dbg->name);
Alan Kwongaa53e682017-07-31 18:21:15 -0400[diff] [blame]2189 if (dbg->cb) {
2190 dbg->cb(dbg->cb_ptr);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2191 /* If there is a list to dump the registers by ranges, use the ranges */
Alan Kwongaa53e682017-07-31 18:21:15 -0400[diff] [blame]2192 } else if (!list_empty(&dbg->sub_range_list)) {
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2193 /* sort the list by start address first */
2194 list_sort(NULL, &dbg->sub_range_list, _sde_dump_reg_range_cmp);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2195 list_for_each_entry(range_node, &dbg->sub_range_list, head) {
2196 len = _sde_dbg_get_dump_range(&range_node->offset,
2197 dbg->max_offset);
2198 addr = dbg->base + range_node->offset.start;
2199 pr_debug("%s: range_base=0x%pK start=0x%x end=0x%x\n",
2200 range_node->range_name,
2201 addr, range_node->offset.start,
2202 range_node->offset.end);
2203
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2204 _sde_dump_reg(range_node->range_name, reg_dump_flag,
2205 dbg->base, addr, len,
2206 &range_node->reg_dump, false);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2207 }
2208 } else {
2209 /* If there is no list to dump ranges, dump all registers */
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2210 dev_info(sde_dbg_base.dev,
2211 "Ranges not found, will dump full registers\n");
2212 dev_info(sde_dbg_base.dev, "base:0x%pK len:0x%zx\n", dbg->base,
2213 dbg->max_offset);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2214 addr = dbg->base;
2215 len = dbg->max_offset;
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2216 _sde_dump_reg(dbg->name, reg_dump_flag, dbg->base, addr, len,
2217 &dbg->reg_dump, false);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2218 }
2219}
2220
2221/**
2222 * _sde_dump_reg_by_blk - dump a named register base region
2223 * @blk_name: register blk name
2224 */
2225static void _sde_dump_reg_by_blk(const char *blk_name)
2226{
2227 struct sde_dbg_base *dbg_base = &sde_dbg_base;
2228 struct sde_dbg_reg_base *blk_base;
2229
2230 if (!dbg_base)
2231 return;
2232
2233 list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head) {
2234 if (strlen(blk_base->name) &&
2235 !strcmp(blk_base->name, blk_name)) {
2236 _sde_dump_reg_by_ranges(blk_base,
2237 dbg_base->enable_reg_dump);
2238 break;
2239 }
2240 }
2241}
2242
2243/**
2244 * _sde_dump_reg_all - dump all register regions
2245 */
2246static void _sde_dump_reg_all(void)
2247{
2248 struct sde_dbg_base *dbg_base = &sde_dbg_base;
2249 struct sde_dbg_reg_base *blk_base;
2250
2251 if (!dbg_base)
2252 return;
2253
2254 list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head)
2255 if (strlen(blk_base->name))
2256 _sde_dump_reg_by_blk(blk_base->name);
2257}
2258
2259/**
2260 * _sde_dump_get_blk_addr - retrieve register block address by name
2261 * @blk_name: register blk name
2262 * @Return: register blk base, or NULL
2263 */
2264static struct sde_dbg_reg_base *_sde_dump_get_blk_addr(const char *blk_name)
2265{
2266 struct sde_dbg_base *dbg_base = &sde_dbg_base;
2267 struct sde_dbg_reg_base *blk_base;
2268
2269 list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head)
2270 if (strlen(blk_base->name) && !strcmp(blk_base->name, blk_name))
2271 return blk_base;
2272
2273 return NULL;
2274}
2275
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2276static void _sde_dbg_dump_sde_dbg_bus(struct sde_dbg_sde_debug_bus *bus)
2277{
2278 bool in_log, in_mem;
2279 u32 **dump_mem = NULL;
2280 u32 *dump_addr = NULL;
2281 u32 status = 0;
2282 struct sde_debug_bus_entry *head;
2283 phys_addr_t phys = 0;
2284 int list_size;
2285 int i;
2286 u32 offset;
2287 void __iomem *mem_base = NULL;
2288 struct sde_dbg_reg_base *reg_base;
2289
2290 if (!bus || !bus->cmn.entries_size)
2291 return;
2292
2293 list_for_each_entry(reg_base, &sde_dbg_base.reg_base_list,
2294 reg_base_head)
2295 if (strlen(reg_base->name) &&
2296 !strcmp(reg_base->name, bus->cmn.name))
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2297 mem_base = reg_base->base + bus->top_blk_off;
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2298
2299 if (!mem_base) {
2300 pr_err("unable to find mem_base for %s\n", bus->cmn.name);
2301 return;
2302 }
2303
2304 dump_mem = &bus->cmn.dumped_content;
2305
2306 /* will keep in memory 4 entries of 4 bytes each */
2307 list_size = (bus->cmn.entries_size * 4 * 4);
2308
2309 in_log = (bus->cmn.enable_mask & SDE_DBG_DUMP_IN_LOG);
2310 in_mem = (bus->cmn.enable_mask & SDE_DBG_DUMP_IN_MEM);
2311
2312 if (!in_log && !in_mem)
2313 return;
2314
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2315 dev_info(sde_dbg_base.dev, "======== start %s dump =========\n",
2316 bus->cmn.name);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2317
2318 if (in_mem) {
2319 if (!(*dump_mem))
2320 *dump_mem = dma_alloc_coherent(sde_dbg_base.dev,
2321 list_size, &phys, GFP_KERNEL);
2322
2323 if (*dump_mem) {
2324 dump_addr = *dump_mem;
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2325 dev_info(sde_dbg_base.dev,
2326 "%s: start_addr:0x%pK len:0x%x\n",
2327 __func__, dump_addr, list_size);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2328 } else {
2329 in_mem = false;
2330 pr_err("dump_mem: allocation fails\n");
2331 }
2332 }
2333
2334 _sde_dbg_enable_power(true);
2335 for (i = 0; i < bus->cmn.entries_size; i++) {
2336 head = bus->entries + i;
2337 writel_relaxed(TEST_MASK(head->block_id, head->test_id),
2338 mem_base + head->wr_addr);
2339 wmb(); /* make sure test bits were written */
2340
Dhaval Patelc063b9e2017-08-08 16:28:10 -0700[diff] [blame]2341 if (bus->cmn.flags & DBGBUS_FLAGS_DSPP) {
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2342 offset = DBGBUS_DSPP_STATUS;
Dhaval Patelc063b9e2017-08-08 16:28:10 -0700[diff] [blame]2343 /* keep DSPP test point enabled */
2344 if (head->wr_addr != DBGBUS_DSPP)
2345 writel_relaxed(0xF, mem_base + DBGBUS_DSPP);
2346 } else {
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2347 offset = head->wr_addr + 0x4;
Dhaval Patelc063b9e2017-08-08 16:28:10 -0700[diff] [blame]2348 }
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2349
2350 status = readl_relaxed(mem_base + offset);
2351
2352 if (in_log)
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2353 dev_info(sde_dbg_base.dev,
2354 "waddr=0x%x blk=%d tst=%d val=0x%x\n",
2355 head->wr_addr, head->block_id,
2356 head->test_id, status);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2357
2358 if (dump_addr && in_mem) {
2359 dump_addr[i*4] = head->wr_addr;
2360 dump_addr[i*4 + 1] = head->block_id;
2361 dump_addr[i*4 + 2] = head->test_id;
2362 dump_addr[i*4 + 3] = status;
2363 }
2364
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]2365 if (head->analyzer)
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -0700[diff] [blame]2366 head->analyzer(mem_base, head, status);
Lloyd Atkinsone221a5c2017-05-01 15:08:23 -0400[diff] [blame]2367
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2368 /* Disable debug bus once we are done */
2369 writel_relaxed(0, mem_base + head->wr_addr);
Dhaval Patelc063b9e2017-08-08 16:28:10 -0700[diff] [blame]2370 if (bus->cmn.flags & DBGBUS_FLAGS_DSPP &&
2371 head->wr_addr != DBGBUS_DSPP)
2372 writel_relaxed(0x0, mem_base + DBGBUS_DSPP);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2373 }
2374 _sde_dbg_enable_power(false);
2375
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2376 dev_info(sde_dbg_base.dev, "======== end %s dump =========\n",
2377 bus->cmn.name);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2378}
2379
2380static void _sde_dbg_dump_vbif_debug_bus_entry(
2381 struct vbif_debug_bus_entry *head, void __iomem *mem_base,
2382 u32 *dump_addr, bool in_log)
2383{
2384 int i, j;
2385 u32 val;
2386
2387 if (!dump_addr && !in_log)
2388 return;
2389
2390 for (i = 0; i < head->block_cnt; i++) {
2391 writel_relaxed(1 << (i + head->bit_offset),
2392 mem_base + head->block_bus_addr);
2393 /* make sure that current bus blcok enable */
2394 wmb();
2395 for (j = head->test_pnt_start; j < head->test_pnt_cnt; j++) {
2396 writel_relaxed(j, mem_base + head->block_bus_addr + 4);
2397 /* make sure that test point is enabled */
2398 wmb();
2399 val = readl_relaxed(mem_base + MMSS_VBIF_TEST_BUS_OUT);
2400 if (dump_addr) {
2401 *dump_addr++ = head->block_bus_addr;
2402 *dump_addr++ = i;
2403 *dump_addr++ = j;
2404 *dump_addr++ = val;
2405 }
2406 if (in_log)
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2407 dev_info(sde_dbg_base.dev,
2408 "testpoint:%x arb/xin id=%d index=%d val=0x%x\n",
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2409 head->block_bus_addr, i, j, val);
2410 }
2411 }
2412}
2413
2414static void _sde_dbg_dump_vbif_dbg_bus(struct sde_dbg_vbif_debug_bus *bus)
2415{
2416 bool in_log, in_mem;
2417 u32 **dump_mem = NULL;
2418 u32 *dump_addr = NULL;
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]2419 u32 value, d0, d1;
Clarence Ip5b730b42017-07-31 18:04:06 -0400[diff] [blame]2420 unsigned long reg, reg1, reg2;
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2421 struct vbif_debug_bus_entry *head;
2422 phys_addr_t phys = 0;
2423 int i, list_size = 0;
2424 void __iomem *mem_base = NULL;
2425 struct vbif_debug_bus_entry *dbg_bus;
2426 u32 bus_size;
2427 struct sde_dbg_reg_base *reg_base;
2428
2429 if (!bus || !bus->cmn.entries_size)
2430 return;
2431
2432 list_for_each_entry(reg_base, &sde_dbg_base.reg_base_list,
2433 reg_base_head)
2434 if (strlen(reg_base->name) &&
2435 !strcmp(reg_base->name, bus->cmn.name))
2436 mem_base = reg_base->base;
2437
2438 if (!mem_base) {
2439 pr_err("unable to find mem_base for %s\n", bus->cmn.name);
2440 return;
2441 }
2442
2443 dbg_bus = bus->entries;
2444 bus_size = bus->cmn.entries_size;
2445 list_size = bus->cmn.entries_size;
2446 dump_mem = &bus->cmn.dumped_content;
2447
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2448 dev_info(sde_dbg_base.dev, "======== start %s dump =========\n",
2449 bus->cmn.name);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2450
2451 if (!dump_mem || !dbg_bus || !bus_size || !list_size)
2452 return;
2453
2454 /* allocate memory for each test point */
2455 for (i = 0; i < bus_size; i++) {
2456 head = dbg_bus + i;
2457 list_size += (head->block_cnt * head->test_pnt_cnt);
2458 }
2459
2460 /* 4 bytes * 4 entries for each test point*/
2461 list_size *= 16;
2462
2463 in_log = (bus->cmn.enable_mask & SDE_DBG_DUMP_IN_LOG);
2464 in_mem = (bus->cmn.enable_mask & SDE_DBG_DUMP_IN_MEM);
2465
2466 if (!in_log && !in_mem)
2467 return;
2468
2469 if (in_mem) {
2470 if (!(*dump_mem))
2471 *dump_mem = dma_alloc_coherent(sde_dbg_base.dev,
2472 list_size, &phys, GFP_KERNEL);
2473
2474 if (*dump_mem) {
2475 dump_addr = *dump_mem;
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2476 dev_info(sde_dbg_base.dev,
2477 "%s: start_addr:0x%pK len:0x%x\n",
2478 __func__, dump_addr, list_size);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2479 } else {
2480 in_mem = false;
2481 pr_err("dump_mem: allocation fails\n");
2482 }
2483 }
2484
2485 _sde_dbg_enable_power(true);
2486
2487 value = readl_relaxed(mem_base + MMSS_VBIF_CLKON);
2488 writel_relaxed(value | BIT(1), mem_base + MMSS_VBIF_CLKON);
2489
2490 /* make sure that vbif core is on */
2491 wmb();
2492
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]2493 /**
Clarence Ip5b730b42017-07-31 18:04:06 -0400[diff] [blame]2494 * Extract VBIF error info based on XIN halt and error status.
2495 * If the XIN client is not in HALT state, or an error is detected,
2496 * then retrieve the VBIF error info for it.
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]2497 */
2498 reg = readl_relaxed(mem_base + MMSS_VBIF_XIN_HALT_CTRL1);
Clarence Ip5b730b42017-07-31 18:04:06 -0400[diff] [blame]2499 reg1 = readl_relaxed(mem_base + MMSS_VBIF_PND_ERR);
2500 reg2 = readl_relaxed(mem_base + MMSS_VBIF_SRC_ERR);
2501 dev_err(sde_dbg_base.dev,
2502 "XIN HALT:0x%lX, PND ERR:0x%lX, SRC ERR:0x%lX\n",
2503 reg, reg1, reg2);
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]2504 reg >>= 16;
Clarence Ip5b730b42017-07-31 18:04:06 -0400[diff] [blame]2505 reg &= ~(reg1 | reg2);
Benjamin Chan4e04eae2017-07-20 22:49:52 -0400[diff] [blame]2506 for (i = 0; i < MMSS_VBIF_CLIENT_NUM; i++) {
2507 if (!test_bit(0, &reg)) {
2508 writel_relaxed(i, mem_base + MMSS_VBIF_ERR_INFO);
2509 /* make sure reg write goes through */
2510 wmb();
2511
2512 d0 = readl_relaxed(mem_base + MMSS_VBIF_ERR_INFO);
2513 d1 = readl_relaxed(mem_base + MMSS_VBIF_ERR_INFO_1);
2514
2515 dev_err(sde_dbg_base.dev,
2516 "Client:%d, errinfo=0x%X, errinfo1=0x%X\n",
2517 i, d0, d1);
2518 }
2519 reg >>= 1;
2520 }
2521
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2522 for (i = 0; i < bus_size; i++) {
2523 head = dbg_bus + i;
2524
2525 writel_relaxed(0, mem_base + head->disable_bus_addr);
2526 writel_relaxed(BIT(0), mem_base + MMSS_VBIF_TEST_BUS_OUT_CTRL);
2527 /* make sure that other bus is off */
2528 wmb();
2529
2530 _sde_dbg_dump_vbif_debug_bus_entry(head, mem_base, dump_addr,
2531 in_log);
2532 if (dump_addr)
2533 dump_addr += (head->block_cnt * head->test_pnt_cnt * 4);
2534 }
2535
2536 _sde_dbg_enable_power(false);
2537
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]2538 dev_info(sde_dbg_base.dev, "======== end %s dump =========\n",
2539 bus->cmn.name);
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2540}
2541
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2542/**
2543 * _sde_dump_array - dump array of register bases
2544 * @blk_arr: array of register base pointers
2545 * @len: length of blk_arr
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2546 * @do_panic: whether to trigger a panic after dumping
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2547 * @name: string indicating origin of dump
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2548 * @dump_dbgbus_sde: whether to dump the sde debug bus
2549 * @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2550 */
2551static void _sde_dump_array(struct sde_dbg_reg_base *blk_arr[],
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2552 u32 len, bool do_panic, const char *name, bool dump_dbgbus_sde,
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2553 bool dump_dbgbus_vbif_rt, bool dump_all)
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2554{
2555 int i;
2556
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2557 sde_evtlog_dump_all(sde_dbg_base.evtlog);
2558
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2559 if (dump_all || !blk_arr || !len) {
2560 _sde_dump_reg_all();
2561 } else {
2562 for (i = 0; i < len; i++) {
2563 if (blk_arr[i] != NULL)
2564 _sde_dump_reg_by_ranges(blk_arr[i],
2565 sde_dbg_base.enable_reg_dump);
2566 }
2567 }
2568
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2569 if (dump_dbgbus_sde)
2570 _sde_dbg_dump_sde_dbg_bus(&sde_dbg_base.dbgbus_sde);
2571
2572 if (dump_dbgbus_vbif_rt)
2573 _sde_dbg_dump_vbif_dbg_bus(&sde_dbg_base.dbgbus_vbif_rt);
2574
Dhaval Patelf9f3ffe2017-08-16 16:03:10 -0700[diff] [blame]2575 if (sde_dbg_base.dsi_dbg_bus || dump_all)
2576 dsi_ctrl_debug_dump();
2577
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2578 if (do_panic && sde_dbg_base.panic_on_err)
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2579 panic(name);
2580}
2581
2582/**
2583 * _sde_dump_work - deferred dump work function
2584 * @work: work structure
2585 */
2586static void _sde_dump_work(struct work_struct *work)
2587{
2588 _sde_dump_array(sde_dbg_base.req_dump_blks,
2589 ARRAY_SIZE(sde_dbg_base.req_dump_blks),
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2590 sde_dbg_base.work_panic, "evtlog_workitem",
2591 sde_dbg_base.dbgbus_sde.cmn.include_in_deferred_work,
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2592 sde_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work,
2593 sde_dbg_base.dump_all);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2594}
2595
2596void sde_dbg_dump(bool queue_work, const char *name, ...)
2597{
2598 int i, index = 0;
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2599 bool do_panic = false;
2600 bool dump_dbgbus_sde = false;
2601 bool dump_dbgbus_vbif_rt = false;
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2602 bool dump_all = false;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2603 va_list args;
2604 char *blk_name = NULL;
2605 struct sde_dbg_reg_base *blk_base = NULL;
2606 struct sde_dbg_reg_base **blk_arr;
2607 u32 blk_len;
2608
Clarence Ip6ac61cc2017-03-22 15:01:53 -0400[diff] [blame]2609 if (!sde_evtlog_is_enabled(sde_dbg_base.evtlog, SDE_EVTLOG_ALWAYS))
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2610 return;
2611
2612 if (queue_work && work_pending(&sde_dbg_base.dump_work))
2613 return;
2614
2615 blk_arr = &sde_dbg_base.req_dump_blks[0];
2616 blk_len = ARRAY_SIZE(sde_dbg_base.req_dump_blks);
2617
2618 memset(sde_dbg_base.req_dump_blks, 0,
2619 sizeof(sde_dbg_base.req_dump_blks));
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2620 sde_dbg_base.dump_all = false;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2621
2622 va_start(args, name);
Lloyd Atkinsonf3e8ef32017-03-22 18:49:49 -0400[diff] [blame]2623 i = 0;
2624 while ((blk_name = va_arg(args, char*))) {
2625 if (i++ >= SDE_EVTLOG_MAX_DATA) {
2626 pr_err("could not parse all dump arguments\n");
2627 break;
2628 }
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2629 if (IS_ERR_OR_NULL(blk_name))
2630 break;
2631
2632 blk_base = _sde_dump_get_blk_addr(blk_name);
2633 if (blk_base) {
2634 if (index < blk_len) {
2635 blk_arr[index] = blk_base;
2636 index++;
2637 } else {
2638 pr_err("insufficient space to to dump %s\n",
2639 blk_name);
2640 }
2641 }
2642
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2643 if (!strcmp(blk_name, "all"))
2644 dump_all = true;
2645
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2646 if (!strcmp(blk_name, "dbg_bus"))
2647 dump_dbgbus_sde = true;
2648
2649 if (!strcmp(blk_name, "vbif_dbg_bus"))
2650 dump_dbgbus_vbif_rt = true;
2651
Dhaval Patelf9f3ffe2017-08-16 16:03:10 -0700[diff] [blame]2652 if (!strcmp(blk_name, "dsi_dbg_bus"))
2653 sde_dbg_base.dsi_dbg_bus = true;
2654
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2655 if (!strcmp(blk_name, "panic"))
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2656 do_panic = true;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2657 }
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2658 va_end(args);
2659
2660 if (queue_work) {
2661 /* schedule work to dump later */
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2662 sde_dbg_base.work_panic = do_panic;
2663 sde_dbg_base.dbgbus_sde.cmn.include_in_deferred_work =
2664 dump_dbgbus_sde;
2665 sde_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
2666 dump_dbgbus_vbif_rt;
Lloyd Atkinsonb5aff9a2017-09-27 15:39:44 -0400[diff] [blame]2667 sde_dbg_base.dump_all = dump_all;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2668 schedule_work(&sde_dbg_base.dump_work);
2669 } else {
Lloyd Atkinson274cc462017-02-21 11:52:06 -0500[diff] [blame]2670 _sde_dump_array(blk_arr, blk_len, do_panic, name,
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2671 dump_dbgbus_sde, dump_dbgbus_vbif_rt, dump_all);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2672 }
2673}
2674
2675/*
2676 * sde_dbg_debugfs_open - debugfs open handler for evtlog dump
2677 * @inode: debugfs inode
2678 * @file: file handle
2679 */
2680static int sde_dbg_debugfs_open(struct inode *inode, struct file *file)
2681{
2682 /* non-seekable */
2683 file->f_mode &= ~(FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE);
2684 file->private_data = inode->i_private;
2685 return 0;
2686}
2687
2688/**
2689 * sde_evtlog_dump_read - debugfs read handler for evtlog dump
2690 * @file: file handler
2691 * @buff: user buffer content for debugfs
2692 * @count: size of user buffer
2693 * @ppos: position offset of user buffer
2694 */
2695static ssize_t sde_evtlog_dump_read(struct file *file, char __user *buff,
2696 size_t count, loff_t *ppos)
2697{
2698 ssize_t len = 0;
2699 char evtlog_buf[SDE_EVTLOG_BUF_MAX];
2700
2701 len = sde_evtlog_dump_to_buffer(sde_dbg_base.evtlog, evtlog_buf,
2702 SDE_EVTLOG_BUF_MAX);
2703 if (copy_to_user(buff, evtlog_buf, len))
2704 return -EFAULT;
2705 *ppos += len;
2706
2707 return len;
2708}
2709
2710/**
2711 * sde_evtlog_dump_write - debugfs write handler for evtlog dump
2712 * @file: file handler
2713 * @user_buf: user buffer content from debugfs
2714 * @count: size of user buffer
2715 * @ppos: position offset of user buffer
2716 */
2717static ssize_t sde_evtlog_dump_write(struct file *file,
2718 const char __user *user_buf, size_t count, loff_t *ppos)
2719{
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]2720 _sde_dump_array(NULL, 0, sde_dbg_base.panic_on_err, "dump_debugfs",
2721 true, true, true);
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2722
2723 return count;
2724}
2725
2726static const struct file_operations sde_evtlog_fops = {
2727 .open = sde_dbg_debugfs_open,
2728 .read = sde_evtlog_dump_read,
2729 .write = sde_evtlog_dump_write,
2730};
2731
Clarence Ip6ac61cc2017-03-22 15:01:53 -0400[diff] [blame]2732/*
2733 * sde_evtlog_filter_show - read callback for evtlog filter
2734 * @s: pointer to seq_file object
2735 * @data: pointer to private data
2736 */
2737static int sde_evtlog_filter_show(struct seq_file *s, void *data)
2738{
2739 struct sde_dbg_evtlog *evtlog;
2740 char buffer[64];
2741 int i;
2742
2743 if (!s || !s->private)
2744 return -EINVAL;
2745
2746 evtlog = s->private;
2747
2748 for (i = 0; !sde_evtlog_get_filter(
2749 evtlog, i, buffer, ARRAY_SIZE(buffer)); ++i)
2750 seq_printf(s, "*%s*\n", buffer);
2751 return 0;
2752}
2753
2754/*
2755 * sde_evtlog_filter_open - debugfs open handler for evtlog filter
2756 * @inode: debugfs inode
2757 * @file: file handle
2758 * Returns: zero on success
2759 */
2760static int sde_evtlog_filter_open(struct inode *inode, struct file *file)
2761{
2762 if (!file)
2763 return -EINVAL;
2764
2765 return single_open(file, sde_evtlog_filter_show, inode->i_private);
2766}
2767
2768/*
2769 * sde_evtlog_filter_write - write callback for evtlog filter
2770 * @file: pointer to file structure
2771 * @user_buf: pointer to incoming user data
2772 * @count: size of incoming user buffer
2773 * @ppos: pointer to file offset
2774 */
2775static ssize_t sde_evtlog_filter_write(struct file *file,
2776 const char __user *user_buf, size_t count, loff_t *ppos)
2777{
2778 char *tmp_filter = NULL;
2779 ssize_t rc = 0;
2780
2781 if (count > 0) {
2782 /* copy user provided string and null terminate it */
2783 tmp_filter = kzalloc(count + 1, GFP_KERNEL);
2784 if (!tmp_filter)
2785 rc = -ENOMEM;
2786 else if (copy_from_user(tmp_filter, user_buf, count))
2787 rc = -EFAULT;
2788 }
2789
2790 /* update actual filter configuration on success */
2791 if (!rc) {
2792 sde_evtlog_set_filter(sde_dbg_base.evtlog, tmp_filter);
2793 rc = count;
2794 }
2795 kfree(tmp_filter);
2796
2797 return rc;
2798}
2799
2800static const struct file_operations sde_evtlog_filter_fops = {
2801 .open = sde_evtlog_filter_open,
2802 .write = sde_evtlog_filter_write,
2803 .read = seq_read,
2804 .llseek = seq_lseek,
2805 .release = seq_release
2806};
2807
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2808/**
2809 * sde_dbg_reg_base_release - release allocated reg dump file private data
2810 * @inode: debugfs inode
2811 * @file: file handle
2812 * @Return: 0 on success
2813 */
2814static int sde_dbg_reg_base_release(struct inode *inode, struct file *file)
2815{
2816 struct sde_dbg_reg_base *dbg = file->private_data;
2817
2818 if (dbg && dbg->buf) {
2819 kfree(dbg->buf);
2820 dbg->buf_len = 0;
2821 dbg->buf = NULL;
2822 }
2823 return 0;
2824}
2825
2826
2827/**
2828 * sde_dbg_reg_base_offset_write - set new offset and len to debugfs reg base
2829 * @file: file handler
2830 * @user_buf: user buffer content from debugfs
2831 * @count: size of user buffer
2832 * @ppos: position offset of user buffer
2833 */
2834static ssize_t sde_dbg_reg_base_offset_write(struct file *file,
2835 const char __user *user_buf, size_t count, loff_t *ppos)
2836{
2837 struct sde_dbg_reg_base *dbg = file->private_data;
2838 u32 off = 0;
2839 u32 cnt = DEFAULT_BASE_REG_CNT;
2840 char buf[24];
2841
2842 if (!dbg)
2843 return -ENODEV;
2844
2845 if (count >= sizeof(buf))
2846 return -EFAULT;
2847
2848 if (copy_from_user(buf, user_buf, count))
2849 return -EFAULT;
2850
2851 buf[count] = 0; /* end of string */
2852
2853 if (sscanf(buf, "%5x %x", &off, &cnt) != 2)
2854 return -EFAULT;
2855
2856 if (off > dbg->max_offset)
2857 return -EINVAL;
2858
Lloyd Atkinsonc0121402017-05-23 11:28:48 -0400[diff] [blame]2859 if (off % sizeof(u32))
2860 return -EINVAL;
2861
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2862 if (cnt > (dbg->max_offset - off))
2863 cnt = dbg->max_offset - off;
2864
2865 dbg->off = off;
2866 dbg->cnt = cnt;
2867
2868 pr_debug("offset=%x cnt=%x\n", off, cnt);
2869
2870 return count;
2871}
2872
2873/**
2874 * sde_dbg_reg_base_offset_read - read current offset and len of register base
2875 * @file: file handler
2876 * @user_buf: user buffer content from debugfs
2877 * @count: size of user buffer
2878 * @ppos: position offset of user buffer
2879 */
2880static ssize_t sde_dbg_reg_base_offset_read(struct file *file,
2881 char __user *buff, size_t count, loff_t *ppos)
2882{
2883 struct sde_dbg_reg_base *dbg = file->private_data;
2884 int len = 0;
2885 char buf[24] = {'\0'};
2886
2887 if (!dbg)
2888 return -ENODEV;
2889
2890 if (*ppos)
2891 return 0; /* the end */
2892
Lloyd Atkinsonc0121402017-05-23 11:28:48 -0400[diff] [blame]2893 if (dbg->off % sizeof(u32))
2894 return -EFAULT;
2895
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2896 len = snprintf(buf, sizeof(buf), "0x%08zx %zx\n", dbg->off, dbg->cnt);
2897 if (len < 0 || len >= sizeof(buf))
2898 return 0;
2899
2900 if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
2901 return -EFAULT;
2902
2903 *ppos += len; /* increase offset */
2904
2905 return len;
2906}
2907
2908/**
2909 * sde_dbg_reg_base_reg_write - write to reg base hw at offset a given value
2910 * @file: file handler
2911 * @user_buf: user buffer content from debugfs
2912 * @count: size of user buffer
2913 * @ppos: position offset of user buffer
2914 */
2915static ssize_t sde_dbg_reg_base_reg_write(struct file *file,
2916 const char __user *user_buf, size_t count, loff_t *ppos)
2917{
2918 struct sde_dbg_reg_base *dbg = file->private_data;
2919 size_t off;
2920 u32 data, cnt;
2921 char buf[24];
2922
2923 if (!dbg)
2924 return -ENODEV;
2925
2926 if (count >= sizeof(buf))
2927 return -EFAULT;
2928
2929 if (copy_from_user(buf, user_buf, count))
2930 return -EFAULT;
2931
2932 buf[count] = 0; /* end of string */
2933
2934 cnt = sscanf(buf, "%zx %x", &off, &data);
2935
2936 if (cnt < 2)
2937 return -EFAULT;
2938
Lloyd Atkinsonc0121402017-05-23 11:28:48 -0400[diff] [blame]2939 if (off % sizeof(u32))
2940 return -EFAULT;
2941
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2942 if (off >= dbg->max_offset)
2943 return -EFAULT;
2944
2945 _sde_dbg_enable_power(true);
2946
2947 writel_relaxed(data, dbg->base + off);
2948
2949 _sde_dbg_enable_power(false);
2950
2951 pr_debug("addr=%zx data=%x\n", off, data);
2952
2953 return count;
2954}
2955
2956/**
2957 * sde_dbg_reg_base_reg_read - read len from reg base hw at current offset
2958 * @file: file handler
2959 * @user_buf: user buffer content from debugfs
2960 * @count: size of user buffer
2961 * @ppos: position offset of user buffer
2962 */
2963static ssize_t sde_dbg_reg_base_reg_read(struct file *file,
2964 char __user *user_buf, size_t count, loff_t *ppos)
2965{
2966 struct sde_dbg_reg_base *dbg = file->private_data;
2967 size_t len;
2968
2969 if (!dbg) {
2970 pr_err("invalid handle\n");
2971 return -ENODEV;
2972 }
2973
2974 if (!dbg->buf) {
2975 char dump_buf[64];
2976 char *ptr;
2977 int cnt, tot;
2978
2979 dbg->buf_len = sizeof(dump_buf) *
2980 DIV_ROUND_UP(dbg->cnt, ROW_BYTES);
2981 dbg->buf = kzalloc(dbg->buf_len, GFP_KERNEL);
2982
2983 if (!dbg->buf)
2984 return -ENOMEM;
2985
Lloyd Atkinsonc0121402017-05-23 11:28:48 -0400[diff] [blame]2986 if (dbg->off % sizeof(u32))
2987 return -EFAULT;
2988
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]2989 ptr = dbg->base + dbg->off;
2990 tot = 0;
2991
2992 _sde_dbg_enable_power(true);
2993
2994 for (cnt = dbg->cnt; cnt > 0; cnt -= ROW_BYTES) {
2995 hex_dump_to_buffer(ptr, min(cnt, ROW_BYTES),
2996 ROW_BYTES, GROUP_BYTES, dump_buf,
2997 sizeof(dump_buf), false);
2998 len = scnprintf(dbg->buf + tot, dbg->buf_len - tot,
2999 "0x%08x: %s\n",
3000 ((int) (unsigned long) ptr) -
3001 ((int) (unsigned long) dbg->base),
3002 dump_buf);
3003
3004 ptr += ROW_BYTES;
3005 tot += len;
3006 if (tot >= dbg->buf_len)
3007 break;
3008 }
3009
3010 _sde_dbg_enable_power(false);
3011
3012 dbg->buf_len = tot;
3013 }
3014
3015 if (*ppos >= dbg->buf_len)
3016 return 0; /* done reading */
3017
3018 len = min(count, dbg->buf_len - (size_t) *ppos);
3019 if (copy_to_user(user_buf, dbg->buf + *ppos, len)) {
3020 pr_err("failed to copy to user\n");
3021 return -EFAULT;
3022 }
3023
3024 *ppos += len; /* increase offset */
3025
3026 return len;
3027}
3028
3029static const struct file_operations sde_off_fops = {
3030 .open = sde_dbg_debugfs_open,
3031 .release = sde_dbg_reg_base_release,
3032 .read = sde_dbg_reg_base_offset_read,
3033 .write = sde_dbg_reg_base_offset_write,
3034};
3035
3036static const struct file_operations sde_reg_fops = {
3037 .open = sde_dbg_debugfs_open,
3038 .release = sde_dbg_reg_base_release,
3039 .read = sde_dbg_reg_base_reg_read,
3040 .write = sde_dbg_reg_base_reg_write,
3041};
3042
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3043int sde_dbg_debugfs_register(struct dentry *debugfs_root)
3044{
3045 static struct sde_dbg_base *dbg = &sde_dbg_base;
3046 struct sde_dbg_reg_base *blk_base;
3047 char debug_name[80] = "";
3048
Dhaval Patel6c666622017-03-21 23:02:59 -0700[diff] [blame]3049 if (!debugfs_root)
3050 return -EINVAL;
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3051
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3052 debugfs_create_file("dump", 0600, debugfs_root, NULL,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3053 &sde_evtlog_fops);
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3054 debugfs_create_u32("enable", 0600, debugfs_root,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3055 &(sde_dbg_base.evtlog->enable));
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3056 debugfs_create_file("filter", 0600, debugfs_root,
Clarence Ip6ac61cc2017-03-22 15:01:53 -0400[diff] [blame]3057 sde_dbg_base.evtlog,
3058 &sde_evtlog_filter_fops);
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3059 debugfs_create_u32("panic", 0600, debugfs_root,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3060 &sde_dbg_base.panic_on_err);
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3061 debugfs_create_u32("reg_dump", 0600, debugfs_root,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3062 &sde_dbg_base.enable_reg_dump);
3063
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3064 if (dbg->dbgbus_sde.entries) {
3065 dbg->dbgbus_sde.cmn.name = DBGBUS_NAME_SDE;
3066 snprintf(debug_name, sizeof(debug_name), "%s_dbgbus",
3067 dbg->dbgbus_sde.cmn.name);
3068 dbg->dbgbus_sde.cmn.enable_mask = DEFAULT_DBGBUS_SDE;
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3069 debugfs_create_u32(debug_name, 0600, debugfs_root,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3070 &dbg->dbgbus_sde.cmn.enable_mask);
3071 }
3072
3073 if (dbg->dbgbus_vbif_rt.entries) {
3074 dbg->dbgbus_vbif_rt.cmn.name = DBGBUS_NAME_VBIF_RT;
3075 snprintf(debug_name, sizeof(debug_name), "%s_dbgbus",
3076 dbg->dbgbus_vbif_rt.cmn.name);
3077 dbg->dbgbus_vbif_rt.cmn.enable_mask = DEFAULT_DBGBUS_VBIFRT;
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3078 debugfs_create_u32(debug_name, 0600, debugfs_root,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3079 &dbg->dbgbus_vbif_rt.cmn.enable_mask);
3080 }
3081
3082 list_for_each_entry(blk_base, &dbg->reg_base_list, reg_base_head) {
3083 snprintf(debug_name, sizeof(debug_name), "%s_off",
3084 blk_base->name);
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3085 debugfs_create_file(debug_name, 0600, debugfs_root, blk_base,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3086 &sde_off_fops);
3087
3088 snprintf(debug_name, sizeof(debug_name), "%s_reg",
3089 blk_base->name);
Lloyd Atkinson8de415a2017-05-23 11:31:16 -0400[diff] [blame]3090 debugfs_create_file(debug_name, 0600, debugfs_root, blk_base,
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3091 &sde_reg_fops);
3092 }
3093
3094 return 0;
3095}
3096
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3097static void _sde_dbg_debugfs_destroy(void)
3098{
3099}
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3100
3101void sde_dbg_init_dbg_buses(u32 hwversion)
3102{
3103 static struct sde_dbg_base *dbg = &sde_dbg_base;
3104
3105 memset(&dbg->dbgbus_sde, 0, sizeof(dbg->dbgbus_sde));
3106 memset(&dbg->dbgbus_vbif_rt, 0, sizeof(dbg->dbgbus_vbif_rt));
3107
Benjamin Chanbeaaf6f2017-09-08 15:25:50 -0400[diff] [blame]3108 if (IS_MSM8998_TARGET(hwversion)) {
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3109 dbg->dbgbus_sde.entries = dbg_bus_sde_8998;
3110 dbg->dbgbus_sde.cmn.entries_size = ARRAY_SIZE(dbg_bus_sde_8998);
3111 dbg->dbgbus_sde.cmn.flags = DBGBUS_FLAGS_DSPP;
3112
3113 dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998;
3114 dbg->dbgbus_vbif_rt.cmn.entries_size =
3115 ARRAY_SIZE(vbif_dbg_bus_msm8998);
Jayant Shekhar2b72ce22017-09-12 11:26:44 +0530[diff] [blame]3116 } else if (IS_SDM845_TARGET(hwversion) || IS_SDM670_TARGET(hwversion)) {
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3117 dbg->dbgbus_sde.entries = dbg_bus_sde_sdm845;
3118 dbg->dbgbus_sde.cmn.entries_size =
3119 ARRAY_SIZE(dbg_bus_sde_sdm845);
3120 dbg->dbgbus_sde.cmn.flags = DBGBUS_FLAGS_DSPP;
3121
3122 /* vbif is unchanged vs 8998 */
3123 dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998;
3124 dbg->dbgbus_vbif_rt.cmn.entries_size =
3125 ARRAY_SIZE(vbif_dbg_bus_msm8998);
Benjamin Chanbeaaf6f2017-09-08 15:25:50 -0400[diff] [blame]3126 } else {
3127 pr_err("unsupported chipset id %X\n", hwversion);
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3128 }
3129}
3130
3131int sde_dbg_init(struct device *dev, struct sde_dbg_power_ctrl *power_ctrl)
3132{
3133 if (!dev || !power_ctrl) {
3134 pr_err("invalid params\n");
3135 return -EINVAL;
3136 }
3137
3138 INIT_LIST_HEAD(&sde_dbg_base.reg_base_list);
3139 sde_dbg_base.dev = dev;
3140 sde_dbg_base.power_ctrl = *power_ctrl;
3141
3142 sde_dbg_base.evtlog = sde_evtlog_init();
3143 if (IS_ERR_OR_NULL(sde_dbg_base.evtlog))
3144 return PTR_ERR(sde_dbg_base.evtlog);
3145
3146 sde_dbg_base_evtlog = sde_dbg_base.evtlog;
3147
3148 INIT_WORK(&sde_dbg_base.dump_work, _sde_dump_work);
3149 sde_dbg_base.work_panic = false;
3150 sde_dbg_base.panic_on_err = DEFAULT_PANIC;
3151 sde_dbg_base.enable_reg_dump = DEFAULT_REGDUMP;
3152
3153 pr_info("evtlog_status: enable:%d, panic:%d, dump:%d\n",
3154 sde_dbg_base.evtlog->enable, sde_dbg_base.panic_on_err,
3155 sde_dbg_base.enable_reg_dump);
3156
3157 return 0;
3158}
3159
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]3160static void sde_dbg_reg_base_destroy(void)
3161{
3162 struct sde_dbg_reg_range *range_node, *range_tmp;
3163 struct sde_dbg_reg_base *blk_base, *blk_tmp;
3164 struct sde_dbg_base *dbg_base = &sde_dbg_base;
3165
3166 if (!dbg_base)
3167 return;
3168
3169 list_for_each_entry_safe(blk_base, blk_tmp, &dbg_base->reg_base_list,
3170 reg_base_head) {
3171 list_for_each_entry_safe(range_node, range_tmp,
3172 &blk_base->sub_range_list, head) {
3173 list_del(&range_node->head);
3174 kfree(range_node);
3175 }
3176 list_del(&blk_base->reg_base_head);
3177 kfree(blk_base);
3178 }
3179}
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3180/**
3181 * sde_dbg_destroy - destroy sde debug facilities
3182 */
3183void sde_dbg_destroy(void)
3184{
3185 _sde_dbg_debugfs_destroy();
3186 sde_dbg_base_evtlog = NULL;
3187 sde_evtlog_destroy(sde_dbg_base.evtlog);
3188 sde_dbg_base.evtlog = NULL;
Dhaval Patela2430842017-06-15 14:32:36 -0700[diff] [blame]3189 sde_dbg_reg_base_destroy();
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3190}
3191
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3192int sde_dbg_reg_register_base(const char *name, void __iomem *base,
3193 size_t max_offset)
3194{
3195 struct sde_dbg_base *dbg_base = &sde_dbg_base;
3196 struct sde_dbg_reg_base *reg_base;
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3197
3198 if (!name || !strlen(name)) {
3199 pr_err("no debug name provided\n");
3200 return -EINVAL;
3201 }
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3202
3203 reg_base = kzalloc(sizeof(*reg_base), GFP_KERNEL);
3204 if (!reg_base)
3205 return -ENOMEM;
3206
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -0700[diff] [blame]3207 strlcpy(reg_base->name, name, sizeof(reg_base->name));
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3208 reg_base->base = base;
3209 reg_base->max_offset = max_offset;
3210 reg_base->off = 0;
3211 reg_base->cnt = DEFAULT_BASE_REG_CNT;
3212 reg_base->reg_dump = NULL;
3213
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3214 /* Initialize list to make sure check for null list will be valid */
3215 INIT_LIST_HEAD(&reg_base->sub_range_list);
3216
3217 pr_debug("%s base: %pK max_offset 0x%zX\n", reg_base->name,
3218 reg_base->base, reg_base->max_offset);
3219
3220 list_add(&reg_base->reg_base_head, &dbg_base->reg_base_list);
3221
3222 return 0;
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3223}
3224
Alan Kwongaa53e682017-07-31 18:21:15 -0400[diff] [blame]3225int sde_dbg_reg_register_cb(const char *name, void (*cb)(void *), void *ptr)
3226{
3227 struct sde_dbg_base *dbg_base = &sde_dbg_base;
3228 struct sde_dbg_reg_base *reg_base;
3229
3230 if (!name || !strlen(name)) {
3231 pr_err("no debug name provided\n");
3232 return -EINVAL;
3233 }
3234
3235 reg_base = kzalloc(sizeof(*reg_base), GFP_KERNEL);
3236 if (!reg_base)
3237 return -ENOMEM;
3238
3239 strlcpy(reg_base->name, name, sizeof(reg_base->name));
3240 reg_base->base = NULL;
3241 reg_base->max_offset = 0;
3242 reg_base->off = 0;
3243 reg_base->cnt = DEFAULT_BASE_REG_CNT;
3244 reg_base->reg_dump = NULL;
3245 reg_base->cb = cb;
3246 reg_base->cb_ptr = ptr;
3247
3248 /* Initialize list to make sure check for null list will be valid */
3249 INIT_LIST_HEAD(&reg_base->sub_range_list);
3250
3251 pr_debug("%s cb: %pK cb_ptr: %pK\n", reg_base->name,
3252 reg_base->cb, reg_base->cb_ptr);
3253
3254 list_add(&reg_base->reg_base_head, &dbg_base->reg_base_list);
3255
3256 return 0;
3257}
3258
3259void sde_dbg_reg_unregister_cb(const char *name, void (*cb)(void *), void *ptr)
3260{
3261 struct sde_dbg_base *dbg_base = &sde_dbg_base;
3262 struct sde_dbg_reg_base *reg_base;
3263
3264 if (!dbg_base)
3265 return;
3266
3267 list_for_each_entry(reg_base, &dbg_base->reg_base_list, reg_base_head) {
3268 if (strlen(reg_base->name) &&
3269 !strcmp(reg_base->name, name)) {
3270 pr_debug("%s cb: %pK cb_ptr: %pK\n", reg_base->name,
3271 reg_base->cb, reg_base->cb_ptr);
3272 list_del(&reg_base->reg_base_head);
3273 kfree(reg_base);
3274 break;
3275 }
3276 }
3277}
3278
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3279void sde_dbg_reg_register_dump_range(const char *base_name,
3280 const char *range_name, u32 offset_start, u32 offset_end,
3281 uint32_t xin_id)
3282{
3283 struct sde_dbg_reg_base *reg_base;
3284 struct sde_dbg_reg_range *range;
3285
3286 reg_base = _sde_dump_get_blk_addr(base_name);
3287 if (!reg_base) {
3288 pr_err("error: for range %s unable to locate base %s\n",
3289 range_name, base_name);
3290 return;
3291 }
3292
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]3293 if (!range_name || strlen(range_name) == 0) {
3294 pr_err("%pS: bad range name, base_name %s, offset_start 0x%X, end 0x%X\n",
3295 __builtin_return_address(0), base_name,
3296 offset_start, offset_end);
3297 return;
3298 }
3299
3300 if (offset_end - offset_start < REG_DUMP_ALIGN ||
3301 offset_start > offset_end) {
3302 pr_err("%pS: bad range, base_name %s, range_name %s, offset_start 0x%X, end 0x%X\n",
3303 __builtin_return_address(0), base_name,
3304 range_name, offset_start, offset_end);
3305 return;
3306 }
3307
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3308 range = kzalloc(sizeof(*range), GFP_KERNEL);
3309 if (!range)
3310 return;
3311
3312 strlcpy(range->range_name, range_name, sizeof(range->range_name));
3313 range->offset.start = offset_start;
3314 range->offset.end = offset_end;
3315 range->xin_id = xin_id;
3316 list_add_tail(&range->head, &reg_base->sub_range_list);
3317
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]3318 pr_debug("base %s, range %s, start 0x%X, end 0x%X\n",
3319 base_name, range->range_name,
Lloyd Atkinson113aefd2016-10-23 13:15:18 -0400[diff] [blame]3320 range->offset.start, range->offset.end);
3321}
Lloyd Atkinsonac4b6e02017-03-23 11:43:48 -0700[diff] [blame]3322
3323void sde_dbg_set_sde_top_offset(u32 blk_off)
3324{
3325 sde_dbg_base.dbgbus_sde.top_blk_off = blk_off;
3326}