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Jingchang Luc9e2e942013-06-07 09:20:40 +08001/*
2 * Freescale lpuart serial port driver
3 *
Jingchang Lu380c9662014-07-14 17:41:11 +08004 * Copyright 2012-2014 Freescale Semiconductor, Inc.
Jingchang Luc9e2e942013-06-07 09:20:40 +08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
Yuan Yaof1cd8c82014-02-17 13:28:07 +080016#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
Jingchang Luc9e2e942013-06-07 09:20:40 +080021#include <linux/io.h>
22#include <linux/irq.h>
Yuan Yaof1cd8c82014-02-17 13:28:07 +080023#include <linux/module.h>
Jingchang Luc9e2e942013-06-07 09:20:40 +080024#include <linux/of.h>
25#include <linux/of_device.h>
Yuan Yaof1cd8c82014-02-17 13:28:07 +080026#include <linux/of_dma.h>
Jingchang Luc9e2e942013-06-07 09:20:40 +080027#include <linux/serial_core.h>
Yuan Yaof1cd8c82014-02-17 13:28:07 +080028#include <linux/slab.h>
Jingchang Luc9e2e942013-06-07 09:20:40 +080029#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
Jingchang Lu380c9662014-07-14 17:41:11 +0800120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800227#define FSL_UART_RX_DMA_BUFFER_SIZE 64
228
Jingchang Luc9e2e942013-06-07 09:20:40 +0800229#define DRIVER_NAME "fsl-lpuart"
230#define DEV_NAME "ttyLP"
231#define UART_NR 6
232
233struct lpuart_port {
234 struct uart_port port;
235 struct clk *clk;
236 unsigned int txfifo_size;
237 unsigned int rxfifo_size;
Jingchang Lu380c9662014-07-14 17:41:11 +0800238 bool lpuart32;
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800239
Stefan Agner4a818c42015-01-10 09:33:45 +0100240 bool lpuart_dma_tx_use;
241 bool lpuart_dma_rx_use;
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800242 struct dma_chan *dma_tx_chan;
243 struct dma_chan *dma_rx_chan;
244 struct dma_async_tx_descriptor *dma_tx_desc;
245 struct dma_async_tx_descriptor *dma_rx_desc;
246 dma_addr_t dma_tx_buf_bus;
247 dma_addr_t dma_rx_buf_bus;
248 dma_cookie_t dma_tx_cookie;
249 dma_cookie_t dma_rx_cookie;
250 unsigned char *dma_tx_buf_virt;
251 unsigned char *dma_rx_buf_virt;
252 unsigned int dma_tx_bytes;
253 unsigned int dma_rx_bytes;
254 int dma_tx_in_progress;
255 int dma_rx_in_progress;
256 unsigned int dma_rx_timeout;
257 struct timer_list lpuart_timer;
Jingchang Luc9e2e942013-06-07 09:20:40 +0800258};
259
260static struct of_device_id lpuart_dt_ids[] = {
261 {
262 .compatible = "fsl,vf610-lpuart",
263 },
Jingchang Lu380c9662014-07-14 17:41:11 +0800264 {
265 .compatible = "fsl,ls1021a-lpuart",
266 },
Jingchang Luc9e2e942013-06-07 09:20:40 +0800267 { /* sentinel */ }
268};
269MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
270
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800271/* Forward declare this for the dma callbacks*/
272static void lpuart_dma_tx_complete(void *arg);
273static void lpuart_dma_rx_complete(void *arg);
274
Jingchang Lu380c9662014-07-14 17:41:11 +0800275static u32 lpuart32_read(void __iomem *addr)
276{
277 return ioread32be(addr);
278}
279
280static void lpuart32_write(u32 val, void __iomem *addr)
281{
282 iowrite32be(val, addr);
283}
284
Jingchang Luc9e2e942013-06-07 09:20:40 +0800285static void lpuart_stop_tx(struct uart_port *port)
286{
287 unsigned char temp;
288
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
292}
293
Jingchang Lu380c9662014-07-14 17:41:11 +0800294static void lpuart32_stop_tx(struct uart_port *port)
295{
296 unsigned long temp;
297
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
301}
302
Jingchang Luc9e2e942013-06-07 09:20:40 +0800303static void lpuart_stop_rx(struct uart_port *port)
304{
305 unsigned char temp;
306
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
309}
310
Jingchang Lu380c9662014-07-14 17:41:11 +0800311static void lpuart32_stop_rx(struct uart_port *port)
312{
313 unsigned long temp;
314
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
317}
318
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800319static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
320 struct tty_port *tty, int count)
321{
322 int copied;
323
324 sport->port.icount.rx += count;
325
326 if (!tty) {
327 dev_err(sport->port.dev, "No tty port\n");
328 return;
329 }
330
331 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
332 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
333 copied = tty_insert_flip_string(tty,
334 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
335
336 if (copied != count) {
337 WARN_ON(1);
338 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
339 }
340
341 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
342 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
343}
344
345static void lpuart_pio_tx(struct lpuart_port *sport)
346{
347 struct circ_buf *xmit = &sport->port.state->xmit;
348 unsigned long flags;
349
350 spin_lock_irqsave(&sport->port.lock, flags);
351
352 while (!uart_circ_empty(xmit) &&
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
355 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
356 sport->port.icount.tx++;
357 }
358
359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
360 uart_write_wakeup(&sport->port);
361
362 if (uart_circ_empty(xmit))
363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
364 sport->port.membase + UARTCR5);
365
366 spin_unlock_irqrestore(&sport->port.lock, flags);
367}
368
369static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
370{
371 struct circ_buf *xmit = &sport->port.state->xmit;
372 dma_addr_t tx_bus_addr;
373
374 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
375 UART_XMIT_SIZE, DMA_TO_DEVICE);
Stefan Agnered9891b2014-07-02 18:02:57 +0200376 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800377 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
378 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
379 tx_bus_addr, sport->dma_tx_bytes,
380 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
381
382 if (!sport->dma_tx_desc) {
383 dev_err(sport->port.dev, "Not able to get desc for tx\n");
384 return -EIO;
385 }
386
387 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
388 sport->dma_tx_desc->callback_param = sport;
389 sport->dma_tx_in_progress = 1;
390 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
391 dma_async_issue_pending(sport->dma_tx_chan);
392
393 return 0;
394}
395
396static void lpuart_prepare_tx(struct lpuart_port *sport)
397{
398 struct circ_buf *xmit = &sport->port.state->xmit;
399 unsigned long count = CIRC_CNT_TO_END(xmit->head,
400 xmit->tail, UART_XMIT_SIZE);
401
402 if (!count)
403 return;
404
Stefan Agnered9891b2014-07-02 18:02:57 +0200405 if (count < sport->txfifo_size)
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
407 sport->port.membase + UARTCR5);
408 else {
409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
410 sport->port.membase + UARTCR5);
411 lpuart_dma_tx(sport, count);
412 }
413}
414
415static void lpuart_dma_tx_complete(void *arg)
416{
417 struct lpuart_port *sport = arg;
418 struct circ_buf *xmit = &sport->port.state->xmit;
419 unsigned long flags;
420
421 async_tx_ack(sport->dma_tx_desc);
422
423 spin_lock_irqsave(&sport->port.lock, flags);
424
425 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
426 sport->dma_tx_in_progress = 0;
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(&sport->port);
430
431 lpuart_prepare_tx(sport);
432
433 spin_unlock_irqrestore(&sport->port.lock, flags);
434}
435
436static int lpuart_dma_rx(struct lpuart_port *sport)
437{
438 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
439 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
440 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
441 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
442 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
443
444 if (!sport->dma_rx_desc) {
445 dev_err(sport->port.dev, "Not able to get desc for rx\n");
446 return -EIO;
447 }
448
449 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
450 sport->dma_rx_desc->callback_param = sport;
451 sport->dma_rx_in_progress = 1;
452 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
453 dma_async_issue_pending(sport->dma_rx_chan);
454
455 return 0;
456}
457
Stefan Agnerbfc2e072015-01-26 01:10:16 +0100458static void lpuart_flush_buffer(struct uart_port *port)
459{
460 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
461 if (sport->lpuart_dma_tx_use) {
462 dmaengine_terminate_all(sport->dma_tx_chan);
463 sport->dma_tx_in_progress = 0;
464 }
465}
466
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800467static void lpuart_dma_rx_complete(void *arg)
468{
469 struct lpuart_port *sport = arg;
470 struct tty_port *port = &sport->port.state->port;
471 unsigned long flags;
472
473 async_tx_ack(sport->dma_rx_desc);
Stefan Agner011f5bd2015-01-10 09:33:46 +0100474 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800475
476 spin_lock_irqsave(&sport->port.lock, flags);
477
478 sport->dma_rx_in_progress = 0;
479 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
480 tty_flip_buffer_push(port);
481 lpuart_dma_rx(sport);
482
483 spin_unlock_irqrestore(&sport->port.lock, flags);
484}
485
486static void lpuart_timer_func(unsigned long data)
487{
488 struct lpuart_port *sport = (struct lpuart_port *)data;
489 struct tty_port *port = &sport->port.state->port;
490 struct dma_tx_state state;
491 unsigned long flags;
492 unsigned char temp;
493 int count;
494
495 del_timer(&sport->lpuart_timer);
496 dmaengine_pause(sport->dma_rx_chan);
497 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
498 dmaengine_terminate_all(sport->dma_rx_chan);
499 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
500 async_tx_ack(sport->dma_rx_desc);
501
502 spin_lock_irqsave(&sport->port.lock, flags);
503
504 sport->dma_rx_in_progress = 0;
505 lpuart_copy_rx_to_tty(sport, port, count);
506 tty_flip_buffer_push(port);
507 temp = readb(sport->port.membase + UARTCR5);
508 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
509
510 spin_unlock_irqrestore(&sport->port.lock, flags);
511}
512
513static inline void lpuart_prepare_rx(struct lpuart_port *sport)
514{
515 unsigned long flags;
516 unsigned char temp;
517
518 spin_lock_irqsave(&sport->port.lock, flags);
519
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800520 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
521 add_timer(&sport->lpuart_timer);
522
523 lpuart_dma_rx(sport);
524 temp = readb(sport->port.membase + UARTCR5);
525 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
526
527 spin_unlock_irqrestore(&sport->port.lock, flags);
528}
529
Jingchang Luc9e2e942013-06-07 09:20:40 +0800530static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
531{
532 struct circ_buf *xmit = &sport->port.state->xmit;
533
534 while (!uart_circ_empty(xmit) &&
535 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
536 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
537 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
538 sport->port.icount.tx++;
539 }
540
541 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
542 uart_write_wakeup(&sport->port);
543
544 if (uart_circ_empty(xmit))
545 lpuart_stop_tx(&sport->port);
546}
547
Jingchang Lu380c9662014-07-14 17:41:11 +0800548static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
549{
550 struct circ_buf *xmit = &sport->port.state->xmit;
551 unsigned long txcnt;
552
553 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
554 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
555 txcnt &= UARTWATER_COUNT_MASK;
556 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
557 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
559 sport->port.icount.tx++;
560 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
561 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
562 txcnt &= UARTWATER_COUNT_MASK;
563 }
564
565 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
566 uart_write_wakeup(&sport->port);
567
568 if (uart_circ_empty(xmit))
569 lpuart32_stop_tx(&sport->port);
570}
571
Jingchang Luc9e2e942013-06-07 09:20:40 +0800572static void lpuart_start_tx(struct uart_port *port)
573{
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800574 struct lpuart_port *sport = container_of(port,
575 struct lpuart_port, port);
576 struct circ_buf *xmit = &sport->port.state->xmit;
Jingchang Luc9e2e942013-06-07 09:20:40 +0800577 unsigned char temp;
578
579 temp = readb(port->membase + UARTCR2);
580 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
581
Stefan Agner4a818c42015-01-10 09:33:45 +0100582 if (sport->lpuart_dma_tx_use) {
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800583 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
584 lpuart_prepare_tx(sport);
585 } else {
586 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
587 lpuart_transmit_buffer(sport);
588 }
Jingchang Luc9e2e942013-06-07 09:20:40 +0800589}
590
Jingchang Lu380c9662014-07-14 17:41:11 +0800591static void lpuart32_start_tx(struct uart_port *port)
592{
593 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
594 unsigned long temp;
595
596 temp = lpuart32_read(port->membase + UARTCTRL);
597 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
598
599 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
600 lpuart32_transmit_buffer(sport);
601}
602
Jingchang Luc9e2e942013-06-07 09:20:40 +0800603static irqreturn_t lpuart_txint(int irq, void *dev_id)
604{
605 struct lpuart_port *sport = dev_id;
606 struct circ_buf *xmit = &sport->port.state->xmit;
607 unsigned long flags;
608
609 spin_lock_irqsave(&sport->port.lock, flags);
610 if (sport->port.x_char) {
Jingchang Lu380c9662014-07-14 17:41:11 +0800611 if (sport->lpuart32)
612 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
613 else
614 writeb(sport->port.x_char, sport->port.membase + UARTDR);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800615 goto out;
616 }
617
618 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
Jingchang Lu380c9662014-07-14 17:41:11 +0800619 if (sport->lpuart32)
620 lpuart32_stop_tx(&sport->port);
621 else
622 lpuart_stop_tx(&sport->port);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800623 goto out;
624 }
625
Jingchang Lu380c9662014-07-14 17:41:11 +0800626 if (sport->lpuart32)
627 lpuart32_transmit_buffer(sport);
628 else
629 lpuart_transmit_buffer(sport);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800630
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&sport->port);
633
634out:
635 spin_unlock_irqrestore(&sport->port.lock, flags);
636 return IRQ_HANDLED;
637}
638
639static irqreturn_t lpuart_rxint(int irq, void *dev_id)
640{
641 struct lpuart_port *sport = dev_id;
642 unsigned int flg, ignored = 0;
643 struct tty_port *port = &sport->port.state->port;
644 unsigned long flags;
645 unsigned char rx, sr;
646
647 spin_lock_irqsave(&sport->port.lock, flags);
648
649 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
650 flg = TTY_NORMAL;
651 sport->port.icount.rx++;
652 /*
653 * to clear the FE, OR, NF, FE, PE flags,
654 * read SR1 then read DR
655 */
656 sr = readb(sport->port.membase + UARTSR1);
657 rx = readb(sport->port.membase + UARTDR);
658
659 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
660 continue;
661
662 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
663 if (sr & UARTSR1_PE)
664 sport->port.icount.parity++;
665 else if (sr & UARTSR1_FE)
666 sport->port.icount.frame++;
667
668 if (sr & UARTSR1_OR)
669 sport->port.icount.overrun++;
670
671 if (sr & sport->port.ignore_status_mask) {
672 if (++ignored > 100)
673 goto out;
674 continue;
675 }
676
677 sr &= sport->port.read_status_mask;
678
679 if (sr & UARTSR1_PE)
680 flg = TTY_PARITY;
681 else if (sr & UARTSR1_FE)
682 flg = TTY_FRAME;
683
684 if (sr & UARTSR1_OR)
685 flg = TTY_OVERRUN;
686
687#ifdef SUPPORT_SYSRQ
688 sport->port.sysrq = 0;
689#endif
690 }
691
692 tty_insert_flip_char(port, rx, flg);
693 }
694
695out:
696 spin_unlock_irqrestore(&sport->port.lock, flags);
697
698 tty_flip_buffer_push(port);
699 return IRQ_HANDLED;
700}
701
Jingchang Lu380c9662014-07-14 17:41:11 +0800702static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
703{
704 struct lpuart_port *sport = dev_id;
705 unsigned int flg, ignored = 0;
706 struct tty_port *port = &sport->port.state->port;
707 unsigned long flags;
708 unsigned long rx, sr;
709
710 spin_lock_irqsave(&sport->port.lock, flags);
711
712 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
713 flg = TTY_NORMAL;
714 sport->port.icount.rx++;
715 /*
716 * to clear the FE, OR, NF, FE, PE flags,
717 * read STAT then read DATA reg
718 */
719 sr = lpuart32_read(sport->port.membase + UARTSTAT);
720 rx = lpuart32_read(sport->port.membase + UARTDATA);
721 rx &= 0x3ff;
722
723 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
724 continue;
725
726 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
727 if (sr & UARTSTAT_PE)
728 sport->port.icount.parity++;
729 else if (sr & UARTSTAT_FE)
730 sport->port.icount.frame++;
731
732 if (sr & UARTSTAT_OR)
733 sport->port.icount.overrun++;
734
735 if (sr & sport->port.ignore_status_mask) {
736 if (++ignored > 100)
737 goto out;
738 continue;
739 }
740
741 sr &= sport->port.read_status_mask;
742
743 if (sr & UARTSTAT_PE)
744 flg = TTY_PARITY;
745 else if (sr & UARTSTAT_FE)
746 flg = TTY_FRAME;
747
748 if (sr & UARTSTAT_OR)
749 flg = TTY_OVERRUN;
750
751#ifdef SUPPORT_SYSRQ
752 sport->port.sysrq = 0;
753#endif
754 }
755
756 tty_insert_flip_char(port, rx, flg);
757 }
758
759out:
760 spin_unlock_irqrestore(&sport->port.lock, flags);
761
762 tty_flip_buffer_push(port);
763 return IRQ_HANDLED;
764}
765
Jingchang Luc9e2e942013-06-07 09:20:40 +0800766static irqreturn_t lpuart_int(int irq, void *dev_id)
767{
768 struct lpuart_port *sport = dev_id;
Stefan Agner5f1437f2015-01-10 01:08:59 +0100769 unsigned char sts, crdma;
Jingchang Luc9e2e942013-06-07 09:20:40 +0800770
771 sts = readb(sport->port.membase + UARTSR1);
Stefan Agner5f1437f2015-01-10 01:08:59 +0100772 crdma = readb(sport->port.membase + UARTCR5);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800773
Stefan Agner5f1437f2015-01-10 01:08:59 +0100774 if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
Stefan Agner4a818c42015-01-10 09:33:45 +0100775 if (sport->lpuart_dma_rx_use)
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800776 lpuart_prepare_rx(sport);
777 else
778 lpuart_rxint(irq, dev_id);
779 }
Stefan Agner5f1437f2015-01-10 01:08:59 +0100780 if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
Stefan Agner4a818c42015-01-10 09:33:45 +0100781 if (sport->lpuart_dma_tx_use)
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800782 lpuart_pio_tx(sport);
783 else
784 lpuart_txint(irq, dev_id);
785 }
Jingchang Luc9e2e942013-06-07 09:20:40 +0800786
787 return IRQ_HANDLED;
788}
789
Jingchang Lu380c9662014-07-14 17:41:11 +0800790static irqreturn_t lpuart32_int(int irq, void *dev_id)
791{
792 struct lpuart_port *sport = dev_id;
793 unsigned long sts, rxcount;
794
795 sts = lpuart32_read(sport->port.membase + UARTSTAT);
796 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
797 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
798
799 if (sts & UARTSTAT_RDRF || rxcount > 0)
800 lpuart32_rxint(irq, dev_id);
801
802 if ((sts & UARTSTAT_TDRE) &&
803 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
804 lpuart_txint(irq, dev_id);
805
806 lpuart32_write(sts, sport->port.membase + UARTSTAT);
807 return IRQ_HANDLED;
808}
809
Jingchang Luc9e2e942013-06-07 09:20:40 +0800810/* return TIOCSER_TEMT when transmitter is not busy */
811static unsigned int lpuart_tx_empty(struct uart_port *port)
812{
813 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
814 TIOCSER_TEMT : 0;
815}
816
Jingchang Lu380c9662014-07-14 17:41:11 +0800817static unsigned int lpuart32_tx_empty(struct uart_port *port)
818{
819 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
820 TIOCSER_TEMT : 0;
821}
822
Jingchang Luc9e2e942013-06-07 09:20:40 +0800823static unsigned int lpuart_get_mctrl(struct uart_port *port)
824{
825 unsigned int temp = 0;
826 unsigned char reg;
827
828 reg = readb(port->membase + UARTMODEM);
829 if (reg & UARTMODEM_TXCTSE)
830 temp |= TIOCM_CTS;
831
832 if (reg & UARTMODEM_RXRTSE)
833 temp |= TIOCM_RTS;
834
835 return temp;
836}
837
Jingchang Lu380c9662014-07-14 17:41:11 +0800838static unsigned int lpuart32_get_mctrl(struct uart_port *port)
839{
840 unsigned int temp = 0;
841 unsigned long reg;
842
843 reg = lpuart32_read(port->membase + UARTMODIR);
844 if (reg & UARTMODIR_TXCTSE)
845 temp |= TIOCM_CTS;
846
847 if (reg & UARTMODIR_RXRTSE)
848 temp |= TIOCM_RTS;
849
850 return temp;
851}
852
Jingchang Luc9e2e942013-06-07 09:20:40 +0800853static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
854{
855 unsigned char temp;
856
857 temp = readb(port->membase + UARTMODEM) &
858 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
859
860 if (mctrl & TIOCM_RTS)
861 temp |= UARTMODEM_RXRTSE;
862
863 if (mctrl & TIOCM_CTS)
864 temp |= UARTMODEM_TXCTSE;
865
866 writeb(temp, port->membase + UARTMODEM);
867}
868
Jingchang Lu380c9662014-07-14 17:41:11 +0800869static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
870{
871 unsigned long temp;
872
873 temp = lpuart32_read(port->membase + UARTMODIR) &
874 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
875
876 if (mctrl & TIOCM_RTS)
877 temp |= UARTMODIR_RXRTSE;
878
879 if (mctrl & TIOCM_CTS)
880 temp |= UARTMODIR_TXCTSE;
881
882 lpuart32_write(temp, port->membase + UARTMODIR);
883}
884
Jingchang Luc9e2e942013-06-07 09:20:40 +0800885static void lpuart_break_ctl(struct uart_port *port, int break_state)
886{
887 unsigned char temp;
888
889 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
890
891 if (break_state != 0)
892 temp |= UARTCR2_SBK;
893
894 writeb(temp, port->membase + UARTCR2);
895}
896
Jingchang Lu380c9662014-07-14 17:41:11 +0800897static void lpuart32_break_ctl(struct uart_port *port, int break_state)
898{
899 unsigned long temp;
900
901 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
902
903 if (break_state != 0)
904 temp |= UARTCTRL_SBK;
905
906 lpuart32_write(temp, port->membase + UARTCTRL);
907}
908
Jingchang Luc9e2e942013-06-07 09:20:40 +0800909static void lpuart_setup_watermark(struct lpuart_port *sport)
910{
911 unsigned char val, cr2;
Shawn Guobc764b82013-07-08 15:53:38 +0800912 unsigned char cr2_saved;
Jingchang Luc9e2e942013-06-07 09:20:40 +0800913
914 cr2 = readb(sport->port.membase + UARTCR2);
Shawn Guobc764b82013-07-08 15:53:38 +0800915 cr2_saved = cr2;
Jingchang Luc9e2e942013-06-07 09:20:40 +0800916 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
917 UARTCR2_RIE | UARTCR2_RE);
918 writeb(cr2, sport->port.membase + UARTCR2);
919
Jingchang Luc9e2e942013-06-07 09:20:40 +0800920 val = readb(sport->port.membase + UARTPFIFO);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800921 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
922 sport->port.membase + UARTPFIFO);
923
924 /* flush Tx and Rx FIFO */
925 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
926 sport->port.membase + UARTCFIFO);
927
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800928 writeb(0, sport->port.membase + UARTTWFIFO);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800929 writeb(1, sport->port.membase + UARTRWFIFO);
Shawn Guobc764b82013-07-08 15:53:38 +0800930
931 /* Restore cr2 */
932 writeb(cr2_saved, sport->port.membase + UARTCR2);
Jingchang Luc9e2e942013-06-07 09:20:40 +0800933}
934
Jingchang Lu380c9662014-07-14 17:41:11 +0800935static void lpuart32_setup_watermark(struct lpuart_port *sport)
936{
937 unsigned long val, ctrl;
938 unsigned long ctrl_saved;
939
940 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
941 ctrl_saved = ctrl;
942 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
943 UARTCTRL_RIE | UARTCTRL_RE);
944 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
945
946 /* enable FIFO mode */
947 val = lpuart32_read(sport->port.membase + UARTFIFO);
948 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
949 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
950 lpuart32_write(val, sport->port.membase + UARTFIFO);
951
952 /* set the watermark */
953 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
954 lpuart32_write(val, sport->port.membase + UARTWATER);
955
956 /* Restore cr2 */
957 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
958}
959
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800960static int lpuart_dma_tx_request(struct uart_port *port)
961{
962 struct lpuart_port *sport = container_of(port,
963 struct lpuart_port, port);
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800964 struct dma_slave_config dma_tx_sconfig;
965 dma_addr_t dma_bus;
966 unsigned char *dma_buf;
967 int ret;
968
Stefan Agner4a818c42015-01-10 09:33:45 +0100969 dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800970 sport->port.state->xmit.buf,
971 UART_XMIT_SIZE, DMA_TO_DEVICE);
972
Stefan Agner4a818c42015-01-10 09:33:45 +0100973 if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800974 dev_err(sport->port.dev, "dma_map_single tx failed\n");
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800975 return -ENOMEM;
976 }
977
978 dma_buf = sport->port.state->xmit.buf;
979 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
980 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
Stefan Agnered9891b2014-07-02 18:02:57 +0200981 dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800982 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
Stefan Agner4a818c42015-01-10 09:33:45 +0100983 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800984
985 if (ret < 0) {
986 dev_err(sport->port.dev,
987 "Dma slave config failed, err = %d\n", ret);
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800988 return ret;
989 }
990
Yuan Yaof1cd8c82014-02-17 13:28:07 +0800991 sport->dma_tx_buf_virt = dma_buf;
992 sport->dma_tx_buf_bus = dma_bus;
993 sport->dma_tx_in_progress = 0;
994
995 return 0;
996}
997
998static int lpuart_dma_rx_request(struct uart_port *port)
999{
1000 struct lpuart_port *sport = container_of(port,
1001 struct lpuart_port, port);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001002 struct dma_slave_config dma_rx_sconfig;
1003 dma_addr_t dma_bus;
1004 unsigned char *dma_buf;
1005 int ret;
1006
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001007 dma_buf = devm_kzalloc(sport->port.dev,
1008 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1009
1010 if (!dma_buf) {
1011 dev_err(sport->port.dev, "Dma rx alloc failed\n");
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001012 return -ENOMEM;
1013 }
1014
Stefan Agner4a818c42015-01-10 09:33:45 +01001015 dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf,
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001016 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1017
Stefan Agner4a818c42015-01-10 09:33:45 +01001018 if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) {
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001019 dev_err(sport->port.dev, "dma_map_single rx failed\n");
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001020 return -ENOMEM;
1021 }
1022
1023 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1024 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1025 dma_rx_sconfig.src_maxburst = 1;
1026 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
Stefan Agner4a818c42015-01-10 09:33:45 +01001027 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001028
1029 if (ret < 0) {
1030 dev_err(sport->port.dev,
1031 "Dma slave config failed, err = %d\n", ret);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001032 return ret;
1033 }
1034
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001035 sport->dma_rx_buf_virt = dma_buf;
1036 sport->dma_rx_buf_bus = dma_bus;
1037 sport->dma_rx_in_progress = 0;
1038
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001039 return 0;
1040}
1041
1042static void lpuart_dma_tx_free(struct uart_port *port)
1043{
1044 struct lpuart_port *sport = container_of(port,
1045 struct lpuart_port, port);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001046
1047 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1048 UART_XMIT_SIZE, DMA_TO_DEVICE);
Stefan Agner4a818c42015-01-10 09:33:45 +01001049
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001050 sport->dma_tx_buf_bus = 0;
1051 sport->dma_tx_buf_virt = NULL;
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001052}
1053
1054static void lpuart_dma_rx_free(struct uart_port *port)
1055{
1056 struct lpuart_port *sport = container_of(port,
1057 struct lpuart_port, port);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001058
1059 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1060 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1061
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001062 sport->dma_rx_buf_bus = 0;
1063 sport->dma_rx_buf_virt = NULL;
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001064}
1065
Jingchang Luc9e2e942013-06-07 09:20:40 +08001066static int lpuart_startup(struct uart_port *port)
1067{
1068 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1069 int ret;
1070 unsigned long flags;
1071 unsigned char temp;
1072
Stefan Agnered9891b2014-07-02 18:02:57 +02001073 /* determine FIFO size and enable FIFO mode */
1074 temp = readb(sport->port.membase + UARTPFIFO);
1075
1076 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1077 UARTPFIFO_FIFOSIZE_MASK) + 1);
1078
Stefan Agner4e8f2452015-03-13 14:51:50 +01001079 sport->port.fifosize = sport->txfifo_size;
1080
Stefan Agnered9891b2014-07-02 18:02:57 +02001081 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1082 UARTPFIFO_FIFOSIZE_MASK) + 1);
1083
Stefan Agner4a818c42015-01-10 09:33:45 +01001084 if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) {
1085 sport->lpuart_dma_rx_use = true;
Stefan Agner4a8588a2015-01-10 01:08:58 +01001086 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1087 (unsigned long)sport);
Stefan Agner4a818c42015-01-10 09:33:45 +01001088 } else
1089 sport->lpuart_dma_rx_use = false;
1090
1091
1092 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1093 sport->lpuart_dma_tx_use = true;
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001094 temp = readb(port->membase + UARTCR5);
Stefan Agner5f1437f2015-01-10 01:08:59 +01001095 temp &= ~UARTCR5_RDMAS;
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001096 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
Stefan Agner4a818c42015-01-10 09:33:45 +01001097 } else
1098 sport->lpuart_dma_tx_use = false;
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001099
Jingchang Luc9e2e942013-06-07 09:20:40 +08001100 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1101 DRIVER_NAME, sport);
1102 if (ret)
1103 return ret;
1104
1105 spin_lock_irqsave(&sport->port.lock, flags);
1106
1107 lpuart_setup_watermark(sport);
1108
1109 temp = readb(sport->port.membase + UARTCR2);
1110 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1111 writeb(temp, sport->port.membase + UARTCR2);
1112
1113 spin_unlock_irqrestore(&sport->port.lock, flags);
1114 return 0;
1115}
1116
Jingchang Lu380c9662014-07-14 17:41:11 +08001117static int lpuart32_startup(struct uart_port *port)
1118{
1119 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1120 int ret;
1121 unsigned long flags;
1122 unsigned long temp;
1123
1124 /* determine FIFO size */
1125 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1126
1127 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1128 UARTFIFO_FIFOSIZE_MASK) - 1);
1129
1130 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1131 UARTFIFO_FIFOSIZE_MASK) - 1);
1132
1133 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1134 DRIVER_NAME, sport);
1135 if (ret)
1136 return ret;
1137
1138 spin_lock_irqsave(&sport->port.lock, flags);
1139
1140 lpuart32_setup_watermark(sport);
1141
1142 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1143 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1144 temp |= UARTCTRL_ILIE;
1145 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1146
1147 spin_unlock_irqrestore(&sport->port.lock, flags);
1148 return 0;
1149}
1150
Jingchang Luc9e2e942013-06-07 09:20:40 +08001151static void lpuart_shutdown(struct uart_port *port)
1152{
1153 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1154 unsigned char temp;
1155 unsigned long flags;
1156
1157 spin_lock_irqsave(&port->lock, flags);
1158
1159 /* disable Rx/Tx and interrupts */
1160 temp = readb(port->membase + UARTCR2);
1161 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1162 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1163 writeb(temp, port->membase + UARTCR2);
1164
1165 spin_unlock_irqrestore(&port->lock, flags);
1166
1167 devm_free_irq(port->dev, port->irq, sport);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001168
Stefan Agner4a818c42015-01-10 09:33:45 +01001169 if (sport->lpuart_dma_rx_use) {
1170 lpuart_dma_rx_free(&sport->port);
Stefan Agner4a8588a2015-01-10 01:08:58 +01001171 del_timer_sync(&sport->lpuart_timer);
Yuan Yaof1cd8c82014-02-17 13:28:07 +08001172 }
Stefan Agner4a818c42015-01-10 09:33:45 +01001173
1174 if (sport->lpuart_dma_tx_use)
1175 lpuart_dma_tx_free(&sport->port);
Jingchang Luc9e2e942013-06-07 09:20:40 +08001176}
1177
Jingchang Lu380c9662014-07-14 17:41:11 +08001178static void lpuart32_shutdown(struct uart_port *port)
1179{
1180 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1181 unsigned long temp;
1182 unsigned long flags;
1183
1184 spin_lock_irqsave(&port->lock, flags);
1185
1186 /* disable Rx/Tx and interrupts */
1187 temp = lpuart32_read(port->membase + UARTCTRL);
1188 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1189 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1190 lpuart32_write(temp, port->membase + UARTCTRL);
1191
1192 spin_unlock_irqrestore(&port->lock, flags);
1193
1194 devm_free_irq(port->dev, port->irq, sport);
1195}
1196
Jingchang Luc9e2e942013-06-07 09:20:40 +08001197static void
1198lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1199 struct ktermios *old)
1200{
1201 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1202 unsigned long flags;
1203 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1204 unsigned int baud;
1205 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1206 unsigned int sbr, brfa;
1207
1208 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1209 old_cr2 = readb(sport->port.membase + UARTCR2);
1210 cr4 = readb(sport->port.membase + UARTCR4);
1211 bdh = readb(sport->port.membase + UARTBDH);
1212 modem = readb(sport->port.membase + UARTMODEM);
1213 /*
1214 * only support CS8 and CS7, and for CS7 must enable PE.
1215 * supported mode:
1216 * - (7,e/o,1)
1217 * - (8,n,1)
1218 * - (8,m/s,1)
1219 * - (8,e/o,1)
1220 */
1221 while ((termios->c_cflag & CSIZE) != CS8 &&
1222 (termios->c_cflag & CSIZE) != CS7) {
1223 termios->c_cflag &= ~CSIZE;
1224 termios->c_cflag |= old_csize;
1225 old_csize = CS8;
1226 }
1227
1228 if ((termios->c_cflag & CSIZE) == CS8 ||
1229 (termios->c_cflag & CSIZE) == CS7)
1230 cr1 = old_cr1 & ~UARTCR1_M;
1231
1232 if (termios->c_cflag & CMSPAR) {
1233 if ((termios->c_cflag & CSIZE) != CS8) {
1234 termios->c_cflag &= ~CSIZE;
1235 termios->c_cflag |= CS8;
1236 }
1237 cr1 |= UARTCR1_M;
1238 }
1239
1240 if (termios->c_cflag & CRTSCTS) {
1241 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1242 } else {
1243 termios->c_cflag &= ~CRTSCTS;
1244 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1245 }
1246
1247 if (termios->c_cflag & CSTOPB)
1248 termios->c_cflag &= ~CSTOPB;
1249
1250 /* parity must be enabled when CS7 to match 8-bits format */
1251 if ((termios->c_cflag & CSIZE) == CS7)
1252 termios->c_cflag |= PARENB;
1253
1254 if ((termios->c_cflag & PARENB)) {
1255 if (termios->c_cflag & CMSPAR) {
1256 cr1 &= ~UARTCR1_PE;
1257 cr1 |= UARTCR1_M;
1258 } else {
1259 cr1 |= UARTCR1_PE;
1260 if ((termios->c_cflag & CSIZE) == CS8)
1261 cr1 |= UARTCR1_M;
1262 if (termios->c_cflag & PARODD)
1263 cr1 |= UARTCR1_PT;
1264 else
1265 cr1 &= ~UARTCR1_PT;
1266 }
1267 }
1268
1269 /* ask the core to calculate the divisor */
1270 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1271
1272 spin_lock_irqsave(&sport->port.lock, flags);
1273
1274 sport->port.read_status_mask = 0;
1275 if (termios->c_iflag & INPCK)
1276 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
Peter Hurleyef8b9dd2014-06-16 08:10:41 -04001277 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
Jingchang Luc9e2e942013-06-07 09:20:40 +08001278 sport->port.read_status_mask |= UARTSR1_FE;
1279
1280 /* characters to ignore */
1281 sport->port.ignore_status_mask = 0;
1282 if (termios->c_iflag & IGNPAR)
1283 sport->port.ignore_status_mask |= UARTSR1_PE;
1284 if (termios->c_iflag & IGNBRK) {
1285 sport->port.ignore_status_mask |= UARTSR1_FE;
1286 /*
1287 * if we're ignoring parity and break indicators,
1288 * ignore overruns too (for real raw support).
1289 */
1290 if (termios->c_iflag & IGNPAR)
1291 sport->port.ignore_status_mask |= UARTSR1_OR;
1292 }
1293
1294 /* update the per-port timeout */
1295 uart_update_timeout(port, termios->c_cflag, baud);
1296
Stefan Agner4a818c42015-01-10 09:33:45 +01001297 if (sport->lpuart_dma_rx_use) {
Stefan Agner90abef92014-07-02 18:02:56 +02001298 /* Calculate delay for 1.5 DMA buffers */
1299 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1300 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1301 sport->rxfifo_size / 2;
1302 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1303 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1304 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1305 sport->dma_rx_timeout = msecs_to_jiffies(20);
1306 }
1307
Jingchang Luc9e2e942013-06-07 09:20:40 +08001308 /* wait transmit engin complete */
1309 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1310 barrier();
1311
1312 /* disable transmit and receive */
1313 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1314 sport->port.membase + UARTCR2);
1315
1316 sbr = sport->port.uartclk / (16 * baud);
1317 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1318 bdh &= ~UARTBDH_SBR_MASK;
1319 bdh |= (sbr >> 8) & 0x1F;
1320 cr4 &= ~UARTCR4_BRFA_MASK;
1321 brfa &= UARTCR4_BRFA_MASK;
1322 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1323 writeb(bdh, sport->port.membase + UARTBDH);
1324 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1325 writeb(cr1, sport->port.membase + UARTCR1);
1326 writeb(modem, sport->port.membase + UARTMODEM);
1327
1328 /* restore control register */
1329 writeb(old_cr2, sport->port.membase + UARTCR2);
1330
1331 spin_unlock_irqrestore(&sport->port.lock, flags);
1332}
1333
Jingchang Lu380c9662014-07-14 17:41:11 +08001334static void
1335lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1336 struct ktermios *old)
1337{
1338 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1339 unsigned long flags;
1340 unsigned long ctrl, old_ctrl, bd, modem;
1341 unsigned int baud;
1342 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1343 unsigned int sbr;
1344
1345 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1346 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1347 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1348 /*
1349 * only support CS8 and CS7, and for CS7 must enable PE.
1350 * supported mode:
1351 * - (7,e/o,1)
1352 * - (8,n,1)
1353 * - (8,m/s,1)
1354 * - (8,e/o,1)
1355 */
1356 while ((termios->c_cflag & CSIZE) != CS8 &&
1357 (termios->c_cflag & CSIZE) != CS7) {
1358 termios->c_cflag &= ~CSIZE;
1359 termios->c_cflag |= old_csize;
1360 old_csize = CS8;
1361 }
1362
1363 if ((termios->c_cflag & CSIZE) == CS8 ||
1364 (termios->c_cflag & CSIZE) == CS7)
1365 ctrl = old_ctrl & ~UARTCTRL_M;
1366
1367 if (termios->c_cflag & CMSPAR) {
1368 if ((termios->c_cflag & CSIZE) != CS8) {
1369 termios->c_cflag &= ~CSIZE;
1370 termios->c_cflag |= CS8;
1371 }
1372 ctrl |= UARTCTRL_M;
1373 }
1374
1375 if (termios->c_cflag & CRTSCTS) {
1376 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1377 } else {
1378 termios->c_cflag &= ~CRTSCTS;
1379 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1380 }
1381
1382 if (termios->c_cflag & CSTOPB)
1383 termios->c_cflag &= ~CSTOPB;
1384
1385 /* parity must be enabled when CS7 to match 8-bits format */
1386 if ((termios->c_cflag & CSIZE) == CS7)
1387 termios->c_cflag |= PARENB;
1388
1389 if ((termios->c_cflag & PARENB)) {
1390 if (termios->c_cflag & CMSPAR) {
1391 ctrl &= ~UARTCTRL_PE;
1392 ctrl |= UARTCTRL_M;
1393 } else {
1394 ctrl |= UARTCR1_PE;
1395 if ((termios->c_cflag & CSIZE) == CS8)
1396 ctrl |= UARTCTRL_M;
1397 if (termios->c_cflag & PARODD)
1398 ctrl |= UARTCTRL_PT;
1399 else
1400 ctrl &= ~UARTCTRL_PT;
1401 }
1402 }
1403
1404 /* ask the core to calculate the divisor */
1405 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1406
1407 spin_lock_irqsave(&sport->port.lock, flags);
1408
1409 sport->port.read_status_mask = 0;
1410 if (termios->c_iflag & INPCK)
1411 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1412 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1413 sport->port.read_status_mask |= UARTSTAT_FE;
1414
1415 /* characters to ignore */
1416 sport->port.ignore_status_mask = 0;
1417 if (termios->c_iflag & IGNPAR)
1418 sport->port.ignore_status_mask |= UARTSTAT_PE;
1419 if (termios->c_iflag & IGNBRK) {
1420 sport->port.ignore_status_mask |= UARTSTAT_FE;
1421 /*
1422 * if we're ignoring parity and break indicators,
1423 * ignore overruns too (for real raw support).
1424 */
1425 if (termios->c_iflag & IGNPAR)
1426 sport->port.ignore_status_mask |= UARTSTAT_OR;
1427 }
1428
1429 /* update the per-port timeout */
1430 uart_update_timeout(port, termios->c_cflag, baud);
1431
1432 /* wait transmit engin complete */
1433 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1434 barrier();
1435
1436 /* disable transmit and receive */
1437 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1438 sport->port.membase + UARTCTRL);
1439
1440 sbr = sport->port.uartclk / (16 * baud);
1441 bd &= ~UARTBAUD_SBR_MASK;
1442 bd |= sbr & UARTBAUD_SBR_MASK;
1443 bd |= UARTBAUD_BOTHEDGE;
1444 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1445 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1446 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1447 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1448 /* restore control register */
1449
1450 spin_unlock_irqrestore(&sport->port.lock, flags);
1451}
1452
Jingchang Luc9e2e942013-06-07 09:20:40 +08001453static const char *lpuart_type(struct uart_port *port)
1454{
1455 return "FSL_LPUART";
1456}
1457
1458static void lpuart_release_port(struct uart_port *port)
1459{
1460 /* nothing to do */
1461}
1462
1463static int lpuart_request_port(struct uart_port *port)
1464{
1465 return 0;
1466}
1467
1468/* configure/autoconfigure the port */
1469static void lpuart_config_port(struct uart_port *port, int flags)
1470{
1471 if (flags & UART_CONFIG_TYPE)
1472 port->type = PORT_LPUART;
1473}
1474
1475static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1476{
1477 int ret = 0;
1478
1479 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1480 ret = -EINVAL;
1481 if (port->irq != ser->irq)
1482 ret = -EINVAL;
1483 if (ser->io_type != UPIO_MEM)
1484 ret = -EINVAL;
1485 if (port->uartclk / 16 != ser->baud_base)
1486 ret = -EINVAL;
1487 if (port->iobase != ser->port)
1488 ret = -EINVAL;
1489 if (ser->hub6 != 0)
1490 ret = -EINVAL;
1491 return ret;
1492}
1493
1494static struct uart_ops lpuart_pops = {
1495 .tx_empty = lpuart_tx_empty,
1496 .set_mctrl = lpuart_set_mctrl,
1497 .get_mctrl = lpuart_get_mctrl,
1498 .stop_tx = lpuart_stop_tx,
1499 .start_tx = lpuart_start_tx,
1500 .stop_rx = lpuart_stop_rx,
Jingchang Luc9e2e942013-06-07 09:20:40 +08001501 .break_ctl = lpuart_break_ctl,
1502 .startup = lpuart_startup,
1503 .shutdown = lpuart_shutdown,
1504 .set_termios = lpuart_set_termios,
1505 .type = lpuart_type,
1506 .request_port = lpuart_request_port,
1507 .release_port = lpuart_release_port,
1508 .config_port = lpuart_config_port,
1509 .verify_port = lpuart_verify_port,
Stefan Agnerbfc2e072015-01-26 01:10:16 +01001510 .flush_buffer = lpuart_flush_buffer,
Jingchang Luc9e2e942013-06-07 09:20:40 +08001511};
1512
Jingchang Lu380c9662014-07-14 17:41:11 +08001513static struct uart_ops lpuart32_pops = {
1514 .tx_empty = lpuart32_tx_empty,
1515 .set_mctrl = lpuart32_set_mctrl,
1516 .get_mctrl = lpuart32_get_mctrl,
1517 .stop_tx = lpuart32_stop_tx,
1518 .start_tx = lpuart32_start_tx,
1519 .stop_rx = lpuart32_stop_rx,
1520 .break_ctl = lpuart32_break_ctl,
1521 .startup = lpuart32_startup,
1522 .shutdown = lpuart32_shutdown,
1523 .set_termios = lpuart32_set_termios,
1524 .type = lpuart_type,
1525 .request_port = lpuart_request_port,
1526 .release_port = lpuart_release_port,
1527 .config_port = lpuart_config_port,
1528 .verify_port = lpuart_verify_port,
Stefan Agnerbfc2e072015-01-26 01:10:16 +01001529 .flush_buffer = lpuart_flush_buffer,
Jingchang Lu380c9662014-07-14 17:41:11 +08001530};
1531
Jingchang Luc9e2e942013-06-07 09:20:40 +08001532static struct lpuart_port *lpuart_ports[UART_NR];
1533
1534#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1535static void lpuart_console_putchar(struct uart_port *port, int ch)
1536{
1537 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1538 barrier();
1539
1540 writeb(ch, port->membase + UARTDR);
1541}
1542
Jingchang Lu380c9662014-07-14 17:41:11 +08001543static void lpuart32_console_putchar(struct uart_port *port, int ch)
1544{
1545 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1546 barrier();
1547
1548 lpuart32_write(ch, port->membase + UARTDATA);
1549}
1550
Jingchang Luc9e2e942013-06-07 09:20:40 +08001551static void
1552lpuart_console_write(struct console *co, const char *s, unsigned int count)
1553{
1554 struct lpuart_port *sport = lpuart_ports[co->index];
1555 unsigned char old_cr2, cr2;
1556
1557 /* first save CR2 and then disable interrupts */
1558 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1559 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1560 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1561 writeb(cr2, sport->port.membase + UARTCR2);
1562
1563 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1564
1565 /* wait for transmitter finish complete and restore CR2 */
1566 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1567 barrier();
1568
1569 writeb(old_cr2, sport->port.membase + UARTCR2);
1570}
1571
Jingchang Lu380c9662014-07-14 17:41:11 +08001572static void
1573lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1574{
1575 struct lpuart_port *sport = lpuart_ports[co->index];
1576 unsigned long old_cr, cr;
1577
1578 /* first save CR2 and then disable interrupts */
1579 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1580 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1581 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1582 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1583
1584 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1585
1586 /* wait for transmitter finish complete and restore CR2 */
1587 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1588 barrier();
1589
1590 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1591}
1592
Jingchang Luc9e2e942013-06-07 09:20:40 +08001593/*
1594 * if the port was already initialised (eg, by a boot loader),
1595 * try to determine the current setup.
1596 */
1597static void __init
1598lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1599 int *parity, int *bits)
1600{
1601 unsigned char cr, bdh, bdl, brfa;
1602 unsigned int sbr, uartclk, baud_raw;
1603
1604 cr = readb(sport->port.membase + UARTCR2);
1605 cr &= UARTCR2_TE | UARTCR2_RE;
1606 if (!cr)
1607 return;
1608
1609 /* ok, the port was enabled */
1610
1611 cr = readb(sport->port.membase + UARTCR1);
1612
1613 *parity = 'n';
1614 if (cr & UARTCR1_PE) {
1615 if (cr & UARTCR1_PT)
1616 *parity = 'o';
1617 else
1618 *parity = 'e';
1619 }
1620
1621 if (cr & UARTCR1_M)
1622 *bits = 9;
1623 else
1624 *bits = 8;
1625
1626 bdh = readb(sport->port.membase + UARTBDH);
1627 bdh &= UARTBDH_SBR_MASK;
1628 bdl = readb(sport->port.membase + UARTBDL);
1629 sbr = bdh;
1630 sbr <<= 8;
1631 sbr |= bdl;
1632 brfa = readb(sport->port.membase + UARTCR4);
1633 brfa &= UARTCR4_BRFA_MASK;
1634
1635 uartclk = clk_get_rate(sport->clk);
1636 /*
1637 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1638 */
1639 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1640
1641 if (*baud != baud_raw)
1642 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1643 "from %d to %d\n", baud_raw, *baud);
1644}
1645
Jingchang Lu380c9662014-07-14 17:41:11 +08001646static void __init
1647lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1648 int *parity, int *bits)
1649{
1650 unsigned long cr, bd;
1651 unsigned int sbr, uartclk, baud_raw;
1652
1653 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1654 cr &= UARTCTRL_TE | UARTCTRL_RE;
1655 if (!cr)
1656 return;
1657
1658 /* ok, the port was enabled */
1659
1660 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1661
1662 *parity = 'n';
1663 if (cr & UARTCTRL_PE) {
1664 if (cr & UARTCTRL_PT)
1665 *parity = 'o';
1666 else
1667 *parity = 'e';
1668 }
1669
1670 if (cr & UARTCTRL_M)
1671 *bits = 9;
1672 else
1673 *bits = 8;
1674
1675 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1676 bd &= UARTBAUD_SBR_MASK;
1677 sbr = bd;
1678 uartclk = clk_get_rate(sport->clk);
1679 /*
1680 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1681 */
1682 baud_raw = uartclk / (16 * sbr);
1683
1684 if (*baud != baud_raw)
1685 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1686 "from %d to %d\n", baud_raw, *baud);
1687}
1688
Jingchang Luc9e2e942013-06-07 09:20:40 +08001689static int __init lpuart_console_setup(struct console *co, char *options)
1690{
1691 struct lpuart_port *sport;
1692 int baud = 115200;
1693 int bits = 8;
1694 int parity = 'n';
1695 int flow = 'n';
1696
1697 /*
1698 * check whether an invalid uart number has been specified, and
1699 * if so, search for the first available port that does have
1700 * console support.
1701 */
1702 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1703 co->index = 0;
1704
1705 sport = lpuart_ports[co->index];
1706 if (sport == NULL)
1707 return -ENODEV;
1708
1709 if (options)
1710 uart_parse_options(options, &baud, &parity, &bits, &flow);
1711 else
Jingchang Lu380c9662014-07-14 17:41:11 +08001712 if (sport->lpuart32)
1713 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1714 else
1715 lpuart_console_get_options(sport, &baud, &parity, &bits);
Jingchang Luc9e2e942013-06-07 09:20:40 +08001716
Jingchang Lu380c9662014-07-14 17:41:11 +08001717 if (sport->lpuart32)
1718 lpuart32_setup_watermark(sport);
1719 else
1720 lpuart_setup_watermark(sport);
Jingchang Luc9e2e942013-06-07 09:20:40 +08001721
1722 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1723}
1724
1725static struct uart_driver lpuart_reg;
1726static struct console lpuart_console = {
1727 .name = DEV_NAME,
1728 .write = lpuart_console_write,
1729 .device = uart_console_device,
1730 .setup = lpuart_console_setup,
1731 .flags = CON_PRINTBUFFER,
1732 .index = -1,
1733 .data = &lpuart_reg,
1734};
1735
Jingchang Lu380c9662014-07-14 17:41:11 +08001736static struct console lpuart32_console = {
1737 .name = DEV_NAME,
1738 .write = lpuart32_console_write,
1739 .device = uart_console_device,
1740 .setup = lpuart_console_setup,
1741 .flags = CON_PRINTBUFFER,
1742 .index = -1,
1743 .data = &lpuart_reg,
1744};
1745
Jingchang Luc9e2e942013-06-07 09:20:40 +08001746#define LPUART_CONSOLE (&lpuart_console)
Jingchang Lu380c9662014-07-14 17:41:11 +08001747#define LPUART32_CONSOLE (&lpuart32_console)
Jingchang Luc9e2e942013-06-07 09:20:40 +08001748#else
1749#define LPUART_CONSOLE NULL
Jingchang Lu380c9662014-07-14 17:41:11 +08001750#define LPUART32_CONSOLE NULL
Jingchang Luc9e2e942013-06-07 09:20:40 +08001751#endif
1752
1753static struct uart_driver lpuart_reg = {
1754 .owner = THIS_MODULE,
1755 .driver_name = DRIVER_NAME,
1756 .dev_name = DEV_NAME,
1757 .nr = ARRAY_SIZE(lpuart_ports),
1758 .cons = LPUART_CONSOLE,
1759};
1760
1761static int lpuart_probe(struct platform_device *pdev)
1762{
1763 struct device_node *np = pdev->dev.of_node;
1764 struct lpuart_port *sport;
1765 struct resource *res;
1766 int ret;
1767
1768 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1769 if (!sport)
1770 return -ENOMEM;
1771
1772 pdev->dev.coherent_dma_mask = 0;
1773
1774 ret = of_alias_get_id(np, "serial");
1775 if (ret < 0) {
1776 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1777 return ret;
1778 }
1779 sport->port.line = ret;
Jingchang Lu380c9662014-07-14 17:41:11 +08001780 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
Jingchang Luc9e2e942013-06-07 09:20:40 +08001781
Fabio Estevam4ae612a2014-11-07 00:23:13 -02001782 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingchang Luc9e2e942013-06-07 09:20:40 +08001783 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1784 if (IS_ERR(sport->port.membase))
1785 return PTR_ERR(sport->port.membase);
1786
Fabio Estevam4ae612a2014-11-07 00:23:13 -02001787 sport->port.mapbase = res->start;
Jingchang Luc9e2e942013-06-07 09:20:40 +08001788 sport->port.dev = &pdev->dev;
1789 sport->port.type = PORT_LPUART;
1790 sport->port.iotype = UPIO_MEM;
1791 sport->port.irq = platform_get_irq(pdev, 0);
Jingchang Lu380c9662014-07-14 17:41:11 +08001792 if (sport->lpuart32)
1793 sport->port.ops = &lpuart32_pops;
1794 else
1795 sport->port.ops = &lpuart_pops;
Jingchang Luc9e2e942013-06-07 09:20:40 +08001796 sport->port.flags = UPF_BOOT_AUTOCONF;
1797
1798 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1799 if (IS_ERR(sport->clk)) {
1800 ret = PTR_ERR(sport->clk);
1801 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1802 return ret;
1803 }
1804
1805 ret = clk_prepare_enable(sport->clk);
1806 if (ret) {
1807 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1808 return ret;
1809 }
1810
1811 sport->port.uartclk = clk_get_rate(sport->clk);
1812
1813 lpuart_ports[sport->port.line] = sport;
1814
1815 platform_set_drvdata(pdev, &sport->port);
1816
Jingchang Lu380c9662014-07-14 17:41:11 +08001817 if (sport->lpuart32)
1818 lpuart_reg.cons = LPUART32_CONSOLE;
1819 else
1820 lpuart_reg.cons = LPUART_CONSOLE;
1821
Jingchang Luc9e2e942013-06-07 09:20:40 +08001822 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1823 if (ret) {
1824 clk_disable_unprepare(sport->clk);
1825 return ret;
1826 }
1827
Stefan Agner4a818c42015-01-10 09:33:45 +01001828 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1829 if (!sport->dma_tx_chan)
1830 dev_info(sport->port.dev, "DMA tx channel request failed, "
1831 "operating without tx DMA\n");
1832
1833 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1834 if (!sport->dma_rx_chan)
1835 dev_info(sport->port.dev, "DMA rx channel request failed, "
1836 "operating without rx DMA\n");
1837
Jingchang Luc9e2e942013-06-07 09:20:40 +08001838 return 0;
1839}
1840
1841static int lpuart_remove(struct platform_device *pdev)
1842{
1843 struct lpuart_port *sport = platform_get_drvdata(pdev);
1844
1845 uart_remove_one_port(&lpuart_reg, &sport->port);
1846
1847 clk_disable_unprepare(sport->clk);
1848
Stefan Agner4a818c42015-01-10 09:33:45 +01001849 if (sport->dma_tx_chan)
1850 dma_release_channel(sport->dma_tx_chan);
1851
1852 if (sport->dma_rx_chan)
1853 dma_release_channel(sport->dma_rx_chan);
1854
Jingchang Luc9e2e942013-06-07 09:20:40 +08001855 return 0;
1856}
1857
1858#ifdef CONFIG_PM_SLEEP
1859static int lpuart_suspend(struct device *dev)
1860{
1861 struct lpuart_port *sport = dev_get_drvdata(dev);
Yuan Yao2fe605d2015-01-23 17:48:54 +08001862 unsigned long temp;
1863
1864 if (sport->lpuart32) {
1865 /* disable Rx/Tx and interrupts */
1866 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1867 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1868 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1869 } else {
1870 /* disable Rx/Tx and interrupts */
1871 temp = readb(sport->port.membase + UARTCR2);
1872 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1873 writeb(temp, sport->port.membase + UARTCR2);
1874 }
Jingchang Luc9e2e942013-06-07 09:20:40 +08001875
1876 uart_suspend_port(&lpuart_reg, &sport->port);
1877
1878 return 0;
1879}
1880
1881static int lpuart_resume(struct device *dev)
1882{
1883 struct lpuart_port *sport = dev_get_drvdata(dev);
Jingchang Lu08de1012014-10-24 17:20:49 +08001884 unsigned long temp;
1885
1886 if (sport->lpuart32) {
1887 lpuart32_setup_watermark(sport);
1888 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1889 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1890 UARTCTRL_TE | UARTCTRL_ILIE);
1891 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1892 } else {
1893 lpuart_setup_watermark(sport);
1894 temp = readb(sport->port.membase + UARTCR2);
1895 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1896 writeb(temp, sport->port.membase + UARTCR2);
1897 }
Jingchang Luc9e2e942013-06-07 09:20:40 +08001898
1899 uart_resume_port(&lpuart_reg, &sport->port);
1900
1901 return 0;
1902}
1903#endif
1904
1905static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1906
1907static struct platform_driver lpuart_driver = {
1908 .probe = lpuart_probe,
1909 .remove = lpuart_remove,
1910 .driver = {
1911 .name = "fsl-lpuart",
Jingchang Luc9e2e942013-06-07 09:20:40 +08001912 .of_match_table = lpuart_dt_ids,
1913 .pm = &lpuart_pm_ops,
1914 },
1915};
1916
1917static int __init lpuart_serial_init(void)
1918{
Fabio Estevam144c29e2014-11-07 00:23:14 -02001919 int ret = uart_register_driver(&lpuart_reg);
Jingchang Luc9e2e942013-06-07 09:20:40 +08001920
Jingchang Luc9e2e942013-06-07 09:20:40 +08001921 if (ret)
1922 return ret;
1923
1924 ret = platform_driver_register(&lpuart_driver);
1925 if (ret)
1926 uart_unregister_driver(&lpuart_reg);
1927
Axel Lin39c34b02013-07-22 09:12:36 +08001928 return ret;
Jingchang Luc9e2e942013-06-07 09:20:40 +08001929}
1930
1931static void __exit lpuart_serial_exit(void)
1932{
1933 platform_driver_unregister(&lpuart_driver);
1934 uart_unregister_driver(&lpuart_reg);
1935}
1936
1937module_init(lpuart_serial_init);
1938module_exit(lpuart_serial_exit);
1939
1940MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1941MODULE_LICENSE("GPL v2");