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Linus Walleije3726fc2010-08-19 12:36:01 +01001/*
Martin Perssone0befb22010-12-08 15:13:28 +01002 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
Linus Walleije3726fc2010-08-19 12:36:01 +01004 *
5 * License Terms: GNU General Public License v2
Martin Perssone0befb22010-12-08 15:13:28 +01006 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
Linus Walleije3726fc2010-08-19 12:36:01 +01008 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
Martin Perssone0befb22010-12-08 15:13:28 +010010 * U8500 PRCM Unit interface driver
11 *
Linus Walleije3726fc2010-08-19 12:36:01 +010012 */
Linus Walleije3726fc2010-08-19 12:36:01 +010013#include <linux/module.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020014#include <linux/kernel.h>
15#include <linux/delay.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010016#include <linux/errno.h>
17#include <linux/err.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020018#include <linux/spinlock.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010019#include <linux/io.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020020#include <linux/slab.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010021#include <linux/mutex.h>
22#include <linux/completion.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020023#include <linux/irq.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010024#include <linux/jiffies.h>
25#include <linux/bitops.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020026#include <linux/fs.h>
Lee Jonesd98a5382013-04-09 20:52:58 +010027#include <linux/of.h>
Linus Walleijf864c462014-02-04 00:35:56 +010028#include <linux/of_irq.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020029#include <linux/platform_device.h>
30#include <linux/uaccess.h>
31#include <linux/mfd/core.h>
Mattias Nilsson73180f82011-08-12 10:28:10 +020032#include <linux/mfd/dbx500-prcmu.h>
Lee Jones3a8e39c2012-07-06 12:46:23 +020033#include <linux/mfd/abx500/ab8500.h>
Bengt Jonsson1032fbf2011-04-01 14:43:33 +020034#include <linux/regulator/db8500-prcmu.h>
35#include <linux/regulator/machine.h>
Ulf Hanssonc280f452012-10-10 13:42:23 +020036#include <linux/cpufreq.h>
Fabio Baltierib3aac622013-01-18 12:40:14 +010037#include <linux/platform_data/ux500_wdt.h>
Arnd Bergmann55b175d2013-03-21 22:51:07 +010038#include <linux/platform_data/db8500_thermal.h>
Mattias Nilsson73180f82011-08-12 10:28:10 +020039#include "dbx500-prcmu-regs.h"
Linus Walleije3726fc2010-08-19 12:36:01 +010040
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020041/* Index of different voltages to be used when accessing AVSData */
42#define PRCM_AVS_BASE 0x2FC
43#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
44#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
45#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
46#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
47#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
48#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
49#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
50#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
51#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
52#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
53#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
54#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
55#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
Martin Perssone0befb22010-12-08 15:13:28 +010056
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020057#define PRCM_AVS_VOLTAGE 0
58#define PRCM_AVS_VOLTAGE_MASK 0x3f
59#define PRCM_AVS_ISSLOWSTARTUP 6
60#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
Martin Perssone0befb22010-12-08 15:13:28 +010061#define PRCM_AVS_ISMODEENABLE 7
62#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
63
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020064#define PRCM_BOOT_STATUS 0xFFF
65#define PRCM_ROMCODE_A2P 0xFFE
66#define PRCM_ROMCODE_P2A 0xFFD
67#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
Linus Walleije3726fc2010-08-19 12:36:01 +010068
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020069#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
70
71#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
72#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
73#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
74#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
75#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
76#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
77#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
78#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
79
80/* Req Mailboxes */
81#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
82#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
83#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
84#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
85#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
86#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
87
88/* Ack Mailboxes */
89#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
90#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
91#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
92#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
93#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
94#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
95
96/* Mailbox 0 headers */
97#define MB0H_POWER_STATE_TRANS 0
98#define MB0H_CONFIG_WAKEUPS_EXE 1
99#define MB0H_READ_WAKEUP_ACK 3
100#define MB0H_CONFIG_WAKEUPS_SLEEP 4
101
102#define MB0H_WAKEUP_EXE 2
103#define MB0H_WAKEUP_SLEEP 5
104
105/* Mailbox 0 REQs */
106#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
107#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
108#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
109#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
110#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
111#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
112
113/* Mailbox 0 ACKs */
114#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
115#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
116#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
117#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
118#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
119#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
120#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
121
122/* Mailbox 1 headers */
123#define MB1H_ARM_APE_OPP 0x0
124#define MB1H_RESET_MODEM 0x2
125#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
126#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
127#define MB1H_RELEASE_USB_WAKEUP 0x5
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200128#define MB1H_PLL_ON_OFF 0x6
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200129
130/* Mailbox 1 Requests */
131#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
132#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200133#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100134#define PLL_SOC0_OFF 0x1
135#define PLL_SOC0_ON 0x2
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200136#define PLL_SOC1_OFF 0x4
137#define PLL_SOC1_ON 0x8
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200138
139/* Mailbox 1 ACKs */
140#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
141#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
142#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
143#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
144
145/* Mailbox 2 headers */
146#define MB2H_DPS 0x0
147#define MB2H_AUTO_PWR 0x1
148
149/* Mailbox 2 REQs */
150#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
151#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
152#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
153#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
154#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
155#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
156#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
157#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
158#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
159#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
160
161/* Mailbox 2 ACKs */
162#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
163#define HWACC_PWR_ST_OK 0xFE
164
165/* Mailbox 3 headers */
166#define MB3H_ANC 0x0
167#define MB3H_SIDETONE 0x1
168#define MB3H_SYSCLK 0xE
169
170/* Mailbox 3 Requests */
171#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
172#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
173#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
174#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
175#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
176#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
177#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
178
179/* Mailbox 4 headers */
180#define MB4H_DDR_INIT 0x0
181#define MB4H_MEM_ST 0x1
182#define MB4H_HOTDOG 0x12
183#define MB4H_HOTMON 0x13
184#define MB4H_HOT_PERIOD 0x14
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200185#define MB4H_A9WDOG_CONF 0x16
186#define MB4H_A9WDOG_EN 0x17
187#define MB4H_A9WDOG_DIS 0x18
188#define MB4H_A9WDOG_LOAD 0x19
189#define MB4H_A9WDOG_KICK 0x20
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200190
191/* Mailbox 4 Requests */
192#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
193#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
194#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
195#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
196#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
197#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
198#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
199#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
200#define HOTMON_CONFIG_LOW BIT(0)
201#define HOTMON_CONFIG_HIGH BIT(1)
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200202#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
203#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
204#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
205#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
206#define A9WDOG_AUTO_OFF_EN BIT(7)
207#define A9WDOG_AUTO_OFF_DIS 0
208#define A9WDOG_ID_MASK 0xf
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200209
210/* Mailbox 5 Requests */
211#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
212#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
213#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
214#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
Linus Walleij7a4f2602012-09-19 19:31:19 +0200215#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
216#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200217#define PRCMU_I2C_STOP_EN BIT(3)
218
219/* Mailbox 5 ACKs */
220#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
221#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
222#define I2C_WR_OK 0x1
223#define I2C_RD_OK 0x2
224
225#define NUM_MB 8
226#define MBOX_BIT BIT
227#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
228
229/*
230 * Wakeups/IRQs
231 */
232
233#define WAKEUP_BIT_RTC BIT(0)
234#define WAKEUP_BIT_RTT0 BIT(1)
235#define WAKEUP_BIT_RTT1 BIT(2)
236#define WAKEUP_BIT_HSI0 BIT(3)
237#define WAKEUP_BIT_HSI1 BIT(4)
238#define WAKEUP_BIT_CA_WAKE BIT(5)
239#define WAKEUP_BIT_USB BIT(6)
240#define WAKEUP_BIT_ABB BIT(7)
241#define WAKEUP_BIT_ABB_FIFO BIT(8)
242#define WAKEUP_BIT_SYSCLK_OK BIT(9)
243#define WAKEUP_BIT_CA_SLEEP BIT(10)
244#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
245#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
246#define WAKEUP_BIT_ANC_OK BIT(13)
247#define WAKEUP_BIT_SW_ERROR BIT(14)
248#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
249#define WAKEUP_BIT_ARM BIT(17)
250#define WAKEUP_BIT_HOTMON_LOW BIT(18)
251#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
252#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
253#define WAKEUP_BIT_GPIO0 BIT(23)
254#define WAKEUP_BIT_GPIO1 BIT(24)
255#define WAKEUP_BIT_GPIO2 BIT(25)
256#define WAKEUP_BIT_GPIO3 BIT(26)
257#define WAKEUP_BIT_GPIO4 BIT(27)
258#define WAKEUP_BIT_GPIO5 BIT(28)
259#define WAKEUP_BIT_GPIO6 BIT(29)
260#define WAKEUP_BIT_GPIO7 BIT(30)
261#define WAKEUP_BIT_GPIO8 BIT(31)
262
Mattias Nilssonb58d12f2012-01-13 16:20:10 +0100263static struct {
264 bool valid;
265 struct prcmu_fw_version version;
266} fw_info;
267
Lee Jonesf3f1f0a2012-09-24 09:11:46 +0100268static struct irq_domain *db8500_irq_domain;
269
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200270/*
271 * This vector maps irq numbers to the bits in the bit field used in
272 * communication with the PRCMU firmware.
273 *
274 * The reason for having this is to keep the irq numbers contiguous even though
275 * the bits in the bit field are not. (The bits also have a tendency to move
276 * around, to further complicate matters.)
277 */
Arnd Bergmann55b175d2013-03-21 22:51:07 +0100278#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200279#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
Arnd Bergmann55b175d2013-03-21 22:51:07 +0100280
281#define IRQ_PRCMU_RTC 0
282#define IRQ_PRCMU_RTT0 1
283#define IRQ_PRCMU_RTT1 2
284#define IRQ_PRCMU_HSI0 3
285#define IRQ_PRCMU_HSI1 4
286#define IRQ_PRCMU_CA_WAKE 5
287#define IRQ_PRCMU_USB 6
288#define IRQ_PRCMU_ABB 7
289#define IRQ_PRCMU_ABB_FIFO 8
290#define IRQ_PRCMU_ARM 9
291#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
292#define IRQ_PRCMU_GPIO0 11
293#define IRQ_PRCMU_GPIO1 12
294#define IRQ_PRCMU_GPIO2 13
295#define IRQ_PRCMU_GPIO3 14
296#define IRQ_PRCMU_GPIO4 15
297#define IRQ_PRCMU_GPIO5 16
298#define IRQ_PRCMU_GPIO6 17
299#define IRQ_PRCMU_GPIO7 18
300#define IRQ_PRCMU_GPIO8 19
301#define IRQ_PRCMU_CA_SLEEP 20
302#define IRQ_PRCMU_HOTMON_LOW 21
303#define IRQ_PRCMU_HOTMON_HIGH 22
304#define NUM_PRCMU_WAKEUPS 23
305
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200306static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
307 IRQ_ENTRY(RTC),
308 IRQ_ENTRY(RTT0),
309 IRQ_ENTRY(RTT1),
310 IRQ_ENTRY(HSI0),
311 IRQ_ENTRY(HSI1),
312 IRQ_ENTRY(CA_WAKE),
313 IRQ_ENTRY(USB),
314 IRQ_ENTRY(ABB),
315 IRQ_ENTRY(ABB_FIFO),
316 IRQ_ENTRY(CA_SLEEP),
317 IRQ_ENTRY(ARM),
318 IRQ_ENTRY(HOTMON_LOW),
319 IRQ_ENTRY(HOTMON_HIGH),
320 IRQ_ENTRY(MODEM_SW_RESET_REQ),
321 IRQ_ENTRY(GPIO0),
322 IRQ_ENTRY(GPIO1),
323 IRQ_ENTRY(GPIO2),
324 IRQ_ENTRY(GPIO3),
325 IRQ_ENTRY(GPIO4),
326 IRQ_ENTRY(GPIO5),
327 IRQ_ENTRY(GPIO6),
328 IRQ_ENTRY(GPIO7),
329 IRQ_ENTRY(GPIO8)
Martin Perssone0befb22010-12-08 15:13:28 +0100330};
331
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200332#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
333#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
334static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
335 WAKEUP_ENTRY(RTC),
336 WAKEUP_ENTRY(RTT0),
337 WAKEUP_ENTRY(RTT1),
338 WAKEUP_ENTRY(HSI0),
339 WAKEUP_ENTRY(HSI1),
340 WAKEUP_ENTRY(USB),
341 WAKEUP_ENTRY(ABB),
342 WAKEUP_ENTRY(ABB_FIFO),
343 WAKEUP_ENTRY(ARM)
344};
345
346/*
347 * mb0_transfer - state needed for mailbox 0 communication.
348 * @lock: The transaction lock.
349 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
350 * the request data.
351 * @mask_work: Work structure used for (un)masking wakeup interrupts.
352 * @req: Request data that need to persist between requests.
353 */
354static struct {
355 spinlock_t lock;
356 spinlock_t dbb_irqs_lock;
357 struct work_struct mask_work;
358 struct mutex ac_wake_lock;
359 struct completion ac_wake_work;
360 struct {
361 u32 dbb_irqs;
362 u32 dbb_wakeups;
363 u32 abb_events;
364 } req;
365} mb0_transfer;
366
367/*
368 * mb1_transfer - state needed for mailbox 1 communication.
369 * @lock: The transaction lock.
370 * @work: The transaction completion structure.
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100371 * @ape_opp: The current APE OPP.
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200372 * @ack: Reply ("acknowledge") data.
373 */
Martin Perssone0befb22010-12-08 15:13:28 +0100374static struct {
375 struct mutex lock;
376 struct completion work;
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100377 u8 ape_opp;
Martin Perssone0befb22010-12-08 15:13:28 +0100378 struct {
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200379 u8 header;
Martin Perssone0befb22010-12-08 15:13:28 +0100380 u8 arm_opp;
381 u8 ape_opp;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200382 u8 ape_voltage_status;
Martin Perssone0befb22010-12-08 15:13:28 +0100383 } ack;
384} mb1_transfer;
385
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200386/*
387 * mb2_transfer - state needed for mailbox 2 communication.
388 * @lock: The transaction lock.
389 * @work: The transaction completion structure.
390 * @auto_pm_lock: The autonomous power management configuration lock.
391 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
392 * @req: Request data that need to persist between requests.
393 * @ack: Reply ("acknowledge") data.
394 */
Linus Walleije3726fc2010-08-19 12:36:01 +0100395static struct {
396 struct mutex lock;
397 struct completion work;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200398 spinlock_t auto_pm_lock;
399 bool auto_pm_enabled;
400 struct {
401 u8 status;
402 } ack;
403} mb2_transfer;
404
405/*
406 * mb3_transfer - state needed for mailbox 3 communication.
407 * @lock: The request lock.
408 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
409 * @sysclk_work: Work structure used for sysclk requests.
410 */
411static struct {
412 spinlock_t lock;
413 struct mutex sysclk_lock;
414 struct completion sysclk_work;
415} mb3_transfer;
416
417/*
418 * mb4_transfer - state needed for mailbox 4 communication.
419 * @lock: The transaction lock.
420 * @work: The transaction completion structure.
421 */
422static struct {
423 struct mutex lock;
424 struct completion work;
425} mb4_transfer;
426
427/*
428 * mb5_transfer - state needed for mailbox 5 communication.
429 * @lock: The transaction lock.
430 * @work: The transaction completion structure.
431 * @ack: Reply ("acknowledge") data.
432 */
433static struct {
434 struct mutex lock;
435 struct completion work;
Linus Walleije3726fc2010-08-19 12:36:01 +0100436 struct {
437 u8 status;
438 u8 value;
439 } ack;
440} mb5_transfer;
441
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200442static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
443
444/* Spinlocks */
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100445static DEFINE_SPINLOCK(prcmu_lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200446static DEFINE_SPINLOCK(clkout_lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200447
448/* Global var to runtime determine TCDM base for v2 or v1 */
449static __iomem void *tcdm_base;
Linus Walleijb047d982013-03-19 14:21:47 +0100450static __iomem void *prcmu_base;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200451
452struct clk_mgt {
Linus Walleijb047d982013-03-19 14:21:47 +0100453 u32 offset;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200454 u32 pllsw;
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100455 int branch;
456 bool clk38div;
457};
458
459enum {
460 PLL_RAW,
461 PLL_FIX,
462 PLL_DIV
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200463};
464
465static DEFINE_SPINLOCK(clk_mgt_lock);
466
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100467#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
468 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
Sachin Kamat6746f232013-08-23 17:05:20 +0530469static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100470 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
471 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
472 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
474 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
475 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
476 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
477 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
485 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
488 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
489 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
491 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
492 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
493 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
494 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
495 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
496 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
497 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
498 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
499};
500
501struct dsiclk {
502 u32 divsel_mask;
503 u32 divsel_shift;
504 u32 divsel;
505};
506
507static struct dsiclk dsiclk[2] = {
508 {
509 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
510 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
512 },
513 {
514 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
515 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
517 }
518};
519
520struct dsiescclk {
521 u32 en;
522 u32 div_mask;
523 u32 div_shift;
524};
525
526static struct dsiescclk dsiescclk[3] = {
527 {
528 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
529 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
530 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
531 },
532 {
533 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
534 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
535 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
536 },
537 {
538 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
539 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
540 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
541 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200542};
543
Michel Jaouen20aee5b2012-08-31 14:21:30 +0200544
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200545/*
546* Used by MCDE to setup all necessary PRCMU registers
547*/
548#define PRCMU_RESET_DSIPLL 0x00004000
549#define PRCMU_UNCLAMP_DSIPLL 0x00400800
550
551#define PRCMU_CLK_PLL_DIV_SHIFT 0
552#define PRCMU_CLK_PLL_SW_SHIFT 5
553#define PRCMU_CLK_38 (1 << 9)
554#define PRCMU_CLK_38_SRC (1 << 10)
555#define PRCMU_CLK_38_DIV (1 << 11)
556
557/* PLLDIV=12, PLLSW=4 (PLLDDR) */
558#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
559
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200560/* DPI 50000000 Hz */
561#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
562 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
563#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
564
565/* D=101, N=1, R=4, SELDIV2=0 */
566#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
567
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200568#define PRCMU_ENABLE_PLLDSI 0x00000001
569#define PRCMU_DISABLE_PLLDSI 0x00000000
570#define PRCMU_RELEASE_RESET_DSS 0x0000400C
571#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
572/* ESC clk, div0=1, div1=1, div2=3 */
573#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
574#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
575#define PRCMU_DSI_RESET_SW 0x00000007
576
577#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
578
Mattias Nilsson73180f82011-08-12 10:28:10 +0200579int db8500_prcmu_enable_dsipll(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200580{
581 int i;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200582
583 /* Clear DSIPLL_RESETN */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200584 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200585 /* Unclamp DSIPLL in/out */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200586 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200587
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200588 /* Set DSI PLL FREQ */
Daniel Willerudc72fe852012-01-13 16:20:03 +0100589 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200590 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200591 /* Enable Escape clocks */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200592 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200593
594 /* Start DSI PLL */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200595 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200596 /* Reset DSI PLL */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200597 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200598 for (i = 0; i < 10; i++) {
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200599 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200600 == PRCMU_PLLDSI_LOCKP_LOCKED)
601 break;
602 udelay(100);
603 }
604 /* Set DSIPLL_RESETN */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200605 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200606 return 0;
607}
608
Mattias Nilsson73180f82011-08-12 10:28:10 +0200609int db8500_prcmu_disable_dsipll(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200610{
611 /* Disable dsi pll */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200612 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200613 /* Disable escapeclock */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200614 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200615 return 0;
616}
617
Mattias Nilsson73180f82011-08-12 10:28:10 +0200618int db8500_prcmu_set_display_clocks(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200619{
620 unsigned long flags;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200621
622 spin_lock_irqsave(&clk_mgt_lock, flags);
623
624 /* Grab the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200625 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200626 cpu_relax();
627
Linus Walleijb047d982013-03-19 14:21:47 +0100628 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
629 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
630 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200631
632 /* Release the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200633 writel(0, PRCM_SEM);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200634
635 spin_unlock_irqrestore(&clk_mgt_lock, flags);
636
637 return 0;
638}
639
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100640u32 db8500_prcmu_read(unsigned int reg)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200641{
Linus Walleijb047d982013-03-19 14:21:47 +0100642 return readl(prcmu_base + reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200643}
644
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100645void db8500_prcmu_write(unsigned int reg, u32 value)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200646{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200647 unsigned long flags;
648
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100649 spin_lock_irqsave(&prcmu_lock, flags);
Linus Walleijb047d982013-03-19 14:21:47 +0100650 writel(value, (prcmu_base + reg));
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100651 spin_unlock_irqrestore(&prcmu_lock, flags);
652}
653
654void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
655{
656 u32 val;
657 unsigned long flags;
658
659 spin_lock_irqsave(&prcmu_lock, flags);
Linus Walleijb047d982013-03-19 14:21:47 +0100660 val = readl(prcmu_base + reg);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100661 val = ((val & ~mask) | (value & mask));
Linus Walleijb047d982013-03-19 14:21:47 +0100662 writel(val, (prcmu_base + reg));
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100663 spin_unlock_irqrestore(&prcmu_lock, flags);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200664}
665
Mattias Nilssonb58d12f2012-01-13 16:20:10 +0100666struct prcmu_fw_version *prcmu_get_fw_version(void)
667{
668 return fw_info.valid ? &fw_info.version : NULL;
669}
670
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200671bool prcmu_has_arm_maxopp(void)
672{
673 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
674 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
675}
676
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200677/**
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200678 * prcmu_set_rc_a2p - This function is used to run few power state sequences
679 * @val: Value to be set, i.e. transition requested
680 * Returns: 0 on success, -EINVAL on invalid argument
681 *
682 * This function is used to run the following power state sequences -
683 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
684 */
685int prcmu_set_rc_a2p(enum romcode_write val)
686{
687 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
688 return -EINVAL;
689 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
690 return 0;
691}
692
693/**
694 * prcmu_get_rc_p2a - This function is used to get power state sequences
695 * Returns: the power transition that has last happened
696 *
697 * This function can return the following transitions-
698 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
699 */
700enum romcode_read prcmu_get_rc_p2a(void)
701{
702 return readb(tcdm_base + PRCM_ROMCODE_P2A);
703}
704
705/**
706 * prcmu_get_current_mode - Return the current XP70 power mode
707 * Returns: Returns the current AP(ARM) power mode: init,
708 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
709 */
710enum ap_pwrst prcmu_get_xp70_current_state(void)
711{
712 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
713}
714
715/**
716 * prcmu_config_clkout - Configure one of the programmable clock outputs.
717 * @clkout: The CLKOUT number (0 or 1).
718 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
719 * @div: The divider to be applied.
720 *
721 * Configures one of the programmable clock outputs (CLKOUTs).
722 * @div should be in the range [1,63] to request a configuration, or 0 to
723 * inform that the configuration is no longer requested.
724 */
725int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
726{
727 static int requests[2];
728 int r = 0;
729 unsigned long flags;
730 u32 val;
731 u32 bits;
732 u32 mask;
733 u32 div_mask;
734
735 BUG_ON(clkout > 1);
736 BUG_ON(div > 63);
737 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
738
739 if (!div && !requests[clkout])
740 return -EINVAL;
741
742 switch (clkout) {
743 case 0:
744 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
745 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
746 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
747 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
748 break;
749 case 1:
750 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
751 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
752 PRCM_CLKOCR_CLK1TYPE);
753 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
754 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
755 break;
756 }
757 bits &= mask;
758
759 spin_lock_irqsave(&clkout_lock, flags);
760
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200761 val = readl(PRCM_CLKOCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200762 if (val & div_mask) {
763 if (div) {
764 if ((val & mask) != bits) {
765 r = -EBUSY;
766 goto unlock_and_return;
767 }
768 } else {
769 if ((val & mask & ~div_mask) != bits) {
770 r = -EINVAL;
771 goto unlock_and_return;
772 }
773 }
774 }
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200775 writel((bits | (val & ~mask)), PRCM_CLKOCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200776 requests[clkout] += (div ? 1 : -1);
777
778unlock_and_return:
779 spin_unlock_irqrestore(&clkout_lock, flags);
780
781 return r;
782}
783
Mattias Nilsson73180f82011-08-12 10:28:10 +0200784int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200785{
786 unsigned long flags;
787
788 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
789
790 spin_lock_irqsave(&mb0_transfer.lock, flags);
791
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200792 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200793 cpu_relax();
794
795 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
796 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
797 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
798 writeb((keep_ulp_clk ? 1 : 0),
799 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
800 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200801 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200802
803 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
804
805 return 0;
806}
807
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100808u8 db8500_prcmu_get_power_state_result(void)
809{
810 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
811}
812
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200813/* This function should only be called while mb0_transfer.lock is held. */
814static void config_wakeups(void)
815{
816 const u8 header[2] = {
817 MB0H_CONFIG_WAKEUPS_EXE,
818 MB0H_CONFIG_WAKEUPS_SLEEP
819 };
820 static u32 last_dbb_events;
821 static u32 last_abb_events;
822 u32 dbb_events;
823 u32 abb_events;
824 unsigned int i;
825
826 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
827 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
828
829 abb_events = mb0_transfer.req.abb_events;
830
831 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
832 return;
833
834 for (i = 0; i < 2; i++) {
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200835 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200836 cpu_relax();
837 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
838 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
839 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200840 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200841 }
842 last_dbb_events = dbb_events;
843 last_abb_events = abb_events;
844}
845
Mattias Nilsson73180f82011-08-12 10:28:10 +0200846void db8500_prcmu_enable_wakeups(u32 wakeups)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200847{
848 unsigned long flags;
849 u32 bits;
850 int i;
851
852 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
853
854 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
855 if (wakeups & BIT(i))
856 bits |= prcmu_wakeup_bit[i];
857 }
858
859 spin_lock_irqsave(&mb0_transfer.lock, flags);
860
861 mb0_transfer.req.dbb_wakeups = bits;
862 config_wakeups();
863
864 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
865}
866
Mattias Nilsson73180f82011-08-12 10:28:10 +0200867void db8500_prcmu_config_abb_event_readout(u32 abb_events)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200868{
869 unsigned long flags;
870
871 spin_lock_irqsave(&mb0_transfer.lock, flags);
872
873 mb0_transfer.req.abb_events = abb_events;
874 config_wakeups();
875
876 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
877}
878
Mattias Nilsson73180f82011-08-12 10:28:10 +0200879void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200880{
881 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
882 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
883 else
884 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
885}
886
887/**
Mattias Nilsson73180f82011-08-12 10:28:10 +0200888 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200889 * @opp: The new ARM operating point to which transition is to be made
890 * Returns: 0 on success, non-zero on failure
891 *
892 * This function sets the the operating point of the ARM.
893 */
Mattias Nilsson73180f82011-08-12 10:28:10 +0200894int db8500_prcmu_set_arm_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200895{
896 int r;
897
898 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
899 return -EINVAL;
900
901 r = 0;
902
903 mutex_lock(&mb1_transfer.lock);
904
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200905 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200906 cpu_relax();
907
908 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
909 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
910 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
911
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200912 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200913 wait_for_completion(&mb1_transfer.work);
914
915 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
916 (mb1_transfer.ack.arm_opp != opp))
917 r = -EIO;
918
919 mutex_unlock(&mb1_transfer.lock);
920
921 return r;
922}
923
924/**
Mattias Nilsson73180f82011-08-12 10:28:10 +0200925 * db8500_prcmu_get_arm_opp - get the current ARM OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200926 *
927 * Returns: the current ARM OPP
928 */
Mattias Nilsson73180f82011-08-12 10:28:10 +0200929int db8500_prcmu_get_arm_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200930{
931 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
932}
933
934/**
Mattias Nilsson05089012012-01-13 16:20:20 +0100935 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200936 *
937 * Returns: the current DDR OPP
938 */
Mattias Nilsson05089012012-01-13 16:20:20 +0100939int db8500_prcmu_get_ddr_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200940{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200941 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200942}
943
944/**
Mattias Nilsson05089012012-01-13 16:20:20 +0100945 * db8500_set_ddr_opp - set the appropriate DDR OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200946 * @opp: The new DDR operating point to which transition is to be made
947 * Returns: 0 on success, non-zero on failure
948 *
949 * This function sets the operating point of the DDR.
950 */
Linus Walleij7a4f2602012-09-19 19:31:19 +0200951static bool enable_set_ddr_opp;
Mattias Nilsson05089012012-01-13 16:20:20 +0100952int db8500_prcmu_set_ddr_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200953{
954 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
955 return -EINVAL;
956 /* Changing the DDR OPP can hang the hardware pre-v21 */
Linus Walleij7a4f2602012-09-19 19:31:19 +0200957 if (enable_set_ddr_opp)
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200958 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200959
960 return 0;
961}
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100962
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100963/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
964static void request_even_slower_clocks(bool enable)
965{
Linus Walleijb047d982013-03-19 14:21:47 +0100966 u32 clock_reg[] = {
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100967 PRCM_ACLK_MGT,
968 PRCM_DMACLK_MGT
969 };
970 unsigned long flags;
971 unsigned int i;
972
973 spin_lock_irqsave(&clk_mgt_lock, flags);
974
975 /* Grab the HW semaphore. */
976 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
977 cpu_relax();
978
979 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
980 u32 val;
981 u32 div;
982
Linus Walleijb047d982013-03-19 14:21:47 +0100983 val = readl(prcmu_base + clock_reg[i]);
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100984 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
985 if (enable) {
986 if ((div <= 1) || (div > 15)) {
987 pr_err("prcmu: Bad clock divider %d in %s\n",
988 div, __func__);
989 goto unlock_and_return;
990 }
991 div <<= 1;
992 } else {
993 if (div <= 2)
994 goto unlock_and_return;
995 div >>= 1;
996 }
997 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
998 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
Linus Walleijb047d982013-03-19 14:21:47 +0100999 writel(val, prcmu_base + clock_reg[i]);
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001000 }
1001
1002unlock_and_return:
1003 /* Release the HW semaphore. */
1004 writel(0, PRCM_SEM);
1005
1006 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1007}
1008
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001009/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001010 * db8500_set_ape_opp - set the appropriate APE OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001011 * @opp: The new APE operating point to which transition is to be made
1012 * Returns: 0 on success, non-zero on failure
1013 *
1014 * This function sets the operating point of the APE.
1015 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001016int db8500_prcmu_set_ape_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001017{
1018 int r = 0;
1019
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001020 if (opp == mb1_transfer.ape_opp)
1021 return 0;
1022
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001023 mutex_lock(&mb1_transfer.lock);
1024
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001025 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1026 request_even_slower_clocks(false);
1027
1028 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1029 goto skip_message;
1030
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001031 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001032 cpu_relax();
1033
1034 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1035 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001036 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1037 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001038
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001039 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001040 wait_for_completion(&mb1_transfer.work);
1041
1042 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1043 (mb1_transfer.ack.ape_opp != opp))
1044 r = -EIO;
1045
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001046skip_message:
1047 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1048 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1049 request_even_slower_clocks(true);
1050 if (!r)
1051 mb1_transfer.ape_opp = opp;
1052
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001053 mutex_unlock(&mb1_transfer.lock);
1054
1055 return r;
1056}
1057
1058/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001059 * db8500_prcmu_get_ape_opp - get the current APE OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001060 *
1061 * Returns: the current APE OPP
1062 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001063int db8500_prcmu_get_ape_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001064{
1065 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1066}
1067
1068/**
Ulf Hansson686f8712012-09-24 16:43:17 +02001069 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001070 * @enable: true to request the higher voltage, false to drop a request.
1071 *
1072 * Calls to this function to enable and disable requests must be balanced.
1073 */
Ulf Hansson686f8712012-09-24 16:43:17 +02001074int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001075{
1076 int r = 0;
1077 u8 header;
1078 static unsigned int requests;
1079
1080 mutex_lock(&mb1_transfer.lock);
1081
1082 if (enable) {
1083 if (0 != requests++)
1084 goto unlock_and_return;
1085 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1086 } else {
1087 if (requests == 0) {
1088 r = -EIO;
1089 goto unlock_and_return;
1090 } else if (1 != requests--) {
1091 goto unlock_and_return;
1092 }
1093 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1094 }
1095
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001096 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001097 cpu_relax();
1098
1099 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1100
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001101 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001102 wait_for_completion(&mb1_transfer.work);
1103
1104 if ((mb1_transfer.ack.header != header) ||
1105 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1106 r = -EIO;
1107
1108unlock_and_return:
1109 mutex_unlock(&mb1_transfer.lock);
1110
1111 return r;
1112}
1113
1114/**
1115 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1116 *
1117 * This function releases the power state requirements of a USB wakeup.
1118 */
1119int prcmu_release_usb_wakeup_state(void)
1120{
1121 int r = 0;
1122
1123 mutex_lock(&mb1_transfer.lock);
1124
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001125 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001126 cpu_relax();
1127
1128 writeb(MB1H_RELEASE_USB_WAKEUP,
1129 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1130
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001131 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001132 wait_for_completion(&mb1_transfer.work);
1133
1134 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1135 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1136 r = -EIO;
1137
1138 mutex_unlock(&mb1_transfer.lock);
1139
1140 return r;
1141}
1142
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001143static int request_pll(u8 clock, bool enable)
1144{
1145 int r = 0;
1146
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001147 if (clock == PRCMU_PLLSOC0)
1148 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1149 else if (clock == PRCMU_PLLSOC1)
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001150 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1151 else
1152 return -EINVAL;
1153
1154 mutex_lock(&mb1_transfer.lock);
1155
1156 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1157 cpu_relax();
1158
1159 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1160 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1161
1162 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1163 wait_for_completion(&mb1_transfer.work);
1164
1165 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1166 r = -EIO;
1167
1168 mutex_unlock(&mb1_transfer.lock);
1169
1170 return r;
1171}
1172
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001173/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001174 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001175 * @epod_id: The EPOD to set
1176 * @epod_state: The new EPOD state
1177 *
1178 * This function sets the state of a EPOD (power domain). It may not be called
1179 * from interrupt context.
1180 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001181int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001182{
1183 int r = 0;
1184 bool ram_retention = false;
1185 int i;
1186
1187 /* check argument */
1188 BUG_ON(epod_id >= NUM_EPOD_ID);
1189
1190 /* set flag if retention is possible */
1191 switch (epod_id) {
1192 case EPOD_ID_SVAMMDSP:
1193 case EPOD_ID_SIAMMDSP:
1194 case EPOD_ID_ESRAM12:
1195 case EPOD_ID_ESRAM34:
1196 ram_retention = true;
1197 break;
1198 }
1199
1200 /* check argument */
1201 BUG_ON(epod_state > EPOD_STATE_ON);
1202 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1203
1204 /* get lock */
1205 mutex_lock(&mb2_transfer.lock);
1206
1207 /* wait for mailbox */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001208 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001209 cpu_relax();
1210
1211 /* fill in mailbox */
1212 for (i = 0; i < NUM_EPOD_ID; i++)
1213 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1214 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1215
1216 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1217
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001218 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001219
1220 /*
1221 * The current firmware version does not handle errors correctly,
1222 * and we cannot recover if there is an error.
1223 * This is expected to change when the firmware is updated.
1224 */
1225 if (!wait_for_completion_timeout(&mb2_transfer.work,
1226 msecs_to_jiffies(20000))) {
1227 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1228 __func__);
1229 r = -EIO;
1230 goto unlock_and_return;
1231 }
1232
1233 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1234 r = -EIO;
1235
1236unlock_and_return:
1237 mutex_unlock(&mb2_transfer.lock);
1238 return r;
1239}
1240
1241/**
1242 * prcmu_configure_auto_pm - Configure autonomous power management.
1243 * @sleep: Configuration for ApSleep.
1244 * @idle: Configuration for ApIdle.
1245 */
1246void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1247 struct prcmu_auto_pm_config *idle)
1248{
1249 u32 sleep_cfg;
1250 u32 idle_cfg;
1251 unsigned long flags;
1252
1253 BUG_ON((sleep == NULL) || (idle == NULL));
1254
1255 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1256 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1257 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1258 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1259 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1260 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1261
1262 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1263 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1264 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1265 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1266 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1267 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1268
1269 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1270
1271 /*
1272 * The autonomous power management configuration is done through
1273 * fields in mailbox 2, but these fields are only used as shared
1274 * variables - i.e. there is no need to send a message.
1275 */
1276 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1277 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1278
1279 mb2_transfer.auto_pm_enabled =
1280 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1281 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1282 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1283 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1284
1285 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1286}
1287EXPORT_SYMBOL(prcmu_configure_auto_pm);
1288
1289bool prcmu_is_auto_pm_enabled(void)
1290{
1291 return mb2_transfer.auto_pm_enabled;
1292}
1293
1294static int request_sysclk(bool enable)
1295{
1296 int r;
1297 unsigned long flags;
1298
1299 r = 0;
1300
1301 mutex_lock(&mb3_transfer.sysclk_lock);
1302
1303 spin_lock_irqsave(&mb3_transfer.lock, flags);
1304
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001305 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001306 cpu_relax();
1307
1308 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1309
1310 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001311 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001312
1313 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1314
1315 /*
1316 * The firmware only sends an ACK if we want to enable the
1317 * SysClk, and it succeeds.
1318 */
1319 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1320 msecs_to_jiffies(20000))) {
1321 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1322 __func__);
1323 r = -EIO;
1324 }
1325
1326 mutex_unlock(&mb3_transfer.sysclk_lock);
1327
1328 return r;
1329}
1330
1331static int request_timclk(bool enable)
1332{
1333 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1334
1335 if (!enable)
1336 val |= PRCM_TCR_STOP_TIMERS;
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001337 writel(val, PRCM_TCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001338
1339 return 0;
1340}
1341
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001342static int request_clock(u8 clock, bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001343{
1344 u32 val;
1345 unsigned long flags;
1346
1347 spin_lock_irqsave(&clk_mgt_lock, flags);
1348
1349 /* Grab the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001350 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001351 cpu_relax();
1352
Linus Walleijb047d982013-03-19 14:21:47 +01001353 val = readl(prcmu_base + clk_mgt[clock].offset);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001354 if (enable) {
1355 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1356 } else {
1357 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1358 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1359 }
Linus Walleijb047d982013-03-19 14:21:47 +01001360 writel(val, prcmu_base + clk_mgt[clock].offset);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001361
1362 /* Release the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001363 writel(0, PRCM_SEM);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001364
1365 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1366
1367 return 0;
1368}
1369
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001370static int request_sga_clock(u8 clock, bool enable)
1371{
1372 u32 val;
1373 int ret;
1374
1375 if (enable) {
1376 val = readl(PRCM_CGATING_BYPASS);
1377 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1378 }
1379
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001380 ret = request_clock(clock, enable);
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001381
1382 if (!ret && !enable) {
1383 val = readl(PRCM_CGATING_BYPASS);
1384 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1385 }
1386
1387 return ret;
1388}
1389
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001390static inline bool plldsi_locked(void)
1391{
1392 return (readl(PRCM_PLLDSI_LOCKP) &
1393 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1394 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1395 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1396 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1397}
1398
1399static int request_plldsi(bool enable)
1400{
1401 int r = 0;
1402 u32 val;
1403
1404 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1405 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1406 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1407
1408 val = readl(PRCM_PLLDSI_ENABLE);
1409 if (enable)
1410 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1411 else
1412 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1413 writel(val, PRCM_PLLDSI_ENABLE);
1414
1415 if (enable) {
1416 unsigned int i;
1417 bool locked = plldsi_locked();
1418
1419 for (i = 10; !locked && (i > 0); --i) {
1420 udelay(100);
1421 locked = plldsi_locked();
1422 }
1423 if (locked) {
1424 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1425 PRCM_APE_RESETN_SET);
1426 } else {
1427 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1428 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1429 PRCM_MMIP_LS_CLAMP_SET);
1430 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1431 writel(val, PRCM_PLLDSI_ENABLE);
1432 r = -EAGAIN;
1433 }
1434 } else {
1435 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1436 }
1437 return r;
1438}
1439
1440static int request_dsiclk(u8 n, bool enable)
1441{
1442 u32 val;
1443
1444 val = readl(PRCM_DSI_PLLOUT_SEL);
1445 val &= ~dsiclk[n].divsel_mask;
1446 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1447 dsiclk[n].divsel_shift);
1448 writel(val, PRCM_DSI_PLLOUT_SEL);
1449 return 0;
1450}
1451
1452static int request_dsiescclk(u8 n, bool enable)
1453{
1454 u32 val;
1455
1456 val = readl(PRCM_DSITVCLK_DIV);
1457 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1458 writel(val, PRCM_DSITVCLK_DIV);
1459 return 0;
1460}
1461
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001462/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001463 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001464 * @clock: The clock for which the request is made.
1465 * @enable: Whether the clock should be enabled (true) or disabled (false).
1466 *
1467 * This function should only be used by the clock implementation.
1468 * Do not use it from any other place!
1469 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001470int db8500_prcmu_request_clock(u8 clock, bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001471{
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001472 if (clock == PRCMU_SGACLK)
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001473 return request_sga_clock(clock, enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001474 else if (clock < PRCMU_NUM_REG_CLOCKS)
1475 return request_clock(clock, enable);
1476 else if (clock == PRCMU_TIMCLK)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001477 return request_timclk(enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001478 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1479 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1480 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1481 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1482 else if (clock == PRCMU_PLLDSI)
1483 return request_plldsi(enable);
1484 else if (clock == PRCMU_SYSCLK)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001485 return request_sysclk(enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001486 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001487 return request_pll(clock, enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001488 else
1489 return -EINVAL;
1490}
1491
1492static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1493 int branch)
1494{
1495 u64 rate;
1496 u32 val;
1497 u32 d;
1498 u32 div = 1;
1499
1500 val = readl(reg);
1501
1502 rate = src_rate;
1503 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1504
1505 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1506 if (d > 1)
1507 div *= d;
1508
1509 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1510 if (d > 1)
1511 div *= d;
1512
1513 if (val & PRCM_PLL_FREQ_SELDIV2)
1514 div *= 2;
1515
1516 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1517 (val & PRCM_PLL_FREQ_DIV2EN) &&
1518 ((reg == PRCM_PLLSOC0_FREQ) ||
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001519 (reg == PRCM_PLLARM_FREQ) ||
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001520 (reg == PRCM_PLLDDR_FREQ))))
1521 div *= 2;
1522
1523 (void)do_div(rate, div);
1524
1525 return (unsigned long)rate;
1526}
1527
1528#define ROOT_CLOCK_RATE 38400000
1529
1530static unsigned long clock_rate(u8 clock)
1531{
1532 u32 val;
1533 u32 pllsw;
1534 unsigned long rate = ROOT_CLOCK_RATE;
1535
Linus Walleijb047d982013-03-19 14:21:47 +01001536 val = readl(prcmu_base + clk_mgt[clock].offset);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001537
1538 if (val & PRCM_CLK_MGT_CLK38) {
1539 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1540 rate /= 2;
1541 return rate;
Linus Walleije62ccf32011-10-10 12:14:14 +02001542 }
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001543
1544 val |= clk_mgt[clock].pllsw;
1545 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1546
1547 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1548 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1549 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1550 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1551 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1552 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1553 else
1554 return 0;
1555
1556 if ((clock == PRCMU_SGACLK) &&
1557 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1558 u64 r = (rate * 10);
1559
1560 (void)do_div(r, 25);
1561 return (unsigned long)r;
1562 }
1563 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1564 if (val)
1565 return rate / val;
1566 else
1567 return 0;
1568}
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001569
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001570static unsigned long armss_rate(void)
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001571{
1572 u32 r;
1573 unsigned long rate;
1574
1575 r = readl(PRCM_ARM_CHGCLKREQ);
1576
1577 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1578 /* External ARMCLKFIX clock */
1579
1580 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1581
1582 /* Check PRCM_ARM_CHGCLKREQ divider */
1583 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1584 rate /= 2;
1585
1586 /* Check PRCM_ARMCLKFIX_MGT divider */
1587 r = readl(PRCM_ARMCLKFIX_MGT);
1588 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1589 rate /= r;
1590
1591 } else {/* ARM PLL */
1592 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1593 }
1594
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001595 return rate;
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001596}
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001597
1598static unsigned long dsiclk_rate(u8 n)
1599{
1600 u32 divsel;
1601 u32 div = 1;
1602
1603 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1604 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1605
1606 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1607 divsel = dsiclk[n].divsel;
Ulf Hanssone9d7b4b2013-05-14 15:14:55 +02001608 else
1609 dsiclk[n].divsel = divsel;
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001610
1611 switch (divsel) {
1612 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1613 div *= 2;
1614 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1615 div *= 2;
1616 case PRCM_DSI_PLLOUT_SEL_PHI:
1617 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1618 PLL_RAW) / div;
1619 default:
1620 return 0;
1621 }
1622}
1623
1624static unsigned long dsiescclk_rate(u8 n)
1625{
1626 u32 div;
1627
1628 div = readl(PRCM_DSITVCLK_DIV);
1629 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1630 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1631}
1632
1633unsigned long prcmu_clock_rate(u8 clock)
1634{
Linus Walleije62ccf32011-10-10 12:14:14 +02001635 if (clock < PRCMU_NUM_REG_CLOCKS)
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001636 return clock_rate(clock);
1637 else if (clock == PRCMU_TIMCLK)
1638 return ROOT_CLOCK_RATE / 16;
1639 else if (clock == PRCMU_SYSCLK)
1640 return ROOT_CLOCK_RATE;
1641 else if (clock == PRCMU_PLLSOC0)
1642 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1643 else if (clock == PRCMU_PLLSOC1)
1644 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
Michel Jaouen20aee5b2012-08-31 14:21:30 +02001645 else if (clock == PRCMU_ARMSS)
1646 return armss_rate();
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001647 else if (clock == PRCMU_PLLDDR)
1648 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1649 else if (clock == PRCMU_PLLDSI)
1650 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1651 PLL_RAW);
1652 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1653 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1654 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1655 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1656 else
1657 return 0;
1658}
1659
1660static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1661{
1662 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1663 return ROOT_CLOCK_RATE;
1664 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1665 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1666 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1667 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1668 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1669 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1670 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1671 else
1672 return 0;
1673}
1674
1675static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1676{
1677 u32 div;
1678
1679 div = (src_rate / rate);
1680 if (div == 0)
1681 return 1;
1682 if (rate < (src_rate / div))
1683 div++;
1684 return div;
1685}
1686
1687static long round_clock_rate(u8 clock, unsigned long rate)
1688{
1689 u32 val;
1690 u32 div;
1691 unsigned long src_rate;
1692 long rounded_rate;
1693
Linus Walleijb047d982013-03-19 14:21:47 +01001694 val = readl(prcmu_base + clk_mgt[clock].offset);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001695 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1696 clk_mgt[clock].branch);
1697 div = clock_divider(src_rate, rate);
1698 if (val & PRCM_CLK_MGT_CLK38) {
1699 if (clk_mgt[clock].clk38div) {
1700 if (div > 2)
1701 div = 2;
1702 } else {
1703 div = 1;
1704 }
1705 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1706 u64 r = (src_rate * 10);
1707
1708 (void)do_div(r, 25);
1709 if (r <= rate)
1710 return (unsigned long)r;
1711 }
1712 rounded_rate = (src_rate / min(div, (u32)31));
1713
1714 return rounded_rate;
1715}
1716
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001717/* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1718static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
Viresh Kumar50701582013-03-30 16:25:15 +05301719 { .frequency = 200000, .driver_data = ARM_EXTCLK,},
1720 { .frequency = 400000, .driver_data = ARM_50_OPP,},
1721 { .frequency = 800000, .driver_data = ARM_100_OPP,},
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001722 { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1723 { .frequency = CPUFREQ_TABLE_END,},
1724};
1725
1726static long round_armss_rate(unsigned long rate)
1727{
Stratos Karafotisfdb56c42014-04-25 23:16:11 +03001728 struct cpufreq_frequency_table *pos;
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001729 long freq = 0;
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001730
1731 /* cpufreq table frequencies is in KHz. */
1732 rate = rate / 1000;
1733
1734 /* Find the corresponding arm opp from the cpufreq table. */
Stratos Karafotisfdb56c42014-04-25 23:16:11 +03001735 cpufreq_for_each_entry(pos, db8500_cpufreq_table) {
1736 freq = pos->frequency;
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001737 if (freq == rate)
1738 break;
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001739 }
1740
1741 /* Return the last valid value, even if a match was not found. */
1742 return freq * 1000;
1743}
1744
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001745#define MIN_PLL_VCO_RATE 600000000ULL
1746#define MAX_PLL_VCO_RATE 1680640000ULL
1747
1748static long round_plldsi_rate(unsigned long rate)
1749{
1750 long rounded_rate = 0;
1751 unsigned long src_rate;
1752 unsigned long rem;
1753 u32 r;
1754
1755 src_rate = clock_rate(PRCMU_HDMICLK);
1756 rem = rate;
1757
1758 for (r = 7; (rem > 0) && (r > 0); r--) {
1759 u64 d;
1760
1761 d = (r * rate);
1762 (void)do_div(d, src_rate);
1763 if (d < 6)
1764 d = 6;
1765 else if (d > 255)
1766 d = 255;
1767 d *= src_rate;
1768 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1769 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1770 continue;
1771 (void)do_div(d, r);
1772 if (rate < d) {
1773 if (rounded_rate == 0)
1774 rounded_rate = (long)d;
1775 break;
1776 }
1777 if ((rate - d) < rem) {
1778 rem = (rate - d);
1779 rounded_rate = (long)d;
1780 }
1781 }
1782 return rounded_rate;
1783}
1784
1785static long round_dsiclk_rate(unsigned long rate)
1786{
1787 u32 div;
1788 unsigned long src_rate;
1789 long rounded_rate;
1790
1791 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1792 PLL_RAW);
1793 div = clock_divider(src_rate, rate);
1794 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1795
1796 return rounded_rate;
1797}
1798
1799static long round_dsiescclk_rate(unsigned long rate)
1800{
1801 u32 div;
1802 unsigned long src_rate;
1803 long rounded_rate;
1804
1805 src_rate = clock_rate(PRCMU_TVCLK);
1806 div = clock_divider(src_rate, rate);
1807 rounded_rate = (src_rate / min(div, (u32)255));
1808
1809 return rounded_rate;
1810}
1811
1812long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1813{
1814 if (clock < PRCMU_NUM_REG_CLOCKS)
1815 return round_clock_rate(clock, rate);
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001816 else if (clock == PRCMU_ARMSS)
1817 return round_armss_rate(rate);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001818 else if (clock == PRCMU_PLLDSI)
1819 return round_plldsi_rate(rate);
1820 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1821 return round_dsiclk_rate(rate);
1822 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1823 return round_dsiescclk_rate(rate);
1824 else
1825 return (long)prcmu_clock_rate(clock);
1826}
1827
1828static void set_clock_rate(u8 clock, unsigned long rate)
1829{
1830 u32 val;
1831 u32 div;
1832 unsigned long src_rate;
1833 unsigned long flags;
1834
1835 spin_lock_irqsave(&clk_mgt_lock, flags);
1836
1837 /* Grab the HW semaphore. */
1838 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1839 cpu_relax();
1840
Linus Walleijb047d982013-03-19 14:21:47 +01001841 val = readl(prcmu_base + clk_mgt[clock].offset);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001842 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1843 clk_mgt[clock].branch);
1844 div = clock_divider(src_rate, rate);
1845 if (val & PRCM_CLK_MGT_CLK38) {
1846 if (clk_mgt[clock].clk38div) {
1847 if (div > 1)
1848 val |= PRCM_CLK_MGT_CLK38DIV;
1849 else
1850 val &= ~PRCM_CLK_MGT_CLK38DIV;
1851 }
1852 } else if (clock == PRCMU_SGACLK) {
1853 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1854 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1855 if (div == 3) {
1856 u64 r = (src_rate * 10);
1857
1858 (void)do_div(r, 25);
1859 if (r <= rate) {
1860 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1861 div = 0;
1862 }
1863 }
1864 val |= min(div, (u32)31);
1865 } else {
1866 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1867 val |= min(div, (u32)31);
1868 }
Linus Walleijb047d982013-03-19 14:21:47 +01001869 writel(val, prcmu_base + clk_mgt[clock].offset);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001870
1871 /* Release the HW semaphore. */
1872 writel(0, PRCM_SEM);
1873
1874 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1875}
1876
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001877static int set_armss_rate(unsigned long rate)
1878{
Stratos Karafotisfdb56c42014-04-25 23:16:11 +03001879 struct cpufreq_frequency_table *pos;
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001880
1881 /* cpufreq table frequencies is in KHz. */
1882 rate = rate / 1000;
1883
1884 /* Find the corresponding arm opp from the cpufreq table. */
Stratos Karafotisfdb56c42014-04-25 23:16:11 +03001885 cpufreq_for_each_entry(pos, db8500_cpufreq_table)
1886 if (pos->frequency == rate)
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001887 break;
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001888
Stratos Karafotisfdb56c42014-04-25 23:16:11 +03001889 if (pos->frequency != rate)
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001890 return -EINVAL;
1891
1892 /* Set the new arm opp. */
Stratos Karafotisfdb56c42014-04-25 23:16:11 +03001893 return db8500_prcmu_set_arm_opp(pos->driver_data);
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001894}
1895
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001896static int set_plldsi_rate(unsigned long rate)
1897{
1898 unsigned long src_rate;
1899 unsigned long rem;
1900 u32 pll_freq = 0;
1901 u32 r;
1902
1903 src_rate = clock_rate(PRCMU_HDMICLK);
1904 rem = rate;
1905
1906 for (r = 7; (rem > 0) && (r > 0); r--) {
1907 u64 d;
1908 u64 hwrate;
1909
1910 d = (r * rate);
1911 (void)do_div(d, src_rate);
1912 if (d < 6)
1913 d = 6;
1914 else if (d > 255)
1915 d = 255;
1916 hwrate = (d * src_rate);
1917 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1918 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1919 continue;
1920 (void)do_div(hwrate, r);
1921 if (rate < hwrate) {
1922 if (pll_freq == 0)
1923 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1924 (r << PRCM_PLL_FREQ_R_SHIFT));
1925 break;
1926 }
1927 if ((rate - hwrate) < rem) {
1928 rem = (rate - hwrate);
1929 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1930 (r << PRCM_PLL_FREQ_R_SHIFT));
1931 }
1932 }
1933 if (pll_freq == 0)
1934 return -EINVAL;
1935
1936 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1937 writel(pll_freq, PRCM_PLLDSI_FREQ);
1938
1939 return 0;
1940}
1941
1942static void set_dsiclk_rate(u8 n, unsigned long rate)
1943{
1944 u32 val;
1945 u32 div;
1946
1947 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1948 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1949
1950 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1951 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1952 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1953
1954 val = readl(PRCM_DSI_PLLOUT_SEL);
1955 val &= ~dsiclk[n].divsel_mask;
1956 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1957 writel(val, PRCM_DSI_PLLOUT_SEL);
1958}
1959
1960static void set_dsiescclk_rate(u8 n, unsigned long rate)
1961{
1962 u32 val;
1963 u32 div;
1964
1965 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1966 val = readl(PRCM_DSITVCLK_DIV);
1967 val &= ~dsiescclk[n].div_mask;
1968 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1969 writel(val, PRCM_DSITVCLK_DIV);
1970}
1971
1972int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1973{
1974 if (clock < PRCMU_NUM_REG_CLOCKS)
1975 set_clock_rate(clock, rate);
Ulf Hanssonb2302c82012-10-10 13:42:26 +02001976 else if (clock == PRCMU_ARMSS)
1977 return set_armss_rate(rate);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001978 else if (clock == PRCMU_PLLDSI)
1979 return set_plldsi_rate(rate);
1980 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1981 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1982 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1983 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1984 return 0;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001985}
1986
Mattias Nilsson73180f82011-08-12 10:28:10 +02001987int db8500_prcmu_config_esram0_deep_sleep(u8 state)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001988{
1989 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1990 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1991 return -EINVAL;
1992
1993 mutex_lock(&mb4_transfer.lock);
1994
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001995 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001996 cpu_relax();
1997
1998 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1999 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2000 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2001 writeb(DDR_PWR_STATE_ON,
2002 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2003 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2004
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002005 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002006 wait_for_completion(&mb4_transfer.work);
2007
2008 mutex_unlock(&mb4_transfer.lock);
2009
2010 return 0;
2011}
2012
Mattias Nilsson05089012012-01-13 16:20:20 +01002013int db8500_prcmu_config_hotdog(u8 threshold)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002014{
2015 mutex_lock(&mb4_transfer.lock);
2016
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002017 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002018 cpu_relax();
2019
2020 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2021 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2022
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002023 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002024 wait_for_completion(&mb4_transfer.work);
2025
2026 mutex_unlock(&mb4_transfer.lock);
2027
2028 return 0;
2029}
2030
Mattias Nilsson05089012012-01-13 16:20:20 +01002031int db8500_prcmu_config_hotmon(u8 low, u8 high)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002032{
2033 mutex_lock(&mb4_transfer.lock);
2034
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002035 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002036 cpu_relax();
2037
2038 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2039 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2040 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2041 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2042 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2043
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002044 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002045 wait_for_completion(&mb4_transfer.work);
2046
2047 mutex_unlock(&mb4_transfer.lock);
2048
2049 return 0;
2050}
2051
2052static int config_hot_period(u16 val)
2053{
2054 mutex_lock(&mb4_transfer.lock);
2055
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002056 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002057 cpu_relax();
2058
2059 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2060 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2061
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002062 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002063 wait_for_completion(&mb4_transfer.work);
2064
2065 mutex_unlock(&mb4_transfer.lock);
2066
2067 return 0;
2068}
2069
Mattias Nilsson05089012012-01-13 16:20:20 +01002070int db8500_prcmu_start_temp_sense(u16 cycles32k)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002071{
2072 if (cycles32k == 0xFFFF)
2073 return -EINVAL;
2074
2075 return config_hot_period(cycles32k);
2076}
2077
Mattias Nilsson05089012012-01-13 16:20:20 +01002078int db8500_prcmu_stop_temp_sense(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002079{
2080 return config_hot_period(0xFFFF);
2081}
2082
Jonas Aberg84165b82011-08-12 10:28:33 +02002083static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2084{
2085
2086 mutex_lock(&mb4_transfer.lock);
2087
2088 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2089 cpu_relax();
2090
2091 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2092 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2093 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2094 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2095
2096 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2097
2098 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2099 wait_for_completion(&mb4_transfer.work);
2100
2101 mutex_unlock(&mb4_transfer.lock);
2102
2103 return 0;
2104
2105}
2106
Mattias Nilsson05089012012-01-13 16:20:20 +01002107int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
Jonas Aberg84165b82011-08-12 10:28:33 +02002108{
2109 BUG_ON(num == 0 || num > 0xf);
2110 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2111 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2112 A9WDOG_AUTO_OFF_DIS);
2113}
Fabio Baltieri6f8cfa92013-01-18 12:40:12 +01002114EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
Jonas Aberg84165b82011-08-12 10:28:33 +02002115
Mattias Nilsson05089012012-01-13 16:20:20 +01002116int db8500_prcmu_enable_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002117{
2118 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2119}
Fabio Baltieri6f8cfa92013-01-18 12:40:12 +01002120EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
Jonas Aberg84165b82011-08-12 10:28:33 +02002121
Mattias Nilsson05089012012-01-13 16:20:20 +01002122int db8500_prcmu_disable_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002123{
2124 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2125}
Fabio Baltieri6f8cfa92013-01-18 12:40:12 +01002126EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
Jonas Aberg84165b82011-08-12 10:28:33 +02002127
Mattias Nilsson05089012012-01-13 16:20:20 +01002128int db8500_prcmu_kick_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002129{
2130 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2131}
Fabio Baltieri6f8cfa92013-01-18 12:40:12 +01002132EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
Jonas Aberg84165b82011-08-12 10:28:33 +02002133
2134/*
2135 * timeout is 28 bit, in ms.
2136 */
Mattias Nilsson05089012012-01-13 16:20:20 +01002137int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
Jonas Aberg84165b82011-08-12 10:28:33 +02002138{
Jonas Aberg84165b82011-08-12 10:28:33 +02002139 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2140 (id & A9WDOG_ID_MASK) |
2141 /*
2142 * Put the lowest 28 bits of timeout at
2143 * offset 4. Four first bits are used for id.
2144 */
2145 (u8)((timeout << 4) & 0xf0),
2146 (u8)((timeout >> 4) & 0xff),
2147 (u8)((timeout >> 12) & 0xff),
2148 (u8)((timeout >> 20) & 0xff));
2149}
Fabio Baltieri6f8cfa92013-01-18 12:40:12 +01002150EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
Jonas Aberg84165b82011-08-12 10:28:33 +02002151
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002152/**
Linus Walleije3726fc2010-08-19 12:36:01 +01002153 * prcmu_abb_read() - Read register value(s) from the ABB.
2154 * @slave: The I2C slave address.
2155 * @reg: The (start) register address.
2156 * @value: The read out value(s).
2157 * @size: The number of registers to read.
2158 *
2159 * Reads register value(s) from the ABB.
2160 * @size has to be 1 for the current firmware version.
2161 */
2162int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2163{
2164 int r;
2165
2166 if (size != 1)
2167 return -EINVAL;
2168
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002169 mutex_lock(&mb5_transfer.lock);
Linus Walleije3726fc2010-08-19 12:36:01 +01002170
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002171 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
Linus Walleije3726fc2010-08-19 12:36:01 +01002172 cpu_relax();
2173
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002174 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002175 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2176 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2177 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2178 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
Linus Walleije3726fc2010-08-19 12:36:01 +01002179
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002180 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002181
Linus Walleije3726fc2010-08-19 12:36:01 +01002182 if (!wait_for_completion_timeout(&mb5_transfer.work,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002183 msecs_to_jiffies(20000))) {
2184 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2185 __func__);
Linus Walleije3726fc2010-08-19 12:36:01 +01002186 r = -EIO;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002187 } else {
2188 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
Linus Walleije3726fc2010-08-19 12:36:01 +01002189 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002190
Linus Walleije3726fc2010-08-19 12:36:01 +01002191 if (!r)
2192 *value = mb5_transfer.ack.value;
2193
Linus Walleije3726fc2010-08-19 12:36:01 +01002194 mutex_unlock(&mb5_transfer.lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002195
Linus Walleije3726fc2010-08-19 12:36:01 +01002196 return r;
2197}
Linus Walleije3726fc2010-08-19 12:36:01 +01002198
2199/**
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002200 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
Linus Walleije3726fc2010-08-19 12:36:01 +01002201 * @slave: The I2C slave address.
2202 * @reg: The (start) register address.
2203 * @value: The value(s) to write.
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002204 * @mask: The mask(s) to use.
Linus Walleije3726fc2010-08-19 12:36:01 +01002205 * @size: The number of registers to write.
2206 *
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002207 * Writes masked register value(s) to the ABB.
2208 * For each @value, only the bits set to 1 in the corresponding @mask
2209 * will be written. The other bits are not changed.
Linus Walleije3726fc2010-08-19 12:36:01 +01002210 * @size has to be 1 for the current firmware version.
2211 */
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002212int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
Linus Walleije3726fc2010-08-19 12:36:01 +01002213{
2214 int r;
2215
2216 if (size != 1)
2217 return -EINVAL;
2218
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002219 mutex_lock(&mb5_transfer.lock);
Linus Walleije3726fc2010-08-19 12:36:01 +01002220
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002221 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
Linus Walleije3726fc2010-08-19 12:36:01 +01002222 cpu_relax();
2223
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002224 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002225 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2226 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2227 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2228 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
Linus Walleije3726fc2010-08-19 12:36:01 +01002229
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002230 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002231
Linus Walleije3726fc2010-08-19 12:36:01 +01002232 if (!wait_for_completion_timeout(&mb5_transfer.work,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002233 msecs_to_jiffies(20000))) {
2234 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2235 __func__);
Linus Walleije3726fc2010-08-19 12:36:01 +01002236 r = -EIO;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002237 } else {
2238 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
Linus Walleije3726fc2010-08-19 12:36:01 +01002239 }
Linus Walleije3726fc2010-08-19 12:36:01 +01002240
Linus Walleije3726fc2010-08-19 12:36:01 +01002241 mutex_unlock(&mb5_transfer.lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002242
Linus Walleije3726fc2010-08-19 12:36:01 +01002243 return r;
2244}
Linus Walleije3726fc2010-08-19 12:36:01 +01002245
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002246/**
Mattias Nilsson3c3e4892012-03-08 14:02:05 +01002247 * prcmu_abb_write() - Write register value(s) to the ABB.
2248 * @slave: The I2C slave address.
2249 * @reg: The (start) register address.
2250 * @value: The value(s) to write.
2251 * @size: The number of registers to write.
2252 *
2253 * Writes register value(s) to the ABB.
2254 * @size has to be 1 for the current firmware version.
2255 */
2256int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2257{
2258 u8 mask = ~0;
2259
2260 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2261}
2262
2263/**
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002264 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2265 */
Arun Murthy5261e102012-05-21 14:28:21 +05302266int prcmu_ac_wake_req(void)
Martin Perssone0befb22010-12-08 15:13:28 +01002267{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002268 u32 val;
Arun Murthy5261e102012-05-21 14:28:21 +05302269 int ret = 0;
Martin Perssone0befb22010-12-08 15:13:28 +01002270
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002271 mutex_lock(&mb0_transfer.ac_wake_lock);
Martin Perssone0befb22010-12-08 15:13:28 +01002272
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002273 val = readl(PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002274 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2275 goto unlock_and_return;
2276
2277 atomic_set(&ac_wake_req_state, 1);
2278
Arun Murthy5261e102012-05-21 14:28:21 +05302279 /*
2280 * Force Modem Wake-up before hostaccess_req ping-pong.
2281 * It prevents Modem to enter in Sleep while acking the hostaccess
2282 * request. The 31us delay has been calculated by HWI.
2283 */
2284 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2285 writel(val, PRCM_HOSTACCESS_REQ);
2286
2287 udelay(31);
2288
2289 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2290 writel(val, PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002291
2292 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
Mattias Nilssond6e30022011-08-12 10:28:43 +02002293 msecs_to_jiffies(5000))) {
Linus Walleij57265bc2011-10-10 13:04:44 +02002294 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
Mattias Nilssond6e30022011-08-12 10:28:43 +02002295 __func__);
Arun Murthy5261e102012-05-21 14:28:21 +05302296 ret = -EFAULT;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002297 }
2298
2299unlock_and_return:
2300 mutex_unlock(&mb0_transfer.ac_wake_lock);
Arun Murthy5261e102012-05-21 14:28:21 +05302301 return ret;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002302}
2303
2304/**
2305 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2306 */
Sachin Kamatffb01162013-08-23 17:05:19 +05302307void prcmu_ac_sleep_req(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002308{
2309 u32 val;
2310
2311 mutex_lock(&mb0_transfer.ac_wake_lock);
2312
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002313 val = readl(PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002314 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2315 goto unlock_and_return;
2316
2317 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002318 PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002319
2320 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
Mattias Nilssond6e30022011-08-12 10:28:43 +02002321 msecs_to_jiffies(5000))) {
Linus Walleij57265bc2011-10-10 13:04:44 +02002322 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002323 __func__);
2324 }
2325
2326 atomic_set(&ac_wake_req_state, 0);
2327
2328unlock_and_return:
2329 mutex_unlock(&mb0_transfer.ac_wake_lock);
2330}
2331
Mattias Nilsson73180f82011-08-12 10:28:10 +02002332bool db8500_prcmu_is_ac_wake_requested(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002333{
2334 return (atomic_read(&ac_wake_req_state) != 0);
2335}
2336
2337/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02002338 * db8500_prcmu_system_reset - System reset
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002339 *
Mattias Nilsson73180f82011-08-12 10:28:10 +02002340 * Saves the reset reason code and then sets the APE_SOFTRST register which
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002341 * fires interrupt to fw
2342 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02002343void db8500_prcmu_system_reset(u16 reset_code)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002344{
2345 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002346 writel(1, PRCM_APE_SOFTRST);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002347}
2348
2349/**
Sebastian Rasmussen597045d2011-08-12 10:28:53 +02002350 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2351 *
2352 * Retrieves the reset reason code stored by prcmu_system_reset() before
2353 * last restart.
2354 */
2355u16 db8500_prcmu_get_reset_code(void)
2356{
2357 return readw(tcdm_base + PRCM_SW_RST_REASON);
2358}
2359
2360/**
Mattias Nilsson05089012012-01-13 16:20:20 +01002361 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002362 */
Mattias Nilsson05089012012-01-13 16:20:20 +01002363void db8500_prcmu_modem_reset(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002364{
Martin Perssone0befb22010-12-08 15:13:28 +01002365 mutex_lock(&mb1_transfer.lock);
2366
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002367 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Martin Perssone0befb22010-12-08 15:13:28 +01002368 cpu_relax();
2369
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002370 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002371 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Martin Perssone0befb22010-12-08 15:13:28 +01002372 wait_for_completion(&mb1_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002373
2374 /*
2375 * No need to check return from PRCMU as modem should go in reset state
2376 * This state is already managed by upper layer
2377 */
Martin Perssone0befb22010-12-08 15:13:28 +01002378
2379 mutex_unlock(&mb1_transfer.lock);
Martin Perssone0befb22010-12-08 15:13:28 +01002380}
2381
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002382static void ack_dbb_wakeup(void)
Martin Perssone0befb22010-12-08 15:13:28 +01002383{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002384 unsigned long flags;
Martin Perssone0befb22010-12-08 15:13:28 +01002385
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002386 spin_lock_irqsave(&mb0_transfer.lock, flags);
Martin Perssone0befb22010-12-08 15:13:28 +01002387
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002388 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002389 cpu_relax();
Martin Perssone0befb22010-12-08 15:13:28 +01002390
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002391 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002392 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Martin Perssone0befb22010-12-08 15:13:28 +01002393
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002394 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
Martin Perssone0befb22010-12-08 15:13:28 +01002395}
2396
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002397static inline void print_unknown_header_warning(u8 n, u8 header)
Linus Walleije3726fc2010-08-19 12:36:01 +01002398{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002399 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2400 header, n);
Linus Walleije3726fc2010-08-19 12:36:01 +01002401}
2402
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002403static bool read_mailbox_0(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002404{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002405 bool r;
2406 u32 ev;
2407 unsigned int n;
2408 u8 header;
2409
2410 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2411 switch (header) {
2412 case MB0H_WAKEUP_EXE:
2413 case MB0H_WAKEUP_SLEEP:
2414 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2415 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2416 else
2417 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2418
2419 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2420 complete(&mb0_transfer.ac_wake_work);
2421 if (ev & WAKEUP_BIT_SYSCLK_OK)
2422 complete(&mb3_transfer.sysclk_work);
2423
2424 ev &= mb0_transfer.req.dbb_irqs;
2425
2426 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2427 if (ev & prcmu_irq_bit[n])
Linus Walleij89d9b1c2012-12-20 10:20:15 +01002428 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002429 }
2430 r = true;
2431 break;
2432 default:
2433 print_unknown_header_warning(0, header);
2434 r = false;
2435 break;
2436 }
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002437 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002438 return r;
2439}
2440
2441static bool read_mailbox_1(void)
2442{
2443 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2444 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2445 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2446 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2447 PRCM_ACK_MB1_CURRENT_APE_OPP);
2448 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2449 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002450 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
Martin Perssone0befb22010-12-08 15:13:28 +01002451 complete(&mb1_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002452 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002453}
2454
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002455static bool read_mailbox_2(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002456{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002457 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002458 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002459 complete(&mb2_transfer.work);
2460 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002461}
2462
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002463static bool read_mailbox_3(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002464{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002465 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002466 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002467}
2468
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002469static bool read_mailbox_4(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002470{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002471 u8 header;
2472 bool do_complete = true;
2473
2474 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2475 switch (header) {
2476 case MB4H_MEM_ST:
2477 case MB4H_HOTDOG:
2478 case MB4H_HOTMON:
2479 case MB4H_HOT_PERIOD:
Mattias Nilssona592c2e2011-08-12 10:27:41 +02002480 case MB4H_A9WDOG_CONF:
2481 case MB4H_A9WDOG_EN:
2482 case MB4H_A9WDOG_DIS:
2483 case MB4H_A9WDOG_LOAD:
2484 case MB4H_A9WDOG_KICK:
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002485 break;
2486 default:
2487 print_unknown_header_warning(4, header);
2488 do_complete = false;
2489 break;
2490 }
2491
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002492 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002493
2494 if (do_complete)
2495 complete(&mb4_transfer.work);
2496
2497 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002498}
2499
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002500static bool read_mailbox_5(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002501{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002502 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2503 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002504 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
Linus Walleije3726fc2010-08-19 12:36:01 +01002505 complete(&mb5_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002506 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002507}
2508
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002509static bool read_mailbox_6(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002510{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002511 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002512 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002513}
2514
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002515static bool read_mailbox_7(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002516{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002517 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002518 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002519}
2520
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002521static bool (* const read_mailbox[NUM_MB])(void) = {
Linus Walleije3726fc2010-08-19 12:36:01 +01002522 read_mailbox_0,
2523 read_mailbox_1,
2524 read_mailbox_2,
2525 read_mailbox_3,
2526 read_mailbox_4,
2527 read_mailbox_5,
2528 read_mailbox_6,
2529 read_mailbox_7
2530};
2531
2532static irqreturn_t prcmu_irq_handler(int irq, void *data)
2533{
2534 u32 bits;
2535 u8 n;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002536 irqreturn_t r;
Linus Walleije3726fc2010-08-19 12:36:01 +01002537
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002538 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
Linus Walleije3726fc2010-08-19 12:36:01 +01002539 if (unlikely(!bits))
2540 return IRQ_NONE;
2541
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002542 r = IRQ_HANDLED;
Linus Walleije3726fc2010-08-19 12:36:01 +01002543 for (n = 0; bits; n++) {
2544 if (bits & MBOX_BIT(n)) {
2545 bits -= MBOX_BIT(n);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002546 if (read_mailbox[n]())
2547 r = IRQ_WAKE_THREAD;
Linus Walleije3726fc2010-08-19 12:36:01 +01002548 }
2549 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002550 return r;
2551}
2552
2553static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2554{
2555 ack_dbb_wakeup();
Linus Walleije3726fc2010-08-19 12:36:01 +01002556 return IRQ_HANDLED;
2557}
2558
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002559static void prcmu_mask_work(struct work_struct *work)
2560{
2561 unsigned long flags;
2562
2563 spin_lock_irqsave(&mb0_transfer.lock, flags);
2564
2565 config_wakeups();
2566
2567 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2568}
2569
2570static void prcmu_irq_mask(struct irq_data *d)
2571{
2572 unsigned long flags;
2573
2574 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2575
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002576 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002577
2578 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2579
2580 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2581 schedule_work(&mb0_transfer.mask_work);
2582}
2583
2584static void prcmu_irq_unmask(struct irq_data *d)
2585{
2586 unsigned long flags;
2587
2588 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2589
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002590 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002591
2592 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2593
2594 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2595 schedule_work(&mb0_transfer.mask_work);
2596}
2597
2598static void noop(struct irq_data *d)
2599{
2600}
2601
2602static struct irq_chip prcmu_irq_chip = {
2603 .name = "prcmu",
2604 .irq_disable = prcmu_irq_mask,
2605 .irq_ack = noop,
2606 .irq_mask = prcmu_irq_mask,
2607 .irq_unmask = prcmu_irq_unmask,
2608};
2609
Linus Walleij05ec2602013-02-07 10:17:31 +01002610static __init char *fw_project_name(u32 project)
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002611{
2612 switch (project) {
2613 case PRCMU_FW_PROJECT_U8500:
2614 return "U8500";
Linus Walleij05ec2602013-02-07 10:17:31 +01002615 case PRCMU_FW_PROJECT_U8400:
2616 return "U8400";
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002617 case PRCMU_FW_PROJECT_U9500:
2618 return "U9500";
Linus Walleij05ec2602013-02-07 10:17:31 +01002619 case PRCMU_FW_PROJECT_U8500_MBB:
2620 return "U8500 MBB";
2621 case PRCMU_FW_PROJECT_U8500_C1:
2622 return "U8500 C1";
2623 case PRCMU_FW_PROJECT_U8500_C2:
2624 return "U8500 C2";
2625 case PRCMU_FW_PROJECT_U8500_C3:
2626 return "U8500 C3";
2627 case PRCMU_FW_PROJECT_U8500_C4:
2628 return "U8500 C4";
2629 case PRCMU_FW_PROJECT_U9500_MBL:
2630 return "U9500 MBL";
2631 case PRCMU_FW_PROJECT_U8500_MBL:
2632 return "U8500 MBL";
2633 case PRCMU_FW_PROJECT_U8500_MBL2:
2634 return "U8500 MBL2";
Bengt Jonsson5f96a1a62012-03-15 19:50:40 +01002635 case PRCMU_FW_PROJECT_U8520:
Linus Walleij05ec2602013-02-07 10:17:31 +01002636 return "U8520 MBL";
Bengt Jonsson1927ddf2012-03-15 19:50:51 +01002637 case PRCMU_FW_PROJECT_U8420:
2638 return "U8420";
Linus Walleij05ec2602013-02-07 10:17:31 +01002639 case PRCMU_FW_PROJECT_U9540:
2640 return "U9540";
2641 case PRCMU_FW_PROJECT_A9420:
2642 return "A9420";
2643 case PRCMU_FW_PROJECT_L8540:
2644 return "L8540";
2645 case PRCMU_FW_PROJECT_L8580:
2646 return "L8580";
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002647 default:
2648 return "Unknown";
2649 }
2650}
2651
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002652static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2653 irq_hw_number_t hwirq)
2654{
2655 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2656 handle_simple_irq);
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002657
2658 return 0;
2659}
2660
Krzysztof Kozlowski7ce7b262015-04-27 21:54:13 +09002661static const struct irq_domain_ops db8500_irq_ops = {
Linus Walleij89d9b1c2012-12-20 10:20:15 +01002662 .map = db8500_irq_map,
2663 .xlate = irq_domain_xlate_twocell,
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002664};
2665
Linus Walleijf864c462014-02-04 00:35:56 +01002666static int db8500_irq_init(struct device_node *np)
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002667{
Linus Walleij89d9b1c2012-12-20 10:20:15 +01002668 int i;
Linus Walleija7238e42012-10-18 18:22:11 +02002669
Linus Walleija7238e42012-10-18 18:22:11 +02002670 db8500_irq_domain = irq_domain_add_simple(
Linus Walleijf864c462014-02-04 00:35:56 +01002671 np, NUM_PRCMU_WAKEUPS, 0,
Linus Walleija7238e42012-10-18 18:22:11 +02002672 &db8500_irq_ops, NULL);
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002673
2674 if (!db8500_irq_domain) {
2675 pr_err("Failed to create irqdomain\n");
2676 return -ENOSYS;
2677 }
2678
Linus Walleij89d9b1c2012-12-20 10:20:15 +01002679 /* All wakeups will be used, so create mappings for all */
2680 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2681 irq_create_mapping(db8500_irq_domain, i);
2682
Lee Jonesf3f1f0a2012-09-24 09:11:46 +01002683 return 0;
2684}
2685
Linus Walleij05ec2602013-02-07 10:17:31 +01002686static void dbx500_fw_version_init(struct platform_device *pdev,
2687 u32 version_offset)
2688{
2689 struct resource *res;
2690 void __iomem *tcpm_base;
Lee Jones741cdec2013-04-04 11:39:00 +01002691 u32 version;
Linus Walleij05ec2602013-02-07 10:17:31 +01002692
2693 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2694 "prcmu-tcpm");
2695 if (!res) {
2696 dev_err(&pdev->dev,
2697 "Error: no prcmu tcpm memory region provided\n");
2698 return;
2699 }
2700 tcpm_base = ioremap(res->start, resource_size(res));
Lee Jones741cdec2013-04-04 11:39:00 +01002701 if (!tcpm_base) {
2702 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2703 return;
Linus Walleij05ec2602013-02-07 10:17:31 +01002704 }
Lee Jones741cdec2013-04-04 11:39:00 +01002705
2706 version = readl(tcpm_base + version_offset);
2707 fw_info.version.project = (version & 0xFF);
2708 fw_info.version.api_version = (version >> 8) & 0xFF;
2709 fw_info.version.func_version = (version >> 16) & 0xFF;
2710 fw_info.version.errata = (version >> 24) & 0xFF;
2711 strncpy(fw_info.version.project_name,
2712 fw_project_name(fw_info.version.project),
2713 PRCMU_FW_PROJECT_NAME_LEN);
2714 fw_info.valid = true;
2715 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2716 fw_info.version.project_name,
2717 fw_info.version.project,
2718 fw_info.version.api_version,
2719 fw_info.version.func_version,
2720 fw_info.version.errata);
2721 iounmap(tcpm_base);
Linus Walleij05ec2602013-02-07 10:17:31 +01002722}
2723
Linus Walleij9a47a8d2013-03-21 12:27:25 +01002724void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002725{
Linus Walleij9a47a8d2013-03-21 12:27:25 +01002726 /*
2727 * This is a temporary remap to bring up the clocks. It is
2728 * subsequently replaces with a real remap. After the merge of
2729 * the mailbox subsystem all of this early code goes away, and the
2730 * clock driver can probe independently. An early initcall will
2731 * still be needed, but it can be diverted into drivers/clk/ux500.
2732 */
2733 prcmu_base = ioremap(phy_base, size);
2734 if (!prcmu_base)
2735 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2736
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002737 spin_lock_init(&mb0_transfer.lock);
2738 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2739 mutex_init(&mb0_transfer.ac_wake_lock);
2740 init_completion(&mb0_transfer.ac_wake_work);
Martin Perssone0befb22010-12-08 15:13:28 +01002741 mutex_init(&mb1_transfer.lock);
2742 init_completion(&mb1_transfer.work);
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01002743 mb1_transfer.ape_opp = APE_NO_CHANGE;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002744 mutex_init(&mb2_transfer.lock);
2745 init_completion(&mb2_transfer.work);
2746 spin_lock_init(&mb2_transfer.auto_pm_lock);
2747 spin_lock_init(&mb3_transfer.lock);
2748 mutex_init(&mb3_transfer.sysclk_lock);
2749 init_completion(&mb3_transfer.sysclk_work);
2750 mutex_init(&mb4_transfer.lock);
2751 init_completion(&mb4_transfer.work);
Linus Walleije3726fc2010-08-19 12:36:01 +01002752 mutex_init(&mb5_transfer.lock);
2753 init_completion(&mb5_transfer.work);
2754
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002755 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
Linus Walleije3726fc2010-08-19 12:36:01 +01002756}
2757
Mattias Nilsson05089012012-01-13 16:20:20 +01002758static void __init init_prcm_registers(void)
Mattias Nilssond65e12d2011-08-12 10:27:50 +02002759{
2760 u32 val;
2761
2762 val = readl(PRCM_A9PL_FORCE_CLKEN);
2763 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2764 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2765 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2766}
2767
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002768/*
2769 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2770 */
2771static struct regulator_consumer_supply db8500_vape_consumers[] = {
2772 REGULATOR_SUPPLY("v-ape", NULL),
2773 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2774 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2775 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2776 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
Lee Jonesae840632012-05-04 19:23:20 +01002777 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002778 /* "v-mmc" changed to "vcore" in the mainline kernel */
2779 REGULATOR_SUPPLY("vcore", "sdi0"),
2780 REGULATOR_SUPPLY("vcore", "sdi1"),
2781 REGULATOR_SUPPLY("vcore", "sdi2"),
2782 REGULATOR_SUPPLY("vcore", "sdi3"),
2783 REGULATOR_SUPPLY("vcore", "sdi4"),
2784 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2785 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2786 /* "v-uart" changed to "vcore" in the mainline kernel */
2787 REGULATOR_SUPPLY("vcore", "uart0"),
2788 REGULATOR_SUPPLY("vcore", "uart1"),
2789 REGULATOR_SUPPLY("vcore", "uart2"),
2790 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
Bengt Jonsson992b1332012-01-13 16:20:36 +01002791 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
Lee Jonesbc367482012-05-03 11:23:47 +01002792 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002793};
2794
2795static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002796 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2797 /* AV8100 regulator */
2798 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2799};
2800
2801static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002802 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002803 REGULATOR_SUPPLY("vsupply", "mcde"),
2804};
2805
2806/* SVA MMDSP regulator switch */
2807static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2808 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2809};
2810
2811/* SVA pipe regulator switch */
2812static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2813 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2814};
2815
2816/* SIA MMDSP regulator switch */
2817static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2818 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2819};
2820
2821/* SIA pipe regulator switch */
2822static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2823 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2824};
2825
2826static struct regulator_consumer_supply db8500_sga_consumers[] = {
2827 REGULATOR_SUPPLY("v-mali", NULL),
2828};
2829
2830/* ESRAM1 and 2 regulator switch */
2831static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2832 REGULATOR_SUPPLY("esram12", "cm_control"),
2833};
2834
2835/* ESRAM3 and 4 regulator switch */
2836static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2837 REGULATOR_SUPPLY("v-esram34", "mcde"),
2838 REGULATOR_SUPPLY("esram34", "cm_control"),
Bengt Jonsson992b1332012-01-13 16:20:36 +01002839 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002840};
2841
2842static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2843 [DB8500_REGULATOR_VAPE] = {
2844 .constraints = {
2845 .name = "db8500-vape",
2846 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
Mark Brown1e458602012-04-13 13:11:50 +01002847 .always_on = true,
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002848 },
2849 .consumer_supplies = db8500_vape_consumers,
2850 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2851 },
2852 [DB8500_REGULATOR_VARM] = {
2853 .constraints = {
2854 .name = "db8500-varm",
2855 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2856 },
2857 },
2858 [DB8500_REGULATOR_VMODEM] = {
2859 .constraints = {
2860 .name = "db8500-vmodem",
2861 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2862 },
2863 },
2864 [DB8500_REGULATOR_VPLL] = {
2865 .constraints = {
2866 .name = "db8500-vpll",
2867 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2868 },
2869 },
2870 [DB8500_REGULATOR_VSMPS1] = {
2871 .constraints = {
2872 .name = "db8500-vsmps1",
2873 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2874 },
2875 },
2876 [DB8500_REGULATOR_VSMPS2] = {
2877 .constraints = {
2878 .name = "db8500-vsmps2",
2879 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2880 },
2881 .consumer_supplies = db8500_vsmps2_consumers,
2882 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2883 },
2884 [DB8500_REGULATOR_VSMPS3] = {
2885 .constraints = {
2886 .name = "db8500-vsmps3",
2887 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2888 },
2889 },
2890 [DB8500_REGULATOR_VRF1] = {
2891 .constraints = {
2892 .name = "db8500-vrf1",
2893 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2894 },
2895 },
2896 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002897 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002898 .constraints = {
2899 .name = "db8500-sva-mmdsp",
2900 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2901 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002902 .consumer_supplies = db8500_svammdsp_consumers,
2903 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002904 },
2905 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2906 .constraints = {
2907 /* "ret" means "retention" */
2908 .name = "db8500-sva-mmdsp-ret",
2909 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2910 },
2911 },
2912 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002913 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002914 .constraints = {
2915 .name = "db8500-sva-pipe",
2916 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2917 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002918 .consumer_supplies = db8500_svapipe_consumers,
2919 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002920 },
2921 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002922 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002923 .constraints = {
2924 .name = "db8500-sia-mmdsp",
2925 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2926 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002927 .consumer_supplies = db8500_siammdsp_consumers,
2928 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002929 },
2930 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2931 .constraints = {
2932 .name = "db8500-sia-mmdsp-ret",
2933 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2934 },
2935 },
2936 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002937 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002938 .constraints = {
2939 .name = "db8500-sia-pipe",
2940 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2941 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002942 .consumer_supplies = db8500_siapipe_consumers,
2943 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002944 },
2945 [DB8500_REGULATOR_SWITCH_SGA] = {
2946 .supply_regulator = "db8500-vape",
2947 .constraints = {
2948 .name = "db8500-sga",
2949 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2950 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002951 .consumer_supplies = db8500_sga_consumers,
2952 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2953
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002954 },
2955 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2956 .supply_regulator = "db8500-vape",
2957 .constraints = {
2958 .name = "db8500-b2r2-mcde",
2959 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2960 },
2961 .consumer_supplies = db8500_b2r2_mcde_consumers,
2962 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2963 },
2964 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002965 /*
2966 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2967 * no need to hold Vape
2968 */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002969 .constraints = {
2970 .name = "db8500-esram12",
2971 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2972 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002973 .consumer_supplies = db8500_esram12_consumers,
2974 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002975 },
2976 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2977 .constraints = {
2978 .name = "db8500-esram12-ret",
2979 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2980 },
2981 },
2982 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002983 /*
2984 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2985 * no need to hold Vape
2986 */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002987 .constraints = {
2988 .name = "db8500-esram34",
2989 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2990 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002991 .consumer_supplies = db8500_esram34_consumers,
2992 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002993 },
2994 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2995 .constraints = {
2996 .name = "db8500-esram34-ret",
2997 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2998 },
2999 },
3000};
3001
Fabio Baltierib3aac622013-01-18 12:40:14 +01003002static struct ux500_wdt_data db8500_wdt_pdata = {
3003 .timeout = 600, /* 10 minutes */
3004 .has_28_bits_resolution = true,
3005};
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003006/*
3007 * Thermal Sensor
3008 */
3009
3010static struct resource db8500_thsens_resources[] = {
3011 {
3012 .name = "IRQ_HOTMON_LOW",
3013 .start = IRQ_PRCMU_HOTMON_LOW,
3014 .end = IRQ_PRCMU_HOTMON_LOW,
3015 .flags = IORESOURCE_IRQ,
3016 },
3017 {
3018 .name = "IRQ_HOTMON_HIGH",
3019 .start = IRQ_PRCMU_HOTMON_HIGH,
3020 .end = IRQ_PRCMU_HOTMON_HIGH,
3021 .flags = IORESOURCE_IRQ,
3022 },
3023};
3024
3025static struct db8500_thsens_platform_data db8500_thsens_data = {
3026 .trip_points[0] = {
3027 .temp = 70000,
3028 .type = THERMAL_TRIP_ACTIVE,
3029 .cdev_name = {
3030 [0] = "thermal-cpufreq-0",
3031 },
3032 },
3033 .trip_points[1] = {
3034 .temp = 75000,
3035 .type = THERMAL_TRIP_ACTIVE,
3036 .cdev_name = {
3037 [0] = "thermal-cpufreq-0",
3038 },
3039 },
3040 .trip_points[2] = {
3041 .temp = 80000,
3042 .type = THERMAL_TRIP_ACTIVE,
3043 .cdev_name = {
3044 [0] = "thermal-cpufreq-0",
3045 },
3046 },
3047 .trip_points[3] = {
3048 .temp = 85000,
3049 .type = THERMAL_TRIP_CRITICAL,
3050 },
3051 .num_trips = 4,
3052};
Fabio Baltierib3aac622013-01-18 12:40:14 +01003053
Geert Uytterhoeven5ac98552013-11-18 14:33:06 +01003054static const struct mfd_cell common_prcmu_devs[] = {
Lee Jonesd98a5382013-04-09 20:52:58 +01003055 {
3056 .name = "ux500_wdt",
3057 .platform_data = &db8500_wdt_pdata,
3058 .pdata_size = sizeof(db8500_wdt_pdata),
3059 .id = -1,
3060 },
3061};
3062
Geert Uytterhoeven5ac98552013-11-18 14:33:06 +01003063static const struct mfd_cell db8500_prcmu_devs[] = {
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003064 {
3065 .name = "db8500-prcmu-regulators",
Lee Jones5d903222012-06-20 13:56:41 +01003066 .of_compatible = "stericsson,db8500-prcmu-regulator",
Mattias Wallin1ed78912011-05-27 11:49:43 +02003067 .platform_data = &db8500_regulators,
3068 .pdata_size = sizeof(db8500_regulators),
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003069 },
3070 {
Lee Jones84c7c202012-12-10 16:25:39 +01003071 .name = "cpufreq-ux500",
3072 .of_compatible = "stericsson,cpufreq-ux500",
Ulf Hanssonc280f452012-10-10 13:42:23 +02003073 .platform_data = &db8500_cpufreq_table,
3074 .pdata_size = sizeof(db8500_cpufreq_table),
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003075 },
Lee Jones6d11d132012-06-29 17:13:35 +02003076 {
Linus Walleij80253952013-07-10 15:35:26 +02003077 .name = "cpuidle-dbx500",
3078 .of_compatible = "stericsson,cpuidle-dbx500",
3079 },
3080 {
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003081 .name = "db8500-thermal",
3082 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3083 .resources = db8500_thsens_resources,
3084 .platform_data = &db8500_thsens_data,
Lee Jonesa3ef0de2013-05-07 12:01:32 +01003085 .pdata_size = sizeof(db8500_thsens_data),
Lee Jones6d11d132012-06-29 17:13:35 +02003086 },
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003087};
3088
Ulf Hanssonc280f452012-10-10 13:42:23 +02003089static void db8500_prcmu_update_cpufreq(void)
3090{
3091 if (prcmu_has_arm_maxopp()) {
3092 db8500_cpufreq_table[3].frequency = 1000000;
Viresh Kumar50701582013-03-30 16:25:15 +05303093 db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP;
Ulf Hanssonc280f452012-10-10 13:42:23 +02003094 }
3095}
3096
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003097static int db8500_prcmu_register_ab8500(struct device *parent,
Linus Walleijf864c462014-02-04 00:35:56 +01003098 struct ab8500_platform_data *pdata)
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003099{
Linus Walleijf864c462014-02-04 00:35:56 +01003100 struct device_node *np;
3101 struct resource ab8500_resource;
Krzysztof Kozlowski5785a972014-05-13 12:58:41 +02003102 const struct mfd_cell ab8500_cell = {
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003103 .name = "ab8500-core",
3104 .of_compatible = "stericsson,ab8500",
3105 .id = AB8500_VERSION_AB8500,
3106 .platform_data = pdata,
3107 .pdata_size = sizeof(struct ab8500_platform_data),
3108 .resources = &ab8500_resource,
3109 .num_resources = 1,
3110 };
3111
Linus Walleijf864c462014-02-04 00:35:56 +01003112 if (!parent->of_node)
3113 return -ENODEV;
3114
3115 /* Look up the device node, sneak the IRQ out of it */
3116 for_each_child_of_node(parent->of_node, np) {
3117 if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3118 break;
3119 }
3120 if (!np) {
3121 dev_info(parent, "could not find AB8500 node in the device tree\n");
3122 return -ENODEV;
3123 }
3124 of_irq_to_resource_table(np, &ab8500_resource, 1);
3125
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003126 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3127}
3128
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003129/**
3130 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3131 *
3132 */
Bill Pembertonf791be42012-11-19 13:23:04 -05003133static int db8500_prcmu_probe(struct platform_device *pdev)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003134{
Lee Jonesca7edd12012-05-09 17:19:25 +02003135 struct device_node *np = pdev->dev.of_node;
Linus Walleij05ec2602013-02-07 10:17:31 +01003136 struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003137 int irq = 0, err = 0;
Linus Walleij05ec2602013-02-07 10:17:31 +01003138 struct resource *res;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003139
Linus Walleijb047d982013-03-19 14:21:47 +01003140 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3141 if (!res) {
3142 dev_err(&pdev->dev, "no prcmu memory region provided\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003143 return -EINVAL;
Linus Walleijb047d982013-03-19 14:21:47 +01003144 }
3145 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3146 if (!prcmu_base) {
3147 dev_err(&pdev->dev,
3148 "failed to ioremap prcmu register memory\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003149 return -ENOMEM;
Linus Walleijb047d982013-03-19 14:21:47 +01003150 }
Mattias Nilsson05089012012-01-13 16:20:20 +01003151 init_prcm_registers();
Linus Walleij05ec2602013-02-07 10:17:31 +01003152 dbx500_fw_version_init(pdev, pdata->version_offset);
3153 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3154 if (!res) {
3155 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003156 return -EINVAL;
Linus Walleij05ec2602013-02-07 10:17:31 +01003157 }
3158 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3159 resource_size(res));
Pramod Gurav51a7e022014-10-30 14:51:35 +05303160 if (!tcdm_base) {
3161 dev_err(&pdev->dev,
3162 "failed to ioremap prcmu-tcdm register memory\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003163 return -ENOMEM;
Pramod Gurav51a7e022014-10-30 14:51:35 +05303164 }
Linus Walleij05ec2602013-02-07 10:17:31 +01003165
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003166 /* Clean up the mailbox interrupts after pre-kernel code. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02003167 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003168
Linus Walleij05ec2602013-02-07 10:17:31 +01003169 irq = platform_get_irq(pdev, 0);
3170 if (irq <= 0) {
3171 dev_err(&pdev->dev, "no prcmu irq provided\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003172 return irq;
Linus Walleij05ec2602013-02-07 10:17:31 +01003173 }
Lee Jonesca7edd12012-05-09 17:19:25 +02003174
3175 err = request_threaded_irq(irq, prcmu_irq_handler,
3176 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003177 if (err < 0) {
3178 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003179 return err;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003180 }
3181
Linus Walleijf864c462014-02-04 00:35:56 +01003182 db8500_irq_init(np);
Lee Jones3a8e39c2012-07-06 12:46:23 +02003183
Linus Walleij7a4f2602012-09-19 19:31:19 +02003184 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003185
Ulf Hanssonc280f452012-10-10 13:42:23 +02003186 db8500_prcmu_update_cpufreq();
3187
Lee Jonesd98a5382013-04-09 20:52:58 +01003188 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3189 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
Lee Jones5d903222012-06-20 13:56:41 +01003190 if (err) {
3191 pr_err("prcmu: Failed to add subdevices\n");
3192 return err;
Lee Jonesca7edd12012-05-09 17:19:25 +02003193 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003194
Lee Jonesd98a5382013-04-09 20:52:58 +01003195 /* TODO: Remove restriction when clk definitions are available. */
3196 if (!of_machine_is_compatible("st-ericsson,u8540")) {
3197 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3198 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3199 db8500_irq_domain);
3200 if (err) {
3201 mfd_remove_devices(&pdev->dev);
3202 pr_err("prcmu: Failed to add subdevices\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003203 return err;
Lee Jonesd98a5382013-04-09 20:52:58 +01003204 }
3205 }
3206
Linus Walleijf864c462014-02-04 00:35:56 +01003207 err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata);
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003208 if (err) {
3209 mfd_remove_devices(&pdev->dev);
3210 pr_err("prcmu: Failed to add ab8500 subdevice\n");
Lee Jones6bdf8912014-11-03 16:12:26 +00003211 return err;
Arnd Bergmann55b175d2013-03-21 22:51:07 +01003212 }
3213
Lee Jonesca7edd12012-05-09 17:19:25 +02003214 pr_info("DB8500 PRCMU initialized\n");
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003215 return err;
3216}
Lee Jones3c144762012-06-29 15:41:38 +02003217static const struct of_device_id db8500_prcmu_match[] = {
3218 { .compatible = "stericsson,db8500-prcmu"},
3219 { },
3220};
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003221
3222static struct platform_driver db8500_prcmu_driver = {
3223 .driver = {
3224 .name = "db8500-prcmu",
Lee Jones3c144762012-06-29 15:41:38 +02003225 .of_match_table = db8500_prcmu_match,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003226 },
Lee Jones9fc63f62012-04-19 21:36:41 +01003227 .probe = db8500_prcmu_probe,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003228};
3229
3230static int __init db8500_prcmu_init(void)
3231{
Lee Jones9fc63f62012-04-19 21:36:41 +01003232 return platform_driver_register(&db8500_prcmu_driver);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003233}
3234
Lee Jonesa661aca2012-06-11 16:24:59 +01003235core_initcall(db8500_prcmu_init);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003236
3237MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3238MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3239MODULE_LICENSE("GPL v2");