Blame - include/linux/mfd/arizona/registers.h - kernel/msm-4.9

2012-06-19 16:28:40 +0100

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/*

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* ARIZONA register definitions

*

*

* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>

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*

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License version 2 as

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* published by the Free Software Foundation.

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*/

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#ifndef _ARIZONA_REGISTERS_H

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#define _ARIZONA_REGISTERS_H

/*

* Register values.

*/

#define ARIZONA_SOFTWARE_RESET 0x00

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#define ARIZONA_DEVICE_REVISION 0x01

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#define ARIZONA_CTRL_IF_SPI_CFG_1 0x08

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#define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09

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#define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A

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#define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B

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#define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C

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#define ARIZONA_CTRL_IF_STATUS_1 0x0D

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#define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16

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#define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17

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#define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18

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#define ARIZONA_WRITE_SEQUENCER_PROM 0x1A

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#define ARIZONA_TONE_GENERATOR_1 0x20

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#define ARIZONA_TONE_GENERATOR_2 0x21

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#define ARIZONA_TONE_GENERATOR_3 0x22

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#define ARIZONA_TONE_GENERATOR_4 0x23

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#define ARIZONA_TONE_GENERATOR_5 0x24

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#define ARIZONA_PWM_DRIVE_1 0x30

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#define ARIZONA_PWM_DRIVE_2 0x31

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#define ARIZONA_PWM_DRIVE_3 0x32

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#define ARIZONA_WAKE_CONTROL 0x40

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#define ARIZONA_SEQUENCE_CONTROL 0x41

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#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61

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#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62

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#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63

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#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64

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#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68

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#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69

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#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A

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#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B

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#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C

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#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D

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#define ARIZONA_COMFORT_NOISE_GENERATOR 0x70

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#define ARIZONA_HAPTICS_CONTROL_1 0x90

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#define ARIZONA_HAPTICS_CONTROL_2 0x91

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#define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92

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#define ARIZONA_HAPTICS_PHASE_1_DURATION 0x93

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#define ARIZONA_HAPTICS_PHASE_2_INTENSITY 0x94

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#define ARIZONA_HAPTICS_PHASE_2_DURATION 0x95

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#define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96

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#define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97

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#define ARIZONA_HAPTICS_STATUS 0x98

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#define ARIZONA_CLOCK_32K_1 0x100

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#define ARIZONA_SYSTEM_CLOCK_1 0x101

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#define ARIZONA_SAMPLE_RATE_1 0x102

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#define ARIZONA_SAMPLE_RATE_2 0x103

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#define ARIZONA_SAMPLE_RATE_3 0x104

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#define ARIZONA_SAMPLE_RATE_1_STATUS 0x10A

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#define ARIZONA_SAMPLE_RATE_2_STATUS 0x10B

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#define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C

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#define ARIZONA_ASYNC_CLOCK_1 0x112

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#define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113

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#define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B

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#define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149

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#define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A

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#define ARIZONA_RATE_ESTIMATOR_1 0x152

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#define ARIZONA_RATE_ESTIMATOR_2 0x153

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#define ARIZONA_RATE_ESTIMATOR_3 0x154

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#define ARIZONA_RATE_ESTIMATOR_4 0x155

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#define ARIZONA_RATE_ESTIMATOR_5 0x156

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#define ARIZONA_DYNAMIC_FREQUENCY_SCALING_1 0x161

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#define ARIZONA_FLL1_CONTROL_1 0x171

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#define ARIZONA_FLL1_CONTROL_2 0x172

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#define ARIZONA_FLL1_CONTROL_3 0x173

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#define ARIZONA_FLL1_CONTROL_4 0x174

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#define ARIZONA_FLL1_CONTROL_5 0x175

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#define ARIZONA_FLL1_CONTROL_6 0x176

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#define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177

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#define ARIZONA_FLL1_NCO_TEST_0 0x178

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#define ARIZONA_FLL1_CONTROL_7 0x179

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#define ARIZONA_FLL1_SYNCHRONISER_1 0x181

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#define ARIZONA_FLL1_SYNCHRONISER_2 0x182

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#define ARIZONA_FLL1_SYNCHRONISER_3 0x183

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#define ARIZONA_FLL1_SYNCHRONISER_4 0x184

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#define ARIZONA_FLL1_SYNCHRONISER_5 0x185

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#define ARIZONA_FLL1_SYNCHRONISER_6 0x186

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#define ARIZONA_FLL1_SYNCHRONISER_7 0x187

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#define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189

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#define ARIZONA_FLL1_GPIO_CLOCK 0x18A

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#define ARIZONA_FLL2_CONTROL_1 0x191

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#define ARIZONA_FLL2_CONTROL_2 0x192

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#define ARIZONA_FLL2_CONTROL_3 0x193

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#define ARIZONA_FLL2_CONTROL_4 0x194

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#define ARIZONA_FLL2_CONTROL_5 0x195

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#define ARIZONA_FLL2_CONTROL_6 0x196

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#define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197

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#define ARIZONA_FLL2_NCO_TEST_0 0x198

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#define ARIZONA_FLL2_CONTROL_7 0x199

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#define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1

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#define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2

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#define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3

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#define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4

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#define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5

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#define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6

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#define ARIZONA_FLL2_SYNCHRONISER_7 0x1A7

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#define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9

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#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA

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#define ARIZONA_MIC_CHARGE_PUMP_1 0x200

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#define ARIZONA_LDO1_CONTROL_1 0x210

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#define ARIZONA_LDO1_CONTROL_2 0x212

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#define ARIZONA_LDO2_CONTROL_1 0x213

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#define ARIZONA_MIC_BIAS_CTRL_1 0x218

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#define ARIZONA_MIC_BIAS_CTRL_2 0x219

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#define ARIZONA_MIC_BIAS_CTRL_3 0x21A

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#define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293

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#define ARIZONA_HEADPHONE_DETECT_1 0x29B

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#define ARIZONA_HEADPHONE_DETECT_2 0x29C

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#define ARIZONA_HP_DACVAL 0x29F

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#define ARIZONA_MICD_CLAMP_CONTROL 0x2A2

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#define ARIZONA_MIC_DETECT_1 0x2A3

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#define ARIZONA_MIC_DETECT_2 0x2A4

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#define ARIZONA_MIC_DETECT_3 0x2A5

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#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3

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#define ARIZONA_ISOLATION_CONTROL 0x2CB

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#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3

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#define ARIZONA_INPUT_ENABLES 0x300

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#define ARIZONA_INPUT_ENABLES_STATUS 0x301

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#define ARIZONA_INPUT_RATE 0x308

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#define ARIZONA_INPUT_VOLUME_RAMP 0x309

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#define ARIZONA_IN1L_CONTROL 0x310

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#define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311

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#define ARIZONA_DMIC1L_CONTROL 0x312

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#define ARIZONA_IN1R_CONTROL 0x314

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#define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315

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#define ARIZONA_DMIC1R_CONTROL 0x316

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#define ARIZONA_IN2L_CONTROL 0x318

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#define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319

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#define ARIZONA_DMIC2L_CONTROL 0x31A

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#define ARIZONA_IN2R_CONTROL 0x31C

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#define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D

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#define ARIZONA_DMIC2R_CONTROL 0x31E

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#define ARIZONA_IN3L_CONTROL 0x320

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#define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321

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#define ARIZONA_DMIC3L_CONTROL 0x322

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#define ARIZONA_IN3R_CONTROL 0x324

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#define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325

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#define ARIZONA_DMIC3R_CONTROL 0x326

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#define ARIZONA_IN4L_CONTROL 0x328

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#define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329

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#define ARIZONA_DMIC4L_CONTROL 0x32A

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#define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D

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#define ARIZONA_DMIC4R_CONTROL 0x32E

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#define ARIZONA_OUTPUT_ENABLES_1 0x400

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#define ARIZONA_OUTPUT_STATUS_1 0x401

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#define ARIZONA_RAW_OUTPUT_STATUS_1 0x406

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#define ARIZONA_OUTPUT_RATE_1 0x408

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#define ARIZONA_OUTPUT_VOLUME_RAMP 0x409

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#define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410

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#define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411

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#define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412

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#define ARIZONA_NOISE_GATE_SELECT_1L 0x413

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#define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414

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#define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415

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#define ARIZONA_DAC_VOLUME_LIMIT_1R 0x416

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#define ARIZONA_NOISE_GATE_SELECT_1R 0x417

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#define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418

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#define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419

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#define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A

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#define ARIZONA_NOISE_GATE_SELECT_2L 0x41B

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#define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C

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#define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D

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#define ARIZONA_DAC_VOLUME_LIMIT_2R 0x41E

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#define ARIZONA_NOISE_GATE_SELECT_2R 0x41F

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#define ARIZONA_OUTPUT_PATH_CONFIG_3L 0x420

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#define ARIZONA_DAC_DIGITAL_VOLUME_3L 0x421

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#define ARIZONA_DAC_VOLUME_LIMIT_3L 0x422

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#define ARIZONA_NOISE_GATE_SELECT_3L 0x423

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#define ARIZONA_OUTPUT_PATH_CONFIG_3R 0x424

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#define ARIZONA_DAC_DIGITAL_VOLUME_3R 0x425

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#define ARIZONA_DAC_VOLUME_LIMIT_3R 0x426

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#define ARIZONA_NOISE_GATE_SELECT_3R 0x427

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#define ARIZONA_OUTPUT_PATH_CONFIG_4L 0x428

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#define ARIZONA_DAC_DIGITAL_VOLUME_4L 0x429

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#define ARIZONA_OUT_VOLUME_4L 0x42A

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#define ARIZONA_NOISE_GATE_SELECT_4L 0x42B

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#define ARIZONA_OUTPUT_PATH_CONFIG_4R 0x42C

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#define ARIZONA_DAC_DIGITAL_VOLUME_4R 0x42D

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#define ARIZONA_OUT_VOLUME_4R 0x42E

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#define ARIZONA_NOISE_GATE_SELECT_4R 0x42F

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#define ARIZONA_OUTPUT_PATH_CONFIG_5L 0x430

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#define ARIZONA_DAC_DIGITAL_VOLUME_5L 0x431

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#define ARIZONA_DAC_VOLUME_LIMIT_5L 0x432

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#define ARIZONA_NOISE_GATE_SELECT_5L 0x433

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#define ARIZONA_OUTPUT_PATH_CONFIG_5R 0x434

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#define ARIZONA_DAC_DIGITAL_VOLUME_5R 0x435

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#define ARIZONA_DAC_VOLUME_LIMIT_5R 0x436

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#define ARIZONA_NOISE_GATE_SELECT_5R 0x437

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#define ARIZONA_OUTPUT_PATH_CONFIG_6L 0x438

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#define ARIZONA_DAC_DIGITAL_VOLUME_6L 0x439

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#define ARIZONA_DAC_VOLUME_LIMIT_6L 0x43A

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#define ARIZONA_NOISE_GATE_SELECT_6L 0x43B

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#define ARIZONA_OUTPUT_PATH_CONFIG_6R 0x43C

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#define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D

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#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E

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#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F

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#define ARIZONA_DAC_AEC_CONTROL_1 0x450

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#define ARIZONA_NOISE_GATE_CONTROL 0x458

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#define ARIZONA_PDM_SPK1_CTRL_1 0x490

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#define ARIZONA_PDM_SPK1_CTRL_2 0x491

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#define ARIZONA_PDM_SPK2_CTRL_1 0x492

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#define ARIZONA_PDM_SPK2_CTRL_2 0x493

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#define ARIZONA_SPK_CTRL_2 0x4B5

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#define ARIZONA_SPK_CTRL_3 0x4B6

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#define ARIZONA_DAC_COMP_1 0x4DC

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#define ARIZONA_DAC_COMP_2 0x4DD

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#define ARIZONA_DAC_COMP_3 0x4DE

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#define ARIZONA_DAC_COMP_4 0x4DF

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#define ARIZONA_AIF1_BCLK_CTRL 0x500

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#define ARIZONA_AIF1_TX_PIN_CTRL 0x501

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#define ARIZONA_AIF1_RX_PIN_CTRL 0x502

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#define ARIZONA_AIF1_RATE_CTRL 0x503

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#define ARIZONA_AIF1_FORMAT 0x504

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#define ARIZONA_AIF1_TX_BCLK_RATE 0x505

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#define ARIZONA_AIF1_RX_BCLK_RATE 0x506

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#define ARIZONA_AIF1_FRAME_CTRL_1 0x507

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#define ARIZONA_AIF1_FRAME_CTRL_2 0x508

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#define ARIZONA_AIF1_FRAME_CTRL_3 0x509

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#define ARIZONA_AIF1_FRAME_CTRL_4 0x50A

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#define ARIZONA_AIF1_FRAME_CTRL_5 0x50B

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#define ARIZONA_AIF1_FRAME_CTRL_6 0x50C

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#define ARIZONA_AIF1_FRAME_CTRL_7 0x50D

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#define ARIZONA_AIF1_FRAME_CTRL_8 0x50E

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#define ARIZONA_AIF1_FRAME_CTRL_9 0x50F

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#define ARIZONA_AIF1_FRAME_CTRL_10 0x510

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#define ARIZONA_AIF1_FRAME_CTRL_11 0x511

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#define ARIZONA_AIF1_FRAME_CTRL_12 0x512

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#define ARIZONA_AIF1_FRAME_CTRL_13 0x513

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#define ARIZONA_AIF1_FRAME_CTRL_14 0x514

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#define ARIZONA_AIF1_FRAME_CTRL_15 0x515

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#define ARIZONA_AIF1_FRAME_CTRL_16 0x516

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#define ARIZONA_AIF1_FRAME_CTRL_17 0x517

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#define ARIZONA_AIF1_FRAME_CTRL_18 0x518

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#define ARIZONA_AIF1_TX_ENABLES 0x519

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#define ARIZONA_AIF1_RX_ENABLES 0x51A

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#define ARIZONA_AIF1_FORCE_WRITE 0x51B

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#define ARIZONA_AIF2_BCLK_CTRL 0x540

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#define ARIZONA_AIF2_TX_PIN_CTRL 0x541

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#define ARIZONA_AIF2_RX_PIN_CTRL 0x542

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#define ARIZONA_AIF2_RATE_CTRL 0x543

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#define ARIZONA_AIF2_FORMAT 0x544

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#define ARIZONA_AIF2_TX_BCLK_RATE 0x545

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#define ARIZONA_AIF2_RX_BCLK_RATE 0x546

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#define ARIZONA_AIF2_FRAME_CTRL_1 0x547

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#define ARIZONA_AIF2_FRAME_CTRL_2 0x548

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#define ARIZONA_AIF2_FRAME_CTRL_3 0x549

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#define ARIZONA_AIF2_FRAME_CTRL_4 0x54A

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#define ARIZONA_AIF2_FRAME_CTRL_11 0x551

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#define ARIZONA_AIF2_FRAME_CTRL_12 0x552

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#define ARIZONA_AIF2_TX_ENABLES 0x559

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#define ARIZONA_AIF2_RX_ENABLES 0x55A

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#define ARIZONA_AIF2_FORCE_WRITE 0x55B

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#define ARIZONA_AIF3_BCLK_CTRL 0x580

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#define ARIZONA_AIF3_TX_PIN_CTRL 0x581

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#define ARIZONA_AIF3_RX_PIN_CTRL 0x582

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#define ARIZONA_AIF3_RATE_CTRL 0x583

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#define ARIZONA_AIF3_FORMAT 0x584

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#define ARIZONA_AIF3_TX_BCLK_RATE 0x585

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#define ARIZONA_AIF3_RX_BCLK_RATE 0x586

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#define ARIZONA_AIF3_FRAME_CTRL_1 0x587

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#define ARIZONA_AIF3_FRAME_CTRL_2 0x588

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#define ARIZONA_AIF3_FRAME_CTRL_3 0x589

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#define ARIZONA_AIF3_FRAME_CTRL_4 0x58A

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#define ARIZONA_AIF3_FRAME_CTRL_11 0x591

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#define ARIZONA_AIF3_FRAME_CTRL_12 0x592

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#define ARIZONA_AIF3_TX_ENABLES 0x599

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#define ARIZONA_AIF3_RX_ENABLES 0x59A

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#define ARIZONA_AIF3_FORCE_WRITE 0x59B

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#define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3

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#define ARIZONA_SLIMBUS_RATES_1 0x5E5

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#define ARIZONA_SLIMBUS_RATES_2 0x5E6

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#define ARIZONA_SLIMBUS_RATES_3 0x5E7

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#define ARIZONA_SLIMBUS_RATES_4 0x5E8

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#define ARIZONA_SLIMBUS_RATES_5 0x5E9

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#define ARIZONA_SLIMBUS_RATES_6 0x5EA

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#define ARIZONA_SLIMBUS_RATES_7 0x5EB

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#define ARIZONA_SLIMBUS_RATES_8 0x5EC

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#define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE 0x5F5

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#define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE 0x5F6

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#define ARIZONA_SLIMBUS_RX_PORT_STATUS 0x5F7

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#define ARIZONA_SLIMBUS_TX_PORT_STATUS 0x5F8

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#define ARIZONA_PWM1MIX_INPUT_1_SOURCE 0x640

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#define ARIZONA_PWM1MIX_INPUT_1_VOLUME 0x641

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#define ARIZONA_PWM1MIX_INPUT_2_SOURCE 0x642

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#define ARIZONA_PWM1MIX_INPUT_2_VOLUME 0x643

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#define ARIZONA_PWM1MIX_INPUT_3_SOURCE 0x644

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#define ARIZONA_PWM1MIX_INPUT_3_VOLUME 0x645

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#define ARIZONA_PWM1MIX_INPUT_4_SOURCE 0x646

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#define ARIZONA_PWM1MIX_INPUT_4_VOLUME 0x647

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#define ARIZONA_PWM2MIX_INPUT_1_SOURCE 0x648

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#define ARIZONA_PWM2MIX_INPUT_1_VOLUME 0x649

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#define ARIZONA_PWM2MIX_INPUT_2_SOURCE 0x64A

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#define ARIZONA_PWM2MIX_INPUT_2_VOLUME 0x64B

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#define ARIZONA_PWM2MIX_INPUT_3_SOURCE 0x64C

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#define ARIZONA_PWM2MIX_INPUT_3_VOLUME 0x64D

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#define ARIZONA_PWM2MIX_INPUT_4_SOURCE 0x64E

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#define ARIZONA_PWM2MIX_INPUT_4_VOLUME 0x64F

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#define ARIZONA_MICMIX_INPUT_1_SOURCE 0x660

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#define ARIZONA_MICMIX_INPUT_1_VOLUME 0x661

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#define ARIZONA_MICMIX_INPUT_2_SOURCE 0x662

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#define ARIZONA_MICMIX_INPUT_2_VOLUME 0x663

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#define ARIZONA_MICMIX_INPUT_3_SOURCE 0x664

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#define ARIZONA_MICMIX_INPUT_3_VOLUME 0x665

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#define ARIZONA_MICMIX_INPUT_4_SOURCE 0x666

322

#define ARIZONA_MICMIX_INPUT_4_VOLUME 0x667

323

#define ARIZONA_NOISEMIX_INPUT_1_SOURCE 0x668

324

#define ARIZONA_NOISEMIX_INPUT_1_VOLUME 0x669

325

#define ARIZONA_NOISEMIX_INPUT_2_SOURCE 0x66A

326

#define ARIZONA_NOISEMIX_INPUT_2_VOLUME 0x66B

327

#define ARIZONA_NOISEMIX_INPUT_3_SOURCE 0x66C

328

#define ARIZONA_NOISEMIX_INPUT_3_VOLUME 0x66D

329

#define ARIZONA_NOISEMIX_INPUT_4_SOURCE 0x66E

330

#define ARIZONA_NOISEMIX_INPUT_4_VOLUME 0x66F

331

#define ARIZONA_OUT1LMIX_INPUT_1_SOURCE 0x680

332

#define ARIZONA_OUT1LMIX_INPUT_1_VOLUME 0x681

333

#define ARIZONA_OUT1LMIX_INPUT_2_SOURCE 0x682

334

#define ARIZONA_OUT1LMIX_INPUT_2_VOLUME 0x683

335

#define ARIZONA_OUT1LMIX_INPUT_3_SOURCE 0x684

336

#define ARIZONA_OUT1LMIX_INPUT_3_VOLUME 0x685

337

#define ARIZONA_OUT1LMIX_INPUT_4_SOURCE 0x686

338

#define ARIZONA_OUT1LMIX_INPUT_4_VOLUME 0x687

339

#define ARIZONA_OUT1RMIX_INPUT_1_SOURCE 0x688

340

#define ARIZONA_OUT1RMIX_INPUT_1_VOLUME 0x689

341

#define ARIZONA_OUT1RMIX_INPUT_2_SOURCE 0x68A

342

#define ARIZONA_OUT1RMIX_INPUT_2_VOLUME 0x68B

343

#define ARIZONA_OUT1RMIX_INPUT_3_SOURCE 0x68C

344

#define ARIZONA_OUT1RMIX_INPUT_3_VOLUME 0x68D

345

#define ARIZONA_OUT1RMIX_INPUT_4_SOURCE 0x68E

346

#define ARIZONA_OUT1RMIX_INPUT_4_VOLUME 0x68F

347

#define ARIZONA_OUT2LMIX_INPUT_1_SOURCE 0x690

348

#define ARIZONA_OUT2LMIX_INPUT_1_VOLUME 0x691

349

#define ARIZONA_OUT2LMIX_INPUT_2_SOURCE 0x692

350

#define ARIZONA_OUT2LMIX_INPUT_2_VOLUME 0x693

351

#define ARIZONA_OUT2LMIX_INPUT_3_SOURCE 0x694

352

#define ARIZONA_OUT2LMIX_INPUT_3_VOLUME 0x695

353

#define ARIZONA_OUT2LMIX_INPUT_4_SOURCE 0x696

354

#define ARIZONA_OUT2LMIX_INPUT_4_VOLUME 0x697

355

#define ARIZONA_OUT2RMIX_INPUT_1_SOURCE 0x698

356

#define ARIZONA_OUT2RMIX_INPUT_1_VOLUME 0x699

357

#define ARIZONA_OUT2RMIX_INPUT_2_SOURCE 0x69A

358

#define ARIZONA_OUT2RMIX_INPUT_2_VOLUME 0x69B

359

#define ARIZONA_OUT2RMIX_INPUT_3_SOURCE 0x69C

360

#define ARIZONA_OUT2RMIX_INPUT_3_VOLUME 0x69D

361

#define ARIZONA_OUT2RMIX_INPUT_4_SOURCE 0x69E

362

#define ARIZONA_OUT2RMIX_INPUT_4_VOLUME 0x69F

363

#define ARIZONA_OUT3LMIX_INPUT_1_SOURCE 0x6A0

364

#define ARIZONA_OUT3LMIX_INPUT_1_VOLUME 0x6A1

365

#define ARIZONA_OUT3LMIX_INPUT_2_SOURCE 0x6A2

366

#define ARIZONA_OUT3LMIX_INPUT_2_VOLUME 0x6A3

367

#define ARIZONA_OUT3LMIX_INPUT_3_SOURCE 0x6A4

368

#define ARIZONA_OUT3LMIX_INPUT_3_VOLUME 0x6A5

369

#define ARIZONA_OUT3LMIX_INPUT_4_SOURCE 0x6A6

370

#define ARIZONA_OUT3LMIX_INPUT_4_VOLUME 0x6A7

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2012-07-05 20:35:28 +0100

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371

#define ARIZONA_OUT3RMIX_INPUT_1_SOURCE 0x6A8

372

#define ARIZONA_OUT3RMIX_INPUT_1_VOLUME 0x6A9

373

#define ARIZONA_OUT3RMIX_INPUT_2_SOURCE 0x6AA

374

#define ARIZONA_OUT3RMIX_INPUT_2_VOLUME 0x6AB

375

#define ARIZONA_OUT3RMIX_INPUT_3_SOURCE 0x6AC

376

#define ARIZONA_OUT3RMIX_INPUT_3_VOLUME 0x6AD

377

#define ARIZONA_OUT3RMIX_INPUT_4_SOURCE 0x6AE

378

#define ARIZONA_OUT3RMIX_INPUT_4_VOLUME 0x6AF

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2012-06-19 16:28:40 +0100

[diff] [blame]

379

#define ARIZONA_OUT4LMIX_INPUT_1_SOURCE 0x6B0

380

#define ARIZONA_OUT4LMIX_INPUT_1_VOLUME 0x6B1

381

#define ARIZONA_OUT4LMIX_INPUT_2_SOURCE 0x6B2

382

#define ARIZONA_OUT4LMIX_INPUT_2_VOLUME 0x6B3

383

#define ARIZONA_OUT4LMIX_INPUT_3_SOURCE 0x6B4

384

#define ARIZONA_OUT4LMIX_INPUT_3_VOLUME 0x6B5

385

#define ARIZONA_OUT4LMIX_INPUT_4_SOURCE 0x6B6

386

#define ARIZONA_OUT4LMIX_INPUT_4_VOLUME 0x6B7

387

#define ARIZONA_OUT4RMIX_INPUT_1_SOURCE 0x6B8

388

#define ARIZONA_OUT4RMIX_INPUT_1_VOLUME 0x6B9

389

#define ARIZONA_OUT4RMIX_INPUT_2_SOURCE 0x6BA

390

#define ARIZONA_OUT4RMIX_INPUT_2_VOLUME 0x6BB

391

#define ARIZONA_OUT4RMIX_INPUT_3_SOURCE 0x6BC

392

#define ARIZONA_OUT4RMIX_INPUT_3_VOLUME 0x6BD

393

#define ARIZONA_OUT4RMIX_INPUT_4_SOURCE 0x6BE

394

#define ARIZONA_OUT4RMIX_INPUT_4_VOLUME 0x6BF

395

#define ARIZONA_OUT5LMIX_INPUT_1_SOURCE 0x6C0

396

#define ARIZONA_OUT5LMIX_INPUT_1_VOLUME 0x6C1

397

#define ARIZONA_OUT5LMIX_INPUT_2_SOURCE 0x6C2

398

#define ARIZONA_OUT5LMIX_INPUT_2_VOLUME 0x6C3

399

#define ARIZONA_OUT5LMIX_INPUT_3_SOURCE 0x6C4

400

#define ARIZONA_OUT5LMIX_INPUT_3_VOLUME 0x6C5

401

#define ARIZONA_OUT5LMIX_INPUT_4_SOURCE 0x6C6

402

#define ARIZONA_OUT5LMIX_INPUT_4_VOLUME 0x6C7

403

#define ARIZONA_OUT5RMIX_INPUT_1_SOURCE 0x6C8

404

#define ARIZONA_OUT5RMIX_INPUT_1_VOLUME 0x6C9

405

#define ARIZONA_OUT5RMIX_INPUT_2_SOURCE 0x6CA

406

#define ARIZONA_OUT5RMIX_INPUT_2_VOLUME 0x6CB

407

#define ARIZONA_OUT5RMIX_INPUT_3_SOURCE 0x6CC

408

#define ARIZONA_OUT5RMIX_INPUT_3_VOLUME 0x6CD

409

#define ARIZONA_OUT5RMIX_INPUT_4_SOURCE 0x6CE

410

#define ARIZONA_OUT5RMIX_INPUT_4_VOLUME 0x6CF

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

411

#define ARIZONA_OUT6LMIX_INPUT_1_SOURCE 0x6D0

412

#define ARIZONA_OUT6LMIX_INPUT_1_VOLUME 0x6D1

413

#define ARIZONA_OUT6LMIX_INPUT_2_SOURCE 0x6D2

414

#define ARIZONA_OUT6LMIX_INPUT_2_VOLUME 0x6D3

415

#define ARIZONA_OUT6LMIX_INPUT_3_SOURCE 0x6D4

416

#define ARIZONA_OUT6LMIX_INPUT_3_VOLUME 0x6D5

417

#define ARIZONA_OUT6LMIX_INPUT_4_SOURCE 0x6D6

418

#define ARIZONA_OUT6LMIX_INPUT_4_VOLUME 0x6D7

419

#define ARIZONA_OUT6RMIX_INPUT_1_SOURCE 0x6D8

420

#define ARIZONA_OUT6RMIX_INPUT_1_VOLUME 0x6D9

421

#define ARIZONA_OUT6RMIX_INPUT_2_SOURCE 0x6DA

422

#define ARIZONA_OUT6RMIX_INPUT_2_VOLUME 0x6DB

423

#define ARIZONA_OUT6RMIX_INPUT_3_SOURCE 0x6DC

424

#define ARIZONA_OUT6RMIX_INPUT_3_VOLUME 0x6DD

425

#define ARIZONA_OUT6RMIX_INPUT_4_SOURCE 0x6DE

426

#define ARIZONA_OUT6RMIX_INPUT_4_VOLUME 0x6DF

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

427

#define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE 0x700

428

#define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME 0x701

429

#define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE 0x702

430

#define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME 0x703

431

#define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE 0x704

432

#define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME 0x705

433

#define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE 0x706

434

#define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME 0x707

435

#define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE 0x708

436

#define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME 0x709

437

#define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE 0x70A

438

#define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME 0x70B

439

#define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE 0x70C

440

#define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME 0x70D

441

#define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE 0x70E

442

#define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME 0x70F

443

#define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE 0x710

444

#define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME 0x711

445

#define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE 0x712

446

#define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME 0x713

447

#define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE 0x714

448

#define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME 0x715

449

#define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE 0x716

450

#define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME 0x717

451

#define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE 0x718

452

#define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME 0x719

453

#define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE 0x71A

454

#define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME 0x71B

455

#define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE 0x71C

456

#define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME 0x71D

457

#define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE 0x71E

458

#define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME 0x71F

459

#define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE 0x720

460

#define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME 0x721

461

#define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE 0x722

462

#define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME 0x723

463

#define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE 0x724

464

#define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME 0x725

465

#define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE 0x726

466

#define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME 0x727

467

#define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE 0x728

468

#define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME 0x729

469

#define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE 0x72A

470

#define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME 0x72B

471

#define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE 0x72C

472

#define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME 0x72D

473

#define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE 0x72E

474

#define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME 0x72F

475

#define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE 0x730

476

#define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME 0x731

477

#define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE 0x732

478

#define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME 0x733

479

#define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE 0x734

480

#define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME 0x735

481

#define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE 0x736

482

#define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME 0x737

483

#define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE 0x738

484

#define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME 0x739

485

#define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE 0x73A

486

#define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME 0x73B

487

#define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE 0x73C

488

#define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME 0x73D

489

#define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE 0x73E

490

#define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME 0x73F

491

#define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE 0x740

492

#define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME 0x741

493

#define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE 0x742

494

#define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME 0x743

495

#define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE 0x744

496

#define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME 0x745

497

#define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE 0x746

498

#define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME 0x747

499

#define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE 0x748

500

#define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME 0x749

501

#define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE 0x74A

502

#define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME 0x74B

503

#define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE 0x74C

504

#define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D

505

#define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E

506

#define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F

507

#define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780

508

#define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781

509

#define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782

510

#define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME 0x783

511

#define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE 0x784

512

#define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME 0x785

513

#define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE 0x786

514

#define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME 0x787

515

#define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE 0x788

516

#define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME 0x789

517

#define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE 0x78A

518

#define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME 0x78B

519

#define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE 0x78C

520

#define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D

521

#define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E

522

#define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F

523

#define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0

524

#define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1

525

#define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2

526

#define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME 0x7C3

527

#define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE 0x7C4

528

#define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME 0x7C5

529

#define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE 0x7C6

530

#define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME 0x7C7

531

#define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE 0x7C8

532

#define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME 0x7C9

533

#define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE 0x7CA

534

#define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME 0x7CB

535

#define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE 0x7CC

536

#define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME 0x7CD

537

#define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE 0x7CE

538

#define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME 0x7CF

539

#define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE 0x7D0

540

#define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME 0x7D1

541

#define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE 0x7D2

542

#define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME 0x7D3

543

#define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE 0x7D4

544

#define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME 0x7D5

545

#define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE 0x7D6

546

#define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME 0x7D7

547

#define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE 0x7D8

548

#define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME 0x7D9

549

#define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE 0x7DA

550

#define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME 0x7DB

551

#define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE 0x7DC

552

#define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME 0x7DD

553

#define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE 0x7DE

554

#define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME 0x7DF

555

#define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE 0x7E0

556

#define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME 0x7E1

557

#define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE 0x7E2

558

#define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME 0x7E3

559

#define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE 0x7E4

560

#define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME 0x7E5

561

#define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE 0x7E6

562

#define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME 0x7E7

563

#define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE 0x7E8

564

#define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME 0x7E9

565

#define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE 0x7EA

566

#define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME 0x7EB

567

#define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE 0x7EC

568

#define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME 0x7ED

569

#define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE 0x7EE

570

#define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME 0x7EF

571

#define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE 0x7F0

572

#define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME 0x7F1

573

#define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE 0x7F2

574

#define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME 0x7F3

575

#define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE 0x7F4

576

#define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME 0x7F5

577

#define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE 0x7F6

578

#define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME 0x7F7

579

#define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE 0x7F8

580

#define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME 0x7F9

581

#define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE 0x7FA

582

#define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME 0x7FB

583

#define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE 0x7FC

584

#define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD

585

#define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE

586

#define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF

587

#define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880

588

#define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881

589

#define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882

590

#define ARIZONA_EQ1MIX_INPUT_2_VOLUME 0x883

591

#define ARIZONA_EQ1MIX_INPUT_3_SOURCE 0x884

592

#define ARIZONA_EQ1MIX_INPUT_3_VOLUME 0x885

593

#define ARIZONA_EQ1MIX_INPUT_4_SOURCE 0x886

594

#define ARIZONA_EQ1MIX_INPUT_4_VOLUME 0x887

595

#define ARIZONA_EQ2MIX_INPUT_1_SOURCE 0x888

596

#define ARIZONA_EQ2MIX_INPUT_1_VOLUME 0x889

597

#define ARIZONA_EQ2MIX_INPUT_2_SOURCE 0x88A

598

#define ARIZONA_EQ2MIX_INPUT_2_VOLUME 0x88B

599

#define ARIZONA_EQ2MIX_INPUT_3_SOURCE 0x88C

600

#define ARIZONA_EQ2MIX_INPUT_3_VOLUME 0x88D

601

#define ARIZONA_EQ2MIX_INPUT_4_SOURCE 0x88E

602

#define ARIZONA_EQ2MIX_INPUT_4_VOLUME 0x88F

603

#define ARIZONA_EQ3MIX_INPUT_1_SOURCE 0x890

604

#define ARIZONA_EQ3MIX_INPUT_1_VOLUME 0x891

605

#define ARIZONA_EQ3MIX_INPUT_2_SOURCE 0x892

606

#define ARIZONA_EQ3MIX_INPUT_2_VOLUME 0x893

607

#define ARIZONA_EQ3MIX_INPUT_3_SOURCE 0x894

608

#define ARIZONA_EQ3MIX_INPUT_3_VOLUME 0x895

609

#define ARIZONA_EQ3MIX_INPUT_4_SOURCE 0x896

610

#define ARIZONA_EQ3MIX_INPUT_4_VOLUME 0x897

611

#define ARIZONA_EQ4MIX_INPUT_1_SOURCE 0x898

612

#define ARIZONA_EQ4MIX_INPUT_1_VOLUME 0x899

613

#define ARIZONA_EQ4MIX_INPUT_2_SOURCE 0x89A

614

#define ARIZONA_EQ4MIX_INPUT_2_VOLUME 0x89B

615

#define ARIZONA_EQ4MIX_INPUT_3_SOURCE 0x89C

616

#define ARIZONA_EQ4MIX_INPUT_3_VOLUME 0x89D

617

#define ARIZONA_EQ4MIX_INPUT_4_SOURCE 0x89E

618

#define ARIZONA_EQ4MIX_INPUT_4_VOLUME 0x89F

619

#define ARIZONA_DRC1LMIX_INPUT_1_SOURCE 0x8C0

620

#define ARIZONA_DRC1LMIX_INPUT_1_VOLUME 0x8C1

621

#define ARIZONA_DRC1LMIX_INPUT_2_SOURCE 0x8C2

622

#define ARIZONA_DRC1LMIX_INPUT_2_VOLUME 0x8C3

623

#define ARIZONA_DRC1LMIX_INPUT_3_SOURCE 0x8C4

624

#define ARIZONA_DRC1LMIX_INPUT_3_VOLUME 0x8C5

625

#define ARIZONA_DRC1LMIX_INPUT_4_SOURCE 0x8C6

626

#define ARIZONA_DRC1LMIX_INPUT_4_VOLUME 0x8C7

627

#define ARIZONA_DRC1RMIX_INPUT_1_SOURCE 0x8C8

628

#define ARIZONA_DRC1RMIX_INPUT_1_VOLUME 0x8C9

629

#define ARIZONA_DRC1RMIX_INPUT_2_SOURCE 0x8CA

630

#define ARIZONA_DRC1RMIX_INPUT_2_VOLUME 0x8CB

631

#define ARIZONA_DRC1RMIX_INPUT_3_SOURCE 0x8CC

632

#define ARIZONA_DRC1RMIX_INPUT_3_VOLUME 0x8CD

633

#define ARIZONA_DRC1RMIX_INPUT_4_SOURCE 0x8CE

634

#define ARIZONA_DRC1RMIX_INPUT_4_VOLUME 0x8CF

635

#define ARIZONA_DRC2LMIX_INPUT_1_SOURCE 0x8D0

636

#define ARIZONA_DRC2LMIX_INPUT_1_VOLUME 0x8D1

637

#define ARIZONA_DRC2LMIX_INPUT_2_SOURCE 0x8D2

638

#define ARIZONA_DRC2LMIX_INPUT_2_VOLUME 0x8D3

639

#define ARIZONA_DRC2LMIX_INPUT_3_SOURCE 0x8D4

640

#define ARIZONA_DRC2LMIX_INPUT_3_VOLUME 0x8D5

641

#define ARIZONA_DRC2LMIX_INPUT_4_SOURCE 0x8D6

642

#define ARIZONA_DRC2LMIX_INPUT_4_VOLUME 0x8D7

643

#define ARIZONA_DRC2RMIX_INPUT_1_SOURCE 0x8D8

644

#define ARIZONA_DRC2RMIX_INPUT_1_VOLUME 0x8D9

645

#define ARIZONA_DRC2RMIX_INPUT_2_SOURCE 0x8DA

646

#define ARIZONA_DRC2RMIX_INPUT_2_VOLUME 0x8DB

647

#define ARIZONA_DRC2RMIX_INPUT_3_SOURCE 0x8DC

648

#define ARIZONA_DRC2RMIX_INPUT_3_VOLUME 0x8DD

649

#define ARIZONA_DRC2RMIX_INPUT_4_SOURCE 0x8DE

650

#define ARIZONA_DRC2RMIX_INPUT_4_VOLUME 0x8DF

651

#define ARIZONA_HPLP1MIX_INPUT_1_SOURCE 0x900

652

#define ARIZONA_HPLP1MIX_INPUT_1_VOLUME 0x901

653

#define ARIZONA_HPLP1MIX_INPUT_2_SOURCE 0x902

654

#define ARIZONA_HPLP1MIX_INPUT_2_VOLUME 0x903

655

#define ARIZONA_HPLP1MIX_INPUT_3_SOURCE 0x904

656

#define ARIZONA_HPLP1MIX_INPUT_3_VOLUME 0x905

657

#define ARIZONA_HPLP1MIX_INPUT_4_SOURCE 0x906

658

#define ARIZONA_HPLP1MIX_INPUT_4_VOLUME 0x907

659

#define ARIZONA_HPLP2MIX_INPUT_1_SOURCE 0x908

660

#define ARIZONA_HPLP2MIX_INPUT_1_VOLUME 0x909

661

#define ARIZONA_HPLP2MIX_INPUT_2_SOURCE 0x90A

662

#define ARIZONA_HPLP2MIX_INPUT_2_VOLUME 0x90B

663

#define ARIZONA_HPLP2MIX_INPUT_3_SOURCE 0x90C

664

#define ARIZONA_HPLP2MIX_INPUT_3_VOLUME 0x90D

665

#define ARIZONA_HPLP2MIX_INPUT_4_SOURCE 0x90E

666

#define ARIZONA_HPLP2MIX_INPUT_4_VOLUME 0x90F

667

#define ARIZONA_HPLP3MIX_INPUT_1_SOURCE 0x910

668

#define ARIZONA_HPLP3MIX_INPUT_1_VOLUME 0x911

669

#define ARIZONA_HPLP3MIX_INPUT_2_SOURCE 0x912

670

#define ARIZONA_HPLP3MIX_INPUT_2_VOLUME 0x913

671

#define ARIZONA_HPLP3MIX_INPUT_3_SOURCE 0x914

672

#define ARIZONA_HPLP3MIX_INPUT_3_VOLUME 0x915

673

#define ARIZONA_HPLP3MIX_INPUT_4_SOURCE 0x916

674

#define ARIZONA_HPLP3MIX_INPUT_4_VOLUME 0x917

675

#define ARIZONA_HPLP4MIX_INPUT_1_SOURCE 0x918

676

#define ARIZONA_HPLP4MIX_INPUT_1_VOLUME 0x919

677

#define ARIZONA_HPLP4MIX_INPUT_2_SOURCE 0x91A

678

#define ARIZONA_HPLP4MIX_INPUT_2_VOLUME 0x91B

679

#define ARIZONA_HPLP4MIX_INPUT_3_SOURCE 0x91C

680

#define ARIZONA_HPLP4MIX_INPUT_3_VOLUME 0x91D

681

#define ARIZONA_HPLP4MIX_INPUT_4_SOURCE 0x91E

682

#define ARIZONA_HPLP4MIX_INPUT_4_VOLUME 0x91F

683

#define ARIZONA_DSP1LMIX_INPUT_1_SOURCE 0x940

684

#define ARIZONA_DSP1LMIX_INPUT_1_VOLUME 0x941

685

#define ARIZONA_DSP1LMIX_INPUT_2_SOURCE 0x942

686

#define ARIZONA_DSP1LMIX_INPUT_2_VOLUME 0x943

687

#define ARIZONA_DSP1LMIX_INPUT_3_SOURCE 0x944

688

#define ARIZONA_DSP1LMIX_INPUT_3_VOLUME 0x945

689

#define ARIZONA_DSP1LMIX_INPUT_4_SOURCE 0x946

690

#define ARIZONA_DSP1LMIX_INPUT_4_VOLUME 0x947

691

#define ARIZONA_DSP1RMIX_INPUT_1_SOURCE 0x948

692

#define ARIZONA_DSP1RMIX_INPUT_1_VOLUME 0x949

693

#define ARIZONA_DSP1RMIX_INPUT_2_SOURCE 0x94A

694

#define ARIZONA_DSP1RMIX_INPUT_2_VOLUME 0x94B

695

#define ARIZONA_DSP1RMIX_INPUT_3_SOURCE 0x94C

696

#define ARIZONA_DSP1RMIX_INPUT_3_VOLUME 0x94D

697

#define ARIZONA_DSP1RMIX_INPUT_4_SOURCE 0x94E

698

#define ARIZONA_DSP1RMIX_INPUT_4_VOLUME 0x94F

699

#define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE 0x950

700

#define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE 0x958

701

#define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE 0x960

702

#define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE 0x968

703

#define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE 0x970

704

#define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE 0x978

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

705

#define ARIZONA_DSP2LMIX_INPUT_1_SOURCE 0x980

706

#define ARIZONA_DSP2LMIX_INPUT_1_VOLUME 0x981

707

#define ARIZONA_DSP2LMIX_INPUT_2_SOURCE 0x982

708

#define ARIZONA_DSP2LMIX_INPUT_2_VOLUME 0x983

709

#define ARIZONA_DSP2LMIX_INPUT_3_SOURCE 0x984

710

#define ARIZONA_DSP2LMIX_INPUT_3_VOLUME 0x985

711

#define ARIZONA_DSP2LMIX_INPUT_4_SOURCE 0x986

712

#define ARIZONA_DSP2LMIX_INPUT_4_VOLUME 0x987

713

#define ARIZONA_DSP2RMIX_INPUT_1_SOURCE 0x988

714

#define ARIZONA_DSP2RMIX_INPUT_1_VOLUME 0x989

715

#define ARIZONA_DSP2RMIX_INPUT_2_SOURCE 0x98A

716

#define ARIZONA_DSP2RMIX_INPUT_2_VOLUME 0x98B

717

#define ARIZONA_DSP2RMIX_INPUT_3_SOURCE 0x98C

718

#define ARIZONA_DSP2RMIX_INPUT_3_VOLUME 0x98D

719

#define ARIZONA_DSP2RMIX_INPUT_4_SOURCE 0x98E

720

#define ARIZONA_DSP2RMIX_INPUT_4_VOLUME 0x98F

721

#define ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE 0x990

722

#define ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE 0x998

723

#define ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0

724

#define ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8

725

#define ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0

726

#define ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8

727

#define ARIZONA_DSP3LMIX_INPUT_1_SOURCE 0x9C0

728

#define ARIZONA_DSP3LMIX_INPUT_1_VOLUME 0x9C1

729

#define ARIZONA_DSP3LMIX_INPUT_2_SOURCE 0x9C2

730

#define ARIZONA_DSP3LMIX_INPUT_2_VOLUME 0x9C3

731

#define ARIZONA_DSP3LMIX_INPUT_3_SOURCE 0x9C4

732

#define ARIZONA_DSP3LMIX_INPUT_3_VOLUME 0x9C5

733

#define ARIZONA_DSP3LMIX_INPUT_4_SOURCE 0x9C6

734

#define ARIZONA_DSP3LMIX_INPUT_4_VOLUME 0x9C7

735

#define ARIZONA_DSP3RMIX_INPUT_1_SOURCE 0x9C8

736

#define ARIZONA_DSP3RMIX_INPUT_1_VOLUME 0x9C9

737

#define ARIZONA_DSP3RMIX_INPUT_2_SOURCE 0x9CA

738

#define ARIZONA_DSP3RMIX_INPUT_2_VOLUME 0x9CB

739

#define ARIZONA_DSP3RMIX_INPUT_3_SOURCE 0x9CC

740

#define ARIZONA_DSP3RMIX_INPUT_3_VOLUME 0x9CD

741

#define ARIZONA_DSP3RMIX_INPUT_4_SOURCE 0x9CE

742

#define ARIZONA_DSP3RMIX_INPUT_4_VOLUME 0x9CF

743

#define ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0

744

#define ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8

745

#define ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0

746

#define ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8

747

#define ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0

748

#define ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8

749

#define ARIZONA_DSP4LMIX_INPUT_1_SOURCE 0xA00

750

#define ARIZONA_DSP4LMIX_INPUT_1_VOLUME 0xA01

751

#define ARIZONA_DSP4LMIX_INPUT_2_SOURCE 0xA02

752

#define ARIZONA_DSP4LMIX_INPUT_2_VOLUME 0xA03

753

#define ARIZONA_DSP4LMIX_INPUT_3_SOURCE 0xA04

754

#define ARIZONA_DSP4LMIX_INPUT_3_VOLUME 0xA05

755

#define ARIZONA_DSP4LMIX_INPUT_4_SOURCE 0xA06

756

#define ARIZONA_DSP4LMIX_INPUT_4_VOLUME 0xA07

757

#define ARIZONA_DSP4RMIX_INPUT_1_SOURCE 0xA08

758

#define ARIZONA_DSP4RMIX_INPUT_1_VOLUME 0xA09

759

#define ARIZONA_DSP4RMIX_INPUT_2_SOURCE 0xA0A

760

#define ARIZONA_DSP4RMIX_INPUT_2_VOLUME 0xA0B

761

#define ARIZONA_DSP4RMIX_INPUT_3_SOURCE 0xA0C

762

#define ARIZONA_DSP4RMIX_INPUT_3_VOLUME 0xA0D

763

#define ARIZONA_DSP4RMIX_INPUT_4_SOURCE 0xA0E

764

#define ARIZONA_DSP4RMIX_INPUT_4_VOLUME 0xA0F

765

#define ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE 0xA10

766

#define ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE 0xA18

767

#define ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE 0xA20

768

#define ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE 0xA28

769

#define ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE 0xA30

770

#define ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE 0xA38

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

771

#define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80

772

#define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88

773

#define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90

774

#define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98

775

#define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00

776

#define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

777

#define ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10

778

#define ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

779

#define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20

780

#define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

781

#define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30

782

#define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

783

#define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40

784

#define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48

785

#define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60

786

#define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

787

#define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30

788

#define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38

789

#define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40

790

#define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48

791

#define ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50

792

#define ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58

793

#define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60

794

#define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68

795

#define ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70

796

#define ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78

797

#define ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE 0xB80

798

#define ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE 0xB88

799

#define ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE 0xB90

800

#define ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE 0xB98

801

#define ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE 0xBA0

802

#define ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE 0xBA8

803

#define ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE 0xBB0

804

#define ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE 0xBB8

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

805

#define ARIZONA_GPIO1_CTRL 0xC00

806

#define ARIZONA_GPIO2_CTRL 0xC01

807

#define ARIZONA_GPIO3_CTRL 0xC02

808

#define ARIZONA_GPIO4_CTRL 0xC03

809

#define ARIZONA_GPIO5_CTRL 0xC04

810

#define ARIZONA_IRQ_CTRL_1 0xC0F

811

#define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10

812

#define ARIZONA_MISC_PAD_CTRL_1 0xC20

813

#define ARIZONA_MISC_PAD_CTRL_2 0xC21

814

#define ARIZONA_MISC_PAD_CTRL_3 0xC22

815

#define ARIZONA_MISC_PAD_CTRL_4 0xC23

816

#define ARIZONA_MISC_PAD_CTRL_5 0xC24

817

#define ARIZONA_MISC_PAD_CTRL_6 0xC25

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

818

#define ARIZONA_MISC_PAD_CTRL_7 0xC30

819

#define ARIZONA_MISC_PAD_CTRL_8 0xC31

820

#define ARIZONA_MISC_PAD_CTRL_9 0xC32

821

#define ARIZONA_MISC_PAD_CTRL_10 0xC33

822

#define ARIZONA_MISC_PAD_CTRL_11 0xC34

823

#define ARIZONA_MISC_PAD_CTRL_12 0xC35

824

#define ARIZONA_MISC_PAD_CTRL_13 0xC36

825

#define ARIZONA_MISC_PAD_CTRL_14 0xC37

826

#define ARIZONA_MISC_PAD_CTRL_15 0xC38

827

#define ARIZONA_MISC_PAD_CTRL_16 0xC39

828

#define ARIZONA_MISC_PAD_CTRL_17 0xC3A

829

#define ARIZONA_MISC_PAD_CTRL_18 0xC3B

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

830

#define ARIZONA_INTERRUPT_STATUS_1 0xD00

831

#define ARIZONA_INTERRUPT_STATUS_2 0xD01

832

#define ARIZONA_INTERRUPT_STATUS_3 0xD02

833

#define ARIZONA_INTERRUPT_STATUS_4 0xD03

834

#define ARIZONA_INTERRUPT_STATUS_5 0xD04

835

#define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08

836

#define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09

837

#define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A

838

#define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B

839

#define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C

840

#define ARIZONA_INTERRUPT_CONTROL 0xD0F

841

#define ARIZONA_IRQ2_STATUS_1 0xD10

842

#define ARIZONA_IRQ2_STATUS_2 0xD11

843

#define ARIZONA_IRQ2_STATUS_3 0xD12

844

#define ARIZONA_IRQ2_STATUS_4 0xD13

845

#define ARIZONA_IRQ2_STATUS_5 0xD14

846

#define ARIZONA_IRQ2_STATUS_1_MASK 0xD18

847

#define ARIZONA_IRQ2_STATUS_2_MASK 0xD19

848

#define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A

849

#define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B

850

#define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C

851

#define ARIZONA_IRQ2_CONTROL 0xD1F

852

#define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20

853

#define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21

854

#define ARIZONA_INTERRUPT_RAW_STATUS_4 0xD22

855

#define ARIZONA_INTERRUPT_RAW_STATUS_5 0xD23

856

#define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24

857

#define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25

858

#define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26

859

#define ARIZONA_IRQ_PIN_STATUS 0xD40

860

#define ARIZONA_ADSP2_IRQ0 0xD41

861

#define ARIZONA_AOD_WKUP_AND_TRIG 0xD50

862

#define ARIZONA_AOD_IRQ1 0xD51

863

#define ARIZONA_AOD_IRQ2 0xD52

864

#define ARIZONA_AOD_IRQ_MASK_IRQ1 0xD53

865

#define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54

866

#define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55

867

#define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56

868

#define ARIZONA_FX_CTRL1 0xE00

869

#define ARIZONA_FX_CTRL2 0xE01

870

#define ARIZONA_EQ1_1 0xE10

871

#define ARIZONA_EQ1_2 0xE11

872

#define ARIZONA_EQ1_3 0xE12

873

#define ARIZONA_EQ1_4 0xE13

874

#define ARIZONA_EQ1_5 0xE14

875

#define ARIZONA_EQ1_6 0xE15

876

#define ARIZONA_EQ1_7 0xE16

877

#define ARIZONA_EQ1_8 0xE17

878

#define ARIZONA_EQ1_9 0xE18

879

#define ARIZONA_EQ1_10 0xE19

880

#define ARIZONA_EQ1_11 0xE1A

881

#define ARIZONA_EQ1_12 0xE1B

882

#define ARIZONA_EQ1_13 0xE1C

883

#define ARIZONA_EQ1_14 0xE1D

884

#define ARIZONA_EQ1_15 0xE1E

885

#define ARIZONA_EQ1_16 0xE1F

886

#define ARIZONA_EQ1_17 0xE20

887

#define ARIZONA_EQ1_18 0xE21

888

#define ARIZONA_EQ1_19 0xE22

889

#define ARIZONA_EQ1_20 0xE23

890

#define ARIZONA_EQ1_21 0xE24

891

#define ARIZONA_EQ2_1 0xE26

892

#define ARIZONA_EQ2_2 0xE27

893

#define ARIZONA_EQ2_3 0xE28

894

#define ARIZONA_EQ2_4 0xE29

895

#define ARIZONA_EQ2_5 0xE2A

896

#define ARIZONA_EQ2_6 0xE2B

897

#define ARIZONA_EQ2_7 0xE2C

898

#define ARIZONA_EQ2_8 0xE2D

899

#define ARIZONA_EQ2_9 0xE2E

900

#define ARIZONA_EQ2_10 0xE2F

901

#define ARIZONA_EQ2_11 0xE30

902

#define ARIZONA_EQ2_12 0xE31

903

#define ARIZONA_EQ2_13 0xE32

904

#define ARIZONA_EQ2_14 0xE33

905

#define ARIZONA_EQ2_15 0xE34

906

#define ARIZONA_EQ2_16 0xE35

907

#define ARIZONA_EQ2_17 0xE36

908

#define ARIZONA_EQ2_18 0xE37

909

#define ARIZONA_EQ2_19 0xE38

910

#define ARIZONA_EQ2_20 0xE39

911

#define ARIZONA_EQ2_21 0xE3A

912

#define ARIZONA_EQ3_1 0xE3C

913

#define ARIZONA_EQ3_2 0xE3D

914

#define ARIZONA_EQ3_3 0xE3E

915

#define ARIZONA_EQ3_4 0xE3F

916

#define ARIZONA_EQ3_5 0xE40

917

#define ARIZONA_EQ3_6 0xE41

918

#define ARIZONA_EQ3_7 0xE42

919

#define ARIZONA_EQ3_8 0xE43

920

#define ARIZONA_EQ3_9 0xE44

921

#define ARIZONA_EQ3_10 0xE45

922

#define ARIZONA_EQ3_11 0xE46

923

#define ARIZONA_EQ3_12 0xE47

924

#define ARIZONA_EQ3_13 0xE48

925

#define ARIZONA_EQ3_14 0xE49

926

#define ARIZONA_EQ3_15 0xE4A

927

#define ARIZONA_EQ3_16 0xE4B

928

#define ARIZONA_EQ3_17 0xE4C

929

#define ARIZONA_EQ3_18 0xE4D

930

#define ARIZONA_EQ3_19 0xE4E

931

#define ARIZONA_EQ3_20 0xE4F

932

#define ARIZONA_EQ3_21 0xE50

933

#define ARIZONA_EQ4_1 0xE52

934

#define ARIZONA_EQ4_2 0xE53

935

#define ARIZONA_EQ4_3 0xE54

936

#define ARIZONA_EQ4_4 0xE55

937

#define ARIZONA_EQ4_5 0xE56

938

#define ARIZONA_EQ4_6 0xE57

939

#define ARIZONA_EQ4_7 0xE58

940

#define ARIZONA_EQ4_8 0xE59

941

#define ARIZONA_EQ4_9 0xE5A

942

#define ARIZONA_EQ4_10 0xE5B

943

#define ARIZONA_EQ4_11 0xE5C

944

#define ARIZONA_EQ4_12 0xE5D

945

#define ARIZONA_EQ4_13 0xE5E

946

#define ARIZONA_EQ4_14 0xE5F

947

#define ARIZONA_EQ4_15 0xE60

948

#define ARIZONA_EQ4_16 0xE61

949

#define ARIZONA_EQ4_17 0xE62

950

#define ARIZONA_EQ4_18 0xE63

951

#define ARIZONA_EQ4_19 0xE64

952

#define ARIZONA_EQ4_20 0xE65

953

#define ARIZONA_EQ4_21 0xE66

954

#define ARIZONA_DRC1_CTRL1 0xE80

955

#define ARIZONA_DRC1_CTRL2 0xE81

956

#define ARIZONA_DRC1_CTRL3 0xE82

957

#define ARIZONA_DRC1_CTRL4 0xE83

958

#define ARIZONA_DRC1_CTRL5 0xE84

959

#define ARIZONA_DRC2_CTRL1 0xE89

960

#define ARIZONA_DRC2_CTRL2 0xE8A

961

#define ARIZONA_DRC2_CTRL3 0xE8B

962

#define ARIZONA_DRC2_CTRL4 0xE8C

963

#define ARIZONA_DRC2_CTRL5 0xE8D

964

#define ARIZONA_HPLPF1_1 0xEC0

965

#define ARIZONA_HPLPF1_2 0xEC1

966

#define ARIZONA_HPLPF2_1 0xEC4

967

#define ARIZONA_HPLPF2_2 0xEC5

968

#define ARIZONA_HPLPF3_1 0xEC8

969

#define ARIZONA_HPLPF3_2 0xEC9

970

#define ARIZONA_HPLPF4_1 0xECC

971

#define ARIZONA_HPLPF4_2 0xECD

972

#define ARIZONA_ASRC_ENABLE 0xEE0

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

973

#define ARIZONA_ASRC_STATUS 0xEE1

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

974

#define ARIZONA_ASRC_RATE1 0xEE2

975

#define ARIZONA_ASRC_RATE2 0xEE3

976

#define ARIZONA_ISRC_1_CTRL_1 0xEF0

977

#define ARIZONA_ISRC_1_CTRL_2 0xEF1

978

#define ARIZONA_ISRC_1_CTRL_3 0xEF2

979

#define ARIZONA_ISRC_2_CTRL_1 0xEF3

980

#define ARIZONA_ISRC_2_CTRL_2 0xEF4

981

#define ARIZONA_ISRC_2_CTRL_3 0xEF5

982

#define ARIZONA_ISRC_3_CTRL_1 0xEF6

983

#define ARIZONA_ISRC_3_CTRL_2 0xEF7

984

#define ARIZONA_ISRC_3_CTRL_3 0xEF8

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

985

#define ARIZONA_CLOCK_CONTROL 0xF00

986

#define ARIZONA_ANC_SRC 0xF01

987

#define ARIZONA_DSP_STATUS 0xF02

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

988

#define ARIZONA_DSP1_CONTROL_1 0x1100

989

#define ARIZONA_DSP1_CLOCKING_1 0x1101

990

#define ARIZONA_DSP1_STATUS_1 0x1104

991

#define ARIZONA_DSP1_STATUS_2 0x1105

Mark Brown

be2f6f5

2012-12-09 15:40:30 +0100

[diff] [blame]

992

#define ARIZONA_DSP1_STATUS_3 0x1106

Mark Brown

2013-01-25 17:09:23 +0800

[diff] [blame]

993

#define ARIZONA_DSP1_SCRATCH_0 0x1140

994

#define ARIZONA_DSP1_SCRATCH_1 0x1141

995

#define ARIZONA_DSP1_SCRATCH_2 0x1142

996

#define ARIZONA_DSP1_SCRATCH_3 0x1143

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

997

#define ARIZONA_DSP2_CONTROL_1 0x1200

998

#define ARIZONA_DSP2_CLOCKING_1 0x1201

999

#define ARIZONA_DSP2_STATUS_1 0x1204

1000

#define ARIZONA_DSP2_STATUS_2 0x1205

Mark Brown

2013-01-25 17:09:23 +0800

[diff] [blame]

1001

#define ARIZONA_DSP2_SCRATCH_0 0x1240

1002

#define ARIZONA_DSP2_SCRATCH_1 0x1241

1003

#define ARIZONA_DSP2_SCRATCH_2 0x1242

1004

#define ARIZONA_DSP2_SCRATCH_3 0x1243

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

1005

#define ARIZONA_DSP3_CONTROL_1 0x1300

1006

#define ARIZONA_DSP3_CLOCKING_1 0x1301

1007

#define ARIZONA_DSP3_STATUS_1 0x1304

1008

#define ARIZONA_DSP3_STATUS_2 0x1305

Mark Brown

2013-01-25 17:09:23 +0800

[diff] [blame]

1009

#define ARIZONA_DSP3_SCRATCH_0 0x1340

1010

#define ARIZONA_DSP3_SCRATCH_1 0x1341

1011

#define ARIZONA_DSP3_SCRATCH_2 0x1342

1012

#define ARIZONA_DSP3_SCRATCH_3 0x1343

Mark Brown

2012-07-05 20:35:28 +0100

[diff] [blame]

1013

#define ARIZONA_DSP4_CONTROL_1 0x1400

1014

#define ARIZONA_DSP4_CLOCKING_1 0x1401

1015

#define ARIZONA_DSP4_STATUS_1 0x1404

1016

#define ARIZONA_DSP4_STATUS_2 0x1405

Mark Brown

2013-01-25 17:09:23 +0800

[diff] [blame]

1017

#define ARIZONA_DSP4_SCRATCH_0 0x1440

1018

#define ARIZONA_DSP4_SCRATCH_1 0x1441

1019

#define ARIZONA_DSP4_SCRATCH_2 0x1442

1020

#define ARIZONA_DSP4_SCRATCH_3 0x1443

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

/*

* Field Definitions.

*/

/*

* R0 (0x00) - software reset

1028

*/

1029

#define ARIZONA_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */

1030

#define ARIZONA_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */

1031

#define ARIZONA_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */

1032

1033

/*

1034

* R1 (0x01) - Device Revision

1035

*/

1036

#define ARIZONA_DEVICE_REVISION_MASK 0x00FF /* DEVICE_REVISION - [7:0] */

1037

#define ARIZONA_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [7:0] */

1038

#define ARIZONA_DEVICE_REVISION_WIDTH 8 /* DEVICE_REVISION - [7:0] */

1039

1040

/*

1041

* R8 (0x08) - Ctrl IF SPI CFG 1

1042

*/

1043

#define ARIZONA_SPI_CFG 0x0010 /* SPI_CFG */

1044

#define ARIZONA_SPI_CFG_MASK 0x0010 /* SPI_CFG */

1045

#define ARIZONA_SPI_CFG_SHIFT 4 /* SPI_CFG */

1046

#define ARIZONA_SPI_CFG_WIDTH 1 /* SPI_CFG */

1047

#define ARIZONA_SPI_4WIRE 0x0008 /* SPI_4WIRE */

1048

#define ARIZONA_SPI_4WIRE_MASK 0x0008 /* SPI_4WIRE */

1049

#define ARIZONA_SPI_4WIRE_SHIFT 3 /* SPI_4WIRE */

1050

#define ARIZONA_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */

1051

#define ARIZONA_SPI_AUTO_INC_MASK 0x0003 /* SPI_AUTO_INC - [1:0] */

1052

#define ARIZONA_SPI_AUTO_INC_SHIFT 0 /* SPI_AUTO_INC - [1:0] */

1053

#define ARIZONA_SPI_AUTO_INC_WIDTH 2 /* SPI_AUTO_INC - [1:0] */

1054

1055

/*

1056

* R9 (0x09) - Ctrl IF I2C1 CFG 1

1057

*/

1058

#define ARIZONA_I2C1_AUTO_INC_MASK 0x0003 /* I2C1_AUTO_INC - [1:0] */

1059

#define ARIZONA_I2C1_AUTO_INC_SHIFT 0 /* I2C1_AUTO_INC - [1:0] */

1060

#define ARIZONA_I2C1_AUTO_INC_WIDTH 2 /* I2C1_AUTO_INC - [1:0] */

1061

1062

/*

1063

* R13 (0x0D) - Ctrl IF Status 1

1064

*/

1065

#define ARIZONA_I2C1_BUSY 0x0020 /* I2C1_BUSY */

1066

#define ARIZONA_I2C1_BUSY_MASK 0x0020 /* I2C1_BUSY */

1067

#define ARIZONA_I2C1_BUSY_SHIFT 5 /* I2C1_BUSY */

1068

#define ARIZONA_I2C1_BUSY_WIDTH 1 /* I2C1_BUSY */

1069

#define ARIZONA_SPI_BUSY 0x0010 /* SPI_BUSY */

1070

#define ARIZONA_SPI_BUSY_MASK 0x0010 /* SPI_BUSY */

1071

#define ARIZONA_SPI_BUSY_SHIFT 4 /* SPI_BUSY */

1072

#define ARIZONA_SPI_BUSY_WIDTH 1 /* SPI_BUSY */

1073

1074

/*

1075

* R22 (0x16) - Write Sequencer Ctrl 0

1076

*/

1077

#define ARIZONA_WSEQ_ABORT 0x0800 /* WSEQ_ABORT */

1078

#define ARIZONA_WSEQ_ABORT_MASK 0x0800 /* WSEQ_ABORT */

1079

#define ARIZONA_WSEQ_ABORT_SHIFT 11 /* WSEQ_ABORT */

1080

#define ARIZONA_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */

1081

#define ARIZONA_WSEQ_START 0x0400 /* WSEQ_START */

1082

#define ARIZONA_WSEQ_START_MASK 0x0400 /* WSEQ_START */

1083

#define ARIZONA_WSEQ_START_SHIFT 10 /* WSEQ_START */

1084

#define ARIZONA_WSEQ_START_WIDTH 1 /* WSEQ_START */

1085

#define ARIZONA_WSEQ_ENA 0x0200 /* WSEQ_ENA */

1086

#define ARIZONA_WSEQ_ENA_MASK 0x0200 /* WSEQ_ENA */

1087

#define ARIZONA_WSEQ_ENA_SHIFT 9 /* WSEQ_ENA */

1088

#define ARIZONA_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */

1089

#define ARIZONA_WSEQ_START_INDEX_MASK 0x01FF /* WSEQ_START_INDEX - [8:0] */

1090

#define ARIZONA_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [8:0] */

1091

#define ARIZONA_WSEQ_START_INDEX_WIDTH 9 /* WSEQ_START_INDEX - [8:0] */

1092

1093

/*

1094

* R23 (0x17) - Write Sequencer Ctrl 1

1095

*/

1096

#define ARIZONA_WSEQ_BUSY 0x0200 /* WSEQ_BUSY */

1097

#define ARIZONA_WSEQ_BUSY_MASK 0x0200 /* WSEQ_BUSY */

1098

#define ARIZONA_WSEQ_BUSY_SHIFT 9 /* WSEQ_BUSY */

1099

#define ARIZONA_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */

1100

#define ARIZONA_WSEQ_CURRENT_INDEX_MASK 0x01FF /* WSEQ_CURRENT_INDEX - [8:0] */

1101

#define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [8:0] */

1102

#define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH 9 /* WSEQ_CURRENT_INDEX - [8:0] */

1103

1104

/*

1105

* R24 (0x18) - Write Sequencer Ctrl 2

1106

*/

1107

#define ARIZONA_LOAD_DEFAULTS 0x0002 /* LOAD_DEFAULTS */

1108

#define ARIZONA_LOAD_DEFAULTS_MASK 0x0002 /* LOAD_DEFAULTS */

1109

#define ARIZONA_LOAD_DEFAULTS_SHIFT 1 /* LOAD_DEFAULTS */

1110

#define ARIZONA_LOAD_DEFAULTS_WIDTH 1 /* LOAD_DEFAULTS */

1111

#define ARIZONA_WSEQ_LOAD_MEM 0x0001 /* WSEQ_LOAD_MEM */

1112

#define ARIZONA_WSEQ_LOAD_MEM_MASK 0x0001 /* WSEQ_LOAD_MEM */

1113

#define ARIZONA_WSEQ_LOAD_MEM_SHIFT 0 /* WSEQ_LOAD_MEM */

1114

#define ARIZONA_WSEQ_LOAD_MEM_WIDTH 1 /* WSEQ_LOAD_MEM */

1115

1116

/*

1117

* R26 (0x1A) - Write Sequencer PROM

1118

*/

1119

#define ARIZONA_WSEQ_OTP_WRITE 0x0001 /* WSEQ_OTP_WRITE */

1120

#define ARIZONA_WSEQ_OTP_WRITE_MASK 0x0001 /* WSEQ_OTP_WRITE */

1121

#define ARIZONA_WSEQ_OTP_WRITE_SHIFT 0 /* WSEQ_OTP_WRITE */

1122

#define ARIZONA_WSEQ_OTP_WRITE_WIDTH 1 /* WSEQ_OTP_WRITE */

1123

1124

/*

1125

* R32 (0x20) - Tone Generator 1

1126

*/

1127

#define ARIZONA_TONE_RATE_MASK 0x7800 /* TONE_RATE - [14:11] */

1128

#define ARIZONA_TONE_RATE_SHIFT 11 /* TONE_RATE - [14:11] */

1129

#define ARIZONA_TONE_RATE_WIDTH 4 /* TONE_RATE - [14:11] */

1130

#define ARIZONA_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */

1131

#define ARIZONA_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */

1132

#define ARIZONA_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */

1133

#define ARIZONA_TONE2_OVD 0x0020 /* TONE2_OVD */

1134

#define ARIZONA_TONE2_OVD_MASK 0x0020 /* TONE2_OVD */

1135

#define ARIZONA_TONE2_OVD_SHIFT 5 /* TONE2_OVD */

1136

#define ARIZONA_TONE2_OVD_WIDTH 1 /* TONE2_OVD */

1137

#define ARIZONA_TONE1_OVD 0x0010 /* TONE1_OVD */

1138

#define ARIZONA_TONE1_OVD_MASK 0x0010 /* TONE1_OVD */

1139

#define ARIZONA_TONE1_OVD_SHIFT 4 /* TONE1_OVD */

1140

#define ARIZONA_TONE1_OVD_WIDTH 1 /* TONE1_OVD */

1141

#define ARIZONA_TONE2_ENA 0x0002 /* TONE2_ENA */

1142

#define ARIZONA_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */

1143

#define ARIZONA_TONE2_ENA_SHIFT 1 /* TONE2_ENA */

1144

#define ARIZONA_TONE2_ENA_WIDTH 1 /* TONE2_ENA */

1145

#define ARIZONA_TONE1_ENA 0x0001 /* TONE1_ENA */

1146

#define ARIZONA_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */

1147

#define ARIZONA_TONE1_ENA_SHIFT 0 /* TONE1_ENA */

1148

#define ARIZONA_TONE1_ENA_WIDTH 1 /* TONE1_ENA */

1149

1150

/*

1151

* R33 (0x21) - Tone Generator 2

1152

*/

1153

#define ARIZONA_TONE1_LVL_0_MASK 0xFFFF /* TONE1_LVL - [15:0] */

1154

#define ARIZONA_TONE1_LVL_0_SHIFT 0 /* TONE1_LVL - [15:0] */

1155

#define ARIZONA_TONE1_LVL_0_WIDTH 16 /* TONE1_LVL - [15:0] */

1156

1157

/*

1158

* R34 (0x22) - Tone Generator 3

1159

*/

1160

#define ARIZONA_TONE1_LVL_MASK 0x00FF /* TONE1_LVL - [7:0] */

1161

#define ARIZONA_TONE1_LVL_SHIFT 0 /* TONE1_LVL - [7:0] */

1162

#define ARIZONA_TONE1_LVL_WIDTH 8 /* TONE1_LVL - [7:0] */

1163

1164

/*

1165

* R35 (0x23) - Tone Generator 4

1166

*/

1167

#define ARIZONA_TONE2_LVL_0_MASK 0xFFFF /* TONE2_LVL - [15:0] */

1168

#define ARIZONA_TONE2_LVL_0_SHIFT 0 /* TONE2_LVL - [15:0] */

1169

#define ARIZONA_TONE2_LVL_0_WIDTH 16 /* TONE2_LVL - [15:0] */

1170

1171

/*

1172

* R36 (0x24) - Tone Generator 5

1173

*/

1174

#define ARIZONA_TONE2_LVL_MASK 0x00FF /* TONE2_LVL - [7:0] */

1175

#define ARIZONA_TONE2_LVL_SHIFT 0 /* TONE2_LVL - [7:0] */

1176

#define ARIZONA_TONE2_LVL_WIDTH 8 /* TONE2_LVL - [7:0] */

1177

1178

/*

1179

* R48 (0x30) - PWM Drive 1

1180

*/

1181

#define ARIZONA_PWM_RATE_MASK 0x7800 /* PWM_RATE - [14:11] */

1182

#define ARIZONA_PWM_RATE_SHIFT 11 /* PWM_RATE - [14:11] */

1183

#define ARIZONA_PWM_RATE_WIDTH 4 /* PWM_RATE - [14:11] */

1184

#define ARIZONA_PWM_CLK_SEL_MASK 0x0700 /* PWM_CLK_SEL - [10:8] */

1185

#define ARIZONA_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [10:8] */

1186

#define ARIZONA_PWM_CLK_SEL_WIDTH 3 /* PWM_CLK_SEL - [10:8] */

1187

#define ARIZONA_PWM2_OVD 0x0020 /* PWM2_OVD */

1188

#define ARIZONA_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */

1189

#define ARIZONA_PWM2_OVD_SHIFT 5 /* PWM2_OVD */

1190

#define ARIZONA_PWM2_OVD_WIDTH 1 /* PWM2_OVD */

1191

#define ARIZONA_PWM1_OVD 0x0010 /* PWM1_OVD */

1192

#define ARIZONA_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */

1193

#define ARIZONA_PWM1_OVD_SHIFT 4 /* PWM1_OVD */

1194

#define ARIZONA_PWM1_OVD_WIDTH 1 /* PWM1_OVD */

1195

#define ARIZONA_PWM2_ENA 0x0002 /* PWM2_ENA */

1196

#define ARIZONA_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */

1197

#define ARIZONA_PWM2_ENA_SHIFT 1 /* PWM2_ENA */

1198

#define ARIZONA_PWM2_ENA_WIDTH 1 /* PWM2_ENA */

1199

#define ARIZONA_PWM1_ENA 0x0001 /* PWM1_ENA */

1200

#define ARIZONA_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */

1201

#define ARIZONA_PWM1_ENA_SHIFT 0 /* PWM1_ENA */

1202

#define ARIZONA_PWM1_ENA_WIDTH 1 /* PWM1_ENA */

1203

1204

/*

1205

* R49 (0x31) - PWM Drive 2

1206

*/

1207

#define ARIZONA_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */

1208

#define ARIZONA_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */

1209

#define ARIZONA_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */

1210

1211

/*

1212

* R50 (0x32) - PWM Drive 3

1213

*/

1214

#define ARIZONA_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */

1215

#define ARIZONA_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */

1216

#define ARIZONA_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */

1217

1218

/*

1219

* R64 (0x40) - Wake control

1220

*/

Mark Brown

689557d

2013-01-11 08:55:57 +0900

[diff] [blame]

1221

#define ARIZONA_WKUP_MICD_CLAMP_FALL 0x0080 /* WKUP_MICD_CLAMP_FALL */

1222

#define ARIZONA_WKUP_MICD_CLAMP_FALL_MASK 0x0080 /* WKUP_MICD_CLAMP_FALL */

1223

#define ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT 7 /* WKUP_MICD_CLAMP_FALL */

1224

#define ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH 1 /* WKUP_MICD_CLAMP_FALL */

1225

#define ARIZONA_WKUP_MICD_CLAMP_RISE 0x0040 /* WKUP_MICD_CLAMP_RISE */

1226

#define ARIZONA_WKUP_MICD_CLAMP_RISE_MASK 0x0040 /* WKUP_MICD_CLAMP_RISE */

1227

#define ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT 6 /* WKUP_MICD_CLAMP_RISE */

1228

#define ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH 1 /* WKUP_MICD_CLAMP_RISE */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1229

#define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */

1230

#define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */

1231

#define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */

1232

#define ARIZONA_WKUP_GP5_FALL_WIDTH 1 /* WKUP_GP5_FALL */

1233

#define ARIZONA_WKUP_GP5_RISE 0x0010 /* WKUP_GP5_RISE */

1234

#define ARIZONA_WKUP_GP5_RISE_MASK 0x0010 /* WKUP_GP5_RISE */

1235

#define ARIZONA_WKUP_GP5_RISE_SHIFT 4 /* WKUP_GP5_RISE */

1236

#define ARIZONA_WKUP_GP5_RISE_WIDTH 1 /* WKUP_GP5_RISE */

1237

#define ARIZONA_WKUP_JD1_FALL 0x0008 /* WKUP_JD1_FALL */

1238

#define ARIZONA_WKUP_JD1_FALL_MASK 0x0008 /* WKUP_JD1_FALL */

1239

#define ARIZONA_WKUP_JD1_FALL_SHIFT 3 /* WKUP_JD1_FALL */

1240

#define ARIZONA_WKUP_JD1_FALL_WIDTH 1 /* WKUP_JD1_FALL */

1241

#define ARIZONA_WKUP_JD1_RISE 0x0004 /* WKUP_JD1_RISE */

1242

#define ARIZONA_WKUP_JD1_RISE_MASK 0x0004 /* WKUP_JD1_RISE */

1243

#define ARIZONA_WKUP_JD1_RISE_SHIFT 2 /* WKUP_JD1_RISE */

1244

#define ARIZONA_WKUP_JD1_RISE_WIDTH 1 /* WKUP_JD1_RISE */

1245

#define ARIZONA_WKUP_JD2_FALL 0x0002 /* WKUP_JD2_FALL */

1246

#define ARIZONA_WKUP_JD2_FALL_MASK 0x0002 /* WKUP_JD2_FALL */

1247

#define ARIZONA_WKUP_JD2_FALL_SHIFT 1 /* WKUP_JD2_FALL */

1248

#define ARIZONA_WKUP_JD2_FALL_WIDTH 1 /* WKUP_JD2_FALL */

1249

#define ARIZONA_WKUP_JD2_RISE 0x0001 /* WKUP_JD2_RISE */

1250

#define ARIZONA_WKUP_JD2_RISE_MASK 0x0001 /* WKUP_JD2_RISE */

1251

#define ARIZONA_WKUP_JD2_RISE_SHIFT 0 /* WKUP_JD2_RISE */

1252

#define ARIZONA_WKUP_JD2_RISE_WIDTH 1 /* WKUP_JD2_RISE */

1253

1254

/*

1255

* R65 (0x41) - Sequence control

1256

*/

1257

#define ARIZONA_WSEQ_ENA_GP5_FALL 0x0020 /* WSEQ_ENA_GP5_FALL */

1258

#define ARIZONA_WSEQ_ENA_GP5_FALL_MASK 0x0020 /* WSEQ_ENA_GP5_FALL */

1259

#define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT 5 /* WSEQ_ENA_GP5_FALL */

1260

#define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH 1 /* WSEQ_ENA_GP5_FALL */

1261

#define ARIZONA_WSEQ_ENA_GP5_RISE 0x0010 /* WSEQ_ENA_GP5_RISE */

1262

#define ARIZONA_WSEQ_ENA_GP5_RISE_MASK 0x0010 /* WSEQ_ENA_GP5_RISE */

1263

#define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT 4 /* WSEQ_ENA_GP5_RISE */

1264

#define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH 1 /* WSEQ_ENA_GP5_RISE */

1265

#define ARIZONA_WSEQ_ENA_JD1_FALL 0x0008 /* WSEQ_ENA_JD1_FALL */

1266

#define ARIZONA_WSEQ_ENA_JD1_FALL_MASK 0x0008 /* WSEQ_ENA_JD1_FALL */

1267

#define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT 3 /* WSEQ_ENA_JD1_FALL */

1268

#define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH 1 /* WSEQ_ENA_JD1_FALL */

1269

#define ARIZONA_WSEQ_ENA_JD1_RISE 0x0004 /* WSEQ_ENA_JD1_RISE */

1270

#define ARIZONA_WSEQ_ENA_JD1_RISE_MASK 0x0004 /* WSEQ_ENA_JD1_RISE */

1271

#define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT 2 /* WSEQ_ENA_JD1_RISE */

1272

#define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH 1 /* WSEQ_ENA_JD1_RISE */

1273

#define ARIZONA_WSEQ_ENA_JD2_FALL 0x0002 /* WSEQ_ENA_JD2_FALL */

1274

#define ARIZONA_WSEQ_ENA_JD2_FALL_MASK 0x0002 /* WSEQ_ENA_JD2_FALL */

1275

#define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT 1 /* WSEQ_ENA_JD2_FALL */

1276

#define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH 1 /* WSEQ_ENA_JD2_FALL */

1277

#define ARIZONA_WSEQ_ENA_JD2_RISE 0x0001 /* WSEQ_ENA_JD2_RISE */

1278

#define ARIZONA_WSEQ_ENA_JD2_RISE_MASK 0x0001 /* WSEQ_ENA_JD2_RISE */

1279

#define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */

1280

#define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */

1281

1282

/*

1283

* R97 (0x61) - Sample Rate Sequence Select 1

1284

*/

1285

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */

1286

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */

1287

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */

1288

1289

/*

1290

* R98 (0x62) - Sample Rate Sequence Select 2

1291

*/

1292

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */

1293

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */

1294

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */

1295

1296

/*

1297

* R99 (0x63) - Sample Rate Sequence Select 3

1298

*/

1299

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */

1300

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */

1301

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */

1302

1303

/*

1304

* R100 (0x64) - Sample Rate Sequence Select 4

1305

*/

1306

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */

1307

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */

1308

#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */

1309

1310

/*

1311

* R104 (0x68) - Always On Triggers Sequence Select 1

1312

*/

1313

#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */

1314

#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */

1315

#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */

1316

1317

/*

1318

* R105 (0x69) - Always On Triggers Sequence Select 2

1319

*/

1320

#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */

1321

#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */

1322

#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */

1323

1324

/*

1325

* R106 (0x6A) - Always On Triggers Sequence Select 3

1326

*/

1327

#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */

1328

#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */

1329

#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */

1330

1331

/*

1332

* R107 (0x6B) - Always On Triggers Sequence Select 4

1333

*/

1334

#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */

1335

#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */

1336

#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */

1337

1338

/*

1339

* R108 (0x6C) - Always On Triggers Sequence Select 5

1340

*/

1341

#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */

1342

#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */

1343

#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */

1344

1345

/*

1346

* R109 (0x6D) - Always On Triggers Sequence Select 6

1347

*/

1348

#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */

1349

#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */

1350

#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */

1351

1352

/*

1353

* R112 (0x70) - Comfort Noise Generator

1354

*/

1355

#define ARIZONA_NOISE_GEN_RATE_MASK 0x7800 /* NOISE_GEN_RATE - [14:11] */

1356

#define ARIZONA_NOISE_GEN_RATE_SHIFT 11 /* NOISE_GEN_RATE - [14:11] */

1357

#define ARIZONA_NOISE_GEN_RATE_WIDTH 4 /* NOISE_GEN_RATE - [14:11] */

1358

#define ARIZONA_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */

1359

#define ARIZONA_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */

1360

#define ARIZONA_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */

1361

#define ARIZONA_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */

1362

#define ARIZONA_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */

1363

#define ARIZONA_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */

1364

#define ARIZONA_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */

1365

1366

/*

1367

* R144 (0x90) - Haptics Control 1

1368

*/

1369

#define ARIZONA_HAP_RATE_MASK 0x7800 /* HAP_RATE - [14:11] */

1370

#define ARIZONA_HAP_RATE_SHIFT 11 /* HAP_RATE - [14:11] */

1371

#define ARIZONA_HAP_RATE_WIDTH 4 /* HAP_RATE - [14:11] */

1372

#define ARIZONA_ONESHOT_TRIG 0x0010 /* ONESHOT_TRIG */

1373

#define ARIZONA_ONESHOT_TRIG_MASK 0x0010 /* ONESHOT_TRIG */

1374

#define ARIZONA_ONESHOT_TRIG_SHIFT 4 /* ONESHOT_TRIG */

1375

#define ARIZONA_ONESHOT_TRIG_WIDTH 1 /* ONESHOT_TRIG */

1376

#define ARIZONA_HAP_CTRL_MASK 0x000C /* HAP_CTRL - [3:2] */

1377

#define ARIZONA_HAP_CTRL_SHIFT 2 /* HAP_CTRL - [3:2] */

1378

#define ARIZONA_HAP_CTRL_WIDTH 2 /* HAP_CTRL - [3:2] */

1379

#define ARIZONA_HAP_ACT 0x0002 /* HAP_ACT */

1380

#define ARIZONA_HAP_ACT_MASK 0x0002 /* HAP_ACT */

1381

#define ARIZONA_HAP_ACT_SHIFT 1 /* HAP_ACT */

1382

#define ARIZONA_HAP_ACT_WIDTH 1 /* HAP_ACT */

1383

1384

/*

1385

* R145 (0x91) - Haptics Control 2

1386

*/

1387

#define ARIZONA_LRA_FREQ_MASK 0x7FFF /* LRA_FREQ - [14:0] */

1388

#define ARIZONA_LRA_FREQ_SHIFT 0 /* LRA_FREQ - [14:0] */

1389

#define ARIZONA_LRA_FREQ_WIDTH 15 /* LRA_FREQ - [14:0] */

1390

1391

/*

1392

* R146 (0x92) - Haptics phase 1 intensity

1393

*/

1394

#define ARIZONA_PHASE1_INTENSITY_MASK 0x00FF /* PHASE1_INTENSITY - [7:0] */

1395

#define ARIZONA_PHASE1_INTENSITY_SHIFT 0 /* PHASE1_INTENSITY - [7:0] */

1396

#define ARIZONA_PHASE1_INTENSITY_WIDTH 8 /* PHASE1_INTENSITY - [7:0] */

1397

1398

/*

1399

* R147 (0x93) - Haptics phase 1 duration

1400

*/

1401

#define ARIZONA_PHASE1_DURATION_MASK 0x01FF /* PHASE1_DURATION - [8:0] */

1402

#define ARIZONA_PHASE1_DURATION_SHIFT 0 /* PHASE1_DURATION - [8:0] */

1403

#define ARIZONA_PHASE1_DURATION_WIDTH 9 /* PHASE1_DURATION - [8:0] */

1404

1405

/*

1406

* R148 (0x94) - Haptics phase 2 intensity

1407

*/

1408

#define ARIZONA_PHASE2_INTENSITY_MASK 0x00FF /* PHASE2_INTENSITY - [7:0] */

1409

#define ARIZONA_PHASE2_INTENSITY_SHIFT 0 /* PHASE2_INTENSITY - [7:0] */

1410

#define ARIZONA_PHASE2_INTENSITY_WIDTH 8 /* PHASE2_INTENSITY - [7:0] */

1411

1412

/*

1413

* R149 (0x95) - Haptics phase 2 duration

1414

*/

1415

#define ARIZONA_PHASE2_DURATION_MASK 0x07FF /* PHASE2_DURATION - [10:0] */

1416

#define ARIZONA_PHASE2_DURATION_SHIFT 0 /* PHASE2_DURATION - [10:0] */

1417

#define ARIZONA_PHASE2_DURATION_WIDTH 11 /* PHASE2_DURATION - [10:0] */

1418

1419

/*

1420

* R150 (0x96) - Haptics phase 3 intensity

1421

*/

1422

#define ARIZONA_PHASE3_INTENSITY_MASK 0x00FF /* PHASE3_INTENSITY - [7:0] */

1423

#define ARIZONA_PHASE3_INTENSITY_SHIFT 0 /* PHASE3_INTENSITY - [7:0] */

1424

#define ARIZONA_PHASE3_INTENSITY_WIDTH 8 /* PHASE3_INTENSITY - [7:0] */

1425

1426

/*

1427

* R151 (0x97) - Haptics phase 3 duration

1428

*/

1429

#define ARIZONA_PHASE3_DURATION_MASK 0x01FF /* PHASE3_DURATION - [8:0] */

1430

#define ARIZONA_PHASE3_DURATION_SHIFT 0 /* PHASE3_DURATION - [8:0] */

1431

#define ARIZONA_PHASE3_DURATION_WIDTH 9 /* PHASE3_DURATION - [8:0] */

1432

1433

/*

1434

* R152 (0x98) - Haptics Status

1435

*/

1436

#define ARIZONA_ONESHOT_STS 0x0001 /* ONESHOT_STS */

1437

#define ARIZONA_ONESHOT_STS_MASK 0x0001 /* ONESHOT_STS */

1438

#define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */

1439

#define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */

1440

1441

/*

1442

* R256 (0x100) - Clock 32k 1

1443

*/

1444

#define ARIZONA_CLK_32K_ENA 0x0040 /* CLK_32K_ENA */

1445

#define ARIZONA_CLK_32K_ENA_MASK 0x0040 /* CLK_32K_ENA */

1446

#define ARIZONA_CLK_32K_ENA_SHIFT 6 /* CLK_32K_ENA */

1447

#define ARIZONA_CLK_32K_ENA_WIDTH 1 /* CLK_32K_ENA */

1448

#define ARIZONA_CLK_32K_SRC_MASK 0x0003 /* CLK_32K_SRC - [1:0] */

1449

#define ARIZONA_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [1:0] */

1450

#define ARIZONA_CLK_32K_SRC_WIDTH 2 /* CLK_32K_SRC - [1:0] */

1451

1452

/*

1453

* R257 (0x101) - System Clock 1

1454

*/

1455

#define ARIZONA_SYSCLK_FRAC 0x8000 /* SYSCLK_FRAC */

1456

#define ARIZONA_SYSCLK_FRAC_MASK 0x8000 /* SYSCLK_FRAC */

1457

#define ARIZONA_SYSCLK_FRAC_SHIFT 15 /* SYSCLK_FRAC */

1458

#define ARIZONA_SYSCLK_FRAC_WIDTH 1 /* SYSCLK_FRAC */

1459

#define ARIZONA_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */

1460

#define ARIZONA_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */

1461

#define ARIZONA_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */

1462

#define ARIZONA_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */

1463

#define ARIZONA_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */

1464

#define ARIZONA_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */

1465

#define ARIZONA_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */

1466

#define ARIZONA_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */

1467

#define ARIZONA_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */

1468

#define ARIZONA_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */

1469

1470

/*

1471

* R258 (0x102) - Sample rate 1

1472

*/

1473

#define ARIZONA_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */

1474

#define ARIZONA_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */

1475

#define ARIZONA_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */

1476

1477

/*

1478

* R259 (0x103) - Sample rate 2

1479

*/

1480

#define ARIZONA_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */

1481

#define ARIZONA_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */

1482

#define ARIZONA_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */

1483

1484

/*

1485

* R260 (0x104) - Sample rate 3

1486

*/

1487

#define ARIZONA_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */

1488

#define ARIZONA_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */

1489

#define ARIZONA_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */

1490

1491

/*

1492

* R266 (0x10A) - Sample rate 1 status

1493

*/

1494

#define ARIZONA_SAMPLE_RATE_1_STS_MASK 0x001F /* SAMPLE_RATE_1_STS - [4:0] */

1495

#define ARIZONA_SAMPLE_RATE_1_STS_SHIFT 0 /* SAMPLE_RATE_1_STS - [4:0] */

1496

#define ARIZONA_SAMPLE_RATE_1_STS_WIDTH 5 /* SAMPLE_RATE_1_STS - [4:0] */

1497

1498

/*

1499

* R267 (0x10B) - Sample rate 2 status

1500

*/

1501

#define ARIZONA_SAMPLE_RATE_2_STS_MASK 0x001F /* SAMPLE_RATE_2_STS - [4:0] */

1502

#define ARIZONA_SAMPLE_RATE_2_STS_SHIFT 0 /* SAMPLE_RATE_2_STS - [4:0] */

1503

#define ARIZONA_SAMPLE_RATE_2_STS_WIDTH 5 /* SAMPLE_RATE_2_STS - [4:0] */

1504

1505

/*

1506

* R268 (0x10C) - Sample rate 3 status

1507

*/

1508

#define ARIZONA_SAMPLE_RATE_3_STS_MASK 0x001F /* SAMPLE_RATE_3_STS - [4:0] */

1509

#define ARIZONA_SAMPLE_RATE_3_STS_SHIFT 0 /* SAMPLE_RATE_3_STS - [4:0] */

1510

#define ARIZONA_SAMPLE_RATE_3_STS_WIDTH 5 /* SAMPLE_RATE_3_STS - [4:0] */

1511

1512

/*

1513

* R274 (0x112) - Async clock 1

1514

*/

1515

#define ARIZONA_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */

1516

#define ARIZONA_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */

1517

#define ARIZONA_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */

1518

#define ARIZONA_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */

1519

#define ARIZONA_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */

1520

#define ARIZONA_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */

1521

#define ARIZONA_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */

1522

#define ARIZONA_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */

1523

#define ARIZONA_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */

1524

#define ARIZONA_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */

1525

1526

/*

1527

* R275 (0x113) - Async sample rate 1

1528

*/

1529

#define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */

1530

#define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */

1531

#define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */

1532

1533

/*

1534

* R283 (0x11B) - Async sample rate 1 status

1535

*/

1536

#define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */

1537

#define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */

1538

#define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */

1539

1540

/*

1541

* R329 (0x149) - Output system clock

1542

*/

1543

#define ARIZONA_OPCLK_ENA 0x8000 /* OPCLK_ENA */

1544

#define ARIZONA_OPCLK_ENA_MASK 0x8000 /* OPCLK_ENA */

1545

#define ARIZONA_OPCLK_ENA_SHIFT 15 /* OPCLK_ENA */

1546

#define ARIZONA_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */

1547

#define ARIZONA_OPCLK_DIV_MASK 0x00F8 /* OPCLK_DIV - [7:3] */

1548

#define ARIZONA_OPCLK_DIV_SHIFT 3 /* OPCLK_DIV - [7:3] */

1549

#define ARIZONA_OPCLK_DIV_WIDTH 5 /* OPCLK_DIV - [7:3] */

1550

#define ARIZONA_OPCLK_SEL_MASK 0x0007 /* OPCLK_SEL - [2:0] */

1551

#define ARIZONA_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [2:0] */

1552

#define ARIZONA_OPCLK_SEL_WIDTH 3 /* OPCLK_SEL - [2:0] */

1553

1554

/*

1555

* R330 (0x14A) - Output async clock

1556

*/

1557

#define ARIZONA_OPCLK_ASYNC_ENA 0x8000 /* OPCLK_ASYNC_ENA */

1558

#define ARIZONA_OPCLK_ASYNC_ENA_MASK 0x8000 /* OPCLK_ASYNC_ENA */

1559

#define ARIZONA_OPCLK_ASYNC_ENA_SHIFT 15 /* OPCLK_ASYNC_ENA */

1560

#define ARIZONA_OPCLK_ASYNC_ENA_WIDTH 1 /* OPCLK_ASYNC_ENA */

1561

#define ARIZONA_OPCLK_ASYNC_DIV_MASK 0x00F8 /* OPCLK_ASYNC_DIV - [7:3] */

1562

#define ARIZONA_OPCLK_ASYNC_DIV_SHIFT 3 /* OPCLK_ASYNC_DIV - [7:3] */

1563

#define ARIZONA_OPCLK_ASYNC_DIV_WIDTH 5 /* OPCLK_ASYNC_DIV - [7:3] */

1564

#define ARIZONA_OPCLK_ASYNC_SEL_MASK 0x0007 /* OPCLK_ASYNC_SEL - [2:0] */

1565

#define ARIZONA_OPCLK_ASYNC_SEL_SHIFT 0 /* OPCLK_ASYNC_SEL - [2:0] */

1566

#define ARIZONA_OPCLK_ASYNC_SEL_WIDTH 3 /* OPCLK_ASYNC_SEL - [2:0] */

1567

1568

/*

1569

* R338 (0x152) - Rate Estimator 1

1570

*/

1571

#define ARIZONA_TRIG_ON_STARTUP 0x0010 /* TRIG_ON_STARTUP */

1572

#define ARIZONA_TRIG_ON_STARTUP_MASK 0x0010 /* TRIG_ON_STARTUP */

1573

#define ARIZONA_TRIG_ON_STARTUP_SHIFT 4 /* TRIG_ON_STARTUP */

1574

#define ARIZONA_TRIG_ON_STARTUP_WIDTH 1 /* TRIG_ON_STARTUP */

1575

#define ARIZONA_LRCLK_SRC_MASK 0x000E /* LRCLK_SRC - [3:1] */

1576

#define ARIZONA_LRCLK_SRC_SHIFT 1 /* LRCLK_SRC - [3:1] */

1577

#define ARIZONA_LRCLK_SRC_WIDTH 3 /* LRCLK_SRC - [3:1] */

1578

#define ARIZONA_RATE_EST_ENA 0x0001 /* RATE_EST_ENA */

1579

#define ARIZONA_RATE_EST_ENA_MASK 0x0001 /* RATE_EST_ENA */

1580

#define ARIZONA_RATE_EST_ENA_SHIFT 0 /* RATE_EST_ENA */

1581

#define ARIZONA_RATE_EST_ENA_WIDTH 1 /* RATE_EST_ENA */

1582

1583

/*

1584

* R339 (0x153) - Rate Estimator 2

1585

*/

1586

#define ARIZONA_SAMPLE_RATE_DETECT_A_MASK 0x001F /* SAMPLE_RATE_DETECT_A - [4:0] */

1587

#define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT 0 /* SAMPLE_RATE_DETECT_A - [4:0] */

1588

#define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH 5 /* SAMPLE_RATE_DETECT_A - [4:0] */

1589

1590

/*

1591

* R340 (0x154) - Rate Estimator 3

1592

*/

1593

#define ARIZONA_SAMPLE_RATE_DETECT_B_MASK 0x001F /* SAMPLE_RATE_DETECT_B - [4:0] */

1594

#define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT 0 /* SAMPLE_RATE_DETECT_B - [4:0] */

1595

#define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH 5 /* SAMPLE_RATE_DETECT_B - [4:0] */

1596

1597

/*

1598

* R341 (0x155) - Rate Estimator 4

1599

*/

1600

#define ARIZONA_SAMPLE_RATE_DETECT_C_MASK 0x001F /* SAMPLE_RATE_DETECT_C - [4:0] */

1601

#define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT 0 /* SAMPLE_RATE_DETECT_C - [4:0] */

1602

#define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH 5 /* SAMPLE_RATE_DETECT_C - [4:0] */

1603

1604

/*

1605

* R342 (0x156) - Rate Estimator 5

1606

*/

1607

#define ARIZONA_SAMPLE_RATE_DETECT_D_MASK 0x001F /* SAMPLE_RATE_DETECT_D - [4:0] */

1608

#define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT 0 /* SAMPLE_RATE_DETECT_D - [4:0] */

1609

#define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */

1610

1611

/*

Mark Brown

2012-11-27 18:48:33 +0000

[diff] [blame]

1612

* R353 (0x161) - Dynamic Frequency Scaling 1

1613

*/

1614

#define ARIZONA_SUBSYS_MAX_FREQ 0x0001 /* SUBSYS_MAX_FREQ */

1615

#define ARIZONA_SUBSYS_MAX_FREQ_SHIFT 0 /* SUBSYS_MAX_FREQ */

1616

#define ARIZONA_SUBSYS_MAX_FREQ_WIDTH 1 /* SUBSYS_MAX_FREQ */

1617

1618

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1619

* R369 (0x171) - FLL1 Control 1

1620

*/

1621

#define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */

1622

#define ARIZONA_FLL1_FREERUN_MASK 0x0002 /* FLL1_FREERUN */

1623

#define ARIZONA_FLL1_FREERUN_SHIFT 1 /* FLL1_FREERUN */

1624

#define ARIZONA_FLL1_FREERUN_WIDTH 1 /* FLL1_FREERUN */

1625

#define ARIZONA_FLL1_ENA 0x0001 /* FLL1_ENA */

1626

#define ARIZONA_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */

1627

#define ARIZONA_FLL1_ENA_SHIFT 0 /* FLL1_ENA */

1628

#define ARIZONA_FLL1_ENA_WIDTH 1 /* FLL1_ENA */

1629

1630

/*

1631

* R370 (0x172) - FLL1 Control 2

1632

*/

1633

#define ARIZONA_FLL1_CTRL_UPD 0x8000 /* FLL1_CTRL_UPD */

1634

#define ARIZONA_FLL1_CTRL_UPD_MASK 0x8000 /* FLL1_CTRL_UPD */

1635

#define ARIZONA_FLL1_CTRL_UPD_SHIFT 15 /* FLL1_CTRL_UPD */

1636

#define ARIZONA_FLL1_CTRL_UPD_WIDTH 1 /* FLL1_CTRL_UPD */

1637

#define ARIZONA_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */

1638

#define ARIZONA_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */

1639

#define ARIZONA_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */

1640

1641

/*

1642

* R371 (0x173) - FLL1 Control 3

1643

*/

1644

#define ARIZONA_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */

1645

#define ARIZONA_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */

1646

#define ARIZONA_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */

1647

1648

/*

1649

* R372 (0x174) - FLL1 Control 4

1650

*/

1651

#define ARIZONA_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */

1652

#define ARIZONA_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */

1653

#define ARIZONA_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */

1654

1655

/*

1656

* R373 (0x175) - FLL1 Control 5

1657

*/

1658

#define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */

1659

#define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */

1660

#define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */

1661

#define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */

1662

#define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */

1663

#define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */

1664

1665

/*

1666

* R374 (0x176) - FLL1 Control 6

1667

*/

1668

#define ARIZONA_FLL1_CLK_REF_DIV_MASK 0x00C0 /* FLL1_CLK_REF_DIV - [7:6] */

1669

#define ARIZONA_FLL1_CLK_REF_DIV_SHIFT 6 /* FLL1_CLK_REF_DIV - [7:6] */

1670

#define ARIZONA_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [7:6] */

1671

#define ARIZONA_FLL1_CLK_REF_SRC_MASK 0x000F /* FLL1_CLK_REF_SRC - [3:0] */

1672

#define ARIZONA_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [3:0] */

1673

#define ARIZONA_FLL1_CLK_REF_SRC_WIDTH 4 /* FLL1_CLK_REF_SRC - [3:0] */

1674

1675

/*

1676

* R375 (0x177) - FLL1 Loop Filter Test 1

1677

*/

1678

#define ARIZONA_FLL1_FRC_INTEG_UPD 0x8000 /* FLL1_FRC_INTEG_UPD */

1679

#define ARIZONA_FLL1_FRC_INTEG_UPD_MASK 0x8000 /* FLL1_FRC_INTEG_UPD */

1680

#define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT 15 /* FLL1_FRC_INTEG_UPD */

1681

#define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH 1 /* FLL1_FRC_INTEG_UPD */

1682

#define ARIZONA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF /* FLL1_FRC_INTEG_VAL - [11:0] */

1683

#define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */

1684

#define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */

1685

1686

/*

Mark Brown

2013-03-05 11:51:55 +0800

[diff] [blame]

1687

* R377 (0x179) - FLL1 Control 7

1688

*/

1689

#define ARIZONA_FLL1_GAIN_MASK 0x003c /* FLL1_GAIN */

1690

#define ARIZONA_FLL1_GAIN_SHIFT 2 /* FLL1_GAIN */

1691

#define ARIZONA_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN */

1692

1693

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1694

* R385 (0x181) - FLL1 Synchroniser 1

1695

*/

1696

#define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */

1697

#define ARIZONA_FLL1_SYNC_ENA_MASK 0x0001 /* FLL1_SYNC_ENA */

1698

#define ARIZONA_FLL1_SYNC_ENA_SHIFT 0 /* FLL1_SYNC_ENA */

1699

#define ARIZONA_FLL1_SYNC_ENA_WIDTH 1 /* FLL1_SYNC_ENA */

1700

1701

/*

1702

* R386 (0x182) - FLL1 Synchroniser 2

1703

*/

1704

#define ARIZONA_FLL1_SYNC_N_MASK 0x03FF /* FLL1_SYNC_N - [9:0] */

1705

#define ARIZONA_FLL1_SYNC_N_SHIFT 0 /* FLL1_SYNC_N - [9:0] */

1706

#define ARIZONA_FLL1_SYNC_N_WIDTH 10 /* FLL1_SYNC_N - [9:0] */

1707

1708

/*

1709

* R387 (0x183) - FLL1 Synchroniser 3

1710

*/

1711

#define ARIZONA_FLL1_SYNC_THETA_MASK 0xFFFF /* FLL1_SYNC_THETA - [15:0] */

1712

#define ARIZONA_FLL1_SYNC_THETA_SHIFT 0 /* FLL1_SYNC_THETA - [15:0] */

1713

#define ARIZONA_FLL1_SYNC_THETA_WIDTH 16 /* FLL1_SYNC_THETA - [15:0] */

1714

1715

/*

1716

* R388 (0x184) - FLL1 Synchroniser 4

1717

*/

1718

#define ARIZONA_FLL1_SYNC_LAMBDA_MASK 0xFFFF /* FLL1_SYNC_LAMBDA - [15:0] */

1719

#define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT 0 /* FLL1_SYNC_LAMBDA - [15:0] */

1720

#define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH 16 /* FLL1_SYNC_LAMBDA - [15:0] */

1721

1722

/*

1723

* R389 (0x185) - FLL1 Synchroniser 5

1724

*/

1725

#define ARIZONA_FLL1_SYNC_FRATIO_MASK 0x0700 /* FLL1_SYNC_FRATIO - [10:8] */

1726

#define ARIZONA_FLL1_SYNC_FRATIO_SHIFT 8 /* FLL1_SYNC_FRATIO - [10:8] */

1727

#define ARIZONA_FLL1_SYNC_FRATIO_WIDTH 3 /* FLL1_SYNC_FRATIO - [10:8] */

1728

1729

/*

1730

* R390 (0x186) - FLL1 Synchroniser 6

1731

*/

1732

#define ARIZONA_FLL1_CLK_SYNC_DIV_MASK 0x00C0 /* FLL1_CLK_SYNC_DIV - [7:6] */

1733

#define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT 6 /* FLL1_CLK_SYNC_DIV - [7:6] */

1734

#define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH 2 /* FLL1_CLK_SYNC_DIV - [7:6] */

1735

#define ARIZONA_FLL1_CLK_SYNC_SRC_MASK 0x000F /* FLL1_CLK_SYNC_SRC - [3:0] */

1736

#define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */

1737

#define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */

1738

1739

/*

Mark Brown

2013-03-05 11:51:55 +0800

[diff] [blame]

1740

* R391 (0x187) - FLL1 Synchroniser 7

1741

*/

1742

#define ARIZONA_FLL1_SYNC_GAIN_MASK 0x003c /* FLL1_SYNC_GAIN */

1743

#define ARIZONA_FLL1_SYNC_GAIN_SHIFT 2 /* FLL1_SYNC_GAIN */

1744

#define ARIZONA_FLL1_SYNC_GAIN_WIDTH 4 /* FLL1_SYNC_GAIN */

1745

#define ARIZONA_FLL1_SYNC_BW 0x0001 /* FLL1_SYNC_BW */

1746

#define ARIZONA_FLL1_SYNC_BW_MASK 0x0001 /* FLL1_SYNC_BW */

1747

#define ARIZONA_FLL1_SYNC_BW_SHIFT 0 /* FLL1_SYNC_BW */

1748

#define ARIZONA_FLL1_SYNC_BW_WIDTH 1 /* FLL1_SYNC_BW */

1749

1750

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1751

* R393 (0x189) - FLL1 Spread Spectrum

1752

*/

1753

#define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */

1754

#define ARIZONA_FLL1_SS_AMPL_SHIFT 4 /* FLL1_SS_AMPL - [5:4] */

1755

#define ARIZONA_FLL1_SS_AMPL_WIDTH 2 /* FLL1_SS_AMPL - [5:4] */

1756

#define ARIZONA_FLL1_SS_FREQ_MASK 0x000C /* FLL1_SS_FREQ - [3:2] */

1757

#define ARIZONA_FLL1_SS_FREQ_SHIFT 2 /* FLL1_SS_FREQ - [3:2] */

1758

#define ARIZONA_FLL1_SS_FREQ_WIDTH 2 /* FLL1_SS_FREQ - [3:2] */

1759

#define ARIZONA_FLL1_SS_SEL_MASK 0x0003 /* FLL1_SS_SEL - [1:0] */

1760

#define ARIZONA_FLL1_SS_SEL_SHIFT 0 /* FLL1_SS_SEL - [1:0] */

1761

#define ARIZONA_FLL1_SS_SEL_WIDTH 2 /* FLL1_SS_SEL - [1:0] */

1762

1763

/*

1764

* R394 (0x18A) - FLL1 GPIO Clock

1765

*/

1766

#define ARIZONA_FLL1_GPDIV_MASK 0x00FE /* FLL1_GPDIV - [7:1] */

1767

#define ARIZONA_FLL1_GPDIV_SHIFT 1 /* FLL1_GPDIV - [7:1] */

1768

#define ARIZONA_FLL1_GPDIV_WIDTH 7 /* FLL1_GPDIV - [7:1] */

1769

#define ARIZONA_FLL1_GPDIV_ENA 0x0001 /* FLL1_GPDIV_ENA */

1770

#define ARIZONA_FLL1_GPDIV_ENA_MASK 0x0001 /* FLL1_GPDIV_ENA */

1771

#define ARIZONA_FLL1_GPDIV_ENA_SHIFT 0 /* FLL1_GPDIV_ENA */

1772

#define ARIZONA_FLL1_GPDIV_ENA_WIDTH 1 /* FLL1_GPDIV_ENA */

1773

1774

/*

1775

* R401 (0x191) - FLL2 Control 1

1776

*/

1777

#define ARIZONA_FLL2_FREERUN 0x0002 /* FLL2_FREERUN */

1778

#define ARIZONA_FLL2_FREERUN_MASK 0x0002 /* FLL2_FREERUN */

1779

#define ARIZONA_FLL2_FREERUN_SHIFT 1 /* FLL2_FREERUN */

1780

#define ARIZONA_FLL2_FREERUN_WIDTH 1 /* FLL2_FREERUN */

1781

#define ARIZONA_FLL2_ENA 0x0001 /* FLL2_ENA */

1782

#define ARIZONA_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */

1783

#define ARIZONA_FLL2_ENA_SHIFT 0 /* FLL2_ENA */

1784

#define ARIZONA_FLL2_ENA_WIDTH 1 /* FLL2_ENA */

1785

1786

/*

1787

* R402 (0x192) - FLL2 Control 2

1788

*/

1789

#define ARIZONA_FLL2_CTRL_UPD 0x8000 /* FLL2_CTRL_UPD */

1790

#define ARIZONA_FLL2_CTRL_UPD_MASK 0x8000 /* FLL2_CTRL_UPD */

1791

#define ARIZONA_FLL2_CTRL_UPD_SHIFT 15 /* FLL2_CTRL_UPD */

1792

#define ARIZONA_FLL2_CTRL_UPD_WIDTH 1 /* FLL2_CTRL_UPD */

1793

#define ARIZONA_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */

1794

#define ARIZONA_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */

1795

#define ARIZONA_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */

1796

1797

/*

1798

* R403 (0x193) - FLL2 Control 3

1799

*/

1800

#define ARIZONA_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */

1801

#define ARIZONA_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */

1802

#define ARIZONA_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */

1803

1804

/*

1805

* R404 (0x194) - FLL2 Control 4

1806

*/

1807

#define ARIZONA_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */

1808

#define ARIZONA_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */

1809

#define ARIZONA_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */

1810

1811

/*

1812

* R405 (0x195) - FLL2 Control 5

1813

*/

1814

#define ARIZONA_FLL2_FRATIO_MASK 0x0700 /* FLL2_FRATIO - [10:8] */

1815

#define ARIZONA_FLL2_FRATIO_SHIFT 8 /* FLL2_FRATIO - [10:8] */

1816

#define ARIZONA_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [10:8] */

1817

#define ARIZONA_FLL2_OUTDIV_MASK 0x000E /* FLL2_OUTDIV - [3:1] */

1818

#define ARIZONA_FLL2_OUTDIV_SHIFT 1 /* FLL2_OUTDIV - [3:1] */

1819

#define ARIZONA_FLL2_OUTDIV_WIDTH 3 /* FLL2_OUTDIV - [3:1] */

1820

1821

/*

1822

* R406 (0x196) - FLL2 Control 6

1823

*/

1824

#define ARIZONA_FLL2_CLK_REF_DIV_MASK 0x00C0 /* FLL2_CLK_REF_DIV - [7:6] */

1825

#define ARIZONA_FLL2_CLK_REF_DIV_SHIFT 6 /* FLL2_CLK_REF_DIV - [7:6] */

1826

#define ARIZONA_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [7:6] */

1827

#define ARIZONA_FLL2_CLK_REF_SRC_MASK 0x000F /* FLL2_CLK_REF_SRC - [3:0] */

1828

#define ARIZONA_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [3:0] */

1829

#define ARIZONA_FLL2_CLK_REF_SRC_WIDTH 4 /* FLL2_CLK_REF_SRC - [3:0] */

1830

1831

/*

1832

* R407 (0x197) - FLL2 Loop Filter Test 1

1833

*/

1834

#define ARIZONA_FLL2_FRC_INTEG_UPD 0x8000 /* FLL2_FRC_INTEG_UPD */

1835

#define ARIZONA_FLL2_FRC_INTEG_UPD_MASK 0x8000 /* FLL2_FRC_INTEG_UPD */

1836

#define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT 15 /* FLL2_FRC_INTEG_UPD */

1837

#define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH 1 /* FLL2_FRC_INTEG_UPD */

1838

#define ARIZONA_FLL2_FRC_INTEG_VAL_MASK 0x0FFF /* FLL2_FRC_INTEG_VAL - [11:0] */

1839

#define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */

1840

#define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */

1841

1842

/*

Mark Brown

2013-03-05 11:51:55 +0800

[diff] [blame]

1843

* R409 (0x199) - FLL2 Control 7

1844

*/

1845

#define ARIZONA_FLL2_GAIN_MASK 0x003c /* FLL2_GAIN */

1846

#define ARIZONA_FLL2_GAIN_SHIFT 2 /* FLL2_GAIN */

1847

#define ARIZONA_FLL2_GAIN_WIDTH 4 /* FLL2_GAIN */

1848

1849

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1850

* R417 (0x1A1) - FLL2 Synchroniser 1

1851

*/

1852

#define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */

1853

#define ARIZONA_FLL2_SYNC_ENA_MASK 0x0001 /* FLL2_SYNC_ENA */

1854

#define ARIZONA_FLL2_SYNC_ENA_SHIFT 0 /* FLL2_SYNC_ENA */

1855

#define ARIZONA_FLL2_SYNC_ENA_WIDTH 1 /* FLL2_SYNC_ENA */

1856

1857

/*

1858

* R418 (0x1A2) - FLL2 Synchroniser 2

1859

*/

1860

#define ARIZONA_FLL2_SYNC_N_MASK 0x03FF /* FLL2_SYNC_N - [9:0] */

1861

#define ARIZONA_FLL2_SYNC_N_SHIFT 0 /* FLL2_SYNC_N - [9:0] */

1862

#define ARIZONA_FLL2_SYNC_N_WIDTH 10 /* FLL2_SYNC_N - [9:0] */

1863

1864

/*

1865

* R419 (0x1A3) - FLL2 Synchroniser 3

1866

*/

1867

#define ARIZONA_FLL2_SYNC_THETA_MASK 0xFFFF /* FLL2_SYNC_THETA - [15:0] */

1868

#define ARIZONA_FLL2_SYNC_THETA_SHIFT 0 /* FLL2_SYNC_THETA - [15:0] */

1869

#define ARIZONA_FLL2_SYNC_THETA_WIDTH 16 /* FLL2_SYNC_THETA - [15:0] */

1870

1871

/*

1872

* R420 (0x1A4) - FLL2 Synchroniser 4

1873

*/

1874

#define ARIZONA_FLL2_SYNC_LAMBDA_MASK 0xFFFF /* FLL2_SYNC_LAMBDA - [15:0] */

1875

#define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT 0 /* FLL2_SYNC_LAMBDA - [15:0] */

1876

#define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH 16 /* FLL2_SYNC_LAMBDA - [15:0] */

1877

1878

/*

1879

* R421 (0x1A5) - FLL2 Synchroniser 5

1880

*/

1881

#define ARIZONA_FLL2_SYNC_FRATIO_MASK 0x0700 /* FLL2_SYNC_FRATIO - [10:8] */

1882

#define ARIZONA_FLL2_SYNC_FRATIO_SHIFT 8 /* FLL2_SYNC_FRATIO - [10:8] */

1883

#define ARIZONA_FLL2_SYNC_FRATIO_WIDTH 3 /* FLL2_SYNC_FRATIO - [10:8] */

1884

1885

/*

1886

* R422 (0x1A6) - FLL2 Synchroniser 6

1887

*/

1888

#define ARIZONA_FLL2_CLK_SYNC_DIV_MASK 0x00C0 /* FLL2_CLK_SYNC_DIV - [7:6] */

1889

#define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT 6 /* FLL2_CLK_SYNC_DIV - [7:6] */

1890

#define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH 2 /* FLL2_CLK_SYNC_DIV - [7:6] */

1891

#define ARIZONA_FLL2_CLK_SYNC_SRC_MASK 0x000F /* FLL2_CLK_SYNC_SRC - [3:0] */

1892

#define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */

1893

#define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */

1894

1895

/*

Mark Brown

2013-03-05 11:51:55 +0800

[diff] [blame]

1896

* R423 (0x1A7) - FLL2 Synchroniser 7

1897

*/

1898

#define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */

1899

#define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */

1900

#define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */

1901

#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */

1902

#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */

1903

#define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */

1904

#define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */

1905

1906

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1907

* R425 (0x1A9) - FLL2 Spread Spectrum

1908

*/

1909

#define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */

1910

#define ARIZONA_FLL2_SS_AMPL_SHIFT 4 /* FLL2_SS_AMPL - [5:4] */

1911

#define ARIZONA_FLL2_SS_AMPL_WIDTH 2 /* FLL2_SS_AMPL - [5:4] */

1912

#define ARIZONA_FLL2_SS_FREQ_MASK 0x000C /* FLL2_SS_FREQ - [3:2] */

1913

#define ARIZONA_FLL2_SS_FREQ_SHIFT 2 /* FLL2_SS_FREQ - [3:2] */

1914

#define ARIZONA_FLL2_SS_FREQ_WIDTH 2 /* FLL2_SS_FREQ - [3:2] */

1915

#define ARIZONA_FLL2_SS_SEL_MASK 0x0003 /* FLL2_SS_SEL - [1:0] */

1916

#define ARIZONA_FLL2_SS_SEL_SHIFT 0 /* FLL2_SS_SEL - [1:0] */

1917

#define ARIZONA_FLL2_SS_SEL_WIDTH 2 /* FLL2_SS_SEL - [1:0] */

1918

1919

/*

1920

* R426 (0x1AA) - FLL2 GPIO Clock

1921

*/

1922

#define ARIZONA_FLL2_GPDIV_MASK 0x00FE /* FLL2_GPDIV - [7:1] */

1923

#define ARIZONA_FLL2_GPDIV_SHIFT 1 /* FLL2_GPDIV - [7:1] */

1924

#define ARIZONA_FLL2_GPDIV_WIDTH 7 /* FLL2_GPDIV - [7:1] */

1925

#define ARIZONA_FLL2_GPDIV_ENA 0x0001 /* FLL2_GPDIV_ENA */

1926

#define ARIZONA_FLL2_GPDIV_ENA_MASK 0x0001 /* FLL2_GPDIV_ENA */

1927

#define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */

1928

#define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */

1929

1930

/*

1931

* R512 (0x200) - Mic Charge Pump 1

1932

*/

1933

#define ARIZONA_CPMIC_DISCH 0x0004 /* CPMIC_DISCH */

1934

#define ARIZONA_CPMIC_DISCH_MASK 0x0004 /* CPMIC_DISCH */

1935

#define ARIZONA_CPMIC_DISCH_SHIFT 2 /* CPMIC_DISCH */

1936

#define ARIZONA_CPMIC_DISCH_WIDTH 1 /* CPMIC_DISCH */

1937

#define ARIZONA_CPMIC_BYPASS 0x0002 /* CPMIC_BYPASS */

1938

#define ARIZONA_CPMIC_BYPASS_MASK 0x0002 /* CPMIC_BYPASS */

1939

#define ARIZONA_CPMIC_BYPASS_SHIFT 1 /* CPMIC_BYPASS */

1940

#define ARIZONA_CPMIC_BYPASS_WIDTH 1 /* CPMIC_BYPASS */

1941

#define ARIZONA_CPMIC_ENA 0x0001 /* CPMIC_ENA */

1942

#define ARIZONA_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */

1943

#define ARIZONA_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */

1944

#define ARIZONA_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */

1945

1946

/*

1947

* R528 (0x210) - LDO1 Control 1

1948

*/

1949

#define ARIZONA_LDO1_VSEL_MASK 0x07E0 /* LDO1_VSEL - [10:5] */

1950

#define ARIZONA_LDO1_VSEL_SHIFT 5 /* LDO1_VSEL - [10:5] */

1951

#define ARIZONA_LDO1_VSEL_WIDTH 6 /* LDO1_VSEL - [10:5] */

1952

#define ARIZONA_LDO1_FAST 0x0010 /* LDO1_FAST */

1953

#define ARIZONA_LDO1_FAST_MASK 0x0010 /* LDO1_FAST */

1954

#define ARIZONA_LDO1_FAST_SHIFT 4 /* LDO1_FAST */

1955

#define ARIZONA_LDO1_FAST_WIDTH 1 /* LDO1_FAST */

1956

#define ARIZONA_LDO1_DISCH 0x0004 /* LDO1_DISCH */

1957

#define ARIZONA_LDO1_DISCH_MASK 0x0004 /* LDO1_DISCH */

1958

#define ARIZONA_LDO1_DISCH_SHIFT 2 /* LDO1_DISCH */

1959

#define ARIZONA_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */

1960

#define ARIZONA_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */

1961

#define ARIZONA_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */

1962

#define ARIZONA_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */

1963

#define ARIZONA_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */

1964

#define ARIZONA_LDO1_ENA 0x0001 /* LDO1_ENA */

1965

#define ARIZONA_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */

1966

#define ARIZONA_LDO1_ENA_SHIFT 0 /* LDO1_ENA */

1967

#define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */

1968

1969

/*

Mark Brown

2012-11-27 18:48:33 +0000

[diff] [blame]

1970

* R530 (0x212) - LDO1 Control 2

1971

*/

1972

#define ARIZONA_LDO1_HI_PWR 0x0001 /* LDO1_HI_PWR */

1973

#define ARIZONA_LDO1_HI_PWR_SHIFT 0 /* LDO1_HI_PWR */

1974

#define ARIZONA_LDO1_HI_PWR_WIDTH 1 /* LDO1_HI_PWR */

1975

1976

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

1977

* R531 (0x213) - LDO2 Control 1

1978

*/

1979

#define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */

1980

#define ARIZONA_LDO2_VSEL_SHIFT 5 /* LDO2_VSEL - [10:5] */

1981

#define ARIZONA_LDO2_VSEL_WIDTH 6 /* LDO2_VSEL - [10:5] */

1982

#define ARIZONA_LDO2_FAST 0x0010 /* LDO2_FAST */

1983

#define ARIZONA_LDO2_FAST_MASK 0x0010 /* LDO2_FAST */

1984

#define ARIZONA_LDO2_FAST_SHIFT 4 /* LDO2_FAST */

1985

#define ARIZONA_LDO2_FAST_WIDTH 1 /* LDO2_FAST */

1986

#define ARIZONA_LDO2_DISCH 0x0004 /* LDO2_DISCH */

1987

#define ARIZONA_LDO2_DISCH_MASK 0x0004 /* LDO2_DISCH */

1988

#define ARIZONA_LDO2_DISCH_SHIFT 2 /* LDO2_DISCH */

1989

#define ARIZONA_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */

1990

#define ARIZONA_LDO2_BYPASS 0x0002 /* LDO2_BYPASS */

1991

#define ARIZONA_LDO2_BYPASS_MASK 0x0002 /* LDO2_BYPASS */

1992

#define ARIZONA_LDO2_BYPASS_SHIFT 1 /* LDO2_BYPASS */

1993

#define ARIZONA_LDO2_BYPASS_WIDTH 1 /* LDO2_BYPASS */

1994

#define ARIZONA_LDO2_ENA 0x0001 /* LDO2_ENA */

1995

#define ARIZONA_LDO2_ENA_MASK 0x0001 /* LDO2_ENA */

1996

#define ARIZONA_LDO2_ENA_SHIFT 0 /* LDO2_ENA */

1997

#define ARIZONA_LDO2_ENA_WIDTH 1 /* LDO2_ENA */

1998

1999

/*

2000

* R536 (0x218) - Mic Bias Ctrl 1

2001

*/

2002

#define ARIZONA_MICB1_EXT_CAP 0x8000 /* MICB1_EXT_CAP */

2003

#define ARIZONA_MICB1_EXT_CAP_MASK 0x8000 /* MICB1_EXT_CAP */

2004

#define ARIZONA_MICB1_EXT_CAP_SHIFT 15 /* MICB1_EXT_CAP */

2005

#define ARIZONA_MICB1_EXT_CAP_WIDTH 1 /* MICB1_EXT_CAP */

2006

#define ARIZONA_MICB1_LVL_MASK 0x01E0 /* MICB1_LVL - [8:5] */

2007

#define ARIZONA_MICB1_LVL_SHIFT 5 /* MICB1_LVL - [8:5] */

2008

#define ARIZONA_MICB1_LVL_WIDTH 4 /* MICB1_LVL - [8:5] */

2009

#define ARIZONA_MICB1_FAST 0x0010 /* MICB1_FAST */

2010

#define ARIZONA_MICB1_FAST_MASK 0x0010 /* MICB1_FAST */

2011

#define ARIZONA_MICB1_FAST_SHIFT 4 /* MICB1_FAST */

2012

#define ARIZONA_MICB1_FAST_WIDTH 1 /* MICB1_FAST */

2013

#define ARIZONA_MICB1_RATE 0x0008 /* MICB1_RATE */

2014

#define ARIZONA_MICB1_RATE_MASK 0x0008 /* MICB1_RATE */

2015

#define ARIZONA_MICB1_RATE_SHIFT 3 /* MICB1_RATE */

2016

#define ARIZONA_MICB1_RATE_WIDTH 1 /* MICB1_RATE */

2017

#define ARIZONA_MICB1_DISCH 0x0004 /* MICB1_DISCH */

2018

#define ARIZONA_MICB1_DISCH_MASK 0x0004 /* MICB1_DISCH */

2019

#define ARIZONA_MICB1_DISCH_SHIFT 2 /* MICB1_DISCH */

2020

#define ARIZONA_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */

2021

#define ARIZONA_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */

2022

#define ARIZONA_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */

2023

#define ARIZONA_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */

2024

#define ARIZONA_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */

2025

#define ARIZONA_MICB1_ENA 0x0001 /* MICB1_ENA */

2026

#define ARIZONA_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */

2027

#define ARIZONA_MICB1_ENA_SHIFT 0 /* MICB1_ENA */

2028

#define ARIZONA_MICB1_ENA_WIDTH 1 /* MICB1_ENA */

2029

2030

/*

2031

* R537 (0x219) - Mic Bias Ctrl 2

2032

*/

2033

#define ARIZONA_MICB2_EXT_CAP 0x8000 /* MICB2_EXT_CAP */

2034

#define ARIZONA_MICB2_EXT_CAP_MASK 0x8000 /* MICB2_EXT_CAP */

2035

#define ARIZONA_MICB2_EXT_CAP_SHIFT 15 /* MICB2_EXT_CAP */

2036

#define ARIZONA_MICB2_EXT_CAP_WIDTH 1 /* MICB2_EXT_CAP */

2037

#define ARIZONA_MICB2_LVL_MASK 0x01E0 /* MICB2_LVL - [8:5] */

2038

#define ARIZONA_MICB2_LVL_SHIFT 5 /* MICB2_LVL - [8:5] */

2039

#define ARIZONA_MICB2_LVL_WIDTH 4 /* MICB2_LVL - [8:5] */

2040

#define ARIZONA_MICB2_FAST 0x0010 /* MICB2_FAST */

2041

#define ARIZONA_MICB2_FAST_MASK 0x0010 /* MICB2_FAST */

2042

#define ARIZONA_MICB2_FAST_SHIFT 4 /* MICB2_FAST */

2043

#define ARIZONA_MICB2_FAST_WIDTH 1 /* MICB2_FAST */

2044

#define ARIZONA_MICB2_RATE 0x0008 /* MICB2_RATE */

2045

#define ARIZONA_MICB2_RATE_MASK 0x0008 /* MICB2_RATE */

2046

#define ARIZONA_MICB2_RATE_SHIFT 3 /* MICB2_RATE */

2047

#define ARIZONA_MICB2_RATE_WIDTH 1 /* MICB2_RATE */

2048

#define ARIZONA_MICB2_DISCH 0x0004 /* MICB2_DISCH */

2049

#define ARIZONA_MICB2_DISCH_MASK 0x0004 /* MICB2_DISCH */

2050

#define ARIZONA_MICB2_DISCH_SHIFT 2 /* MICB2_DISCH */

2051

#define ARIZONA_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */

2052

#define ARIZONA_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */

2053

#define ARIZONA_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */

2054

#define ARIZONA_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */

2055

#define ARIZONA_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */

2056

#define ARIZONA_MICB2_ENA 0x0001 /* MICB2_ENA */

2057

#define ARIZONA_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */

2058

#define ARIZONA_MICB2_ENA_SHIFT 0 /* MICB2_ENA */

2059

#define ARIZONA_MICB2_ENA_WIDTH 1 /* MICB2_ENA */

2060

2061

/*

2062

* R538 (0x21A) - Mic Bias Ctrl 3

2063

*/

2064

#define ARIZONA_MICB3_EXT_CAP 0x8000 /* MICB3_EXT_CAP */

2065

#define ARIZONA_MICB3_EXT_CAP_MASK 0x8000 /* MICB3_EXT_CAP */

2066

#define ARIZONA_MICB3_EXT_CAP_SHIFT 15 /* MICB3_EXT_CAP */

2067

#define ARIZONA_MICB3_EXT_CAP_WIDTH 1 /* MICB3_EXT_CAP */

2068

#define ARIZONA_MICB3_LVL_MASK 0x01E0 /* MICB3_LVL - [8:5] */

2069

#define ARIZONA_MICB3_LVL_SHIFT 5 /* MICB3_LVL - [8:5] */

2070

#define ARIZONA_MICB3_LVL_WIDTH 4 /* MICB3_LVL - [8:5] */

2071

#define ARIZONA_MICB3_FAST 0x0010 /* MICB3_FAST */

2072

#define ARIZONA_MICB3_FAST_MASK 0x0010 /* MICB3_FAST */

2073

#define ARIZONA_MICB3_FAST_SHIFT 4 /* MICB3_FAST */

2074

#define ARIZONA_MICB3_FAST_WIDTH 1 /* MICB3_FAST */

2075

#define ARIZONA_MICB3_RATE 0x0008 /* MICB3_RATE */

2076

#define ARIZONA_MICB3_RATE_MASK 0x0008 /* MICB3_RATE */

2077

#define ARIZONA_MICB3_RATE_SHIFT 3 /* MICB3_RATE */

2078

#define ARIZONA_MICB3_RATE_WIDTH 1 /* MICB3_RATE */

2079

#define ARIZONA_MICB3_DISCH 0x0004 /* MICB3_DISCH */

2080

#define ARIZONA_MICB3_DISCH_MASK 0x0004 /* MICB3_DISCH */

2081

#define ARIZONA_MICB3_DISCH_SHIFT 2 /* MICB3_DISCH */

2082

#define ARIZONA_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */

2083

#define ARIZONA_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */

2084

#define ARIZONA_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */

2085

#define ARIZONA_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */

2086

#define ARIZONA_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */

2087

#define ARIZONA_MICB3_ENA 0x0001 /* MICB3_ENA */

2088

#define ARIZONA_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */

2089

#define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */

2090

#define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */

2091

2092

/*

2093

* R659 (0x293) - Accessory Detect Mode 1

2094

*/

2095

#define ARIZONA_ACCDET_SRC 0x2000 /* ACCDET_SRC */

2096

#define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */

2097

#define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */

2098

#define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */

2099

#define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */

2100

#define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */

2101

#define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */

2102

2103

/*

2104

* R667 (0x29B) - Headphone Detect 1

2105

*/

Mark Brown

4f34033

2013-01-11 08:55:43 +0900

[diff] [blame]

2106

#define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */

2107

#define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */

2108

#define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

2109

#define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */

2110

#define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */

2111

#define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */

2112

#define ARIZONA_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */

2113

#define ARIZONA_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */

2114

#define ARIZONA_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */

2115

#define ARIZONA_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */

2116

#define ARIZONA_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */

2117

#define ARIZONA_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */

2118

#define ARIZONA_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */

2119

#define ARIZONA_HP_IDAC_STEER 0x0004 /* HP_IDAC_STEER */

2120

#define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */

2121

#define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */

2122

#define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */

2123

#define ARIZONA_HP_RATE 0x0002 /* HP_RATE */

2124

#define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */

2125

#define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */

2126

#define ARIZONA_HP_RATE_WIDTH 1 /* HP_RATE */

2127

#define ARIZONA_HP_POLL 0x0001 /* HP_POLL */

2128

#define ARIZONA_HP_POLL_MASK 0x0001 /* HP_POLL */

2129

#define ARIZONA_HP_POLL_SHIFT 0 /* HP_POLL */

2130

#define ARIZONA_HP_POLL_WIDTH 1 /* HP_POLL */

2131

2132

/*

2133

* R668 (0x29C) - Headphone Detect 2

2134

*/

2135

#define ARIZONA_HP_DONE 0x0080 /* HP_DONE */

2136

#define ARIZONA_HP_DONE_MASK 0x0080 /* HP_DONE */

2137

#define ARIZONA_HP_DONE_SHIFT 7 /* HP_DONE */

2138

#define ARIZONA_HP_DONE_WIDTH 1 /* HP_DONE */

2139

#define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */

2140

#define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */

2141

#define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */

2142

Mark Brown

4f34033

2013-01-11 08:55:43 +0900

[diff] [blame]

2143

#define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */

2144

#define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */

2145

#define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */

2146

#define ARIZONA_HP_DONE_B_WIDTH 1 /* HP_DONE */

2147

#define ARIZONA_HP_LVL_B_MASK 0x7FFF /* HP_LVL - [14:0] */

2148

#define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */

2149

#define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */

2150

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

2151

/*

Mark Brown

2013-01-11 08:55:36 +0900

[diff] [blame]

2152

* R674 (0x2A2) - MICD clamp control

2153

*/

2154

#define ARIZONA_MICD_CLAMP_MODE_MASK 0x000F /* MICD_CLAMP_MODE - [3:0] */

2155

#define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */

2156

#define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */

2157

2158

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

2159

* R675 (0x2A3) - Mic Detect 1

2160

*/

2161

#define ARIZONA_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */

2162

#define ARIZONA_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */

2163

#define ARIZONA_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */

2164

#define ARIZONA_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */

2165

#define ARIZONA_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */

2166

#define ARIZONA_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */

2167

#define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */

2168

#define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */

2169

#define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */

2170

#define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */

2171

#define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */

2172

#define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */

2173

#define ARIZONA_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */

2174

#define ARIZONA_MICD_ENA 0x0001 /* MICD_ENA */

2175

#define ARIZONA_MICD_ENA_MASK 0x0001 /* MICD_ENA */

2176

#define ARIZONA_MICD_ENA_SHIFT 0 /* MICD_ENA */

2177

#define ARIZONA_MICD_ENA_WIDTH 1 /* MICD_ENA */

2178

2179

/*

2180

* R676 (0x2A4) - Mic Detect 2

2181

*/

2182

#define ARIZONA_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */

2183

#define ARIZONA_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */

2184

#define ARIZONA_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */

2185

2186

/*

2187

* R677 (0x2A5) - Mic Detect 3

2188

*/

2189

#define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */

2190

#define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */

2191

#define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */

2192

#define ARIZONA_MICD_VALID 0x0002 /* MICD_VALID */

2193

#define ARIZONA_MICD_VALID_MASK 0x0002 /* MICD_VALID */

2194

#define ARIZONA_MICD_VALID_SHIFT 1 /* MICD_VALID */

2195

#define ARIZONA_MICD_VALID_WIDTH 1 /* MICD_VALID */

2196

#define ARIZONA_MICD_STS 0x0001 /* MICD_STS */

2197

#define ARIZONA_MICD_STS_MASK 0x0001 /* MICD_STS */

2198

#define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */

2199

#define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */

2200

2201

/*

2202

* R707 (0x2C3) - Mic noise mix control 1

2203

*/

2204

#define ARIZONA_MICMUTE_RATE_MASK 0x7800 /* MICMUTE_RATE - [14:11] */

2205

#define ARIZONA_MICMUTE_RATE_SHIFT 11 /* MICMUTE_RATE - [14:11] */

2206

#define ARIZONA_MICMUTE_RATE_WIDTH 4 /* MICMUTE_RATE - [14:11] */

2207

#define ARIZONA_MICMUTE_MIX_ENA 0x0040 /* MICMUTE_MIX_ENA */

2208

#define ARIZONA_MICMUTE_MIX_ENA_MASK 0x0040 /* MICMUTE_MIX_ENA */

2209

#define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */

2210

#define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */

2211

2212

/*

2213

* R715 (0x2CB) - Isolation control

2214

*/

2215

#define ARIZONA_ISOLATE_DCVDD1 0x0001 /* ISOLATE_DCVDD1 */

2216

#define ARIZONA_ISOLATE_DCVDD1_MASK 0x0001 /* ISOLATE_DCVDD1 */

2217

#define ARIZONA_ISOLATE_DCVDD1_SHIFT 0 /* ISOLATE_DCVDD1 */

2218

#define ARIZONA_ISOLATE_DCVDD1_WIDTH 1 /* ISOLATE_DCVDD1 */

2219

2220

/*

2221

* R723 (0x2D3) - Jack detect analogue

2222

*/

2223

#define ARIZONA_JD2_ENA 0x0002 /* JD2_ENA */

2224

#define ARIZONA_JD2_ENA_MASK 0x0002 /* JD2_ENA */

2225

#define ARIZONA_JD2_ENA_SHIFT 1 /* JD2_ENA */

2226

#define ARIZONA_JD2_ENA_WIDTH 1 /* JD2_ENA */

2227

#define ARIZONA_JD1_ENA 0x0001 /* JD1_ENA */

2228

#define ARIZONA_JD1_ENA_MASK 0x0001 /* JD1_ENA */

2229

#define ARIZONA_JD1_ENA_SHIFT 0 /* JD1_ENA */

2230

#define ARIZONA_JD1_ENA_WIDTH 1 /* JD1_ENA */

2231

2232

/*

2233

* R768 (0x300) - Input Enables

2234

*/

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

2235

#define ARIZONA_IN4L_ENA 0x0080 /* IN4L_ENA */

2236

#define ARIZONA_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */

2237

#define ARIZONA_IN4L_ENA_SHIFT 7 /* IN4L_ENA */

2238

#define ARIZONA_IN4L_ENA_WIDTH 1 /* IN4L_ENA */

2239

#define ARIZONA_IN4R_ENA 0x0040 /* IN4R_ENA */

2240

#define ARIZONA_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */

2241

#define ARIZONA_IN4R_ENA_SHIFT 6 /* IN4R_ENA */

2242

#define ARIZONA_IN4R_ENA_WIDTH 1 /* IN4R_ENA */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

2243

#define ARIZONA_IN3L_ENA 0x0020 /* IN3L_ENA */

2244

#define ARIZONA_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */

2245

#define ARIZONA_IN3L_ENA_SHIFT 5 /* IN3L_ENA */

2246

#define ARIZONA_IN3L_ENA_WIDTH 1 /* IN3L_ENA */

2247

#define ARIZONA_IN3R_ENA 0x0010 /* IN3R_ENA */

2248

#define ARIZONA_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */

2249

#define ARIZONA_IN3R_ENA_SHIFT 4 /* IN3R_ENA */

2250

#define ARIZONA_IN3R_ENA_WIDTH 1 /* IN3R_ENA */

2251

#define ARIZONA_IN2L_ENA 0x0008 /* IN2L_ENA */

2252

#define ARIZONA_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */

2253

#define ARIZONA_IN2L_ENA_SHIFT 3 /* IN2L_ENA */

2254

#define ARIZONA_IN2L_ENA_WIDTH 1 /* IN2L_ENA */

2255

#define ARIZONA_IN2R_ENA 0x0004 /* IN2R_ENA */

2256

#define ARIZONA_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */

2257

#define ARIZONA_IN2R_ENA_SHIFT 2 /* IN2R_ENA */

2258

#define ARIZONA_IN2R_ENA_WIDTH 1 /* IN2R_ENA */

2259

#define ARIZONA_IN1L_ENA 0x0002 /* IN1L_ENA */

2260

#define ARIZONA_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */

2261

#define ARIZONA_IN1L_ENA_SHIFT 1 /* IN1L_ENA */

2262

#define ARIZONA_IN1L_ENA_WIDTH 1 /* IN1L_ENA */

2263

#define ARIZONA_IN1R_ENA 0x0001 /* IN1R_ENA */

2264

#define ARIZONA_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */

2265

#define ARIZONA_IN1R_ENA_SHIFT 0 /* IN1R_ENA */

2266

#define ARIZONA_IN1R_ENA_WIDTH 1 /* IN1R_ENA */

2267

2268

/*

2269

* R776 (0x308) - Input Rate

2270

*/

2271

#define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */

2272

#define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */

2273

#define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */

2274

2275

/*

2276

* R777 (0x309) - Input Volume Ramp

2277

*/

2278

#define ARIZONA_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */

2279

#define ARIZONA_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */

2280

#define ARIZONA_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */

2281

#define ARIZONA_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */

2282

#define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */

2283

#define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */

2284

2285

/*

2286

* R784 (0x310) - IN1L Control

2287

*/

2288

#define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */

2289

#define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */

2290

#define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */

2291

#define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */

2292

#define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */

2293

#define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */

2294

#define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */

2295

#define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */

2296

#define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */

2297

#define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */

2298

#define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */

2299

#define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */

2300

2301

/*

2302

* R785 (0x311) - ADC Digital Volume 1L

2303

*/

2304

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2305

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2306

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2307

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2308

#define ARIZONA_IN1L_MUTE 0x0100 /* IN1L_MUTE */

2309

#define ARIZONA_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */

2310

#define ARIZONA_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */

2311

#define ARIZONA_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */

2312

#define ARIZONA_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */

2313

#define ARIZONA_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */

2314

#define ARIZONA_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */

2315

2316

/*

2317

* R786 (0x312) - DMIC1L Control

2318

*/

2319

#define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */

2320

#define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */

2321

#define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */

2322

2323

/*

2324

* R788 (0x314) - IN1R Control

2325

*/

2326

#define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */

2327

#define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */

2328

#define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */

2329

2330

/*

2331

* R789 (0x315) - ADC Digital Volume 1R

2332

*/

2333

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2334

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2335

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2336

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2337

#define ARIZONA_IN1R_MUTE 0x0100 /* IN1R_MUTE */

2338

#define ARIZONA_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */

2339

#define ARIZONA_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */

2340

#define ARIZONA_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */

2341

#define ARIZONA_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */

2342

#define ARIZONA_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */

2343

#define ARIZONA_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */

2344

2345

/*

2346

* R790 (0x316) - DMIC1R Control

2347

*/

2348

#define ARIZONA_IN1_DMICR_DLY_MASK 0x003F /* IN1_DMICR_DLY - [5:0] */

2349

#define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */

2350

#define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */

2351

2352

/*

2353

* R792 (0x318) - IN2L Control

2354

*/

2355

#define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */

2356

#define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */

2357

#define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */

2358

#define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */

2359

#define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */

2360

#define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */

2361

#define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */

2362

#define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */

2363

#define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */

2364

#define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */

2365

#define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */

2366

#define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */

2367

2368

/*

2369

* R793 (0x319) - ADC Digital Volume 2L

2370

*/

2371

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2372

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2373

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2374

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2375

#define ARIZONA_IN2L_MUTE 0x0100 /* IN2L_MUTE */

2376

#define ARIZONA_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */

2377

#define ARIZONA_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */

2378

#define ARIZONA_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */

2379

#define ARIZONA_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */

2380

#define ARIZONA_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */

2381

#define ARIZONA_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */

2382

2383

/*

2384

* R794 (0x31A) - DMIC2L Control

2385

*/

2386

#define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */

2387

#define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */

2388

#define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */

2389

2390

/*

2391

* R796 (0x31C) - IN2R Control

2392

*/

2393

#define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */

2394

#define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */

2395

#define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */

2396

2397

/*

2398

* R797 (0x31D) - ADC Digital Volume 2R

2399

*/

2400

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2401

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2402

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2403

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2404

#define ARIZONA_IN2R_MUTE 0x0100 /* IN2R_MUTE */

2405

#define ARIZONA_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */

2406

#define ARIZONA_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */

2407

#define ARIZONA_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */

2408

#define ARIZONA_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */

2409

#define ARIZONA_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */

2410

#define ARIZONA_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */

2411

2412

/*

2413

* R798 (0x31E) - DMIC2R Control

2414

*/

2415

#define ARIZONA_IN2_DMICR_DLY_MASK 0x003F /* IN2_DMICR_DLY - [5:0] */

2416

#define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */

2417

#define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */

2418

2419

/*

2420

* R800 (0x320) - IN3L Control

2421

*/

2422

#define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */

2423

#define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */

2424

#define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */

2425

#define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */

2426

#define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */

2427

#define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */

2428

#define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */

2429

#define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */

2430

#define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */

2431

#define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */

2432

#define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */

2433

#define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */

2434

2435

/*

2436

* R801 (0x321) - ADC Digital Volume 3L

2437

*/

2438

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2439

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2440

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2441

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2442

#define ARIZONA_IN3L_MUTE 0x0100 /* IN3L_MUTE */

2443

#define ARIZONA_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */

2444

#define ARIZONA_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */

2445

#define ARIZONA_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */

2446

#define ARIZONA_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */

2447

#define ARIZONA_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */

2448

#define ARIZONA_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */

2449

2450

/*

2451

* R802 (0x322) - DMIC3L Control

2452

*/

2453

#define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */

2454

#define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */

2455

#define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */

2456

2457

/*

2458

* R804 (0x324) - IN3R Control

2459

*/

2460

#define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */

2461

#define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */

2462

#define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */

2463

2464

/*

2465

* R805 (0x325) - ADC Digital Volume 3R

2466

*/

2467

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2468

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2469

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2470

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2471

#define ARIZONA_IN3R_MUTE 0x0100 /* IN3R_MUTE */

2472

#define ARIZONA_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */

2473

#define ARIZONA_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */

2474

#define ARIZONA_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */

2475

#define ARIZONA_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */

2476

#define ARIZONA_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */

2477

#define ARIZONA_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */

2478

2479

/*

2480

* R806 (0x326) - DMIC3R Control

2481

*/

2482

#define ARIZONA_IN3_DMICR_DLY_MASK 0x003F /* IN3_DMICR_DLY - [5:0] */

2483

#define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */

2484

#define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */

2485

2486

/*

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

2487

* R808 (0x328) - IN4 Control

2488

*/

2489

#define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */

2490

#define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */

2491

#define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */

2492

#define ARIZONA_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */

2493

#define ARIZONA_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */

2494

#define ARIZONA_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */

2495

2496

/*

2497

* R809 (0x329) - ADC Digital Volume 4L

2498

*/

2499

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2500

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2501

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2502

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2503

#define ARIZONA_IN4L_MUTE 0x0100 /* IN4L_MUTE */

2504

#define ARIZONA_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */

2505

#define ARIZONA_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */

2506

#define ARIZONA_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */

2507

#define ARIZONA_IN4L_DIG_VOL_MASK 0x00FF /* IN4L_DIG_VOL - [7:0] */

2508

#define ARIZONA_IN4L_DIG_VOL_SHIFT 0 /* IN4L_DIG_VOL - [7:0] */

2509

#define ARIZONA_IN4L_DIG_VOL_WIDTH 8 /* IN4L_DIG_VOL - [7:0] */

2510

2511

/*

2512

* R810 (0x32A) - DMIC4L Control

2513

*/

2514

#define ARIZONA_IN4L_DMIC_DLY_MASK 0x003F /* IN4L_DMIC_DLY - [5:0] */

2515

#define ARIZONA_IN4L_DMIC_DLY_SHIFT 0 /* IN4L_DMIC_DLY - [5:0] */

2516

#define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */

2517

2518

/*

2519

* R813 (0x32D) - ADC Digital Volume 4R

2520

*/

2521

#define ARIZONA_IN_VU 0x0200 /* IN_VU */

2522

#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */

2523

#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */

2524

#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */

2525

#define ARIZONA_IN4R_MUTE 0x0100 /* IN4R_MUTE */

2526

#define ARIZONA_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */

2527

#define ARIZONA_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */

2528

#define ARIZONA_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */

2529

#define ARIZONA_IN4R_DIG_VOL_MASK 0x00FF /* IN4R_DIG_VOL - [7:0] */

2530

#define ARIZONA_IN4R_DIG_VOL_SHIFT 0 /* IN4R_DIG_VOL - [7:0] */

2531

#define ARIZONA_IN4R_DIG_VOL_WIDTH 8 /* IN4R_DIG_VOL - [7:0] */

2532

2533

/*

2534

* R814 (0x32E) - DMIC4R Control

2535

*/

2536

#define ARIZONA_IN4R_DMIC_DLY_MASK 0x003F /* IN4R_DMIC_DLY - [5:0] */

2537

#define ARIZONA_IN4R_DMIC_DLY_SHIFT 0 /* IN4R_DMIC_DLY - [5:0] */

2538

#define ARIZONA_IN4R_DMIC_DLY_WIDTH 6 /* IN4R_DMIC_DLY - [5:0] */

2539

2540

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

2541

* R1024 (0x400) - Output Enables 1

2542

*/

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

2543

#define ARIZONA_OUT6L_ENA 0x0800 /* OUT6L_ENA */

2544

#define ARIZONA_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */

2545

#define ARIZONA_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */

2546

#define ARIZONA_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */

2547

#define ARIZONA_OUT6R_ENA 0x0400 /* OUT6R_ENA */

2548

#define ARIZONA_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */

2549

#define ARIZONA_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */

2550

#define ARIZONA_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

2551

#define ARIZONA_OUT5L_ENA 0x0200 /* OUT5L_ENA */

2552

#define ARIZONA_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */

2553

#define ARIZONA_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */

2554

#define ARIZONA_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */

2555

#define ARIZONA_OUT5R_ENA 0x0100 /* OUT5R_ENA */

2556

#define ARIZONA_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */

2557

#define ARIZONA_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */

2558

#define ARIZONA_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */

2559

#define ARIZONA_OUT4L_ENA 0x0080 /* OUT4L_ENA */

2560

#define ARIZONA_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */

2561

#define ARIZONA_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */

2562

#define ARIZONA_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */

2563

#define ARIZONA_OUT4R_ENA 0x0040 /* OUT4R_ENA */

2564

#define ARIZONA_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */

2565

#define ARIZONA_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */

2566

#define ARIZONA_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */

2567

#define ARIZONA_OUT3L_ENA 0x0020 /* OUT3L_ENA */

2568

#define ARIZONA_OUT3L_ENA_MASK 0x0020 /* OUT3L_ENA */

2569

#define ARIZONA_OUT3L_ENA_SHIFT 5 /* OUT3L_ENA */

2570

#define ARIZONA_OUT3L_ENA_WIDTH 1 /* OUT3L_ENA */

2571

#define ARIZONA_OUT3R_ENA 0x0010 /* OUT3R_ENA */

2572

#define ARIZONA_OUT3R_ENA_MASK 0x0010 /* OUT3R_ENA */

2573

#define ARIZONA_OUT3R_ENA_SHIFT 4 /* OUT3R_ENA */

2574

#define ARIZONA_OUT3R_ENA_WIDTH 1 /* OUT3R_ENA */

2575

#define ARIZONA_OUT2L_ENA 0x0008 /* OUT2L_ENA */

2576

#define ARIZONA_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */

2577

#define ARIZONA_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */

2578

#define ARIZONA_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */

2579

#define ARIZONA_OUT2R_ENA 0x0004 /* OUT2R_ENA */

2580

#define ARIZONA_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */

2581

#define ARIZONA_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */

2582

#define ARIZONA_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */

2583

#define ARIZONA_OUT1L_ENA 0x0002 /* OUT1L_ENA */

2584

#define ARIZONA_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */

2585

#define ARIZONA_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */

2586

#define ARIZONA_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */

2587

#define ARIZONA_OUT1R_ENA 0x0001 /* OUT1R_ENA */

2588

#define ARIZONA_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */

2589

#define ARIZONA_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */

2590

#define ARIZONA_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */

2591

2592

/*

2593

* R1025 (0x401) - Output Status 1

2594

*/

2595

#define ARIZONA_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */

2596

#define ARIZONA_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */

2597

#define ARIZONA_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */

2598

#define ARIZONA_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */

2599

#define ARIZONA_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */

2600

#define ARIZONA_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */

2601

#define ARIZONA_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */

2602

#define ARIZONA_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */

2603

#define ARIZONA_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */

2604

#define ARIZONA_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */

2605

#define ARIZONA_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */

2606

#define ARIZONA_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */

2607

#define ARIZONA_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */

2608

#define ARIZONA_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */

2609

#define ARIZONA_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */

2610

#define ARIZONA_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */

2611

#define ARIZONA_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */

2612

#define ARIZONA_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */

2613

#define ARIZONA_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */

2614

#define ARIZONA_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */

2615

#define ARIZONA_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */

2616

#define ARIZONA_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */

2617

#define ARIZONA_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */

2618

#define ARIZONA_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */

2619

2620

/*

2621

* R1032 (0x408) - Output Rate 1

2622

*/

2623

#define ARIZONA_OUT_RATE_MASK 0x7800 /* OUT_RATE - [14:11] */

2624

#define ARIZONA_OUT_RATE_SHIFT 11 /* OUT_RATE - [14:11] */

2625

#define ARIZONA_OUT_RATE_WIDTH 4 /* OUT_RATE - [14:11] */

2626

2627

/*

2628

* R1033 (0x409) - Output Volume Ramp

2629

*/

2630

#define ARIZONA_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */

2631

#define ARIZONA_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */

2632

#define ARIZONA_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */

2633

#define ARIZONA_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */

2634

#define ARIZONA_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */

2635

#define ARIZONA_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */

2636

2637

/*

2638

* R1040 (0x410) - Output Path Config 1L

2639

*/

2640

#define ARIZONA_OUT1_LP_MODE 0x8000 /* OUT1_LP_MODE */

2641

#define ARIZONA_OUT1_LP_MODE_MASK 0x8000 /* OUT1_LP_MODE */

2642

#define ARIZONA_OUT1_LP_MODE_SHIFT 15 /* OUT1_LP_MODE */

2643

#define ARIZONA_OUT1_LP_MODE_WIDTH 1 /* OUT1_LP_MODE */

2644

#define ARIZONA_OUT1_OSR 0x2000 /* OUT1_OSR */

2645

#define ARIZONA_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */

2646

#define ARIZONA_OUT1_OSR_SHIFT 13 /* OUT1_OSR */

2647

#define ARIZONA_OUT1_OSR_WIDTH 1 /* OUT1_OSR */

2648

#define ARIZONA_OUT1_MONO 0x1000 /* OUT1_MONO */

2649

#define ARIZONA_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */

2650

#define ARIZONA_OUT1_MONO_SHIFT 12 /* OUT1_MONO */

2651

#define ARIZONA_OUT1_MONO_WIDTH 1 /* OUT1_MONO */

2652

#define ARIZONA_OUT1L_ANC_SRC_MASK 0x0C00 /* OUT1L_ANC_SRC - [11:10] */

2653

#define ARIZONA_OUT1L_ANC_SRC_SHIFT 10 /* OUT1L_ANC_SRC - [11:10] */

2654

#define ARIZONA_OUT1L_ANC_SRC_WIDTH 2 /* OUT1L_ANC_SRC - [11:10] */

2655

#define ARIZONA_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */

2656

#define ARIZONA_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */

2657

#define ARIZONA_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */

2658

2659

/*

2660

* R1041 (0x411) - DAC Digital Volume 1L

2661

*/

2662

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2663

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2664

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2665

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2666

#define ARIZONA_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */

2667

#define ARIZONA_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */

2668

#define ARIZONA_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */

2669

#define ARIZONA_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */

2670

#define ARIZONA_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */

2671

#define ARIZONA_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */

2672

#define ARIZONA_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */

2673

2674

/*

2675

* R1042 (0x412) - DAC Volume Limit 1L

2676

*/

2677

#define ARIZONA_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */

2678

#define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */

2679

#define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */

2680

2681

/*

2682

* R1043 (0x413) - Noise Gate Select 1L

2683

*/

2684

#define ARIZONA_OUT1L_NGATE_SRC_MASK 0x0FFF /* OUT1L_NGATE_SRC - [11:0] */

2685

#define ARIZONA_OUT1L_NGATE_SRC_SHIFT 0 /* OUT1L_NGATE_SRC - [11:0] */

2686

#define ARIZONA_OUT1L_NGATE_SRC_WIDTH 12 /* OUT1L_NGATE_SRC - [11:0] */

2687

2688

/*

2689

* R1044 (0x414) - Output Path Config 1R

2690

*/

2691

#define ARIZONA_OUT1R_ANC_SRC_MASK 0x0C00 /* OUT1R_ANC_SRC - [11:10] */

2692

#define ARIZONA_OUT1R_ANC_SRC_SHIFT 10 /* OUT1R_ANC_SRC - [11:10] */

2693

#define ARIZONA_OUT1R_ANC_SRC_WIDTH 2 /* OUT1R_ANC_SRC - [11:10] */

2694

#define ARIZONA_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */

2695

#define ARIZONA_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */

2696

#define ARIZONA_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */

2697

2698

/*

2699

* R1045 (0x415) - DAC Digital Volume 1R

2700

*/

2701

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2702

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2703

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2704

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2705

#define ARIZONA_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */

2706

#define ARIZONA_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */

2707

#define ARIZONA_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */

2708

#define ARIZONA_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */

2709

#define ARIZONA_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */

2710

#define ARIZONA_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */

2711

#define ARIZONA_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */

2712

2713

/*

2714

* R1046 (0x416) - DAC Volume Limit 1R

2715

*/

2716

#define ARIZONA_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */

2717

#define ARIZONA_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */

2718

#define ARIZONA_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */

2719

2720

/*

2721

* R1047 (0x417) - Noise Gate Select 1R

2722

*/

2723

#define ARIZONA_OUT1R_NGATE_SRC_MASK 0x0FFF /* OUT1R_NGATE_SRC - [11:0] */

2724

#define ARIZONA_OUT1R_NGATE_SRC_SHIFT 0 /* OUT1R_NGATE_SRC - [11:0] */

2725

#define ARIZONA_OUT1R_NGATE_SRC_WIDTH 12 /* OUT1R_NGATE_SRC - [11:0] */

2726

2727

/*

2728

* R1048 (0x418) - Output Path Config 2L

2729

*/

2730

#define ARIZONA_OUT2_LP_MODE 0x8000 /* OUT2_LP_MODE */

2731

#define ARIZONA_OUT2_LP_MODE_MASK 0x8000 /* OUT2_LP_MODE */

2732

#define ARIZONA_OUT2_LP_MODE_SHIFT 15 /* OUT2_LP_MODE */

2733

#define ARIZONA_OUT2_LP_MODE_WIDTH 1 /* OUT2_LP_MODE */

2734

#define ARIZONA_OUT2_OSR 0x2000 /* OUT2_OSR */

2735

#define ARIZONA_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */

2736

#define ARIZONA_OUT2_OSR_SHIFT 13 /* OUT2_OSR */

2737

#define ARIZONA_OUT2_OSR_WIDTH 1 /* OUT2_OSR */

2738

#define ARIZONA_OUT2_MONO 0x1000 /* OUT2_MONO */

2739

#define ARIZONA_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */

2740

#define ARIZONA_OUT2_MONO_SHIFT 12 /* OUT2_MONO */

2741

#define ARIZONA_OUT2_MONO_WIDTH 1 /* OUT2_MONO */

2742

#define ARIZONA_OUT2L_ANC_SRC_MASK 0x0C00 /* OUT2L_ANC_SRC - [11:10] */

2743

#define ARIZONA_OUT2L_ANC_SRC_SHIFT 10 /* OUT2L_ANC_SRC - [11:10] */

2744

#define ARIZONA_OUT2L_ANC_SRC_WIDTH 2 /* OUT2L_ANC_SRC - [11:10] */

2745

#define ARIZONA_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */

2746

#define ARIZONA_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */

2747

#define ARIZONA_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */

2748

2749

/*

2750

* R1049 (0x419) - DAC Digital Volume 2L

2751

*/

2752

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2753

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2754

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2755

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2756

#define ARIZONA_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */

2757

#define ARIZONA_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */

2758

#define ARIZONA_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */

2759

#define ARIZONA_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */

2760

#define ARIZONA_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */

2761

#define ARIZONA_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */

2762

#define ARIZONA_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */

2763

2764

/*

2765

* R1050 (0x41A) - DAC Volume Limit 2L

2766

*/

2767

#define ARIZONA_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */

2768

#define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */

2769

#define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */

2770

2771

/*

2772

* R1051 (0x41B) - Noise Gate Select 2L

2773

*/

2774

#define ARIZONA_OUT2L_NGATE_SRC_MASK 0x0FFF /* OUT2L_NGATE_SRC - [11:0] */

2775

#define ARIZONA_OUT2L_NGATE_SRC_SHIFT 0 /* OUT2L_NGATE_SRC - [11:0] */

2776

#define ARIZONA_OUT2L_NGATE_SRC_WIDTH 12 /* OUT2L_NGATE_SRC - [11:0] */

2777

2778

/*

2779

* R1052 (0x41C) - Output Path Config 2R

2780

*/

2781

#define ARIZONA_OUT2R_ANC_SRC_MASK 0x0C00 /* OUT2R_ANC_SRC - [11:10] */

2782

#define ARIZONA_OUT2R_ANC_SRC_SHIFT 10 /* OUT2R_ANC_SRC - [11:10] */

2783

#define ARIZONA_OUT2R_ANC_SRC_WIDTH 2 /* OUT2R_ANC_SRC - [11:10] */

2784

#define ARIZONA_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */

2785

#define ARIZONA_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */

2786

#define ARIZONA_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */

2787

2788

/*

2789

* R1053 (0x41D) - DAC Digital Volume 2R

2790

*/

2791

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2792

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2793

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2794

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2795

#define ARIZONA_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */

2796

#define ARIZONA_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */

2797

#define ARIZONA_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */

2798

#define ARIZONA_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */

2799

#define ARIZONA_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */

2800

#define ARIZONA_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */

2801

#define ARIZONA_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */

2802

2803

/*

2804

* R1054 (0x41E) - DAC Volume Limit 2R

2805

*/

2806

#define ARIZONA_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */

2807

#define ARIZONA_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */

2808

#define ARIZONA_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */

2809

2810

/*

2811

* R1055 (0x41F) - Noise Gate Select 2R

2812

*/

2813

#define ARIZONA_OUT2R_NGATE_SRC_MASK 0x0FFF /* OUT2R_NGATE_SRC - [11:0] */

2814

#define ARIZONA_OUT2R_NGATE_SRC_SHIFT 0 /* OUT2R_NGATE_SRC - [11:0] */

2815

#define ARIZONA_OUT2R_NGATE_SRC_WIDTH 12 /* OUT2R_NGATE_SRC - [11:0] */

2816

2817

/*

2818

* R1056 (0x420) - Output Path Config 3L

2819

*/

2820

#define ARIZONA_OUT3_LP_MODE 0x8000 /* OUT3_LP_MODE */

2821

#define ARIZONA_OUT3_LP_MODE_MASK 0x8000 /* OUT3_LP_MODE */

2822

#define ARIZONA_OUT3_LP_MODE_SHIFT 15 /* OUT3_LP_MODE */

2823

#define ARIZONA_OUT3_LP_MODE_WIDTH 1 /* OUT3_LP_MODE */

2824

#define ARIZONA_OUT3_OSR 0x2000 /* OUT3_OSR */

2825

#define ARIZONA_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */

2826

#define ARIZONA_OUT3_OSR_SHIFT 13 /* OUT3_OSR */

2827

#define ARIZONA_OUT3_OSR_WIDTH 1 /* OUT3_OSR */

2828

#define ARIZONA_OUT3_MONO 0x1000 /* OUT3_MONO */

2829

#define ARIZONA_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */

2830

#define ARIZONA_OUT3_MONO_SHIFT 12 /* OUT3_MONO */

2831

#define ARIZONA_OUT3_MONO_WIDTH 1 /* OUT3_MONO */

2832

#define ARIZONA_OUT3L_ANC_SRC_MASK 0x0C00 /* OUT3L_ANC_SRC - [11:10] */

2833

#define ARIZONA_OUT3L_ANC_SRC_SHIFT 10 /* OUT3L_ANC_SRC - [11:10] */

2834

#define ARIZONA_OUT3L_ANC_SRC_WIDTH 2 /* OUT3L_ANC_SRC - [11:10] */

2835

#define ARIZONA_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */

2836

#define ARIZONA_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */

2837

#define ARIZONA_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */

2838

2839

/*

2840

* R1057 (0x421) - DAC Digital Volume 3L

2841

*/

2842

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2843

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2844

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2845

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2846

#define ARIZONA_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */

2847

#define ARIZONA_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */

2848

#define ARIZONA_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */

2849

#define ARIZONA_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */

2850

#define ARIZONA_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */

2851

#define ARIZONA_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */

2852

#define ARIZONA_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */

2853

2854

/*

2855

* R1058 (0x422) - DAC Volume Limit 3L

2856

*/

2857

#define ARIZONA_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */

2858

#define ARIZONA_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */

2859

#define ARIZONA_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */

2860

2861

/*

2862

* R1059 (0x423) - Noise Gate Select 3L

2863

*/

2864

#define ARIZONA_OUT3_NGATE_SRC_MASK 0x0FFF /* OUT3_NGATE_SRC - [11:0] */

2865

#define ARIZONA_OUT3_NGATE_SRC_SHIFT 0 /* OUT3_NGATE_SRC - [11:0] */

2866

#define ARIZONA_OUT3_NGATE_SRC_WIDTH 12 /* OUT3_NGATE_SRC - [11:0] */

2867

2868

/*

2869

* R1060 (0x424) - Output Path Config 3R

2870

*/

2871

#define ARIZONA_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */

2872

#define ARIZONA_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */

2873

#define ARIZONA_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */

2874

2875

/*

2876

* R1061 (0x425) - DAC Digital Volume 3R

2877

*/

2878

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2879

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2880

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2881

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2882

#define ARIZONA_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */

2883

#define ARIZONA_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */

2884

#define ARIZONA_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */

2885

#define ARIZONA_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */

2886

#define ARIZONA_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */

2887

#define ARIZONA_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */

2888

#define ARIZONA_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */

2889

2890

/*

2891

* R1062 (0x426) - DAC Volume Limit 3R

2892

*/

2893

#define ARIZONA_OUT3R_ANC_SRC_MASK 0x0C00 /* OUT3R_ANC_SRC - [11:10] */

2894

#define ARIZONA_OUT3R_ANC_SRC_SHIFT 10 /* OUT3R_ANC_SRC - [11:10] */

2895

#define ARIZONA_OUT3R_ANC_SRC_WIDTH 2 /* OUT3R_ANC_SRC - [11:10] */

2896

#define ARIZONA_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */

2897

#define ARIZONA_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */

2898

#define ARIZONA_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */

2899

2900

/*

2901

* R1064 (0x428) - Output Path Config 4L

2902

*/

2903

#define ARIZONA_OUT4_OSR 0x2000 /* OUT4_OSR */

2904

#define ARIZONA_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */

2905

#define ARIZONA_OUT4_OSR_SHIFT 13 /* OUT4_OSR */

2906

#define ARIZONA_OUT4_OSR_WIDTH 1 /* OUT4_OSR */

2907

#define ARIZONA_OUT4L_ANC_SRC_MASK 0x0C00 /* OUT4L_ANC_SRC - [11:10] */

2908

#define ARIZONA_OUT4L_ANC_SRC_SHIFT 10 /* OUT4L_ANC_SRC - [11:10] */

2909

#define ARIZONA_OUT4L_ANC_SRC_WIDTH 2 /* OUT4L_ANC_SRC - [11:10] */

2910

2911

/*

2912

* R1065 (0x429) - DAC Digital Volume 4L

2913

*/

2914

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2915

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2916

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2917

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2918

#define ARIZONA_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */

2919

#define ARIZONA_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */

2920

#define ARIZONA_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */

2921

#define ARIZONA_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */

2922

#define ARIZONA_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */

2923

#define ARIZONA_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */

2924

#define ARIZONA_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */

2925

2926

/*

2927

* R1066 (0x42A) - Out Volume 4L

2928

*/

2929

#define ARIZONA_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */

2930

#define ARIZONA_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */

2931

#define ARIZONA_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */

2932

2933

/*

2934

* R1067 (0x42B) - Noise Gate Select 4L

2935

*/

2936

#define ARIZONA_OUT4L_NGATE_SRC_MASK 0x0FFF /* OUT4L_NGATE_SRC - [11:0] */

2937

#define ARIZONA_OUT4L_NGATE_SRC_SHIFT 0 /* OUT4L_NGATE_SRC - [11:0] */

2938

#define ARIZONA_OUT4L_NGATE_SRC_WIDTH 12 /* OUT4L_NGATE_SRC - [11:0] */

2939

2940

/*

2941

* R1068 (0x42C) - Output Path Config 4R

2942

*/

2943

#define ARIZONA_OUT4R_ANC_SRC_MASK 0x0C00 /* OUT4R_ANC_SRC - [11:10] */

2944

#define ARIZONA_OUT4R_ANC_SRC_SHIFT 10 /* OUT4R_ANC_SRC - [11:10] */

2945

#define ARIZONA_OUT4R_ANC_SRC_WIDTH 2 /* OUT4R_ANC_SRC - [11:10] */

2946

2947

/*

2948

* R1069 (0x42D) - DAC Digital Volume 4R

2949

*/

2950

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2951

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2952

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2953

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2954

#define ARIZONA_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */

2955

#define ARIZONA_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */

2956

#define ARIZONA_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */

2957

#define ARIZONA_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */

2958

#define ARIZONA_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */

2959

#define ARIZONA_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */

2960

#define ARIZONA_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */

2961

2962

/*

2963

* R1070 (0x42E) - Out Volume 4R

2964

*/

2965

#define ARIZONA_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */

2966

#define ARIZONA_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */

2967

#define ARIZONA_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */

2968

2969

/*

2970

* R1071 (0x42F) - Noise Gate Select 4R

2971

*/

2972

#define ARIZONA_OUT4R_NGATE_SRC_MASK 0x0FFF /* OUT4R_NGATE_SRC - [11:0] */

2973

#define ARIZONA_OUT4R_NGATE_SRC_SHIFT 0 /* OUT4R_NGATE_SRC - [11:0] */

2974

#define ARIZONA_OUT4R_NGATE_SRC_WIDTH 12 /* OUT4R_NGATE_SRC - [11:0] */

2975

2976

/*

2977

* R1072 (0x430) - Output Path Config 5L

2978

*/

2979

#define ARIZONA_OUT5_OSR 0x2000 /* OUT5_OSR */

2980

#define ARIZONA_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */

2981

#define ARIZONA_OUT5_OSR_SHIFT 13 /* OUT5_OSR */

2982

#define ARIZONA_OUT5_OSR_WIDTH 1 /* OUT5_OSR */

2983

#define ARIZONA_OUT5L_ANC_SRC_MASK 0x0C00 /* OUT5L_ANC_SRC - [11:10] */

2984

#define ARIZONA_OUT5L_ANC_SRC_SHIFT 10 /* OUT5L_ANC_SRC - [11:10] */

2985

#define ARIZONA_OUT5L_ANC_SRC_WIDTH 2 /* OUT5L_ANC_SRC - [11:10] */

2986

2987

/*

2988

* R1073 (0x431) - DAC Digital Volume 5L

2989

*/

2990

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

2991

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

2992

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

2993

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

2994

#define ARIZONA_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */

2995

#define ARIZONA_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */

2996

#define ARIZONA_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */

2997

#define ARIZONA_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */

2998

#define ARIZONA_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */

2999

#define ARIZONA_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */

3000

#define ARIZONA_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */

3001

3002

/*

3003

* R1074 (0x432) - DAC Volume Limit 5L

3004

*/

3005

#define ARIZONA_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */

3006

#define ARIZONA_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */

3007

#define ARIZONA_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */

3008

3009

/*

3010

* R1075 (0x433) - Noise Gate Select 5L

3011

*/

3012

#define ARIZONA_OUT5L_NGATE_SRC_MASK 0x0FFF /* OUT5L_NGATE_SRC - [11:0] */

3013

#define ARIZONA_OUT5L_NGATE_SRC_SHIFT 0 /* OUT5L_NGATE_SRC - [11:0] */

3014

#define ARIZONA_OUT5L_NGATE_SRC_WIDTH 12 /* OUT5L_NGATE_SRC - [11:0] */

3015

3016

/*

3017

* R1076 (0x434) - Output Path Config 5R

3018

*/

3019

#define ARIZONA_OUT5R_ANC_SRC_MASK 0x0C00 /* OUT5R_ANC_SRC - [11:10] */

3020

#define ARIZONA_OUT5R_ANC_SRC_SHIFT 10 /* OUT5R_ANC_SRC - [11:10] */

3021

#define ARIZONA_OUT5R_ANC_SRC_WIDTH 2 /* OUT5R_ANC_SRC - [11:10] */

3022

3023

/*

3024

* R1077 (0x435) - DAC Digital Volume 5R

3025

*/

3026

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

3027

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

3028

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

3029

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

3030

#define ARIZONA_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */

3031

#define ARIZONA_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */

3032

#define ARIZONA_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */

3033

#define ARIZONA_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */

3034

#define ARIZONA_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */

3035

#define ARIZONA_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */

3036

#define ARIZONA_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */

3037

3038

/*

3039

* R1078 (0x436) - DAC Volume Limit 5R

3040

*/

3041

#define ARIZONA_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */

3042

#define ARIZONA_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */

3043

#define ARIZONA_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */

3044

3045

/*

3046

* R1079 (0x437) - Noise Gate Select 5R

3047

*/

3048

#define ARIZONA_OUT5R_NGATE_SRC_MASK 0x0FFF /* OUT5R_NGATE_SRC - [11:0] */

3049

#define ARIZONA_OUT5R_NGATE_SRC_SHIFT 0 /* OUT5R_NGATE_SRC - [11:0] */

3050

#define ARIZONA_OUT5R_NGATE_SRC_WIDTH 12 /* OUT5R_NGATE_SRC - [11:0] */

3051

3052

/*

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

3053

* R1080 (0x438) - Output Path Config 6L

3054

*/

3055

#define ARIZONA_OUT6_OSR 0x2000 /* OUT6_OSR */

3056

#define ARIZONA_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */

3057

#define ARIZONA_OUT6_OSR_SHIFT 13 /* OUT6_OSR */

3058

#define ARIZONA_OUT6_OSR_WIDTH 1 /* OUT6_OSR */

3059

#define ARIZONA_OUT6L_ANC_SRC_MASK 0x0C00 /* OUT6L_ANC_SRC - [11:10] */

3060

#define ARIZONA_OUT6L_ANC_SRC_SHIFT 10 /* OUT6L_ANC_SRC - [11:10] */

3061

#define ARIZONA_OUT6L_ANC_SRC_WIDTH 2 /* OUT6L_ANC_SRC - [11:10] */

3062

3063

/*

3064

* R1081 (0x439) - DAC Digital Volume 6L

3065

*/

3066

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

3067

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

3068

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

3069

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

3070

#define ARIZONA_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */

3071

#define ARIZONA_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */

3072

#define ARIZONA_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */

3073

#define ARIZONA_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */

3074

#define ARIZONA_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */

3075

#define ARIZONA_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */

3076

#define ARIZONA_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */

3077

3078

/*

3079

* R1082 (0x43A) - DAC Volume Limit 6L

3080

*/

3081

#define ARIZONA_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */

3082

#define ARIZONA_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */

3083

#define ARIZONA_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */

3084

3085

/*

3086

* R1083 (0x43B) - Noise Gate Select 6L

3087

*/

3088

#define ARIZONA_OUT6L_NGATE_SRC_MASK 0x0FFF /* OUT6L_NGATE_SRC - [11:0] */

3089

#define ARIZONA_OUT6L_NGATE_SRC_SHIFT 0 /* OUT6L_NGATE_SRC - [11:0] */

3090

#define ARIZONA_OUT6L_NGATE_SRC_WIDTH 12 /* OUT6L_NGATE_SRC - [11:0] */

3091

3092

/*

3093

* R1084 (0x43C) - Output Path Config 6R

3094

*/

3095

#define ARIZONA_OUT6R_ANC_SRC_MASK 0x0C00 /* OUT6R_ANC_SRC - [11:10] */

3096

#define ARIZONA_OUT6R_ANC_SRC_SHIFT 10 /* OUT6R_ANC_SRC - [11:10] */

3097

#define ARIZONA_OUT6R_ANC_SRC_WIDTH 2 /* OUT6R_ANC_SRC - [11:10] */

3098

3099

/*

3100

* R1085 (0x43D) - DAC Digital Volume 6R

3101

*/

3102

#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */

3103

#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */

3104

#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */

3105

#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */

3106

#define ARIZONA_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */

3107

#define ARIZONA_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */

3108

#define ARIZONA_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */

3109

#define ARIZONA_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */

3110

#define ARIZONA_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */

3111

#define ARIZONA_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */

3112

#define ARIZONA_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */

3113

3114

/*

3115

* R1086 (0x43E) - DAC Volume Limit 6R

3116

*/

3117

#define ARIZONA_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */

3118

#define ARIZONA_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */

3119

#define ARIZONA_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */

3120

3121

/*

3122

* R1087 (0x43F) - Noise Gate Select 6R

3123

*/

3124

#define ARIZONA_OUT6R_NGATE_SRC_MASK 0x0FFF /* OUT6R_NGATE_SRC - [11:0] */

3125

#define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */

3126

#define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */

3127

3128

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

3129

* R1104 (0x450) - DAC AEC Control 1

3130

*/

3131

#define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */

3132

#define ARIZONA_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */

3133

#define ARIZONA_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */

3134

#define ARIZONA_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */

3135

#define ARIZONA_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */

3136

#define ARIZONA_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */

3137

#define ARIZONA_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */

3138

#define ARIZONA_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */

3139

#define ARIZONA_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */

3140

#define ARIZONA_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */

3141

#define ARIZONA_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */

3142

3143

/*

3144

* R1112 (0x458) - Noise Gate Control

3145

*/

3146

#define ARIZONA_NGATE_HOLD_MASK 0x0030 /* NGATE_HOLD - [5:4] */

3147

#define ARIZONA_NGATE_HOLD_SHIFT 4 /* NGATE_HOLD - [5:4] */

3148

#define ARIZONA_NGATE_HOLD_WIDTH 2 /* NGATE_HOLD - [5:4] */

3149

#define ARIZONA_NGATE_THR_MASK 0x000E /* NGATE_THR - [3:1] */

3150

#define ARIZONA_NGATE_THR_SHIFT 1 /* NGATE_THR - [3:1] */

3151

#define ARIZONA_NGATE_THR_WIDTH 3 /* NGATE_THR - [3:1] */

3152

#define ARIZONA_NGATE_ENA 0x0001 /* NGATE_ENA */

3153

#define ARIZONA_NGATE_ENA_MASK 0x0001 /* NGATE_ENA */

3154

#define ARIZONA_NGATE_ENA_SHIFT 0 /* NGATE_ENA */

3155

#define ARIZONA_NGATE_ENA_WIDTH 1 /* NGATE_ENA */

3156

3157

/*

3158

* R1168 (0x490) - PDM SPK1 CTRL 1

3159

*/

3160

#define ARIZONA_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */

3161

#define ARIZONA_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */

3162

#define ARIZONA_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */

3163

#define ARIZONA_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */

3164

#define ARIZONA_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */

3165

#define ARIZONA_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */

3166

#define ARIZONA_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */

3167

#define ARIZONA_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */

3168

#define ARIZONA_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */

3169

#define ARIZONA_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */

3170

#define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */

3171

#define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */

3172

#define ARIZONA_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */

3173

#define ARIZONA_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */

3174

#define ARIZONA_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */

3175

3176

/*

3177

* R1169 (0x491) - PDM SPK1 CTRL 2

3178

*/

3179

#define ARIZONA_SPK1_FMT 0x0001 /* SPK1_FMT */

3180

#define ARIZONA_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */

3181

#define ARIZONA_SPK1_FMT_SHIFT 0 /* SPK1_FMT */

3182

#define ARIZONA_SPK1_FMT_WIDTH 1 /* SPK1_FMT */

3183

3184

/*

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

3185

* R1170 (0x492) - PDM SPK2 CTRL 1

3186

*/

3187

#define ARIZONA_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */

3188

#define ARIZONA_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */

3189

#define ARIZONA_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */

3190

#define ARIZONA_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */

3191

#define ARIZONA_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */

3192

#define ARIZONA_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */

3193

#define ARIZONA_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */

3194

#define ARIZONA_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */

3195

#define ARIZONA_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */

3196

#define ARIZONA_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */

3197

#define ARIZONA_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */

3198

#define ARIZONA_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */

3199

#define ARIZONA_SPK2_MUTE_SEQ_MASK 0x00FF /* SPK2_MUTE_SEQ - [7:0] */

3200

#define ARIZONA_SPK2_MUTE_SEQ_SHIFT 0 /* SPK2_MUTE_SEQ - [7:0] */

3201

#define ARIZONA_SPK2_MUTE_SEQ_WIDTH 8 /* SPK2_MUTE_SEQ - [7:0] */

3202

3203

/*

3204

* R1171 (0x493) - PDM SPK2 CTRL 2

3205

*/

3206

#define ARIZONA_SPK2_FMT 0x0001 /* SPK2_FMT */

3207

#define ARIZONA_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */

3208

#define ARIZONA_SPK2_FMT_SHIFT 0 /* SPK2_FMT */

3209

#define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */

3210

3211

/*

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

3212

* R1244 (0x4DC) - DAC comp 1

3213

*/

3214

#define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */

3215

#define ARIZONA_OUT_COMP_COEFF_SHIFT 0 /* OUT_COMP_COEFF - [15:0] */

3216

#define ARIZONA_OUT_COMP_COEFF_WIDTH 16 /* OUT_COMP_COEFF - [15:0] */

3217

3218

/*

3219

* R1245 (0x4DD) - DAC comp 2

3220

*/

3221

#define ARIZONA_OUT_COMP_COEFF_1 0x0002 /* OUT_COMP_COEFF */

3222

#define ARIZONA_OUT_COMP_COEFF_1_MASK 0x0002 /* OUT_COMP_COEFF */

3223

#define ARIZONA_OUT_COMP_COEFF_1_SHIFT 1 /* OUT_COMP_COEFF */

3224

#define ARIZONA_OUT_COMP_COEFF_1_WIDTH 1 /* OUT_COMP_COEFF */

3225

#define ARIZONA_OUT_COMP_COEFF_SEL 0x0001 /* OUT_COMP_COEFF_SEL */

3226

#define ARIZONA_OUT_COMP_COEFF_SEL_MASK 0x0001 /* OUT_COMP_COEFF_SEL */

3227

#define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT 0 /* OUT_COMP_COEFF_SEL */

3228

#define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH 1 /* OUT_COMP_COEFF_SEL */

3229

3230

/*

3231

* R1246 (0x4DE) - DAC comp 3

3232

*/

3233

#define ARIZONA_AEC_COMP_COEFF_MASK 0xFFFF /* AEC_COMP_COEFF - [15:0] */

3234

#define ARIZONA_AEC_COMP_COEFF_SHIFT 0 /* AEC_COMP_COEFF - [15:0] */

3235

#define ARIZONA_AEC_COMP_COEFF_WIDTH 16 /* AEC_COMP_COEFF - [15:0] */

3236

3237

/*

3238

* R1247 (0x4DF) - DAC comp 4

3239

*/

3240

#define ARIZONA_AEC_COMP_COEFF_1 0x0002 /* AEC_COMP_COEFF */

3241

#define ARIZONA_AEC_COMP_COEFF_1_MASK 0x0002 /* AEC_COMP_COEFF */

3242

#define ARIZONA_AEC_COMP_COEFF_1_SHIFT 1 /* AEC_COMP_COEFF */

3243

#define ARIZONA_AEC_COMP_COEFF_1_WIDTH 1 /* AEC_COMP_COEFF */

3244

#define ARIZONA_AEC_COMP_COEFF_SEL 0x0001 /* AEC_COMP_COEFF_SEL */

3245

#define ARIZONA_AEC_COMP_COEFF_SEL_MASK 0x0001 /* AEC_COMP_COEFF_SEL */

3246

#define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT 0 /* AEC_COMP_COEFF_SEL */

3247

#define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH 1 /* AEC_COMP_COEFF_SEL */

3248

3249

/*

3250

* R1280 (0x500) - AIF1 BCLK Ctrl

3251

*/

3252

#define ARIZONA_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */

3253

#define ARIZONA_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */

3254

#define ARIZONA_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */

3255

#define ARIZONA_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */

3256

#define ARIZONA_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */

3257

#define ARIZONA_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */

3258

#define ARIZONA_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */

3259

#define ARIZONA_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */

3260

#define ARIZONA_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */

3261

#define ARIZONA_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */

3262

#define ARIZONA_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */

3263

#define ARIZONA_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */

3264

#define ARIZONA_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */

3265

#define ARIZONA_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */

3266

#define ARIZONA_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */

3267

3268

/*

3269

* R1281 (0x501) - AIF1 Tx Pin Ctrl

3270

*/

3271

#define ARIZONA_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */

3272

#define ARIZONA_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */

3273

#define ARIZONA_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */

3274

#define ARIZONA_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */

3275

#define ARIZONA_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */

3276

#define ARIZONA_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */

3277

#define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */

3278

#define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */

3279

#define ARIZONA_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */

3280

#define ARIZONA_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */

3281

#define ARIZONA_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */

3282

#define ARIZONA_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */

3283

#define ARIZONA_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */

3284

#define ARIZONA_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */

3285

#define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */

3286

#define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */

3287

#define ARIZONA_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */

3288

#define ARIZONA_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */

3289

#define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */

3290

#define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */

3291

3292

/*

3293

* R1282 (0x502) - AIF1 Rx Pin Ctrl

3294

*/

3295

#define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */

3296

#define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */

3297

#define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */

3298

#define ARIZONA_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */

3299

#define ARIZONA_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */

3300

#define ARIZONA_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */

3301

#define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */

3302

#define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */

3303

#define ARIZONA_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */

3304

#define ARIZONA_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */

3305

#define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */

3306

#define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */

3307

3308

/*

3309

* R1283 (0x503) - AIF1 Rate Ctrl

3310

*/

3311

#define ARIZONA_AIF1_RATE_MASK 0x7800 /* AIF1_RATE - [14:11] */

3312

#define ARIZONA_AIF1_RATE_SHIFT 11 /* AIF1_RATE - [14:11] */

3313

#define ARIZONA_AIF1_RATE_WIDTH 4 /* AIF1_RATE - [14:11] */

3314

#define ARIZONA_AIF1_TRI 0x0040 /* AIF1_TRI */

3315

#define ARIZONA_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */

3316

#define ARIZONA_AIF1_TRI_SHIFT 6 /* AIF1_TRI */

3317

#define ARIZONA_AIF1_TRI_WIDTH 1 /* AIF1_TRI */

3318

3319

/*

3320

* R1284 (0x504) - AIF1 Format

3321

*/

3322

#define ARIZONA_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */

3323

#define ARIZONA_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */

3324

#define ARIZONA_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */

3325

3326

/*

3327

* R1285 (0x505) - AIF1 Tx BCLK Rate

3328

*/

3329

#define ARIZONA_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */

3330

#define ARIZONA_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */

3331

#define ARIZONA_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */

3332

3333

/*

3334

* R1286 (0x506) - AIF1 Rx BCLK Rate

3335

*/

3336

#define ARIZONA_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */

3337

#define ARIZONA_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */

3338

#define ARIZONA_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */

3339

3340

/*

3341

* R1287 (0x507) - AIF1 Frame Ctrl 1

3342

*/

3343

#define ARIZONA_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */

3344

#define ARIZONA_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */

3345

#define ARIZONA_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */

3346

#define ARIZONA_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */

3347

#define ARIZONA_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */

3348

#define ARIZONA_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */

3349

3350

/*

3351

* R1288 (0x508) - AIF1 Frame Ctrl 2

3352

*/

3353

#define ARIZONA_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */

3354

#define ARIZONA_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */

3355

#define ARIZONA_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */

3356

#define ARIZONA_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */

3357

#define ARIZONA_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */

3358

#define ARIZONA_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */

3359

3360

/*

3361

* R1289 (0x509) - AIF1 Frame Ctrl 3

3362

*/

3363

#define ARIZONA_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */

3364

#define ARIZONA_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */

3365

#define ARIZONA_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */

3366

3367

/*

3368

* R1290 (0x50A) - AIF1 Frame Ctrl 4

3369

*/

3370

#define ARIZONA_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */

3371

#define ARIZONA_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */

3372

#define ARIZONA_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */

3373

3374

/*

3375

* R1291 (0x50B) - AIF1 Frame Ctrl 5

3376

*/

3377

#define ARIZONA_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */

3378

#define ARIZONA_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */

3379

#define ARIZONA_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */

3380

3381

/*

3382

* R1292 (0x50C) - AIF1 Frame Ctrl 6

3383

*/

3384

#define ARIZONA_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */

3385

#define ARIZONA_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */

3386

#define ARIZONA_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */

3387

3388

/*

3389

* R1293 (0x50D) - AIF1 Frame Ctrl 7

3390

*/

3391

#define ARIZONA_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */

3392

#define ARIZONA_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */

3393

#define ARIZONA_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */

3394

3395

/*

3396

* R1294 (0x50E) - AIF1 Frame Ctrl 8

3397

*/

3398

#define ARIZONA_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */

3399

#define ARIZONA_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */

3400

#define ARIZONA_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */

3401

3402

/*

3403

* R1295 (0x50F) - AIF1 Frame Ctrl 9

3404

*/

3405

#define ARIZONA_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */

3406

#define ARIZONA_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */

3407

#define ARIZONA_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */

3408

3409

/*

3410

* R1296 (0x510) - AIF1 Frame Ctrl 10

3411

*/

3412

#define ARIZONA_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */

3413

#define ARIZONA_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */

3414

#define ARIZONA_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */

3415

3416

/*

3417

* R1297 (0x511) - AIF1 Frame Ctrl 11

3418

*/

3419

#define ARIZONA_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */

3420

#define ARIZONA_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */

3421

#define ARIZONA_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */

3422

3423

/*

3424

* R1298 (0x512) - AIF1 Frame Ctrl 12

3425

*/

3426

#define ARIZONA_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */

3427

#define ARIZONA_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */

3428

#define ARIZONA_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */

3429

3430

/*

3431

* R1299 (0x513) - AIF1 Frame Ctrl 13

3432

*/

3433

#define ARIZONA_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */

3434

#define ARIZONA_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */

3435

#define ARIZONA_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */

3436

3437

/*

3438

* R1300 (0x514) - AIF1 Frame Ctrl 14

3439

*/

3440

#define ARIZONA_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */

3441

#define ARIZONA_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */

3442

#define ARIZONA_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */

3443

3444

/*

3445

* R1301 (0x515) - AIF1 Frame Ctrl 15

3446

*/

3447

#define ARIZONA_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */

3448

#define ARIZONA_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */

3449

#define ARIZONA_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */

3450

3451

/*

3452

* R1302 (0x516) - AIF1 Frame Ctrl 16

3453

*/

3454

#define ARIZONA_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */

3455

#define ARIZONA_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */

3456

#define ARIZONA_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */

3457

3458

/*

3459

* R1303 (0x517) - AIF1 Frame Ctrl 17

3460

*/

3461

#define ARIZONA_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */

3462

#define ARIZONA_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */

3463

#define ARIZONA_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */

3464

3465

/*

3466

* R1304 (0x518) - AIF1 Frame Ctrl 18

3467

*/

3468

#define ARIZONA_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */

3469

#define ARIZONA_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */

3470

#define ARIZONA_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */

3471

3472

/*

3473

* R1305 (0x519) - AIF1 Tx Enables

3474

*/

3475

#define ARIZONA_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */

3476

#define ARIZONA_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */

3477

#define ARIZONA_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */

3478

#define ARIZONA_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */

3479

#define ARIZONA_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */

3480

#define ARIZONA_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */

3481

#define ARIZONA_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */

3482

#define ARIZONA_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */

3483

#define ARIZONA_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */

3484

#define ARIZONA_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */

3485

#define ARIZONA_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */

3486

#define ARIZONA_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */

3487

#define ARIZONA_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */

3488

#define ARIZONA_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */

3489

#define ARIZONA_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */

3490

#define ARIZONA_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */

3491

#define ARIZONA_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */

3492

#define ARIZONA_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */

3493

#define ARIZONA_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */

3494

#define ARIZONA_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */

3495

#define ARIZONA_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */

3496

#define ARIZONA_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */

3497

#define ARIZONA_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */

3498

#define ARIZONA_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */

3499

#define ARIZONA_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */

3500

#define ARIZONA_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */

3501

#define ARIZONA_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */

3502

#define ARIZONA_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */

3503

#define ARIZONA_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */

3504

#define ARIZONA_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */

3505

#define ARIZONA_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */

3506

#define ARIZONA_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */

3507

3508

/*

3509

* R1306 (0x51A) - AIF1 Rx Enables

3510

*/

3511

#define ARIZONA_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */

3512

#define ARIZONA_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */

3513

#define ARIZONA_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */

3514

#define ARIZONA_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */

3515

#define ARIZONA_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */

3516

#define ARIZONA_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */

3517

#define ARIZONA_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */

3518

#define ARIZONA_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */

3519

#define ARIZONA_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */

3520

#define ARIZONA_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */

3521

#define ARIZONA_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */

3522

#define ARIZONA_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */

3523

#define ARIZONA_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */

3524

#define ARIZONA_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */

3525

#define ARIZONA_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */

3526

#define ARIZONA_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */

3527

#define ARIZONA_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */

3528

#define ARIZONA_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */

3529

#define ARIZONA_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */

3530

#define ARIZONA_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */

3531

#define ARIZONA_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */

3532

#define ARIZONA_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */

3533

#define ARIZONA_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */

3534

#define ARIZONA_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */

3535

#define ARIZONA_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */

3536

#define ARIZONA_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */

3537

#define ARIZONA_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */

3538

#define ARIZONA_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */

3539

#define ARIZONA_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */

3540

#define ARIZONA_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */

3541

#define ARIZONA_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */

3542

#define ARIZONA_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */

3543

3544

/*

3545

* R1307 (0x51B) - AIF1 Force Write

3546

*/

3547

#define ARIZONA_AIF1_FRC_WR 0x0001 /* AIF1_FRC_WR */

3548

#define ARIZONA_AIF1_FRC_WR_MASK 0x0001 /* AIF1_FRC_WR */

3549

#define ARIZONA_AIF1_FRC_WR_SHIFT 0 /* AIF1_FRC_WR */

3550

#define ARIZONA_AIF1_FRC_WR_WIDTH 1 /* AIF1_FRC_WR */

3551

3552

/*

3553

* R1344 (0x540) - AIF2 BCLK Ctrl

3554

*/

3555

#define ARIZONA_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */

3556

#define ARIZONA_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */

3557

#define ARIZONA_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */

3558

#define ARIZONA_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */

3559

#define ARIZONA_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */

3560

#define ARIZONA_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */

3561

#define ARIZONA_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */

3562

#define ARIZONA_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */

3563

#define ARIZONA_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */

3564

#define ARIZONA_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */

3565

#define ARIZONA_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */

3566

#define ARIZONA_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */

3567

#define ARIZONA_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */

3568

#define ARIZONA_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */

3569

#define ARIZONA_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */

3570

3571

/*

3572

* R1345 (0x541) - AIF2 Tx Pin Ctrl

3573

*/

3574

#define ARIZONA_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */

3575

#define ARIZONA_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */

3576

#define ARIZONA_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */

3577

#define ARIZONA_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */

3578

#define ARIZONA_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */

3579

#define ARIZONA_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */

3580

#define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */

3581

#define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */

3582

#define ARIZONA_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */

3583

#define ARIZONA_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */

3584

#define ARIZONA_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */

3585

#define ARIZONA_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */

3586

#define ARIZONA_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */

3587

#define ARIZONA_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */

3588

#define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */

3589

#define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */

3590

#define ARIZONA_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */

3591

#define ARIZONA_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */

3592

#define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */

3593

#define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */

3594

3595

/*

3596

* R1346 (0x542) - AIF2 Rx Pin Ctrl

3597

*/

3598

#define ARIZONA_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */

3599

#define ARIZONA_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */

3600

#define ARIZONA_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */

3601

#define ARIZONA_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */

3602

#define ARIZONA_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */

3603

#define ARIZONA_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */

3604

#define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */

3605

#define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */

3606

#define ARIZONA_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */

3607

#define ARIZONA_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */

3608

#define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */

3609

#define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */

3610

3611

/*

3612

* R1347 (0x543) - AIF2 Rate Ctrl

3613

*/

3614

#define ARIZONA_AIF2_RATE_MASK 0x7800 /* AIF2_RATE - [14:11] */

3615

#define ARIZONA_AIF2_RATE_SHIFT 11 /* AIF2_RATE - [14:11] */

3616

#define ARIZONA_AIF2_RATE_WIDTH 4 /* AIF2_RATE - [14:11] */

3617

#define ARIZONA_AIF2_TRI 0x0040 /* AIF2_TRI */

3618

#define ARIZONA_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */

3619

#define ARIZONA_AIF2_TRI_SHIFT 6 /* AIF2_TRI */

3620

#define ARIZONA_AIF2_TRI_WIDTH 1 /* AIF2_TRI */

3621

3622

/*

3623

* R1348 (0x544) - AIF2 Format

3624

*/

3625

#define ARIZONA_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */

3626

#define ARIZONA_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */

3627

#define ARIZONA_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */

3628

3629

/*

3630

* R1349 (0x545) - AIF2 Tx BCLK Rate

3631

*/

3632

#define ARIZONA_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */

3633

#define ARIZONA_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */

3634

#define ARIZONA_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */

3635

3636

/*

3637

* R1350 (0x546) - AIF2 Rx BCLK Rate

3638

*/

3639

#define ARIZONA_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */

3640

#define ARIZONA_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */

3641

#define ARIZONA_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */

3642

3643

/*

3644

* R1351 (0x547) - AIF2 Frame Ctrl 1

3645

*/

3646

#define ARIZONA_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */

3647

#define ARIZONA_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */

3648

#define ARIZONA_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */

3649

#define ARIZONA_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */

3650

#define ARIZONA_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */

3651

#define ARIZONA_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */

3652

3653

/*

3654

* R1352 (0x548) - AIF2 Frame Ctrl 2

3655

*/

3656

#define ARIZONA_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */

3657

#define ARIZONA_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */

3658

#define ARIZONA_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */

3659

#define ARIZONA_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */

3660

#define ARIZONA_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */

3661

#define ARIZONA_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */

3662

3663

/*

3664

* R1353 (0x549) - AIF2 Frame Ctrl 3

3665

*/

3666

#define ARIZONA_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */

3667

#define ARIZONA_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */

3668

#define ARIZONA_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */

3669

3670

/*

3671

* R1354 (0x54A) - AIF2 Frame Ctrl 4

3672

*/

3673

#define ARIZONA_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */

3674

#define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */

3675

#define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */

3676

3677

/*

3678

* R1361 (0x551) - AIF2 Frame Ctrl 11

3679

*/

3680

#define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */

3681

#define ARIZONA_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */

3682

#define ARIZONA_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */

3683

3684

/*

3685

* R1362 (0x552) - AIF2 Frame Ctrl 12

3686

*/

3687

#define ARIZONA_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */

3688

#define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */

3689

#define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */

3690

3691

/*

3692

* R1369 (0x559) - AIF2 Tx Enables

3693

*/

3694

#define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */

3695

#define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */

3696

#define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */

3697

#define ARIZONA_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */

3698

#define ARIZONA_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */

3699

#define ARIZONA_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */

3700

#define ARIZONA_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */

3701

#define ARIZONA_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */

3702

3703

/*

3704

* R1370 (0x55A) - AIF2 Rx Enables

3705

*/

3706

#define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */

3707

#define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */

3708

#define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */

3709

#define ARIZONA_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */

3710

#define ARIZONA_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */

3711

#define ARIZONA_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */

3712

#define ARIZONA_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */

3713

#define ARIZONA_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */

3714

3715

/*

3716

* R1371 (0x55B) - AIF2 Force Write

3717

*/

3718

#define ARIZONA_AIF2_FRC_WR 0x0001 /* AIF2_FRC_WR */

3719

#define ARIZONA_AIF2_FRC_WR_MASK 0x0001 /* AIF2_FRC_WR */

3720

#define ARIZONA_AIF2_FRC_WR_SHIFT 0 /* AIF2_FRC_WR */

3721

#define ARIZONA_AIF2_FRC_WR_WIDTH 1 /* AIF2_FRC_WR */

3722

3723

/*

3724

* R1408 (0x580) - AIF3 BCLK Ctrl

3725

*/

3726

#define ARIZONA_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */

3727

#define ARIZONA_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */

3728

#define ARIZONA_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */

3729

#define ARIZONA_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */

3730

#define ARIZONA_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */

3731

#define ARIZONA_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */

3732

#define ARIZONA_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */

3733

#define ARIZONA_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */

3734

#define ARIZONA_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */

3735

#define ARIZONA_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */

3736

#define ARIZONA_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */

3737

#define ARIZONA_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */

3738

#define ARIZONA_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */

3739

#define ARIZONA_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */

3740

#define ARIZONA_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */

3741

3742

/*

3743

* R1409 (0x581) - AIF3 Tx Pin Ctrl

3744

*/

3745

#define ARIZONA_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */

3746

#define ARIZONA_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */

3747

#define ARIZONA_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */

3748

#define ARIZONA_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */

3749

#define ARIZONA_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */

3750

#define ARIZONA_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */

3751

#define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */

3752

#define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */

3753

#define ARIZONA_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */

3754

#define ARIZONA_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */

3755

#define ARIZONA_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */

3756

#define ARIZONA_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */

3757

#define ARIZONA_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */

3758

#define ARIZONA_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */

3759

#define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */

3760

#define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */

3761

#define ARIZONA_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */

3762

#define ARIZONA_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */

3763

#define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */

3764

#define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */

3765

3766

/*

3767

* R1410 (0x582) - AIF3 Rx Pin Ctrl

3768

*/

3769

#define ARIZONA_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */

3770

#define ARIZONA_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */

3771

#define ARIZONA_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */

3772

#define ARIZONA_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */

3773

#define ARIZONA_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */

3774

#define ARIZONA_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */

3775

#define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */

3776

#define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */

3777

#define ARIZONA_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */

3778

#define ARIZONA_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */

3779

#define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */

3780

#define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */

3781

3782

/*

3783

* R1411 (0x583) - AIF3 Rate Ctrl

3784

*/

3785

#define ARIZONA_AIF3_RATE_MASK 0x7800 /* AIF3_RATE - [14:11] */

3786

#define ARIZONA_AIF3_RATE_SHIFT 11 /* AIF3_RATE - [14:11] */

3787

#define ARIZONA_AIF3_RATE_WIDTH 4 /* AIF3_RATE - [14:11] */

3788

#define ARIZONA_AIF3_TRI 0x0040 /* AIF3_TRI */

3789

#define ARIZONA_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */

3790

#define ARIZONA_AIF3_TRI_SHIFT 6 /* AIF3_TRI */

3791

#define ARIZONA_AIF3_TRI_WIDTH 1 /* AIF3_TRI */

3792

3793

/*

3794

* R1412 (0x584) - AIF3 Format

3795

*/

3796

#define ARIZONA_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */

3797

#define ARIZONA_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */

3798

#define ARIZONA_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */

3799

3800

/*

3801

* R1413 (0x585) - AIF3 Tx BCLK Rate

3802

*/

3803

#define ARIZONA_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */

3804

#define ARIZONA_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */

3805

#define ARIZONA_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */

3806

3807

/*

3808

* R1414 (0x586) - AIF3 Rx BCLK Rate

3809

*/

3810

#define ARIZONA_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */

3811

#define ARIZONA_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */

3812

#define ARIZONA_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */

3813

3814

/*

3815

* R1415 (0x587) - AIF3 Frame Ctrl 1

3816

*/

3817

#define ARIZONA_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */

3818

#define ARIZONA_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */

3819

#define ARIZONA_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */

3820

#define ARIZONA_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */

3821

#define ARIZONA_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */

3822

#define ARIZONA_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */

3823

3824

/*

3825

* R1416 (0x588) - AIF3 Frame Ctrl 2

3826

*/

3827

#define ARIZONA_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */

3828

#define ARIZONA_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */

3829

#define ARIZONA_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */

3830

#define ARIZONA_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */

3831

#define ARIZONA_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */

3832

#define ARIZONA_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */

3833

3834

/*

3835

* R1417 (0x589) - AIF3 Frame Ctrl 3

3836

*/

3837

#define ARIZONA_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */

3838

#define ARIZONA_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */

3839

#define ARIZONA_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */

3840

3841

/*

3842

* R1418 (0x58A) - AIF3 Frame Ctrl 4

3843

*/

3844

#define ARIZONA_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */

3845

#define ARIZONA_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */

3846

#define ARIZONA_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */

3847

3848

/*

3849

* R1425 (0x591) - AIF3 Frame Ctrl 11

3850

*/

3851

#define ARIZONA_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */

3852

#define ARIZONA_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */

3853

#define ARIZONA_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */

3854

3855

/*

3856

* R1426 (0x592) - AIF3 Frame Ctrl 12

3857

*/

3858

#define ARIZONA_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */

3859

#define ARIZONA_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */

3860

#define ARIZONA_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */

3861

3862

/*

3863

* R1433 (0x599) - AIF3 Tx Enables

3864

*/

3865

#define ARIZONA_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */

3866

#define ARIZONA_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */

3867

#define ARIZONA_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */

3868

#define ARIZONA_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */

3869

#define ARIZONA_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */

3870

#define ARIZONA_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */

3871

#define ARIZONA_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */

3872

#define ARIZONA_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */

3873

3874

/*

3875

* R1434 (0x59A) - AIF3 Rx Enables

3876

*/

3877

#define ARIZONA_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */

3878

#define ARIZONA_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */

3879

#define ARIZONA_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */

3880

#define ARIZONA_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */

3881

#define ARIZONA_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */

3882

#define ARIZONA_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */

3883

#define ARIZONA_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */

3884

#define ARIZONA_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */

3885

3886

/*

3887

* R1435 (0x59B) - AIF3 Force Write

3888

*/

3889

#define ARIZONA_AIF3_FRC_WR 0x0001 /* AIF3_FRC_WR */

3890

#define ARIZONA_AIF3_FRC_WR_MASK 0x0001 /* AIF3_FRC_WR */

3891

#define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */

3892

#define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */

3893

3894

/*

3895

* R1507 (0x5E3) - SLIMbus Framer Ref Gear

3896

*/

3897

#define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */

3898

#define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */

3899

#define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */

3900

#define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */

3901

#define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */

3902

#define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */

3903

#define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */

3904

3905

/*

3906

* R1509 (0x5E5) - SLIMbus Rates 1

3907

*/

3908

#define ARIZONA_SLIMRX2_RATE_MASK 0x7800 /* SLIMRX2_RATE - [14:11] */

3909

#define ARIZONA_SLIMRX2_RATE_SHIFT 11 /* SLIMRX2_RATE - [14:11] */

3910

#define ARIZONA_SLIMRX2_RATE_WIDTH 4 /* SLIMRX2_RATE - [14:11] */

3911

#define ARIZONA_SLIMRX1_RATE_MASK 0x0078 /* SLIMRX1_RATE - [6:3] */

3912

#define ARIZONA_SLIMRX1_RATE_SHIFT 3 /* SLIMRX1_RATE - [6:3] */

3913

#define ARIZONA_SLIMRX1_RATE_WIDTH 4 /* SLIMRX1_RATE - [6:3] */

3914

3915

/*

3916

* R1510 (0x5E6) - SLIMbus Rates 2

3917

*/

3918

#define ARIZONA_SLIMRX4_RATE_MASK 0x7800 /* SLIMRX4_RATE - [14:11] */

3919

#define ARIZONA_SLIMRX4_RATE_SHIFT 11 /* SLIMRX4_RATE - [14:11] */

3920

#define ARIZONA_SLIMRX4_RATE_WIDTH 4 /* SLIMRX4_RATE - [14:11] */

3921

#define ARIZONA_SLIMRX3_RATE_MASK 0x0078 /* SLIMRX3_RATE - [6:3] */

3922

#define ARIZONA_SLIMRX3_RATE_SHIFT 3 /* SLIMRX3_RATE - [6:3] */

3923

#define ARIZONA_SLIMRX3_RATE_WIDTH 4 /* SLIMRX3_RATE - [6:3] */

3924

3925

/*

3926

* R1511 (0x5E7) - SLIMbus Rates 3

3927

*/

3928

#define ARIZONA_SLIMRX6_RATE_MASK 0x7800 /* SLIMRX6_RATE - [14:11] */

3929

#define ARIZONA_SLIMRX6_RATE_SHIFT 11 /* SLIMRX6_RATE - [14:11] */

3930

#define ARIZONA_SLIMRX6_RATE_WIDTH 4 /* SLIMRX6_RATE - [14:11] */

3931

#define ARIZONA_SLIMRX5_RATE_MASK 0x0078 /* SLIMRX5_RATE - [6:3] */

3932

#define ARIZONA_SLIMRX5_RATE_SHIFT 3 /* SLIMRX5_RATE - [6:3] */

3933

#define ARIZONA_SLIMRX5_RATE_WIDTH 4 /* SLIMRX5_RATE - [6:3] */

3934

3935

/*

3936

* R1512 (0x5E8) - SLIMbus Rates 4

3937

*/

3938

#define ARIZONA_SLIMRX8_RATE_MASK 0x7800 /* SLIMRX8_RATE - [14:11] */

3939

#define ARIZONA_SLIMRX8_RATE_SHIFT 11 /* SLIMRX8_RATE - [14:11] */

3940

#define ARIZONA_SLIMRX8_RATE_WIDTH 4 /* SLIMRX8_RATE - [14:11] */

3941

#define ARIZONA_SLIMRX7_RATE_MASK 0x0078 /* SLIMRX7_RATE - [6:3] */

3942

#define ARIZONA_SLIMRX7_RATE_SHIFT 3 /* SLIMRX7_RATE - [6:3] */

3943

#define ARIZONA_SLIMRX7_RATE_WIDTH 4 /* SLIMRX7_RATE - [6:3] */

3944

3945

/*

3946

* R1513 (0x5E9) - SLIMbus Rates 5

3947

*/

3948

#define ARIZONA_SLIMTX2_RATE_MASK 0x7800 /* SLIMTX2_RATE - [14:11] */

3949

#define ARIZONA_SLIMTX2_RATE_SHIFT 11 /* SLIMTX2_RATE - [14:11] */

3950

#define ARIZONA_SLIMTX2_RATE_WIDTH 4 /* SLIMTX2_RATE - [14:11] */

3951

#define ARIZONA_SLIMTX1_RATE_MASK 0x0078 /* SLIMTX1_RATE - [6:3] */

3952

#define ARIZONA_SLIMTX1_RATE_SHIFT 3 /* SLIMTX1_RATE - [6:3] */

3953

#define ARIZONA_SLIMTX1_RATE_WIDTH 4 /* SLIMTX1_RATE - [6:3] */

3954

3955

/*

3956

* R1514 (0x5EA) - SLIMbus Rates 6

3957

*/

3958

#define ARIZONA_SLIMTX4_RATE_MASK 0x7800 /* SLIMTX4_RATE - [14:11] */

3959

#define ARIZONA_SLIMTX4_RATE_SHIFT 11 /* SLIMTX4_RATE - [14:11] */

3960

#define ARIZONA_SLIMTX4_RATE_WIDTH 4 /* SLIMTX4_RATE - [14:11] */

3961

#define ARIZONA_SLIMTX3_RATE_MASK 0x0078 /* SLIMTX3_RATE - [6:3] */

3962

#define ARIZONA_SLIMTX3_RATE_SHIFT 3 /* SLIMTX3_RATE - [6:3] */

3963

#define ARIZONA_SLIMTX3_RATE_WIDTH 4 /* SLIMTX3_RATE - [6:3] */

3964

3965

/*

3966

* R1515 (0x5EB) - SLIMbus Rates 7

3967

*/

3968

#define ARIZONA_SLIMTX6_RATE_MASK 0x7800 /* SLIMTX6_RATE - [14:11] */

3969

#define ARIZONA_SLIMTX6_RATE_SHIFT 11 /* SLIMTX6_RATE - [14:11] */

3970

#define ARIZONA_SLIMTX6_RATE_WIDTH 4 /* SLIMTX6_RATE - [14:11] */

3971

#define ARIZONA_SLIMTX5_RATE_MASK 0x0078 /* SLIMTX5_RATE - [6:3] */

3972

#define ARIZONA_SLIMTX5_RATE_SHIFT 3 /* SLIMTX5_RATE - [6:3] */

3973

#define ARIZONA_SLIMTX5_RATE_WIDTH 4 /* SLIMTX5_RATE - [6:3] */

3974

3975

/*

3976

* R1516 (0x5EC) - SLIMbus Rates 8

3977

*/

3978

#define ARIZONA_SLIMTX8_RATE_MASK 0x7800 /* SLIMTX8_RATE - [14:11] */

3979

#define ARIZONA_SLIMTX8_RATE_SHIFT 11 /* SLIMTX8_RATE - [14:11] */

3980

#define ARIZONA_SLIMTX8_RATE_WIDTH 4 /* SLIMTX8_RATE - [14:11] */

3981

#define ARIZONA_SLIMTX7_RATE_MASK 0x0078 /* SLIMTX7_RATE - [6:3] */

3982

#define ARIZONA_SLIMTX7_RATE_SHIFT 3 /* SLIMTX7_RATE - [6:3] */

3983

#define ARIZONA_SLIMTX7_RATE_WIDTH 4 /* SLIMTX7_RATE - [6:3] */

3984

3985

/*

3986

* R1525 (0x5F5) - SLIMbus RX Channel Enable

3987

*/

3988

#define ARIZONA_SLIMRX8_ENA 0x0080 /* SLIMRX8_ENA */

3989

#define ARIZONA_SLIMRX8_ENA_MASK 0x0080 /* SLIMRX8_ENA */

3990

#define ARIZONA_SLIMRX8_ENA_SHIFT 7 /* SLIMRX8_ENA */

3991

#define ARIZONA_SLIMRX8_ENA_WIDTH 1 /* SLIMRX8_ENA */

3992

#define ARIZONA_SLIMRX7_ENA 0x0040 /* SLIMRX7_ENA */

3993

#define ARIZONA_SLIMRX7_ENA_MASK 0x0040 /* SLIMRX7_ENA */

3994

#define ARIZONA_SLIMRX7_ENA_SHIFT 6 /* SLIMRX7_ENA */

3995

#define ARIZONA_SLIMRX7_ENA_WIDTH 1 /* SLIMRX7_ENA */

3996

#define ARIZONA_SLIMRX6_ENA 0x0020 /* SLIMRX6_ENA */

3997

#define ARIZONA_SLIMRX6_ENA_MASK 0x0020 /* SLIMRX6_ENA */

3998

#define ARIZONA_SLIMRX6_ENA_SHIFT 5 /* SLIMRX6_ENA */

3999

#define ARIZONA_SLIMRX6_ENA_WIDTH 1 /* SLIMRX6_ENA */

4000

#define ARIZONA_SLIMRX5_ENA 0x0010 /* SLIMRX5_ENA */

4001

#define ARIZONA_SLIMRX5_ENA_MASK 0x0010 /* SLIMRX5_ENA */

4002

#define ARIZONA_SLIMRX5_ENA_SHIFT 4 /* SLIMRX5_ENA */

4003

#define ARIZONA_SLIMRX5_ENA_WIDTH 1 /* SLIMRX5_ENA */

4004

#define ARIZONA_SLIMRX4_ENA 0x0008 /* SLIMRX4_ENA */

4005

#define ARIZONA_SLIMRX4_ENA_MASK 0x0008 /* SLIMRX4_ENA */

4006

#define ARIZONA_SLIMRX4_ENA_SHIFT 3 /* SLIMRX4_ENA */

4007

#define ARIZONA_SLIMRX4_ENA_WIDTH 1 /* SLIMRX4_ENA */

4008

#define ARIZONA_SLIMRX3_ENA 0x0004 /* SLIMRX3_ENA */

4009

#define ARIZONA_SLIMRX3_ENA_MASK 0x0004 /* SLIMRX3_ENA */

4010

#define ARIZONA_SLIMRX3_ENA_SHIFT 2 /* SLIMRX3_ENA */

4011

#define ARIZONA_SLIMRX3_ENA_WIDTH 1 /* SLIMRX3_ENA */

4012

#define ARIZONA_SLIMRX2_ENA 0x0002 /* SLIMRX2_ENA */

4013

#define ARIZONA_SLIMRX2_ENA_MASK 0x0002 /* SLIMRX2_ENA */

4014

#define ARIZONA_SLIMRX2_ENA_SHIFT 1 /* SLIMRX2_ENA */

4015

#define ARIZONA_SLIMRX2_ENA_WIDTH 1 /* SLIMRX2_ENA */

4016

#define ARIZONA_SLIMRX1_ENA 0x0001 /* SLIMRX1_ENA */

4017

#define ARIZONA_SLIMRX1_ENA_MASK 0x0001 /* SLIMRX1_ENA */

4018

#define ARIZONA_SLIMRX1_ENA_SHIFT 0 /* SLIMRX1_ENA */

4019

#define ARIZONA_SLIMRX1_ENA_WIDTH 1 /* SLIMRX1_ENA */

4020

4021

/*

4022

* R1526 (0x5F6) - SLIMbus TX Channel Enable

4023

*/

4024

#define ARIZONA_SLIMTX8_ENA 0x0080 /* SLIMTX8_ENA */

4025

#define ARIZONA_SLIMTX8_ENA_MASK 0x0080 /* SLIMTX8_ENA */

4026

#define ARIZONA_SLIMTX8_ENA_SHIFT 7 /* SLIMTX8_ENA */

4027

#define ARIZONA_SLIMTX8_ENA_WIDTH 1 /* SLIMTX8_ENA */

4028

#define ARIZONA_SLIMTX7_ENA 0x0040 /* SLIMTX7_ENA */

4029

#define ARIZONA_SLIMTX7_ENA_MASK 0x0040 /* SLIMTX7_ENA */

4030

#define ARIZONA_SLIMTX7_ENA_SHIFT 6 /* SLIMTX7_ENA */

4031

#define ARIZONA_SLIMTX7_ENA_WIDTH 1 /* SLIMTX7_ENA */

4032

#define ARIZONA_SLIMTX6_ENA 0x0020 /* SLIMTX6_ENA */

4033

#define ARIZONA_SLIMTX6_ENA_MASK 0x0020 /* SLIMTX6_ENA */

4034

#define ARIZONA_SLIMTX6_ENA_SHIFT 5 /* SLIMTX6_ENA */

4035

#define ARIZONA_SLIMTX6_ENA_WIDTH 1 /* SLIMTX6_ENA */

4036

#define ARIZONA_SLIMTX5_ENA 0x0010 /* SLIMTX5_ENA */

4037

#define ARIZONA_SLIMTX5_ENA_MASK 0x0010 /* SLIMTX5_ENA */

4038

#define ARIZONA_SLIMTX5_ENA_SHIFT 4 /* SLIMTX5_ENA */

4039

#define ARIZONA_SLIMTX5_ENA_WIDTH 1 /* SLIMTX5_ENA */

4040

#define ARIZONA_SLIMTX4_ENA 0x0008 /* SLIMTX4_ENA */

4041

#define ARIZONA_SLIMTX4_ENA_MASK 0x0008 /* SLIMTX4_ENA */

4042

#define ARIZONA_SLIMTX4_ENA_SHIFT 3 /* SLIMTX4_ENA */

4043

#define ARIZONA_SLIMTX4_ENA_WIDTH 1 /* SLIMTX4_ENA */

4044

#define ARIZONA_SLIMTX3_ENA 0x0004 /* SLIMTX3_ENA */

4045

#define ARIZONA_SLIMTX3_ENA_MASK 0x0004 /* SLIMTX3_ENA */

4046

#define ARIZONA_SLIMTX3_ENA_SHIFT 2 /* SLIMTX3_ENA */

4047

#define ARIZONA_SLIMTX3_ENA_WIDTH 1 /* SLIMTX3_ENA */

4048

#define ARIZONA_SLIMTX2_ENA 0x0002 /* SLIMTX2_ENA */

4049

#define ARIZONA_SLIMTX2_ENA_MASK 0x0002 /* SLIMTX2_ENA */

4050

#define ARIZONA_SLIMTX2_ENA_SHIFT 1 /* SLIMTX2_ENA */

4051

#define ARIZONA_SLIMTX2_ENA_WIDTH 1 /* SLIMTX2_ENA */

4052

#define ARIZONA_SLIMTX1_ENA 0x0001 /* SLIMTX1_ENA */

4053

#define ARIZONA_SLIMTX1_ENA_MASK 0x0001 /* SLIMTX1_ENA */

4054

#define ARIZONA_SLIMTX1_ENA_SHIFT 0 /* SLIMTX1_ENA */

4055

#define ARIZONA_SLIMTX1_ENA_WIDTH 1 /* SLIMTX1_ENA */

4056

4057

/*

4058

* R1527 (0x5F7) - SLIMbus RX Port Status

4059

*/

4060

#define ARIZONA_SLIMRX8_PORT_STS 0x0080 /* SLIMRX8_PORT_STS */

4061

#define ARIZONA_SLIMRX8_PORT_STS_MASK 0x0080 /* SLIMRX8_PORT_STS */

4062

#define ARIZONA_SLIMRX8_PORT_STS_SHIFT 7 /* SLIMRX8_PORT_STS */

4063

#define ARIZONA_SLIMRX8_PORT_STS_WIDTH 1 /* SLIMRX8_PORT_STS */

4064

#define ARIZONA_SLIMRX7_PORT_STS 0x0040 /* SLIMRX7_PORT_STS */

4065

#define ARIZONA_SLIMRX7_PORT_STS_MASK 0x0040 /* SLIMRX7_PORT_STS */

4066

#define ARIZONA_SLIMRX7_PORT_STS_SHIFT 6 /* SLIMRX7_PORT_STS */

4067

#define ARIZONA_SLIMRX7_PORT_STS_WIDTH 1 /* SLIMRX7_PORT_STS */

4068

#define ARIZONA_SLIMRX6_PORT_STS 0x0020 /* SLIMRX6_PORT_STS */

4069

#define ARIZONA_SLIMRX6_PORT_STS_MASK 0x0020 /* SLIMRX6_PORT_STS */

4070

#define ARIZONA_SLIMRX6_PORT_STS_SHIFT 5 /* SLIMRX6_PORT_STS */

4071

#define ARIZONA_SLIMRX6_PORT_STS_WIDTH 1 /* SLIMRX6_PORT_STS */

4072

#define ARIZONA_SLIMRX5_PORT_STS 0x0010 /* SLIMRX5_PORT_STS */

4073

#define ARIZONA_SLIMRX5_PORT_STS_MASK 0x0010 /* SLIMRX5_PORT_STS */

4074

#define ARIZONA_SLIMRX5_PORT_STS_SHIFT 4 /* SLIMRX5_PORT_STS */

4075

#define ARIZONA_SLIMRX5_PORT_STS_WIDTH 1 /* SLIMRX5_PORT_STS */

4076

#define ARIZONA_SLIMRX4_PORT_STS 0x0008 /* SLIMRX4_PORT_STS */

4077

#define ARIZONA_SLIMRX4_PORT_STS_MASK 0x0008 /* SLIMRX4_PORT_STS */

4078

#define ARIZONA_SLIMRX4_PORT_STS_SHIFT 3 /* SLIMRX4_PORT_STS */

4079

#define ARIZONA_SLIMRX4_PORT_STS_WIDTH 1 /* SLIMRX4_PORT_STS */

4080

#define ARIZONA_SLIMRX3_PORT_STS 0x0004 /* SLIMRX3_PORT_STS */

4081

#define ARIZONA_SLIMRX3_PORT_STS_MASK 0x0004 /* SLIMRX3_PORT_STS */

4082

#define ARIZONA_SLIMRX3_PORT_STS_SHIFT 2 /* SLIMRX3_PORT_STS */

4083

#define ARIZONA_SLIMRX3_PORT_STS_WIDTH 1 /* SLIMRX3_PORT_STS */

4084

#define ARIZONA_SLIMRX2_PORT_STS 0x0002 /* SLIMRX2_PORT_STS */

4085

#define ARIZONA_SLIMRX2_PORT_STS_MASK 0x0002 /* SLIMRX2_PORT_STS */

4086

#define ARIZONA_SLIMRX2_PORT_STS_SHIFT 1 /* SLIMRX2_PORT_STS */

4087

#define ARIZONA_SLIMRX2_PORT_STS_WIDTH 1 /* SLIMRX2_PORT_STS */

4088

#define ARIZONA_SLIMRX1_PORT_STS 0x0001 /* SLIMRX1_PORT_STS */

4089

#define ARIZONA_SLIMRX1_PORT_STS_MASK 0x0001 /* SLIMRX1_PORT_STS */

4090

#define ARIZONA_SLIMRX1_PORT_STS_SHIFT 0 /* SLIMRX1_PORT_STS */

4091

#define ARIZONA_SLIMRX1_PORT_STS_WIDTH 1 /* SLIMRX1_PORT_STS */

4092

4093

/*

4094

* R1528 (0x5F8) - SLIMbus TX Port Status

4095

*/

4096

#define ARIZONA_SLIMTX8_PORT_STS 0x0080 /* SLIMTX8_PORT_STS */

4097

#define ARIZONA_SLIMTX8_PORT_STS_MASK 0x0080 /* SLIMTX8_PORT_STS */

4098

#define ARIZONA_SLIMTX8_PORT_STS_SHIFT 7 /* SLIMTX8_PORT_STS */

4099

#define ARIZONA_SLIMTX8_PORT_STS_WIDTH 1 /* SLIMTX8_PORT_STS */

4100

#define ARIZONA_SLIMTX7_PORT_STS 0x0040 /* SLIMTX7_PORT_STS */

4101

#define ARIZONA_SLIMTX7_PORT_STS_MASK 0x0040 /* SLIMTX7_PORT_STS */

4102

#define ARIZONA_SLIMTX7_PORT_STS_SHIFT 6 /* SLIMTX7_PORT_STS */

4103

#define ARIZONA_SLIMTX7_PORT_STS_WIDTH 1 /* SLIMTX7_PORT_STS */

4104

#define ARIZONA_SLIMTX6_PORT_STS 0x0020 /* SLIMTX6_PORT_STS */

4105

#define ARIZONA_SLIMTX6_PORT_STS_MASK 0x0020 /* SLIMTX6_PORT_STS */

4106

#define ARIZONA_SLIMTX6_PORT_STS_SHIFT 5 /* SLIMTX6_PORT_STS */

4107

#define ARIZONA_SLIMTX6_PORT_STS_WIDTH 1 /* SLIMTX6_PORT_STS */

4108

#define ARIZONA_SLIMTX5_PORT_STS 0x0010 /* SLIMTX5_PORT_STS */

4109

#define ARIZONA_SLIMTX5_PORT_STS_MASK 0x0010 /* SLIMTX5_PORT_STS */

4110

#define ARIZONA_SLIMTX5_PORT_STS_SHIFT 4 /* SLIMTX5_PORT_STS */

4111

#define ARIZONA_SLIMTX5_PORT_STS_WIDTH 1 /* SLIMTX5_PORT_STS */

4112

#define ARIZONA_SLIMTX4_PORT_STS 0x0008 /* SLIMTX4_PORT_STS */

4113

#define ARIZONA_SLIMTX4_PORT_STS_MASK 0x0008 /* SLIMTX4_PORT_STS */

4114

#define ARIZONA_SLIMTX4_PORT_STS_SHIFT 3 /* SLIMTX4_PORT_STS */

4115

#define ARIZONA_SLIMTX4_PORT_STS_WIDTH 1 /* SLIMTX4_PORT_STS */

4116

#define ARIZONA_SLIMTX3_PORT_STS 0x0004 /* SLIMTX3_PORT_STS */

4117

#define ARIZONA_SLIMTX3_PORT_STS_MASK 0x0004 /* SLIMTX3_PORT_STS */

4118

#define ARIZONA_SLIMTX3_PORT_STS_SHIFT 2 /* SLIMTX3_PORT_STS */

4119

#define ARIZONA_SLIMTX3_PORT_STS_WIDTH 1 /* SLIMTX3_PORT_STS */

4120

#define ARIZONA_SLIMTX2_PORT_STS 0x0002 /* SLIMTX2_PORT_STS */

4121

#define ARIZONA_SLIMTX2_PORT_STS_MASK 0x0002 /* SLIMTX2_PORT_STS */

4122

#define ARIZONA_SLIMTX2_PORT_STS_SHIFT 1 /* SLIMTX2_PORT_STS */

4123

#define ARIZONA_SLIMTX2_PORT_STS_WIDTH 1 /* SLIMTX2_PORT_STS */

4124

#define ARIZONA_SLIMTX1_PORT_STS 0x0001 /* SLIMTX1_PORT_STS */

4125

#define ARIZONA_SLIMTX1_PORT_STS_MASK 0x0001 /* SLIMTX1_PORT_STS */

4126

#define ARIZONA_SLIMTX1_PORT_STS_SHIFT 0 /* SLIMTX1_PORT_STS */

4127

#define ARIZONA_SLIMTX1_PORT_STS_WIDTH 1 /* SLIMTX1_PORT_STS */

4128

4129

/*

4130

* R3087 (0xC0F) - IRQ CTRL 1

4131

*/

4132

#define ARIZONA_IRQ_POL 0x0400 /* IRQ_POL */

4133

#define ARIZONA_IRQ_POL_MASK 0x0400 /* IRQ_POL */

4134

#define ARIZONA_IRQ_POL_SHIFT 10 /* IRQ_POL */

4135

#define ARIZONA_IRQ_POL_WIDTH 1 /* IRQ_POL */

4136

#define ARIZONA_IRQ_OP_CFG 0x0200 /* IRQ_OP_CFG */

4137

#define ARIZONA_IRQ_OP_CFG_MASK 0x0200 /* IRQ_OP_CFG */

4138

#define ARIZONA_IRQ_OP_CFG_SHIFT 9 /* IRQ_OP_CFG */

4139

#define ARIZONA_IRQ_OP_CFG_WIDTH 1 /* IRQ_OP_CFG */

4140

4141

/*

4142

* R3088 (0xC10) - GPIO Debounce Config

4143

*/

4144

#define ARIZONA_GP_DBTIME_MASK 0xF000 /* GP_DBTIME - [15:12] */

4145

#define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */

4146

#define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */

4147

4148

/*

4149

* R3104 (0xC20) - Misc Pad Ctrl 1

4150

*/

4151

#define ARIZONA_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */

4152

#define ARIZONA_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */

4153

#define ARIZONA_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */

4154

#define ARIZONA_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */

4155

#define ARIZONA_MCLK2_PD 0x2000 /* MCLK2_PD */

4156

#define ARIZONA_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */

4157

#define ARIZONA_MCLK2_PD_SHIFT 13 /* MCLK2_PD */

4158

#define ARIZONA_MCLK2_PD_WIDTH 1 /* MCLK2_PD */

4159

#define ARIZONA_RSTB_PU 0x0002 /* RSTB_PU */

4160

#define ARIZONA_RSTB_PU_MASK 0x0002 /* RSTB_PU */

4161

#define ARIZONA_RSTB_PU_SHIFT 1 /* RSTB_PU */

4162

#define ARIZONA_RSTB_PU_WIDTH 1 /* RSTB_PU */

4163

4164

/*

4165

* R3105 (0xC21) - Misc Pad Ctrl 2

4166

*/

4167

#define ARIZONA_MCLK1_PD 0x1000 /* MCLK1_PD */

4168

#define ARIZONA_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */

4169

#define ARIZONA_MCLK1_PD_SHIFT 12 /* MCLK1_PD */

4170

#define ARIZONA_MCLK1_PD_WIDTH 1 /* MCLK1_PD */

4171

#define ARIZONA_MICD_PD 0x0100 /* MICD_PD */

4172

#define ARIZONA_MICD_PD_MASK 0x0100 /* MICD_PD */

4173

#define ARIZONA_MICD_PD_SHIFT 8 /* MICD_PD */

4174

#define ARIZONA_MICD_PD_WIDTH 1 /* MICD_PD */

4175

#define ARIZONA_ADDR_PD 0x0001 /* ADDR_PD */

4176

#define ARIZONA_ADDR_PD_MASK 0x0001 /* ADDR_PD */

4177

#define ARIZONA_ADDR_PD_SHIFT 0 /* ADDR_PD */

4178

#define ARIZONA_ADDR_PD_WIDTH 1 /* ADDR_PD */

4179

4180

/*

4181

* R3106 (0xC22) - Misc Pad Ctrl 3

4182

*/

4183

#define ARIZONA_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */

4184

#define ARIZONA_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */

4185

#define ARIZONA_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */

4186

#define ARIZONA_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */

4187

#define ARIZONA_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */

4188

#define ARIZONA_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */

4189

#define ARIZONA_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */

4190

#define ARIZONA_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */

4191

#define ARIZONA_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */

4192

#define ARIZONA_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */

4193

#define ARIZONA_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */

4194

#define ARIZONA_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */

4195

#define ARIZONA_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */

4196

#define ARIZONA_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */

4197

#define ARIZONA_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */

4198

#define ARIZONA_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */

4199

4200

/*

4201

* R3107 (0xC23) - Misc Pad Ctrl 4

4202

*/

4203

#define ARIZONA_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */

4204

#define ARIZONA_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */

4205

#define ARIZONA_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */

4206

#define ARIZONA_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */

4207

#define ARIZONA_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */

4208

#define ARIZONA_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */

4209

#define ARIZONA_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */

4210

#define ARIZONA_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */

4211

#define ARIZONA_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */

4212

#define ARIZONA_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */

4213

#define ARIZONA_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */

4214

#define ARIZONA_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */

4215

#define ARIZONA_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */

4216

#define ARIZONA_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */

4217

#define ARIZONA_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */

4218

#define ARIZONA_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */

4219

#define ARIZONA_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */

4220

#define ARIZONA_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */

4221

#define ARIZONA_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */

4222

#define ARIZONA_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */

4223

#define ARIZONA_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */

4224

#define ARIZONA_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */

4225

#define ARIZONA_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */

4226

#define ARIZONA_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */

4227

4228

/*

4229

* R3108 (0xC24) - Misc Pad Ctrl 5

4230

*/

4231

#define ARIZONA_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */

4232

#define ARIZONA_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */

4233

#define ARIZONA_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */

4234

#define ARIZONA_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */

4235

#define ARIZONA_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */

4236

#define ARIZONA_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */

4237

#define ARIZONA_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */

4238

#define ARIZONA_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */

4239

#define ARIZONA_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */

4240

#define ARIZONA_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */

4241

#define ARIZONA_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */

4242

#define ARIZONA_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */

4243

#define ARIZONA_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */

4244

#define ARIZONA_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */

4245

#define ARIZONA_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */

4246

#define ARIZONA_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */

4247

#define ARIZONA_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */

4248

#define ARIZONA_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */

4249

#define ARIZONA_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */

4250

#define ARIZONA_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */

4251

#define ARIZONA_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */

4252

#define ARIZONA_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */

4253

#define ARIZONA_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */

4254

#define ARIZONA_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */

4255

4256

/*

4257

* R3109 (0xC25) - Misc Pad Ctrl 6

4258

*/

4259

#define ARIZONA_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */

4260

#define ARIZONA_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */

4261

#define ARIZONA_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */

4262

#define ARIZONA_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */

4263

#define ARIZONA_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */

4264

#define ARIZONA_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */

4265

#define ARIZONA_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */

4266

#define ARIZONA_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */

4267

#define ARIZONA_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */

4268

#define ARIZONA_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */

4269

#define ARIZONA_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */

4270

#define ARIZONA_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */

4271

#define ARIZONA_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */

4272

#define ARIZONA_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */

4273

#define ARIZONA_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */

4274

#define ARIZONA_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */

4275

#define ARIZONA_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */

4276

#define ARIZONA_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */

4277

#define ARIZONA_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */

4278

#define ARIZONA_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */

4279

#define ARIZONA_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */

4280

#define ARIZONA_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */

4281

#define ARIZONA_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */

4282

#define ARIZONA_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */

4283

4284

/*

4285

* R3328 (0xD00) - Interrupt Status 1

4286

*/

4287

#define ARIZONA_GP4_EINT1 0x0008 /* GP4_EINT1 */

4288

#define ARIZONA_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */

4289

#define ARIZONA_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */

4290

#define ARIZONA_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */

4291

#define ARIZONA_GP3_EINT1 0x0004 /* GP3_EINT1 */

4292

#define ARIZONA_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */

4293

#define ARIZONA_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */

4294

#define ARIZONA_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */

4295

#define ARIZONA_GP2_EINT1 0x0002 /* GP2_EINT1 */

4296

#define ARIZONA_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */

4297

#define ARIZONA_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */

4298

#define ARIZONA_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */

4299

#define ARIZONA_GP1_EINT1 0x0001 /* GP1_EINT1 */

4300

#define ARIZONA_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */

4301

#define ARIZONA_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */

4302

#define ARIZONA_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */

4303

4304

/*

4305

* R3329 (0xD01) - Interrupt Status 2

4306

*/

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

4307

#define ARIZONA_DSP4_RAM_RDY_EINT1 0x0800 /* DSP4_RAM_RDY_EINT1 */

4308

#define ARIZONA_DSP4_RAM_RDY_EINT1_MASK 0x0800 /* DSP4_RAM_RDY_EINT1 */

4309

#define ARIZONA_DSP4_RAM_RDY_EINT1_SHIFT 11 /* DSP4_RAM_RDY_EINT1 */

4310

#define ARIZONA_DSP4_RAM_RDY_EINT1_WIDTH 1 /* DSP4_RAM_RDY_EINT1 */

4311

#define ARIZONA_DSP3_RAM_RDY_EINT1 0x0400 /* DSP3_RAM_RDY_EINT1 */

4312

#define ARIZONA_DSP3_RAM_RDY_EINT1_MASK 0x0400 /* DSP3_RAM_RDY_EINT1 */

4313

#define ARIZONA_DSP3_RAM_RDY_EINT1_SHIFT 10 /* DSP3_RAM_RDY_EINT1 */

4314

#define ARIZONA_DSP3_RAM_RDY_EINT1_WIDTH 1 /* DSP3_RAM_RDY_EINT1 */

4315

#define ARIZONA_DSP2_RAM_RDY_EINT1 0x0200 /* DSP2_RAM_RDY_EINT1 */

4316

#define ARIZONA_DSP2_RAM_RDY_EINT1_MASK 0x0200 /* DSP2_RAM_RDY_EINT1 */

4317

#define ARIZONA_DSP2_RAM_RDY_EINT1_SHIFT 9 /* DSP2_RAM_RDY_EINT1 */

4318

#define ARIZONA_DSP2_RAM_RDY_EINT1_WIDTH 1 /* DSP2_RAM_RDY_EINT1 */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

4319

#define ARIZONA_DSP1_RAM_RDY_EINT1 0x0100 /* DSP1_RAM_RDY_EINT1 */

4320

#define ARIZONA_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* DSP1_RAM_RDY_EINT1 */

4321

#define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT 8 /* DSP1_RAM_RDY_EINT1 */

4322

#define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH 1 /* DSP1_RAM_RDY_EINT1 */

Mark Brown

2012-07-09 19:33:15 +0100

[diff] [blame]

4323

#define ARIZONA_DSP_IRQ8_EINT1 0x0080 /* DSP_IRQ8_EINT1 */

4324

#define ARIZONA_DSP_IRQ8_EINT1_MASK 0x0080 /* DSP_IRQ8_EINT1 */

4325

#define ARIZONA_DSP_IRQ8_EINT1_SHIFT 7 /* DSP_IRQ8_EINT1 */

4326

#define ARIZONA_DSP_IRQ8_EINT1_WIDTH 1 /* DSP_IRQ8_EINT1 */

4327

#define ARIZONA_DSP_IRQ7_EINT1 0x0040 /* DSP_IRQ7_EINT1 */

4328

#define ARIZONA_DSP_IRQ7_EINT1_MASK 0x0040 /* DSP_IRQ7_EINT1 */

4329

#define ARIZONA_DSP_IRQ7_EINT1_SHIFT 6 /* DSP_IRQ7_EINT1 */

4330

#define ARIZONA_DSP_IRQ7_EINT1_WIDTH 1 /* DSP_IRQ7_EINT1 */

4331

#define ARIZONA_DSP_IRQ6_EINT1 0x0020 /* DSP_IRQ6_EINT1 */

4332

#define ARIZONA_DSP_IRQ6_EINT1_MASK 0x0020 /* DSP_IRQ6_EINT1 */

4333

#define ARIZONA_DSP_IRQ6_EINT1_SHIFT 5 /* DSP_IRQ6_EINT1 */

4334

#define ARIZONA_DSP_IRQ6_EINT1_WIDTH 1 /* DSP_IRQ6_EINT1 */

4335

#define ARIZONA_DSP_IRQ5_EINT1 0x0010 /* DSP_IRQ5_EINT1 */

4336

#define ARIZONA_DSP_IRQ5_EINT1_MASK 0x0010 /* DSP_IRQ5_EINT1 */

4337

#define ARIZONA_DSP_IRQ5_EINT1_SHIFT 4 /* DSP_IRQ5_EINT1 */

4338

#define ARIZONA_DSP_IRQ5_EINT1_WIDTH 1 /* DSP_IRQ5_EINT1 */

4339

#define ARIZONA_DSP_IRQ4_EINT1 0x0008 /* DSP_IRQ4_EINT1 */

4340

#define ARIZONA_DSP_IRQ4_EINT1_MASK 0x0008 /* DSP_IRQ4_EINT1 */

4341

#define ARIZONA_DSP_IRQ4_EINT1_SHIFT 3 /* DSP_IRQ4_EINT1 */

4342

#define ARIZONA_DSP_IRQ4_EINT1_WIDTH 1 /* DSP_IRQ4_EINT1 */

4343

#define ARIZONA_DSP_IRQ3_EINT1 0x0004 /* DSP_IRQ3_EINT1 */

4344

#define ARIZONA_DSP_IRQ3_EINT1_MASK 0x0004 /* DSP_IRQ3_EINT1 */

4345

#define ARIZONA_DSP_IRQ3_EINT1_SHIFT 2 /* DSP_IRQ3_EINT1 */

4346

#define ARIZONA_DSP_IRQ3_EINT1_WIDTH 1 /* DSP_IRQ3_EINT1 */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

4347

#define ARIZONA_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */

4348

#define ARIZONA_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */

4349

#define ARIZONA_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */

4350

#define ARIZONA_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */

4351

#define ARIZONA_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */

4352

#define ARIZONA_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */

4353

#define ARIZONA_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */

4354

#define ARIZONA_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */

4355

4356

/*

4357

* R3330 (0xD02) - Interrupt Status 3

4358

*/

4359

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */

4360

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */

4361

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */

4362

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */

4363

#define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */

4364

#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */

4365

#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */

4366

#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */

4367

#define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */

4368

#define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */

4369

#define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */

4370

#define ARIZONA_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */

4371

#define ARIZONA_MICDET_EINT1 0x1000 /* MICDET_EINT1 */

4372

#define ARIZONA_MICDET_EINT1_MASK 0x1000 /* MICDET_EINT1 */

4373

#define ARIZONA_MICDET_EINT1_SHIFT 12 /* MICDET_EINT1 */

4374

#define ARIZONA_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */

4375

#define ARIZONA_WSEQ_DONE_EINT1 0x0800 /* WSEQ_DONE_EINT1 */

4376

#define ARIZONA_WSEQ_DONE_EINT1_MASK 0x0800 /* WSEQ_DONE_EINT1 */

4377

#define ARIZONA_WSEQ_DONE_EINT1_SHIFT 11 /* WSEQ_DONE_EINT1 */

4378

#define ARIZONA_WSEQ_DONE_EINT1_WIDTH 1 /* WSEQ_DONE_EINT1 */

4379

#define ARIZONA_DRC2_SIG_DET_EINT1 0x0400 /* DRC2_SIG_DET_EINT1 */

4380

#define ARIZONA_DRC2_SIG_DET_EINT1_MASK 0x0400 /* DRC2_SIG_DET_EINT1 */

4381

#define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT 10 /* DRC2_SIG_DET_EINT1 */

4382

#define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */

4383

#define ARIZONA_DRC1_SIG_DET_EINT1 0x0200 /* DRC1_SIG_DET_EINT1 */

4384

#define ARIZONA_DRC1_SIG_DET_EINT1_MASK 0x0200 /* DRC1_SIG_DET_EINT1 */

4385

#define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT 9 /* DRC1_SIG_DET_EINT1 */

4386

#define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */

4387

#define ARIZONA_ASRC2_LOCK_EINT1 0x0100 /* ASRC2_LOCK_EINT1 */

4388

#define ARIZONA_ASRC2_LOCK_EINT1_MASK 0x0100 /* ASRC2_LOCK_EINT1 */

4389

#define ARIZONA_ASRC2_LOCK_EINT1_SHIFT 8 /* ASRC2_LOCK_EINT1 */

4390

#define ARIZONA_ASRC2_LOCK_EINT1_WIDTH 1 /* ASRC2_LOCK_EINT1 */

4391

#define ARIZONA_ASRC1_LOCK_EINT1 0x0080 /* ASRC1_LOCK_EINT1 */

4392

#define ARIZONA_ASRC1_LOCK_EINT1_MASK 0x0080 /* ASRC1_LOCK_EINT1 */

4393

#define ARIZONA_ASRC1_LOCK_EINT1_SHIFT 7 /* ASRC1_LOCK_EINT1 */

4394

#define ARIZONA_ASRC1_LOCK_EINT1_WIDTH 1 /* ASRC1_LOCK_EINT1 */

4395

#define ARIZONA_UNDERCLOCKED_EINT1 0x0040 /* UNDERCLOCKED_EINT1 */

4396

#define ARIZONA_UNDERCLOCKED_EINT1_MASK 0x0040 /* UNDERCLOCKED_EINT1 */

4397

#define ARIZONA_UNDERCLOCKED_EINT1_SHIFT 6 /* UNDERCLOCKED_EINT1 */

4398

#define ARIZONA_UNDERCLOCKED_EINT1_WIDTH 1 /* UNDERCLOCKED_EINT1 */

4399

#define ARIZONA_OVERCLOCKED_EINT1 0x0020 /* OVERCLOCKED_EINT1 */

4400

#define ARIZONA_OVERCLOCKED_EINT1_MASK 0x0020 /* OVERCLOCKED_EINT1 */

4401

#define ARIZONA_OVERCLOCKED_EINT1_SHIFT 5 /* OVERCLOCKED_EINT1 */

4402

#define ARIZONA_OVERCLOCKED_EINT1_WIDTH 1 /* OVERCLOCKED_EINT1 */

4403

#define ARIZONA_FLL2_LOCK_EINT1 0x0008 /* FLL2_LOCK_EINT1 */

4404

#define ARIZONA_FLL2_LOCK_EINT1_MASK 0x0008 /* FLL2_LOCK_EINT1 */

4405

#define ARIZONA_FLL2_LOCK_EINT1_SHIFT 3 /* FLL2_LOCK_EINT1 */

4406

#define ARIZONA_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */

4407

#define ARIZONA_FLL1_LOCK_EINT1 0x0004 /* FLL1_LOCK_EINT1 */

4408

#define ARIZONA_FLL1_LOCK_EINT1_MASK 0x0004 /* FLL1_LOCK_EINT1 */

4409

#define ARIZONA_FLL1_LOCK_EINT1_SHIFT 2 /* FLL1_LOCK_EINT1 */

4410

#define ARIZONA_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */

4411

#define ARIZONA_CLKGEN_ERR_EINT1 0x0002 /* CLKGEN_ERR_EINT1 */

4412

#define ARIZONA_CLKGEN_ERR_EINT1_MASK 0x0002 /* CLKGEN_ERR_EINT1 */

4413

#define ARIZONA_CLKGEN_ERR_EINT1_SHIFT 1 /* CLKGEN_ERR_EINT1 */

4414

#define ARIZONA_CLKGEN_ERR_EINT1_WIDTH 1 /* CLKGEN_ERR_EINT1 */

4415

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */

4416

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */

4417

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT1 */

4418

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT1 */

4419

4420

/*

4421

* R3331 (0xD03) - Interrupt Status 4

4422

*/

4423

#define ARIZONA_ASRC_CFG_ERR_EINT1 0x8000 /* ASRC_CFG_ERR_EINT1 */

4424

#define ARIZONA_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* ASRC_CFG_ERR_EINT1 */

4425

#define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT 15 /* ASRC_CFG_ERR_EINT1 */

4426

#define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */

4427

#define ARIZONA_AIF3_ERR_EINT1 0x4000 /* AIF3_ERR_EINT1 */

4428

#define ARIZONA_AIF3_ERR_EINT1_MASK 0x4000 /* AIF3_ERR_EINT1 */

4429

#define ARIZONA_AIF3_ERR_EINT1_SHIFT 14 /* AIF3_ERR_EINT1 */

4430

#define ARIZONA_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */

4431

#define ARIZONA_AIF2_ERR_EINT1 0x2000 /* AIF2_ERR_EINT1 */

4432

#define ARIZONA_AIF2_ERR_EINT1_MASK 0x2000 /* AIF2_ERR_EINT1 */

4433

#define ARIZONA_AIF2_ERR_EINT1_SHIFT 13 /* AIF2_ERR_EINT1 */

4434

#define ARIZONA_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */

4435

#define ARIZONA_AIF1_ERR_EINT1 0x1000 /* AIF1_ERR_EINT1 */

4436

#define ARIZONA_AIF1_ERR_EINT1_MASK 0x1000 /* AIF1_ERR_EINT1 */

4437

#define ARIZONA_AIF1_ERR_EINT1_SHIFT 12 /* AIF1_ERR_EINT1 */

4438

#define ARIZONA_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */

4439

#define ARIZONA_CTRLIF_ERR_EINT1 0x0800 /* CTRLIF_ERR_EINT1 */

4440

#define ARIZONA_CTRLIF_ERR_EINT1_MASK 0x0800 /* CTRLIF_ERR_EINT1 */

4441

#define ARIZONA_CTRLIF_ERR_EINT1_SHIFT 11 /* CTRLIF_ERR_EINT1 */

4442

#define ARIZONA_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */

4443

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */

4444

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */

4445

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT1 */

4446

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */

4447

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */

4448

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */

4449

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT1 */

4450

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */

4451

#define ARIZONA_SYSCLK_ENA_LOW_EINT1 0x0100 /* SYSCLK_ENA_LOW_EINT1 */

4452

#define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT1 */

4453

#define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* SYSCLK_ENA_LOW_EINT1 */

4454

#define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */

4455

#define ARIZONA_ISRC1_CFG_ERR_EINT1 0x0080 /* ISRC1_CFG_ERR_EINT1 */

4456

#define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* ISRC1_CFG_ERR_EINT1 */

4457

#define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* ISRC1_CFG_ERR_EINT1 */

4458

#define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */

4459

#define ARIZONA_ISRC2_CFG_ERR_EINT1 0x0040 /* ISRC2_CFG_ERR_EINT1 */

4460

#define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */

4461

#define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */

4462

#define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */

4463

4464

/*

4465

* R3332 (0xD04) - Interrupt Status 5

4466

*/

4467

#define ARIZONA_BOOT_DONE_EINT1 0x0100 /* BOOT_DONE_EINT1 */

4468

#define ARIZONA_BOOT_DONE_EINT1_MASK 0x0100 /* BOOT_DONE_EINT1 */

4469

#define ARIZONA_BOOT_DONE_EINT1_SHIFT 8 /* BOOT_DONE_EINT1 */

4470

#define ARIZONA_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */

4471

#define ARIZONA_DCS_DAC_DONE_EINT1 0x0080 /* DCS_DAC_DONE_EINT1 */

4472

#define ARIZONA_DCS_DAC_DONE_EINT1_MASK 0x0080 /* DCS_DAC_DONE_EINT1 */

4473

#define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT 7 /* DCS_DAC_DONE_EINT1 */

4474

#define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH 1 /* DCS_DAC_DONE_EINT1 */

4475

#define ARIZONA_DCS_HP_DONE_EINT1 0x0040 /* DCS_HP_DONE_EINT1 */

4476

#define ARIZONA_DCS_HP_DONE_EINT1_MASK 0x0040 /* DCS_HP_DONE_EINT1 */

4477

#define ARIZONA_DCS_HP_DONE_EINT1_SHIFT 6 /* DCS_HP_DONE_EINT1 */

4478

#define ARIZONA_DCS_HP_DONE_EINT1_WIDTH 1 /* DCS_HP_DONE_EINT1 */

4479

#define ARIZONA_FLL2_CLOCK_OK_EINT1 0x0002 /* FLL2_CLOCK_OK_EINT1 */

4480

#define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* FLL2_CLOCK_OK_EINT1 */

4481

#define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* FLL2_CLOCK_OK_EINT1 */

4482

#define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* FLL2_CLOCK_OK_EINT1 */

4483

#define ARIZONA_FLL1_CLOCK_OK_EINT1 0x0001 /* FLL1_CLOCK_OK_EINT1 */

4484

#define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* FLL1_CLOCK_OK_EINT1 */

4485

#define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */

4486

#define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */

4487

4488

/*

4489

* R3336 (0xD08) - Interrupt Status 1 Mask

4490

*/

4491

#define ARIZONA_IM_GP4_EINT1 0x0008 /* IM_GP4_EINT1 */

4492

#define ARIZONA_IM_GP4_EINT1_MASK 0x0008 /* IM_GP4_EINT1 */

4493

#define ARIZONA_IM_GP4_EINT1_SHIFT 3 /* IM_GP4_EINT1 */

4494

#define ARIZONA_IM_GP4_EINT1_WIDTH 1 /* IM_GP4_EINT1 */

4495

#define ARIZONA_IM_GP3_EINT1 0x0004 /* IM_GP3_EINT1 */

4496

#define ARIZONA_IM_GP3_EINT1_MASK 0x0004 /* IM_GP3_EINT1 */

4497

#define ARIZONA_IM_GP3_EINT1_SHIFT 2 /* IM_GP3_EINT1 */

4498

#define ARIZONA_IM_GP3_EINT1_WIDTH 1 /* IM_GP3_EINT1 */

4499

#define ARIZONA_IM_GP2_EINT1 0x0002 /* IM_GP2_EINT1 */

4500

#define ARIZONA_IM_GP2_EINT1_MASK 0x0002 /* IM_GP2_EINT1 */

4501

#define ARIZONA_IM_GP2_EINT1_SHIFT 1 /* IM_GP2_EINT1 */

4502

#define ARIZONA_IM_GP2_EINT1_WIDTH 1 /* IM_GP2_EINT1 */

4503

#define ARIZONA_IM_GP1_EINT1 0x0001 /* IM_GP1_EINT1 */

4504

#define ARIZONA_IM_GP1_EINT1_MASK 0x0001 /* IM_GP1_EINT1 */

4505

#define ARIZONA_IM_GP1_EINT1_SHIFT 0 /* IM_GP1_EINT1 */

4506

#define ARIZONA_IM_GP1_EINT1_WIDTH 1 /* IM_GP1_EINT1 */

4507

4508

/*

4509

* R3337 (0xD09) - Interrupt Status 2 Mask

4510

*/

4511

#define ARIZONA_IM_DSP1_RAM_RDY_EINT1 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */

4512

#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */

4513

#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT1 */

4514

#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT1 */

4515

#define ARIZONA_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */

4516

#define ARIZONA_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */

4517

#define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */

4518

#define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */

4519

#define ARIZONA_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */

4520

#define ARIZONA_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */

4521

#define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */

4522

#define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */

4523

4524

/*

4525

* R3338 (0xD0A) - Interrupt Status 3 Mask

4526

*/

4527

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */

4528

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */

4529

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */

4530

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */

4531

#define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */

4532

#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */

4533

#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */

4534

#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */

4535

#define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */

4536

#define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */

4537

#define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */

4538

#define ARIZONA_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */

4539

#define ARIZONA_IM_MICDET_EINT1 0x1000 /* IM_MICDET_EINT1 */

4540

#define ARIZONA_IM_MICDET_EINT1_MASK 0x1000 /* IM_MICDET_EINT1 */

4541

#define ARIZONA_IM_MICDET_EINT1_SHIFT 12 /* IM_MICDET_EINT1 */

4542

#define ARIZONA_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */

4543

#define ARIZONA_IM_WSEQ_DONE_EINT1 0x0800 /* IM_WSEQ_DONE_EINT1 */

4544

#define ARIZONA_IM_WSEQ_DONE_EINT1_MASK 0x0800 /* IM_WSEQ_DONE_EINT1 */

4545

#define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT 11 /* IM_WSEQ_DONE_EINT1 */

4546

#define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH 1 /* IM_WSEQ_DONE_EINT1 */

4547

#define ARIZONA_IM_DRC2_SIG_DET_EINT1 0x0400 /* IM_DRC2_SIG_DET_EINT1 */

4548

#define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT1 */

4549

#define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT 10 /* IM_DRC2_SIG_DET_EINT1 */

4550

#define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */

4551

#define ARIZONA_IM_DRC1_SIG_DET_EINT1 0x0200 /* IM_DRC1_SIG_DET_EINT1 */

4552

#define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT1 */

4553

#define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT 9 /* IM_DRC1_SIG_DET_EINT1 */

4554

#define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */

4555

#define ARIZONA_IM_ASRC2_LOCK_EINT1 0x0100 /* IM_ASRC2_LOCK_EINT1 */

4556

#define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK 0x0100 /* IM_ASRC2_LOCK_EINT1 */

4557

#define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT 8 /* IM_ASRC2_LOCK_EINT1 */

4558

#define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_LOCK_EINT1 */

4559

#define ARIZONA_IM_ASRC1_LOCK_EINT1 0x0080 /* IM_ASRC1_LOCK_EINT1 */

4560

#define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK 0x0080 /* IM_ASRC1_LOCK_EINT1 */

4561

#define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT 7 /* IM_ASRC1_LOCK_EINT1 */

4562

#define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_LOCK_EINT1 */

4563

#define ARIZONA_IM_UNDERCLOCKED_EINT1 0x0040 /* IM_UNDERCLOCKED_EINT1 */

4564

#define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK 0x0040 /* IM_UNDERCLOCKED_EINT1 */

4565

#define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT 6 /* IM_UNDERCLOCKED_EINT1 */

4566

#define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH 1 /* IM_UNDERCLOCKED_EINT1 */

4567

#define ARIZONA_IM_OVERCLOCKED_EINT1 0x0020 /* IM_OVERCLOCKED_EINT1 */

4568

#define ARIZONA_IM_OVERCLOCKED_EINT1_MASK 0x0020 /* IM_OVERCLOCKED_EINT1 */

4569

#define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT 5 /* IM_OVERCLOCKED_EINT1 */

4570

#define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH 1 /* IM_OVERCLOCKED_EINT1 */

4571

#define ARIZONA_IM_FLL2_LOCK_EINT1 0x0008 /* IM_FLL2_LOCK_EINT1 */

4572

#define ARIZONA_IM_FLL2_LOCK_EINT1_MASK 0x0008 /* IM_FLL2_LOCK_EINT1 */

4573

#define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT 3 /* IM_FLL2_LOCK_EINT1 */

4574

#define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */

4575

#define ARIZONA_IM_FLL1_LOCK_EINT1 0x0004 /* IM_FLL1_LOCK_EINT1 */

4576

#define ARIZONA_IM_FLL1_LOCK_EINT1_MASK 0x0004 /* IM_FLL1_LOCK_EINT1 */

4577

#define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT 2 /* IM_FLL1_LOCK_EINT1 */

4578

#define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */

4579

#define ARIZONA_IM_CLKGEN_ERR_EINT1 0x0002 /* IM_CLKGEN_ERR_EINT1 */

4580

#define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK 0x0002 /* IM_CLKGEN_ERR_EINT1 */

4581

#define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT 1 /* IM_CLKGEN_ERR_EINT1 */

4582

#define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_EINT1 */

4583

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */

4584

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */

4585

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT1 */

4586

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT1 */

4587

4588

/*

4589

* R3339 (0xD0B) - Interrupt Status 4 Mask

4590

*/

4591

#define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */

4592

#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */

4593

#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */

4594

#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */

4595

#define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */

4596

#define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */

4597

#define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */

4598

#define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */

4599

#define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */

4600

#define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */

4601

#define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */

4602

#define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */

4603

#define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */

4604

#define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */

4605

#define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */

4606

#define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */

4607

#define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */

4608

#define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */

4609

#define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */

4610

#define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */

4611

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */

4612

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */

4613

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */

4614

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */

4615

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */

4616

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */

4617

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */

4618

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */

4619

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */

4620

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */

4621

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */

4622

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */

4623

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */

4624

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */

4625

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */

4626

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */

4627

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */

4628

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */

4629

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */

4630

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */

4631

4632

/*

4633

* R3340 (0xD0C) - Interrupt Status 5 Mask

4634

*/

4635

#define ARIZONA_IM_BOOT_DONE_EINT1 0x0100 /* IM_BOOT_DONE_EINT1 */

4636

#define ARIZONA_IM_BOOT_DONE_EINT1_MASK 0x0100 /* IM_BOOT_DONE_EINT1 */

4637

#define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT 8 /* IM_BOOT_DONE_EINT1 */

4638

#define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */

4639

#define ARIZONA_IM_DCS_DAC_DONE_EINT1 0x0080 /* IM_DCS_DAC_DONE_EINT1 */

4640

#define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT1 */

4641

#define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT 7 /* IM_DCS_DAC_DONE_EINT1 */

4642

#define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH 1 /* IM_DCS_DAC_DONE_EINT1 */

4643

#define ARIZONA_IM_DCS_HP_DONE_EINT1 0x0040 /* IM_DCS_HP_DONE_EINT1 */

4644

#define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK 0x0040 /* IM_DCS_HP_DONE_EINT1 */

4645

#define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT 6 /* IM_DCS_HP_DONE_EINT1 */

4646

#define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH 1 /* IM_DCS_HP_DONE_EINT1 */

4647

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */

4648

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */

4649

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT1 */

4650

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT1 */

4651

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */

4652

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */

4653

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */

4654

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */

4655

4656

/*

4657

* R3343 (0xD0F) - Interrupt Control

4658

*/

4659

#define ARIZONA_IM_IRQ1 0x0001 /* IM_IRQ1 */

4660

#define ARIZONA_IM_IRQ1_MASK 0x0001 /* IM_IRQ1 */

4661

#define ARIZONA_IM_IRQ1_SHIFT 0 /* IM_IRQ1 */

4662

#define ARIZONA_IM_IRQ1_WIDTH 1 /* IM_IRQ1 */

4663

4664

/*

4665

* R3344 (0xD10) - IRQ2 Status 1

4666

*/

4667

#define ARIZONA_GP4_EINT2 0x0008 /* GP4_EINT2 */

4668

#define ARIZONA_GP4_EINT2_MASK 0x0008 /* GP4_EINT2 */

4669

#define ARIZONA_GP4_EINT2_SHIFT 3 /* GP4_EINT2 */

4670

#define ARIZONA_GP4_EINT2_WIDTH 1 /* GP4_EINT2 */

4671

#define ARIZONA_GP3_EINT2 0x0004 /* GP3_EINT2 */

4672

#define ARIZONA_GP3_EINT2_MASK 0x0004 /* GP3_EINT2 */

4673

#define ARIZONA_GP3_EINT2_SHIFT 2 /* GP3_EINT2 */

4674

#define ARIZONA_GP3_EINT2_WIDTH 1 /* GP3_EINT2 */

4675

#define ARIZONA_GP2_EINT2 0x0002 /* GP2_EINT2 */

4676

#define ARIZONA_GP2_EINT2_MASK 0x0002 /* GP2_EINT2 */

4677

#define ARIZONA_GP2_EINT2_SHIFT 1 /* GP2_EINT2 */

4678

#define ARIZONA_GP2_EINT2_WIDTH 1 /* GP2_EINT2 */

4679

#define ARIZONA_GP1_EINT2 0x0001 /* GP1_EINT2 */

4680

#define ARIZONA_GP1_EINT2_MASK 0x0001 /* GP1_EINT2 */

4681

#define ARIZONA_GP1_EINT2_SHIFT 0 /* GP1_EINT2 */

4682

#define ARIZONA_GP1_EINT2_WIDTH 1 /* GP1_EINT2 */

4683

4684

/*

4685

* R3345 (0xD11) - IRQ2 Status 2

4686

*/

4687

#define ARIZONA_DSP1_RAM_RDY_EINT2 0x0100 /* DSP1_RAM_RDY_EINT2 */

4688

#define ARIZONA_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* DSP1_RAM_RDY_EINT2 */

4689

#define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT 8 /* DSP1_RAM_RDY_EINT2 */

4690

#define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH 1 /* DSP1_RAM_RDY_EINT2 */

4691

#define ARIZONA_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */

4692

#define ARIZONA_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */

4693

#define ARIZONA_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */

4694

#define ARIZONA_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */

4695

#define ARIZONA_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */

4696

#define ARIZONA_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */

4697

#define ARIZONA_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */

4698

#define ARIZONA_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */

4699

4700

/*

4701

* R3346 (0xD12) - IRQ2 Status 3

4702

*/

4703

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */

4704

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */

4705

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */

4706

#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */

4707

#define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */

4708

#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */

4709

#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */

4710

#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */

4711

#define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */

4712

#define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */

4713

#define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */

4714

#define ARIZONA_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */

4715

#define ARIZONA_MICDET_EINT2 0x1000 /* MICDET_EINT2 */

4716

#define ARIZONA_MICDET_EINT2_MASK 0x1000 /* MICDET_EINT2 */

4717

#define ARIZONA_MICDET_EINT2_SHIFT 12 /* MICDET_EINT2 */

4718

#define ARIZONA_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */

4719

#define ARIZONA_WSEQ_DONE_EINT2 0x0800 /* WSEQ_DONE_EINT2 */

4720

#define ARIZONA_WSEQ_DONE_EINT2_MASK 0x0800 /* WSEQ_DONE_EINT2 */

4721

#define ARIZONA_WSEQ_DONE_EINT2_SHIFT 11 /* WSEQ_DONE_EINT2 */

4722

#define ARIZONA_WSEQ_DONE_EINT2_WIDTH 1 /* WSEQ_DONE_EINT2 */

4723

#define ARIZONA_DRC2_SIG_DET_EINT2 0x0400 /* DRC2_SIG_DET_EINT2 */

4724

#define ARIZONA_DRC2_SIG_DET_EINT2_MASK 0x0400 /* DRC2_SIG_DET_EINT2 */

4725

#define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT 10 /* DRC2_SIG_DET_EINT2 */

4726

#define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */

4727

#define ARIZONA_DRC1_SIG_DET_EINT2 0x0200 /* DRC1_SIG_DET_EINT2 */

4728

#define ARIZONA_DRC1_SIG_DET_EINT2_MASK 0x0200 /* DRC1_SIG_DET_EINT2 */

4729

#define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT 9 /* DRC1_SIG_DET_EINT2 */

4730

#define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */

4731

#define ARIZONA_ASRC2_LOCK_EINT2 0x0100 /* ASRC2_LOCK_EINT2 */

4732

#define ARIZONA_ASRC2_LOCK_EINT2_MASK 0x0100 /* ASRC2_LOCK_EINT2 */

4733

#define ARIZONA_ASRC2_LOCK_EINT2_SHIFT 8 /* ASRC2_LOCK_EINT2 */

4734

#define ARIZONA_ASRC2_LOCK_EINT2_WIDTH 1 /* ASRC2_LOCK_EINT2 */

4735

#define ARIZONA_ASRC1_LOCK_EINT2 0x0080 /* ASRC1_LOCK_EINT2 */

4736

#define ARIZONA_ASRC1_LOCK_EINT2_MASK 0x0080 /* ASRC1_LOCK_EINT2 */

4737

#define ARIZONA_ASRC1_LOCK_EINT2_SHIFT 7 /* ASRC1_LOCK_EINT2 */

4738

#define ARIZONA_ASRC1_LOCK_EINT2_WIDTH 1 /* ASRC1_LOCK_EINT2 */

4739

#define ARIZONA_UNDERCLOCKED_EINT2 0x0040 /* UNDERCLOCKED_EINT2 */

4740

#define ARIZONA_UNDERCLOCKED_EINT2_MASK 0x0040 /* UNDERCLOCKED_EINT2 */

4741

#define ARIZONA_UNDERCLOCKED_EINT2_SHIFT 6 /* UNDERCLOCKED_EINT2 */

4742

#define ARIZONA_UNDERCLOCKED_EINT2_WIDTH 1 /* UNDERCLOCKED_EINT2 */

4743

#define ARIZONA_OVERCLOCKED_EINT2 0x0020 /* OVERCLOCKED_EINT2 */

4744

#define ARIZONA_OVERCLOCKED_EINT2_MASK 0x0020 /* OVERCLOCKED_EINT2 */

4745

#define ARIZONA_OVERCLOCKED_EINT2_SHIFT 5 /* OVERCLOCKED_EINT2 */

4746

#define ARIZONA_OVERCLOCKED_EINT2_WIDTH 1 /* OVERCLOCKED_EINT2 */

4747

#define ARIZONA_FLL2_LOCK_EINT2 0x0008 /* FLL2_LOCK_EINT2 */

4748

#define ARIZONA_FLL2_LOCK_EINT2_MASK 0x0008 /* FLL2_LOCK_EINT2 */

4749

#define ARIZONA_FLL2_LOCK_EINT2_SHIFT 3 /* FLL2_LOCK_EINT2 */

4750

#define ARIZONA_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */

4751

#define ARIZONA_FLL1_LOCK_EINT2 0x0004 /* FLL1_LOCK_EINT2 */

4752

#define ARIZONA_FLL1_LOCK_EINT2_MASK 0x0004 /* FLL1_LOCK_EINT2 */

4753

#define ARIZONA_FLL1_LOCK_EINT2_SHIFT 2 /* FLL1_LOCK_EINT2 */

4754

#define ARIZONA_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */

4755

#define ARIZONA_CLKGEN_ERR_EINT2 0x0002 /* CLKGEN_ERR_EINT2 */

4756

#define ARIZONA_CLKGEN_ERR_EINT2_MASK 0x0002 /* CLKGEN_ERR_EINT2 */

4757

#define ARIZONA_CLKGEN_ERR_EINT2_SHIFT 1 /* CLKGEN_ERR_EINT2 */

4758

#define ARIZONA_CLKGEN_ERR_EINT2_WIDTH 1 /* CLKGEN_ERR_EINT2 */

4759

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */

4760

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */

4761

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT2 */

4762

#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT2 */

4763

4764

/*

4765

* R3347 (0xD13) - IRQ2 Status 4

4766

*/

4767

#define ARIZONA_ASRC_CFG_ERR_EINT2 0x8000 /* ASRC_CFG_ERR_EINT2 */

4768

#define ARIZONA_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* ASRC_CFG_ERR_EINT2 */

4769

#define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT 15 /* ASRC_CFG_ERR_EINT2 */

4770

#define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */

4771

#define ARIZONA_AIF3_ERR_EINT2 0x4000 /* AIF3_ERR_EINT2 */

4772

#define ARIZONA_AIF3_ERR_EINT2_MASK 0x4000 /* AIF3_ERR_EINT2 */

4773

#define ARIZONA_AIF3_ERR_EINT2_SHIFT 14 /* AIF3_ERR_EINT2 */

4774

#define ARIZONA_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */

4775

#define ARIZONA_AIF2_ERR_EINT2 0x2000 /* AIF2_ERR_EINT2 */

4776

#define ARIZONA_AIF2_ERR_EINT2_MASK 0x2000 /* AIF2_ERR_EINT2 */

4777

#define ARIZONA_AIF2_ERR_EINT2_SHIFT 13 /* AIF2_ERR_EINT2 */

4778

#define ARIZONA_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */

4779

#define ARIZONA_AIF1_ERR_EINT2 0x1000 /* AIF1_ERR_EINT2 */

4780

#define ARIZONA_AIF1_ERR_EINT2_MASK 0x1000 /* AIF1_ERR_EINT2 */

4781

#define ARIZONA_AIF1_ERR_EINT2_SHIFT 12 /* AIF1_ERR_EINT2 */

4782

#define ARIZONA_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */

4783

#define ARIZONA_CTRLIF_ERR_EINT2 0x0800 /* CTRLIF_ERR_EINT2 */

4784

#define ARIZONA_CTRLIF_ERR_EINT2_MASK 0x0800 /* CTRLIF_ERR_EINT2 */

4785

#define ARIZONA_CTRLIF_ERR_EINT2_SHIFT 11 /* CTRLIF_ERR_EINT2 */

4786

#define ARIZONA_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */

4787

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */

4788

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */

4789

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT2 */

4790

#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */

4791

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */

4792

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */

4793

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT2 */

4794

#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */

4795

#define ARIZONA_SYSCLK_ENA_LOW_EINT2 0x0100 /* SYSCLK_ENA_LOW_EINT2 */

4796

#define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT2 */

4797

#define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* SYSCLK_ENA_LOW_EINT2 */

4798

#define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */

4799

#define ARIZONA_ISRC1_CFG_ERR_EINT2 0x0080 /* ISRC1_CFG_ERR_EINT2 */

4800

#define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* ISRC1_CFG_ERR_EINT2 */

4801

#define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* ISRC1_CFG_ERR_EINT2 */

4802

#define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */

4803

#define ARIZONA_ISRC2_CFG_ERR_EINT2 0x0040 /* ISRC2_CFG_ERR_EINT2 */

4804

#define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */

4805

#define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */

4806

#define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */

4807

4808

/*

4809

* R3348 (0xD14) - IRQ2 Status 5

4810

*/

4811

#define ARIZONA_BOOT_DONE_EINT2 0x0100 /* BOOT_DONE_EINT2 */

4812

#define ARIZONA_BOOT_DONE_EINT2_MASK 0x0100 /* BOOT_DONE_EINT2 */

4813

#define ARIZONA_BOOT_DONE_EINT2_SHIFT 8 /* BOOT_DONE_EINT2 */

4814

#define ARIZONA_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */

4815

#define ARIZONA_DCS_DAC_DONE_EINT2 0x0080 /* DCS_DAC_DONE_EINT2 */

4816

#define ARIZONA_DCS_DAC_DONE_EINT2_MASK 0x0080 /* DCS_DAC_DONE_EINT2 */

4817

#define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT 7 /* DCS_DAC_DONE_EINT2 */

4818

#define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH 1 /* DCS_DAC_DONE_EINT2 */

4819

#define ARIZONA_DCS_HP_DONE_EINT2 0x0040 /* DCS_HP_DONE_EINT2 */

4820

#define ARIZONA_DCS_HP_DONE_EINT2_MASK 0x0040 /* DCS_HP_DONE_EINT2 */

4821

#define ARIZONA_DCS_HP_DONE_EINT2_SHIFT 6 /* DCS_HP_DONE_EINT2 */

4822

#define ARIZONA_DCS_HP_DONE_EINT2_WIDTH 1 /* DCS_HP_DONE_EINT2 */

4823

#define ARIZONA_FLL2_CLOCK_OK_EINT2 0x0002 /* FLL2_CLOCK_OK_EINT2 */

4824

#define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* FLL2_CLOCK_OK_EINT2 */

4825

#define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* FLL2_CLOCK_OK_EINT2 */

4826

#define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* FLL2_CLOCK_OK_EINT2 */

4827

#define ARIZONA_FLL1_CLOCK_OK_EINT2 0x0001 /* FLL1_CLOCK_OK_EINT2 */

4828

#define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* FLL1_CLOCK_OK_EINT2 */

4829

#define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */

4830

#define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */

4831

4832

/*

4833

* R3352 (0xD18) - IRQ2 Status 1 Mask

4834

*/

4835

#define ARIZONA_IM_GP4_EINT2 0x0008 /* IM_GP4_EINT2 */

4836

#define ARIZONA_IM_GP4_EINT2_MASK 0x0008 /* IM_GP4_EINT2 */

4837

#define ARIZONA_IM_GP4_EINT2_SHIFT 3 /* IM_GP4_EINT2 */

4838

#define ARIZONA_IM_GP4_EINT2_WIDTH 1 /* IM_GP4_EINT2 */

4839

#define ARIZONA_IM_GP3_EINT2 0x0004 /* IM_GP3_EINT2 */

4840

#define ARIZONA_IM_GP3_EINT2_MASK 0x0004 /* IM_GP3_EINT2 */

4841

#define ARIZONA_IM_GP3_EINT2_SHIFT 2 /* IM_GP3_EINT2 */

4842

#define ARIZONA_IM_GP3_EINT2_WIDTH 1 /* IM_GP3_EINT2 */

4843

#define ARIZONA_IM_GP2_EINT2 0x0002 /* IM_GP2_EINT2 */

4844

#define ARIZONA_IM_GP2_EINT2_MASK 0x0002 /* IM_GP2_EINT2 */

4845

#define ARIZONA_IM_GP2_EINT2_SHIFT 1 /* IM_GP2_EINT2 */

4846

#define ARIZONA_IM_GP2_EINT2_WIDTH 1 /* IM_GP2_EINT2 */

4847

#define ARIZONA_IM_GP1_EINT2 0x0001 /* IM_GP1_EINT2 */

4848

#define ARIZONA_IM_GP1_EINT2_MASK 0x0001 /* IM_GP1_EINT2 */

4849

#define ARIZONA_IM_GP1_EINT2_SHIFT 0 /* IM_GP1_EINT2 */

4850

#define ARIZONA_IM_GP1_EINT2_WIDTH 1 /* IM_GP1_EINT2 */

4851

4852

/*

4853

* R3353 (0xD19) - IRQ2 Status 2 Mask

4854

*/

4855

#define ARIZONA_IM_DSP1_RAM_RDY_EINT2 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */

4856

#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */

4857

#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT2 */

4858

#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT2 */

4859

#define ARIZONA_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */

4860

#define ARIZONA_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */

4861

#define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */

4862

#define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */

4863

#define ARIZONA_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */

4864

#define ARIZONA_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */

4865

#define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */

4866

#define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */

4867

4868

/*

4869

* R3354 (0xD1A) - IRQ2 Status 3 Mask

4870

*/

4871

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */

4872

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */

4873

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */

4874

#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */

4875

#define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */

4876

#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */

4877

#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */

4878

#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */

4879

#define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */

4880

#define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */

4881

#define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */

4882

#define ARIZONA_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */

4883

#define ARIZONA_IM_MICDET_EINT2 0x1000 /* IM_MICDET_EINT2 */

4884

#define ARIZONA_IM_MICDET_EINT2_MASK 0x1000 /* IM_MICDET_EINT2 */

4885

#define ARIZONA_IM_MICDET_EINT2_SHIFT 12 /* IM_MICDET_EINT2 */

4886

#define ARIZONA_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */

4887

#define ARIZONA_IM_WSEQ_DONE_EINT2 0x0800 /* IM_WSEQ_DONE_EINT2 */

4888

#define ARIZONA_IM_WSEQ_DONE_EINT2_MASK 0x0800 /* IM_WSEQ_DONE_EINT2 */

4889

#define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT 11 /* IM_WSEQ_DONE_EINT2 */

4890

#define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH 1 /* IM_WSEQ_DONE_EINT2 */

4891

#define ARIZONA_IM_DRC2_SIG_DET_EINT2 0x0400 /* IM_DRC2_SIG_DET_EINT2 */

4892

#define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT2 */

4893

#define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT 10 /* IM_DRC2_SIG_DET_EINT2 */

4894

#define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */

4895

#define ARIZONA_IM_DRC1_SIG_DET_EINT2 0x0200 /* IM_DRC1_SIG_DET_EINT2 */

4896

#define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT2 */

4897

#define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT 9 /* IM_DRC1_SIG_DET_EINT2 */

4898

#define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */

4899

#define ARIZONA_IM_ASRC2_LOCK_EINT2 0x0100 /* IM_ASRC2_LOCK_EINT2 */

4900

#define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK 0x0100 /* IM_ASRC2_LOCK_EINT2 */

4901

#define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT 8 /* IM_ASRC2_LOCK_EINT2 */

4902

#define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_LOCK_EINT2 */

4903

#define ARIZONA_IM_ASRC1_LOCK_EINT2 0x0080 /* IM_ASRC1_LOCK_EINT2 */

4904

#define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK 0x0080 /* IM_ASRC1_LOCK_EINT2 */

4905

#define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT 7 /* IM_ASRC1_LOCK_EINT2 */

4906

#define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_LOCK_EINT2 */

4907

#define ARIZONA_IM_UNDERCLOCKED_EINT2 0x0040 /* IM_UNDERCLOCKED_EINT2 */

4908

#define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK 0x0040 /* IM_UNDERCLOCKED_EINT2 */

4909

#define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT 6 /* IM_UNDERCLOCKED_EINT2 */

4910

#define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH 1 /* IM_UNDERCLOCKED_EINT2 */

4911

#define ARIZONA_IM_OVERCLOCKED_EINT2 0x0020 /* IM_OVERCLOCKED_EINT2 */

4912

#define ARIZONA_IM_OVERCLOCKED_EINT2_MASK 0x0020 /* IM_OVERCLOCKED_EINT2 */

4913

#define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT 5 /* IM_OVERCLOCKED_EINT2 */

4914

#define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH 1 /* IM_OVERCLOCKED_EINT2 */

4915

#define ARIZONA_IM_FLL2_LOCK_EINT2 0x0008 /* IM_FLL2_LOCK_EINT2 */

4916

#define ARIZONA_IM_FLL2_LOCK_EINT2_MASK 0x0008 /* IM_FLL2_LOCK_EINT2 */

4917

#define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT 3 /* IM_FLL2_LOCK_EINT2 */

4918

#define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */

4919

#define ARIZONA_IM_FLL1_LOCK_EINT2 0x0004 /* IM_FLL1_LOCK_EINT2 */

4920

#define ARIZONA_IM_FLL1_LOCK_EINT2_MASK 0x0004 /* IM_FLL1_LOCK_EINT2 */

4921

#define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT 2 /* IM_FLL1_LOCK_EINT2 */

4922

#define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */

4923

#define ARIZONA_IM_CLKGEN_ERR_EINT2 0x0002 /* IM_CLKGEN_ERR_EINT2 */

4924

#define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK 0x0002 /* IM_CLKGEN_ERR_EINT2 */

4925

#define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT 1 /* IM_CLKGEN_ERR_EINT2 */

4926

#define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_EINT2 */

4927

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */

4928

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */

4929

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT2 */

4930

#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT2 */

4931

4932

/*

4933

* R3355 (0xD1B) - IRQ2 Status 4 Mask

4934

*/

4935

#define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */

4936

#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */

4937

#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */

4938

#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */

4939

#define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */

4940

#define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */

4941

#define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */

4942

#define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */

4943

#define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */

4944

#define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */

4945

#define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */

4946

#define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */

4947

#define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */

4948

#define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */

4949

#define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */

4950

#define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */

4951

#define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */

4952

#define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */

4953

#define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */

4954

#define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */

4955

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */

4956

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */

4957

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */

4958

#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */

4959

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */

4960

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */

4961

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */

4962

#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */

4963

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */

4964

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */

4965

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */

4966

#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */

4967

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */

4968

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */

4969

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */

4970

#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */

4971

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */

4972

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */

4973

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */

4974

#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */

4975

4976

/*

4977

* R3356 (0xD1C) - IRQ2 Status 5 Mask

4978

*/

4979

4980

#define ARIZONA_IM_BOOT_DONE_EINT2 0x0100 /* IM_BOOT_DONE_EINT2 */

4981

#define ARIZONA_IM_BOOT_DONE_EINT2_MASK 0x0100 /* IM_BOOT_DONE_EINT2 */

4982

#define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT 8 /* IM_BOOT_DONE_EINT2 */

4983

#define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */

4984

#define ARIZONA_IM_DCS_DAC_DONE_EINT2 0x0080 /* IM_DCS_DAC_DONE_EINT2 */

4985

#define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT2 */

4986

#define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT 7 /* IM_DCS_DAC_DONE_EINT2 */

4987

#define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH 1 /* IM_DCS_DAC_DONE_EINT2 */

4988

#define ARIZONA_IM_DCS_HP_DONE_EINT2 0x0040 /* IM_DCS_HP_DONE_EINT2 */

4989

#define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK 0x0040 /* IM_DCS_HP_DONE_EINT2 */

4990

#define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT 6 /* IM_DCS_HP_DONE_EINT2 */

4991

#define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH 1 /* IM_DCS_HP_DONE_EINT2 */

4992

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */

4993

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */

4994

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT2 */

4995

#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT2 */

4996

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */

4997

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */

4998

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */

4999

#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */

5000

5001

/*

5002

* R3359 (0xD1F) - IRQ2 Control

5003

*/

5004

#define ARIZONA_IM_IRQ2 0x0001 /* IM_IRQ2 */

5005

#define ARIZONA_IM_IRQ2_MASK 0x0001 /* IM_IRQ2 */

5006

#define ARIZONA_IM_IRQ2_SHIFT 0 /* IM_IRQ2 */

5007

#define ARIZONA_IM_IRQ2_WIDTH 1 /* IM_IRQ2 */

5008

5009

/*

5010

* R3360 (0xD20) - Interrupt Raw Status 2

5011

*/

5012

#define ARIZONA_DSP1_RAM_RDY_STS 0x0100 /* DSP1_RAM_RDY_STS */

5013

#define ARIZONA_DSP1_RAM_RDY_STS_MASK 0x0100 /* DSP1_RAM_RDY_STS */

5014

#define ARIZONA_DSP1_RAM_RDY_STS_SHIFT 8 /* DSP1_RAM_RDY_STS */

5015

#define ARIZONA_DSP1_RAM_RDY_STS_WIDTH 1 /* DSP1_RAM_RDY_STS */

5016

#define ARIZONA_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */

5017

#define ARIZONA_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */

5018

#define ARIZONA_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */

5019

#define ARIZONA_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */

5020

#define ARIZONA_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */

5021

#define ARIZONA_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */

5022

#define ARIZONA_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */

5023

#define ARIZONA_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */

5024

5025

/*

5026

* R3361 (0xD21) - Interrupt Raw Status 3

5027

*/

5028

#define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */

5029

#define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */

5030

#define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */

5031

#define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */

5032

#define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */

5033

#define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */

5034

#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */

5035

#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */

5036

#define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */

5037

#define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */

5038

#define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */

5039

#define ARIZONA_HPDET_STS_WIDTH 1 /* HPDET_STS */

5040

#define ARIZONA_MICDET_STS 0x1000 /* MICDET_STS */

5041

#define ARIZONA_MICDET_STS_MASK 0x1000 /* MICDET_STS */

5042

#define ARIZONA_MICDET_STS_SHIFT 12 /* MICDET_STS */

5043

#define ARIZONA_MICDET_STS_WIDTH 1 /* MICDET_STS */

5044

#define ARIZONA_WSEQ_DONE_STS 0x0800 /* WSEQ_DONE_STS */

5045

#define ARIZONA_WSEQ_DONE_STS_MASK 0x0800 /* WSEQ_DONE_STS */

5046

#define ARIZONA_WSEQ_DONE_STS_SHIFT 11 /* WSEQ_DONE_STS */

5047

#define ARIZONA_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */

5048

#define ARIZONA_DRC2_SIG_DET_STS 0x0400 /* DRC2_SIG_DET_STS */

5049

#define ARIZONA_DRC2_SIG_DET_STS_MASK 0x0400 /* DRC2_SIG_DET_STS */

5050

#define ARIZONA_DRC2_SIG_DET_STS_SHIFT 10 /* DRC2_SIG_DET_STS */

5051

#define ARIZONA_DRC2_SIG_DET_STS_WIDTH 1 /* DRC2_SIG_DET_STS */

5052

#define ARIZONA_DRC1_SIG_DET_STS 0x0200 /* DRC1_SIG_DET_STS */

5053

#define ARIZONA_DRC1_SIG_DET_STS_MASK 0x0200 /* DRC1_SIG_DET_STS */

5054

#define ARIZONA_DRC1_SIG_DET_STS_SHIFT 9 /* DRC1_SIG_DET_STS */

5055

#define ARIZONA_DRC1_SIG_DET_STS_WIDTH 1 /* DRC1_SIG_DET_STS */

5056

#define ARIZONA_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */

5057

#define ARIZONA_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */

5058

#define ARIZONA_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */

5059

#define ARIZONA_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */

5060

#define ARIZONA_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */

5061

#define ARIZONA_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */

5062

#define ARIZONA_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */

5063

#define ARIZONA_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */

5064

#define ARIZONA_UNDERCLOCKED_STS 0x0040 /* UNDERCLOCKED_STS */

5065

#define ARIZONA_UNDERCLOCKED_STS_MASK 0x0040 /* UNDERCLOCKED_STS */

5066

#define ARIZONA_UNDERCLOCKED_STS_SHIFT 6 /* UNDERCLOCKED_STS */

5067

#define ARIZONA_UNDERCLOCKED_STS_WIDTH 1 /* UNDERCLOCKED_STS */

5068

#define ARIZONA_OVERCLOCKED_STS 0x0020 /* OVERCLOCKED_STS */

5069

#define ARIZONA_OVERCLOCKED_STS_MASK 0x0020 /* OVERCLOCKED_STS */

5070

#define ARIZONA_OVERCLOCKED_STS_SHIFT 5 /* OVERCLOCKED_STS */

5071

#define ARIZONA_OVERCLOCKED_STS_WIDTH 1 /* OVERCLOCKED_STS */

5072

#define ARIZONA_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */

5073

#define ARIZONA_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */

5074

#define ARIZONA_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */

5075

#define ARIZONA_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */

5076

#define ARIZONA_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */

5077

#define ARIZONA_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */

5078

#define ARIZONA_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */

5079

#define ARIZONA_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */

5080

#define ARIZONA_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */

5081

#define ARIZONA_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */

5082

#define ARIZONA_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */

5083

#define ARIZONA_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */

5084

#define ARIZONA_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */

5085

#define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */

5086

#define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */

5087

#define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */

5088

5089

/*

5090

* R3362 (0xD22) - Interrupt Raw Status 4

5091

*/

5092

#define ARIZONA_ASRC_CFG_ERR_STS 0x8000 /* ASRC_CFG_ERR_STS */

5093

#define ARIZONA_ASRC_CFG_ERR_STS_MASK 0x8000 /* ASRC_CFG_ERR_STS */

5094

#define ARIZONA_ASRC_CFG_ERR_STS_SHIFT 15 /* ASRC_CFG_ERR_STS */

5095

#define ARIZONA_ASRC_CFG_ERR_STS_WIDTH 1 /* ASRC_CFG_ERR_STS */

5096

#define ARIZONA_AIF3_ERR_STS 0x4000 /* AIF3_ERR_STS */

5097

#define ARIZONA_AIF3_ERR_STS_MASK 0x4000 /* AIF3_ERR_STS */

5098

#define ARIZONA_AIF3_ERR_STS_SHIFT 14 /* AIF3_ERR_STS */

5099

#define ARIZONA_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */

5100

#define ARIZONA_AIF2_ERR_STS 0x2000 /* AIF2_ERR_STS */

5101

#define ARIZONA_AIF2_ERR_STS_MASK 0x2000 /* AIF2_ERR_STS */

5102

#define ARIZONA_AIF2_ERR_STS_SHIFT 13 /* AIF2_ERR_STS */

5103

#define ARIZONA_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */

5104

#define ARIZONA_AIF1_ERR_STS 0x1000 /* AIF1_ERR_STS */

5105

#define ARIZONA_AIF1_ERR_STS_MASK 0x1000 /* AIF1_ERR_STS */

5106

#define ARIZONA_AIF1_ERR_STS_SHIFT 12 /* AIF1_ERR_STS */

5107

#define ARIZONA_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */

5108

#define ARIZONA_CTRLIF_ERR_STS 0x0800 /* CTRLIF_ERR_STS */

5109

#define ARIZONA_CTRLIF_ERR_STS_MASK 0x0800 /* CTRLIF_ERR_STS */

5110

#define ARIZONA_CTRLIF_ERR_STS_SHIFT 11 /* CTRLIF_ERR_STS */

5111

#define ARIZONA_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */

5112

#define ARIZONA_MIXER_DROPPED_SAMPLE_STS 0x0400 /* MIXER_DROPPED_SAMPLE_STS */

5113

#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_STS */

5114

#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT 10 /* MIXER_DROPPED_SAMPLE_STS */

5115

#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH 1 /* MIXER_DROPPED_SAMPLE_STS */

5116

#define ARIZONA_ASYNC_CLK_ENA_LOW_STS 0x0200 /* ASYNC_CLK_ENA_LOW_STS */

5117

#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_STS */

5118

#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT 9 /* ASYNC_CLK_ENA_LOW_STS */

5119

#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH 1 /* ASYNC_CLK_ENA_LOW_STS */

5120

#define ARIZONA_SYSCLK_ENA_LOW_STS 0x0100 /* SYSCLK_ENA_LOW_STS */

5121

#define ARIZONA_SYSCLK_ENA_LOW_STS_MASK 0x0100 /* SYSCLK_ENA_LOW_STS */

5122

#define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT 8 /* SYSCLK_ENA_LOW_STS */

5123

#define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH 1 /* SYSCLK_ENA_LOW_STS */

5124

#define ARIZONA_ISRC1_CFG_ERR_STS 0x0080 /* ISRC1_CFG_ERR_STS */

5125

#define ARIZONA_ISRC1_CFG_ERR_STS_MASK 0x0080 /* ISRC1_CFG_ERR_STS */

5126

#define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT 7 /* ISRC1_CFG_ERR_STS */

5127

#define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH 1 /* ISRC1_CFG_ERR_STS */

5128

#define ARIZONA_ISRC2_CFG_ERR_STS 0x0040 /* ISRC2_CFG_ERR_STS */

5129

#define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */

5130

#define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */

5131

#define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */

5132

5133

/*

5134

* R3363 (0xD23) - Interrupt Raw Status 5

5135

*/

5136

#define ARIZONA_BOOT_DONE_STS 0x0100 /* BOOT_DONE_STS */

5137

#define ARIZONA_BOOT_DONE_STS_MASK 0x0100 /* BOOT_DONE_STS */

5138

#define ARIZONA_BOOT_DONE_STS_SHIFT 8 /* BOOT_DONE_STS */

5139

#define ARIZONA_BOOT_DONE_STS_WIDTH 1 /* BOOT_DONE_STS */

5140

#define ARIZONA_DCS_DAC_DONE_STS 0x0080 /* DCS_DAC_DONE_STS */

5141

#define ARIZONA_DCS_DAC_DONE_STS_MASK 0x0080 /* DCS_DAC_DONE_STS */

5142

#define ARIZONA_DCS_DAC_DONE_STS_SHIFT 7 /* DCS_DAC_DONE_STS */

5143

#define ARIZONA_DCS_DAC_DONE_STS_WIDTH 1 /* DCS_DAC_DONE_STS */

5144

#define ARIZONA_DCS_HP_DONE_STS 0x0040 /* DCS_HP_DONE_STS */

5145

#define ARIZONA_DCS_HP_DONE_STS_MASK 0x0040 /* DCS_HP_DONE_STS */

5146

#define ARIZONA_DCS_HP_DONE_STS_SHIFT 6 /* DCS_HP_DONE_STS */

5147

#define ARIZONA_DCS_HP_DONE_STS_WIDTH 1 /* DCS_HP_DONE_STS */

5148

#define ARIZONA_FLL2_CLOCK_OK_STS 0x0002 /* FLL2_CLOCK_OK_STS */

5149

#define ARIZONA_FLL2_CLOCK_OK_STS_MASK 0x0002 /* FLL2_CLOCK_OK_STS */

5150

#define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT 1 /* FLL2_CLOCK_OK_STS */

5151

#define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH 1 /* FLL2_CLOCK_OK_STS */

5152

#define ARIZONA_FLL1_CLOCK_OK_STS 0x0001 /* FLL1_CLOCK_OK_STS */

5153

#define ARIZONA_FLL1_CLOCK_OK_STS_MASK 0x0001 /* FLL1_CLOCK_OK_STS */

5154

#define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT 0 /* FLL1_CLOCK_OK_STS */

5155

#define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH 1 /* FLL1_CLOCK_OK_STS */

5156

5157

/*

5158

* R3364 (0xD24) - Interrupt Raw Status 6

5159

*/

5160

#define ARIZONA_PWM_OVERCLOCKED_STS 0x2000 /* PWM_OVERCLOCKED_STS */

5161

#define ARIZONA_PWM_OVERCLOCKED_STS_MASK 0x2000 /* PWM_OVERCLOCKED_STS */

5162

#define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT 13 /* PWM_OVERCLOCKED_STS */

5163

#define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH 1 /* PWM_OVERCLOCKED_STS */

5164

#define ARIZONA_FX_CORE_OVERCLOCKED_STS 0x1000 /* FX_CORE_OVERCLOCKED_STS */

5165

#define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK 0x1000 /* FX_CORE_OVERCLOCKED_STS */

5166

#define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT 12 /* FX_CORE_OVERCLOCKED_STS */

5167

#define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH 1 /* FX_CORE_OVERCLOCKED_STS */

5168

#define ARIZONA_DAC_SYS_OVERCLOCKED_STS 0x0400 /* DAC_SYS_OVERCLOCKED_STS */

5169

#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* DAC_SYS_OVERCLOCKED_STS */

5170

#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT 10 /* DAC_SYS_OVERCLOCKED_STS */

5171

#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH 1 /* DAC_SYS_OVERCLOCKED_STS */

5172

#define ARIZONA_DAC_WARP_OVERCLOCKED_STS 0x0200 /* DAC_WARP_OVERCLOCKED_STS */

5173

#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* DAC_WARP_OVERCLOCKED_STS */

5174

#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT 9 /* DAC_WARP_OVERCLOCKED_STS */

5175

#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH 1 /* DAC_WARP_OVERCLOCKED_STS */

5176

#define ARIZONA_ADC_OVERCLOCKED_STS 0x0100 /* ADC_OVERCLOCKED_STS */

5177

#define ARIZONA_ADC_OVERCLOCKED_STS_MASK 0x0100 /* ADC_OVERCLOCKED_STS */

5178

#define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT 8 /* ADC_OVERCLOCKED_STS */

5179

#define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH 1 /* ADC_OVERCLOCKED_STS */

5180

#define ARIZONA_MIXER_OVERCLOCKED_STS 0x0080 /* MIXER_OVERCLOCKED_STS */

5181

#define ARIZONA_MIXER_OVERCLOCKED_STS_MASK 0x0080 /* MIXER_OVERCLOCKED_STS */

5182

#define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT 7 /* MIXER_OVERCLOCKED_STS */

5183

#define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH 1 /* MIXER_OVERCLOCKED_STS */

5184

#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */

5185

#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */

5186

#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT 6 /* AIF3_ASYNC_OVERCLOCKED_STS */

5187

#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_ASYNC_OVERCLOCKED_STS */

5188

#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */

5189

#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */

5190

#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT 5 /* AIF2_ASYNC_OVERCLOCKED_STS */

5191

#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_ASYNC_OVERCLOCKED_STS */

5192

#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */

5193

#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */

5194

#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT 4 /* AIF1_ASYNC_OVERCLOCKED_STS */

5195

#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_ASYNC_OVERCLOCKED_STS */

5196

#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */

5197

#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */

5198

#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT 3 /* AIF3_SYNC_OVERCLOCKED_STS */

5199

#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_SYNC_OVERCLOCKED_STS */

5200

#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */

5201

#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */

5202

#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT 2 /* AIF2_SYNC_OVERCLOCKED_STS */

5203

#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_SYNC_OVERCLOCKED_STS */

5204

#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */

5205

#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */

5206

#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT 1 /* AIF1_SYNC_OVERCLOCKED_STS */

5207

#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_SYNC_OVERCLOCKED_STS */

5208

#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */

5209

#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */

5210

#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT 0 /* PAD_CTRL_OVERCLOCKED_STS */

5211

#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH 1 /* PAD_CTRL_OVERCLOCKED_STS */

5212

5213

/*

5214

* R3365 (0xD25) - Interrupt Raw Status 7

5215

*/

5216

#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */

5217

#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */

5218

#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */

5219

#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */

5220

#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */

5221

#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */

5222

#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */

5223

#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */

5224

#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */

5225

#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */

5226

#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */

5227

#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */

5228

#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */

5229

#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */

5230

#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */

5231

#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */

5232

#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */

5233

#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */

5234

#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */

5235

#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */

5236

#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */

5237

#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */

5238

#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */

5239

#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */

5240

#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */

5241

#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */

5242

#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */

5243

#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */

5244

#define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */

5245

#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */

5246

#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */

5247

#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */

5248

#define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */

5249

#define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */

5250

#define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */

5251

#define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */

5252

#define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */

5253

#define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */

5254

#define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */

5255

#define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */

5256

5257

/*

5258

* R3366 (0xD26) - Interrupt Raw Status 8

5259

*/

5260

#define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */

5261

#define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */

5262

#define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */

5263

#define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */

5264

#define ARIZONA_AIF2_UNDERCLOCKED_STS 0x0200 /* AIF2_UNDERCLOCKED_STS */

5265

#define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK 0x0200 /* AIF2_UNDERCLOCKED_STS */

5266

#define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT 9 /* AIF2_UNDERCLOCKED_STS */

5267

#define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */

5268

#define ARIZONA_AIF1_UNDERCLOCKED_STS 0x0100 /* AIF1_UNDERCLOCKED_STS */

5269

#define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */

5270

#define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */

5271

#define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */

5272

#define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */

5273

#define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */

5274

#define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */

5275

#define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */

5276

#define ARIZONA_ISRC1_UNDERCLOCKED_STS 0x0020 /* ISRC1_UNDERCLOCKED_STS */

5277

#define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK 0x0020 /* ISRC1_UNDERCLOCKED_STS */

5278

#define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT 5 /* ISRC1_UNDERCLOCKED_STS */

5279

#define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */

5280

#define ARIZONA_FX_UNDERCLOCKED_STS 0x0010 /* FX_UNDERCLOCKED_STS */

5281

#define ARIZONA_FX_UNDERCLOCKED_STS_MASK 0x0010 /* FX_UNDERCLOCKED_STS */

5282

#define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT 4 /* FX_UNDERCLOCKED_STS */

5283

#define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */

5284

#define ARIZONA_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */

5285

#define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */

5286

#define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */

5287

#define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */

5288

#define ARIZONA_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */

5289

#define ARIZONA_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */

5290

#define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */

5291

#define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */

5292

#define ARIZONA_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */

5293

#define ARIZONA_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */

5294

#define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */

5295

#define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */

5296

#define ARIZONA_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */

5297

#define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */

5298

#define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */

5299

#define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */

5300

5301

/*

5302

* R3392 (0xD40) - IRQ Pin Status

5303

*/

5304

#define ARIZONA_IRQ2_STS 0x0002 /* IRQ2_STS */

5305

#define ARIZONA_IRQ2_STS_MASK 0x0002 /* IRQ2_STS */

5306

#define ARIZONA_IRQ2_STS_SHIFT 1 /* IRQ2_STS */

5307

#define ARIZONA_IRQ2_STS_WIDTH 1 /* IRQ2_STS */

5308

#define ARIZONA_IRQ1_STS 0x0001 /* IRQ1_STS */

5309

#define ARIZONA_IRQ1_STS_MASK 0x0001 /* IRQ1_STS */

5310

#define ARIZONA_IRQ1_STS_SHIFT 0 /* IRQ1_STS */

5311

#define ARIZONA_IRQ1_STS_WIDTH 1 /* IRQ1_STS */

5312

5313

/*

5314

* R3393 (0xD41) - ADSP2 IRQ0

5315

*/

5316

#define ARIZONA_DSP_IRQ2 0x0002 /* DSP_IRQ2 */

5317

#define ARIZONA_DSP_IRQ2_MASK 0x0002 /* DSP_IRQ2 */

5318

#define ARIZONA_DSP_IRQ2_SHIFT 1 /* DSP_IRQ2 */

5319

#define ARIZONA_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */

5320

#define ARIZONA_DSP_IRQ1 0x0001 /* DSP_IRQ1 */

5321

#define ARIZONA_DSP_IRQ1_MASK 0x0001 /* DSP_IRQ1 */

5322

#define ARIZONA_DSP_IRQ1_SHIFT 0 /* DSP_IRQ1 */

5323

#define ARIZONA_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */

5324

5325

/*

5326

* R3408 (0xD50) - AOD wkup and trig

5327

*/

Charles Keepax

5d9ab70

2013-02-05 10:13:38 +0000

[diff] [blame]

5328

#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */

5329

#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */

5330

#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT 7 /* MICD_CLAMP_FALL_TRIG_STS */

5331

#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH 1 /* MICD_CLAMP_FALL_TRIG_STS */

5332

#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */

5333

#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */

5334

#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT 6 /* MICD_CLAMP_RISE_TRIG_STS */

5335

#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH 1 /* MICD_CLAMP_RISE_TRIG_STS */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

5336

#define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */

5337

#define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */

5338

#define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */

5339

#define ARIZONA_GP5_FALL_TRIG_STS_WIDTH 1 /* GP5_FALL_TRIG_STS */

5340

#define ARIZONA_GP5_RISE_TRIG_STS 0x0010 /* GP5_RISE_TRIG_STS */

5341

#define ARIZONA_GP5_RISE_TRIG_STS_MASK 0x0010 /* GP5_RISE_TRIG_STS */

5342

#define ARIZONA_GP5_RISE_TRIG_STS_SHIFT 4 /* GP5_RISE_TRIG_STS */

5343

#define ARIZONA_GP5_RISE_TRIG_STS_WIDTH 1 /* GP5_RISE_TRIG_STS */

5344

#define ARIZONA_JD1_FALL_TRIG_STS 0x0008 /* JD1_FALL_TRIG_STS */

5345

#define ARIZONA_JD1_FALL_TRIG_STS_MASK 0x0008 /* JD1_FALL_TRIG_STS */

5346

#define ARIZONA_JD1_FALL_TRIG_STS_SHIFT 3 /* JD1_FALL_TRIG_STS */

5347

#define ARIZONA_JD1_FALL_TRIG_STS_WIDTH 1 /* JD1_FALL_TRIG_STS */

5348

#define ARIZONA_JD1_RISE_TRIG_STS 0x0004 /* JD1_RISE_TRIG_STS */

5349

#define ARIZONA_JD1_RISE_TRIG_STS_MASK 0x0004 /* JD1_RISE_TRIG_STS */

5350

#define ARIZONA_JD1_RISE_TRIG_STS_SHIFT 2 /* JD1_RISE_TRIG_STS */

5351

#define ARIZONA_JD1_RISE_TRIG_STS_WIDTH 1 /* JD1_RISE_TRIG_STS */

5352

#define ARIZONA_JD2_FALL_TRIG_STS 0x0002 /* JD2_FALL_TRIG_STS */

5353

#define ARIZONA_JD2_FALL_TRIG_STS_MASK 0x0002 /* JD2_FALL_TRIG_STS */

5354

#define ARIZONA_JD2_FALL_TRIG_STS_SHIFT 1 /* JD2_FALL_TRIG_STS */

5355

#define ARIZONA_JD2_FALL_TRIG_STS_WIDTH 1 /* JD2_FALL_TRIG_STS */

5356

#define ARIZONA_JD2_RISE_TRIG_STS 0x0001 /* JD2_RISE_TRIG_STS */

5357

#define ARIZONA_JD2_RISE_TRIG_STS_MASK 0x0001 /* JD2_RISE_TRIG_STS */

5358

#define ARIZONA_JD2_RISE_TRIG_STS_SHIFT 0 /* JD2_RISE_TRIG_STS */

5359

#define ARIZONA_JD2_RISE_TRIG_STS_WIDTH 1 /* JD2_RISE_TRIG_STS */

5360

5361

/*

5362

* R3409 (0xD51) - AOD IRQ1

5363

*/

Mark Brown

2013-01-11 08:55:36 +0900

[diff] [blame]

5364

#define ARIZONA_MICD_CLAMP_FALL_EINT1 0x0080 /* MICD_CLAMP_FALL_EINT1 */

5365

#define ARIZONA_MICD_CLAMP_FALL_EINT1_MASK 0x0080 /* MICD_CLAMP_FALL_EINT1 */

5366

#define ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT 7 /* MICD_CLAMP_FALL_EINT1 */

5367

#define ARIZONA_MICD_CLAMP_RISE_EINT1 0x0040 /* MICD_CLAMP_RISE_EINT1 */

5368

#define ARIZONA_MICD_CLAMP_RISE_EINT1_MASK 0x0040 /* MICD_CLAMP_RISE_EINT1 */

5369

#define ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT 6 /* MICD_CLAMP_RISE_EINT1 */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

5370

#define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */

5371

#define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */

5372

#define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */

5373

#define ARIZONA_GP5_FALL_EINT1_WIDTH 1 /* GP5_FALL_EINT1 */

5374

#define ARIZONA_GP5_RISE_EINT1 0x0010 /* GP5_RISE_EINT1 */

5375

#define ARIZONA_GP5_RISE_EINT1_MASK 0x0010 /* GP5_RISE_EINT1 */

5376

#define ARIZONA_GP5_RISE_EINT1_SHIFT 4 /* GP5_RISE_EINT1 */

5377

#define ARIZONA_GP5_RISE_EINT1_WIDTH 1 /* GP5_RISE_EINT1 */

5378

#define ARIZONA_JD1_FALL_EINT1 0x0008 /* JD1_FALL_EINT1 */

5379

#define ARIZONA_JD1_FALL_EINT1_MASK 0x0008 /* JD1_FALL_EINT1 */

5380

#define ARIZONA_JD1_FALL_EINT1_SHIFT 3 /* JD1_FALL_EINT1 */

5381

#define ARIZONA_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */

5382

#define ARIZONA_JD1_RISE_EINT1 0x0004 /* JD1_RISE_EINT1 */

5383

#define ARIZONA_JD1_RISE_EINT1_MASK 0x0004 /* JD1_RISE_EINT1 */

5384

#define ARIZONA_JD1_RISE_EINT1_SHIFT 2 /* JD1_RISE_EINT1 */

5385

#define ARIZONA_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */

5386

#define ARIZONA_JD2_FALL_EINT1 0x0002 /* JD2_FALL_EINT1 */

5387

#define ARIZONA_JD2_FALL_EINT1_MASK 0x0002 /* JD2_FALL_EINT1 */

5388

#define ARIZONA_JD2_FALL_EINT1_SHIFT 1 /* JD2_FALL_EINT1 */

5389

#define ARIZONA_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */

5390

#define ARIZONA_JD2_RISE_EINT1 0x0001 /* JD2_RISE_EINT1 */

5391

#define ARIZONA_JD2_RISE_EINT1_MASK 0x0001 /* JD2_RISE_EINT1 */

5392

#define ARIZONA_JD2_RISE_EINT1_SHIFT 0 /* JD2_RISE_EINT1 */

5393

#define ARIZONA_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */

5394

5395

/*

5396

* R3410 (0xD52) - AOD IRQ2

5397

*/

Mark Brown

2013-01-11 08:55:36 +0900

[diff] [blame]

5398

#define ARIZONA_MICD_CLAMP_FALL_EINT2 0x0080 /* MICD_CLAMP_FALL_EINT2 */

5399

#define ARIZONA_MICD_CLAMP_FALL_EINT2_MASK 0x0080 /* MICD_CLAMP_FALL_EINT2 */

5400

#define ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT 7 /* MICD_CLAMP_FALL_EINT2 */

5401

#define ARIZONA_MICD_CLAMP_RISE_EINT2 0x0040 /* MICD_CLAMP_RISE_EINT2 */

5402

#define ARIZONA_MICD_CLAMP_RISE_EINT2_MASK 0x0040 /* MICD_CLAMP_RISE_EINT2 */

5403

#define ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT 6 /* MICD_CLAMP_RISE_EINT2 */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

5404

#define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */

5405

#define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */

5406

#define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */

5407

#define ARIZONA_GP5_FALL_EINT2_WIDTH 1 /* GP5_FALL_EINT2 */

5408

#define ARIZONA_GP5_RISE_EINT2 0x0010 /* GP5_RISE_EINT2 */

5409

#define ARIZONA_GP5_RISE_EINT2_MASK 0x0010 /* GP5_RISE_EINT2 */

5410

#define ARIZONA_GP5_RISE_EINT2_SHIFT 4 /* GP5_RISE_EINT2 */

5411

#define ARIZONA_GP5_RISE_EINT2_WIDTH 1 /* GP5_RISE_EINT2 */

5412

#define ARIZONA_JD1_FALL_EINT2 0x0008 /* JD1_FALL_EINT2 */

5413

#define ARIZONA_JD1_FALL_EINT2_MASK 0x0008 /* JD1_FALL_EINT2 */

5414

#define ARIZONA_JD1_FALL_EINT2_SHIFT 3 /* JD1_FALL_EINT2 */

5415

#define ARIZONA_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */

5416

#define ARIZONA_JD1_RISE_EINT2 0x0004 /* JD1_RISE_EINT2 */

5417

#define ARIZONA_JD1_RISE_EINT2_MASK 0x0004 /* JD1_RISE_EINT2 */

5418

#define ARIZONA_JD1_RISE_EINT2_SHIFT 2 /* JD1_RISE_EINT2 */

5419

#define ARIZONA_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */

5420

#define ARIZONA_JD2_FALL_EINT2 0x0002 /* JD2_FALL_EINT2 */

5421

#define ARIZONA_JD2_FALL_EINT2_MASK 0x0002 /* JD2_FALL_EINT2 */

5422

#define ARIZONA_JD2_FALL_EINT2_SHIFT 1 /* JD2_FALL_EINT2 */

5423

#define ARIZONA_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */

5424

#define ARIZONA_JD2_RISE_EINT2 0x0001 /* JD2_RISE_EINT2 */

5425

#define ARIZONA_JD2_RISE_EINT2_MASK 0x0001 /* JD2_RISE_EINT2 */

5426

#define ARIZONA_JD2_RISE_EINT2_SHIFT 0 /* JD2_RISE_EINT2 */

5427

#define ARIZONA_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */

5428

5429

/*

5430

* R3411 (0xD53) - AOD IRQ Mask IRQ1

5431

*/

5432

#define ARIZONA_IM_GP5_FALL_EINT1 0x0020 /* IM_GP5_FALL_EINT1 */

5433

#define ARIZONA_IM_GP5_FALL_EINT1_MASK 0x0020 /* IM_GP5_FALL_EINT1 */

5434

#define ARIZONA_IM_GP5_FALL_EINT1_SHIFT 5 /* IM_GP5_FALL_EINT1 */

5435

#define ARIZONA_IM_GP5_FALL_EINT1_WIDTH 1 /* IM_GP5_FALL_EINT1 */

5436

#define ARIZONA_IM_GP5_RISE_EINT1 0x0010 /* IM_GP5_RISE_EINT1 */

5437

#define ARIZONA_IM_GP5_RISE_EINT1_MASK 0x0010 /* IM_GP5_RISE_EINT1 */

5438

#define ARIZONA_IM_GP5_RISE_EINT1_SHIFT 4 /* IM_GP5_RISE_EINT1 */

5439

#define ARIZONA_IM_GP5_RISE_EINT1_WIDTH 1 /* IM_GP5_RISE_EINT1 */

5440

#define ARIZONA_IM_JD1_FALL_EINT1 0x0008 /* IM_JD1_FALL_EINT1 */

5441

#define ARIZONA_IM_JD1_FALL_EINT1_MASK 0x0008 /* IM_JD1_FALL_EINT1 */

5442

#define ARIZONA_IM_JD1_FALL_EINT1_SHIFT 3 /* IM_JD1_FALL_EINT1 */

5443

#define ARIZONA_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */

5444

#define ARIZONA_IM_JD1_RISE_EINT1 0x0004 /* IM_JD1_RISE_EINT1 */

5445

#define ARIZONA_IM_JD1_RISE_EINT1_MASK 0x0004 /* IM_JD1_RISE_EINT1 */

5446

#define ARIZONA_IM_JD1_RISE_EINT1_SHIFT 2 /* IM_JD1_RISE_EINT1 */

5447

#define ARIZONA_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */

5448

#define ARIZONA_IM_JD2_FALL_EINT1 0x0002 /* IM_JD2_FALL_EINT1 */

5449

#define ARIZONA_IM_JD2_FALL_EINT1_MASK 0x0002 /* IM_JD2_FALL_EINT1 */

5450

#define ARIZONA_IM_JD2_FALL_EINT1_SHIFT 1 /* IM_JD2_FALL_EINT1 */

5451

#define ARIZONA_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */

5452

#define ARIZONA_IM_JD2_RISE_EINT1 0x0001 /* IM_JD2_RISE_EINT1 */

5453

#define ARIZONA_IM_JD2_RISE_EINT1_MASK 0x0001 /* IM_JD2_RISE_EINT1 */

5454

#define ARIZONA_IM_JD2_RISE_EINT1_SHIFT 0 /* IM_JD2_RISE_EINT1 */

5455

#define ARIZONA_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */

5456

5457

/*

5458

* R3412 (0xD54) - AOD IRQ Mask IRQ2

5459

*/

5460

#define ARIZONA_IM_GP5_FALL_EINT2 0x0020 /* IM_GP5_FALL_EINT2 */

5461

#define ARIZONA_IM_GP5_FALL_EINT2_MASK 0x0020 /* IM_GP5_FALL_EINT2 */

5462

#define ARIZONA_IM_GP5_FALL_EINT2_SHIFT 5 /* IM_GP5_FALL_EINT2 */

5463

#define ARIZONA_IM_GP5_FALL_EINT2_WIDTH 1 /* IM_GP5_FALL_EINT2 */

5464

#define ARIZONA_IM_GP5_RISE_EINT2 0x0010 /* IM_GP5_RISE_EINT2 */

5465

#define ARIZONA_IM_GP5_RISE_EINT2_MASK 0x0010 /* IM_GP5_RISE_EINT2 */

5466

#define ARIZONA_IM_GP5_RISE_EINT2_SHIFT 4 /* IM_GP5_RISE_EINT2 */

5467

#define ARIZONA_IM_GP5_RISE_EINT2_WIDTH 1 /* IM_GP5_RISE_EINT2 */

5468

#define ARIZONA_IM_JD1_FALL_EINT2 0x0008 /* IM_JD1_FALL_EINT2 */

5469

#define ARIZONA_IM_JD1_FALL_EINT2_MASK 0x0008 /* IM_JD1_FALL_EINT2 */

5470

#define ARIZONA_IM_JD1_FALL_EINT2_SHIFT 3 /* IM_JD1_FALL_EINT2 */

5471

#define ARIZONA_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */

5472

#define ARIZONA_IM_JD1_RISE_EINT2 0x0004 /* IM_JD1_RISE_EINT2 */

5473

#define ARIZONA_IM_JD1_RISE_EINT2_MASK 0x0004 /* IM_JD1_RISE_EINT2 */

5474

#define ARIZONA_IM_JD1_RISE_EINT2_SHIFT 2 /* IM_JD1_RISE_EINT2 */

5475

#define ARIZONA_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */

5476

#define ARIZONA_IM_JD2_FALL_EINT2 0x0002 /* IM_JD2_FALL_EINT2 */

5477

#define ARIZONA_IM_JD2_FALL_EINT2_MASK 0x0002 /* IM_JD2_FALL_EINT2 */

5478

#define ARIZONA_IM_JD2_FALL_EINT2_SHIFT 1 /* IM_JD2_FALL_EINT2 */

5479

#define ARIZONA_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */

5480

#define ARIZONA_IM_JD2_RISE_EINT2 0x0001 /* IM_JD2_RISE_EINT2 */

5481

#define ARIZONA_IM_JD2_RISE_EINT2_MASK 0x0001 /* IM_JD2_RISE_EINT2 */

5482

#define ARIZONA_IM_JD2_RISE_EINT2_SHIFT 0 /* IM_JD2_RISE_EINT2 */

5483

#define ARIZONA_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */

5484

5485

/*

5486

* R3413 (0xD55) - AOD IRQ Raw Status

5487

*/

Mark Brown

2013-01-11 08:55:36 +0900

[diff] [blame]

5488

#define ARIZONA_MICD_CLAMP_STS 0x0008 /* MICD_CLAMP_STS */

5489

#define ARIZONA_MICD_CLAMP_STS_MASK 0x0008 /* MICD_CLAMP_STS */

5490

#define ARIZONA_MICD_CLAMP_STS_SHIFT 3 /* MICD_CLAMP_STS */

5491

#define ARIZONA_MICD_CLAMP_STS_WIDTH 1 /* MICD_CLAMP_STS */

Mark Brown

2012-06-19 16:28:40 +0100

[diff] [blame]

5492

#define ARIZONA_GP5_STS 0x0004 /* GP5_STS */

5493

#define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */

5494

#define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */

5495

#define ARIZONA_GP5_STS_WIDTH 1 /* GP5_STS */

5496

#define ARIZONA_JD2_STS 0x0002 /* JD2_STS */

5497

#define ARIZONA_JD2_STS_MASK 0x0002 /* JD2_STS */

5498

#define ARIZONA_JD2_STS_SHIFT 1 /* JD2_STS */

5499

#define ARIZONA_JD2_STS_WIDTH 1 /* JD2_STS */

5500

#define ARIZONA_JD1_STS 0x0001 /* JD1_STS */

5501

#define ARIZONA_JD1_STS_MASK 0x0001 /* JD1_STS */

5502

#define ARIZONA_JD1_STS_SHIFT 0 /* JD1_STS */

5503

#define ARIZONA_JD1_STS_WIDTH 1 /* JD1_STS */

5504

5505

/*

5506

* R3414 (0xD56) - Jack detect debounce

5507

*/

Mark Brown

2013-01-11 08:55:36 +0900

[diff] [blame]

5508

#define ARIZONA_MICD_CLAMP_DB 0x0008 /* MICD_CLAMP_DB */

5509

#define ARIZONA_MICD_CLAMP_DB_MASK 0x0008 /* MICD_CLAMP_DB */

5510

#define ARIZONA_MICD_CLAMP_DB_SHIFT 3 /* MICD_CLAMP_DB */

5511

#define ARIZONA_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */

Mark Brown