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Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +00001/*
2 * Renesas SuperH DMA Engine support
3 *
4 * base is drivers/dma/flsdma.c
5 *
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +02006 * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +00007 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
9 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * - DMA of SuperH does not have Hardware DMA chain mode.
17 * - MAX DMA size is 16MB.
18 *
19 */
20
21#include <linux/init.h>
22#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090023#include <linux/slab.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000024#include <linux/interrupt.h>
25#include <linux/dmaengine.h>
26#include <linux/delay.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000027#include <linux/platform_device.h>
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +000028#include <linux/pm_runtime.h>
Magnus Dammb2623a62010-03-19 04:47:10 +000029#include <linux/sh_dma.h>
Paul Mundt03aa18f2010-12-17 19:16:10 +090030#include <linux/notifier.h>
31#include <linux/kdebug.h>
32#include <linux/spinlock.h>
33#include <linux/rculist.h>
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000034
Guennadi Liakhovetskie95be942012-07-02 22:30:53 +020035#include "../dmaengine.h"
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000036#include "shdma.h"
37
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020038#define SH_DMAE_DRV_NAME "sh-dma-engine"
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000039
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +000040/* Default MEMCPY transfer size = 2^2 = 4 bytes */
41#define LOG2_DEFAULT_XFER_SIZE 2
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020042#define SH_DMA_SLAVE_NUMBER 256
43#define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000044
Paul Mundt03aa18f2010-12-17 19:16:10 +090045/*
46 * Used for write-side mutual exclusion for the global device list,
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +000047 * read-side synchronization by way of RCU, and per-controller data.
Paul Mundt03aa18f2010-12-17 19:16:10 +090048 */
49static DEFINE_SPINLOCK(sh_dmae_lock);
50static LIST_HEAD(sh_dmae_devices);
51
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010052static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data)
53{
54 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
55
56 __raw_writel(data, shdev->chan_reg +
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020057 shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset);
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010058}
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -070059
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000060static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
61{
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000062 __raw_writel(data, sh_dc->base + reg / sizeof(u32));
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000063}
64
65static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
66{
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000067 return __raw_readl(sh_dc->base + reg / sizeof(u32));
68}
69
70static u16 dmaor_read(struct sh_dmae_device *shdev)
71{
Kuninori Morimotoe76c3af2011-06-17 08:20:56 +000072 u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
73
74 if (shdev->pdata->dmaor_is_32bit)
75 return __raw_readl(addr);
76 else
77 return __raw_readw(addr);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000078}
79
80static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
81{
Kuninori Morimotoe76c3af2011-06-17 08:20:56 +000082 u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
83
84 if (shdev->pdata->dmaor_is_32bit)
85 __raw_writel(data, addr);
86 else
87 __raw_writew(data, addr);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000088}
89
Kuninori Morimoto5899a722011-06-17 08:20:40 +000090static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
91{
92 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
93
94 __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
95}
96
97static u32 chcr_read(struct sh_dmae_chan *sh_dc)
98{
99 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
100
101 return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000102}
103
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000104/*
105 * Reset DMA controller
106 *
107 * SH7780 has two DMAOR register
108 */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000109static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000110{
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000111 unsigned short dmaor;
112 unsigned long flags;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000113
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000114 spin_lock_irqsave(&sh_dmae_lock, flags);
115
116 dmaor = dmaor_read(shdev);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000117 dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000118
119 spin_unlock_irqrestore(&sh_dmae_lock, flags);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000120}
121
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000122static int sh_dmae_rst(struct sh_dmae_device *shdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000123{
124 unsigned short dmaor;
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000125 unsigned long flags;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000126
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000127 spin_lock_irqsave(&sh_dmae_lock, flags);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000128
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000129 dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
130
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100131 if (shdev->pdata->chclr_present) {
132 int i;
133 for (i = 0; i < shdev->pdata->channel_num; i++) {
134 struct sh_dmae_chan *sh_chan = shdev->chan[i];
135 if (sh_chan)
136 chclr_write(sh_chan, 0);
137 }
138 }
139
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000140 dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
141
142 dmaor = dmaor_read(shdev);
143
144 spin_unlock_irqrestore(&sh_dmae_lock, flags);
145
146 if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200147 dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000148 return -EIO;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000149 }
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100150 if (shdev->pdata->dmaor_init & ~dmaor)
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200151 dev_warn(shdev->shdma_dev.dma_dev.dev,
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100152 "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
153 dmaor, shdev->pdata->dmaor_init);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000154 return 0;
155}
156
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000157static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000158{
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000159 u32 chcr = chcr_read(sh_chan);
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000160
161 if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
162 return true; /* working */
163
164 return false; /* waiting */
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000165}
166
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000167static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000168{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000169 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000170 struct sh_dmae_pdata *pdata = shdev->pdata;
171 int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
172 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
Guennadi Liakhovetski623b4ac2010-02-03 14:44:12 +0000173
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000174 if (cnt >= pdata->ts_shift_num)
175 cnt = 0;
176
177 return pdata->ts_shift[cnt];
178}
179
180static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
181{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000182 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000183 struct sh_dmae_pdata *pdata = shdev->pdata;
184 int i;
185
186 for (i = 0; i < pdata->ts_shift_num; i++)
187 if (pdata->ts_shift[i] == l2size)
188 break;
189
190 if (i == pdata->ts_shift_num)
191 i = 0;
192
193 return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
194 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000195}
196
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -0700197static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000198{
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -0700199 sh_dmae_writel(sh_chan, hw->sar, SAR);
200 sh_dmae_writel(sh_chan, hw->dar, DAR);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000201 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000202}
203
204static void dmae_start(struct sh_dmae_chan *sh_chan)
205{
Kuninori Morimoto67c62692011-06-17 08:20:51 +0000206 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000207 u32 chcr = chcr_read(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000208
Kuninori Morimoto260bf2c2011-06-17 08:21:05 +0000209 if (shdev->pdata->needs_tend_set)
210 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
211
Kuninori Morimoto67c62692011-06-17 08:20:51 +0000212 chcr |= CHCR_DE | shdev->chcr_ie_bit;
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000213 chcr_write(sh_chan, chcr & ~CHCR_TE);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000214}
215
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000216static void dmae_init(struct sh_dmae_chan *sh_chan)
217{
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000218 /*
219 * Default configuration for dual address memory-memory transfer.
220 * 0x400 represents auto-request.
221 */
222 u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
223 LOG2_DEFAULT_XFER_SIZE);
224 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000225 chcr_write(sh_chan, chcr);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000226}
227
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000228static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
229{
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000230 /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000231 if (dmae_is_busy(sh_chan))
232 return -EBUSY;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000233
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000234 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000235 chcr_write(sh_chan, val);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000236
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000237 return 0;
238}
239
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000240static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
241{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000242 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000243 struct sh_dmae_pdata *pdata = shdev->pdata;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200244 const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
Magnus Damm26fc02a2011-05-24 10:31:12 +0000245 u16 __iomem *addr = shdev->dmars;
Kuninori Morimoto090b9182011-06-16 05:08:28 +0000246 unsigned int shift = chan_pdata->dmars_bit;
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000247
248 if (dmae_is_busy(sh_chan))
249 return -EBUSY;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000250
Kuninori Morimoto260bf2c2011-06-17 08:21:05 +0000251 if (pdata->no_dmars)
252 return 0;
253
Magnus Damm26fc02a2011-05-24 10:31:12 +0000254 /* in the case of a missing DMARS resource use first memory window */
255 if (!addr)
256 addr = (u16 __iomem *)shdev->chan_reg;
257 addr += chan_pdata->dmars / sizeof(u16);
258
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000259 __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
260 addr);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000261
262 return 0;
263}
264
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200265static void sh_dmae_start_xfer(struct shdma_chan *schan,
266 struct shdma_desc *sdesc)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000267{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200268 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
269 shdma_chan);
270 struct sh_dmae_desc *sh_desc = container_of(sdesc,
271 struct sh_dmae_desc, shdma_desc);
272 dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
273 sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
274 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
275 /* Get the ld start address from ld_queue */
276 dmae_set_reg(sh_chan, &sh_desc->hw);
277 dmae_start(sh_chan);
278}
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000279
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200280static bool sh_dmae_channel_busy(struct shdma_chan *schan)
281{
282 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
283 shdma_chan);
284 return dmae_is_busy(sh_chan);
285}
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200286
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200287static void sh_dmae_setup_xfer(struct shdma_chan *schan,
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200288 int slave_id)
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200289{
290 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
291 shdma_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000292
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200293 if (slave_id >= 0) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200294 const struct sh_dmae_slave_config *cfg =
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200295 sh_chan->config;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000296
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200297 dmae_set_dmars(sh_chan, cfg->mid_rid);
298 dmae_set_chcr(sh_chan, cfg->chcr);
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100299 } else {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200300 dmae_init(sh_chan);
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200301 }
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000302}
303
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200304static const struct sh_dmae_slave_config *dmae_find_slave(
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200305 struct sh_dmae_chan *sh_chan, int slave_id)
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000306{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000307 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000308 struct sh_dmae_pdata *pdata = shdev->pdata;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200309 const struct sh_dmae_slave_config *cfg;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000310 int i;
311
Guennadi Liakhovetski341f4dc2012-07-05 12:29:37 +0200312 if (slave_id >= SH_DMA_SLAVE_NUMBER)
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000313 return NULL;
314
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200315 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
Guennadi Liakhovetski341f4dc2012-07-05 12:29:37 +0200316 if (cfg->slave_id == slave_id)
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200317 return cfg;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000318
319 return NULL;
320}
321
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200322static int sh_dmae_set_slave(struct shdma_chan *schan,
Guennadi Liakhovetski1ff8df42012-07-05 12:29:42 +0200323 int slave_id, bool try)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000324{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200325 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
326 shdma_chan);
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200327 const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200328 if (!cfg)
329 return -ENODEV;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000330
Guennadi Liakhovetski1ff8df42012-07-05 12:29:42 +0200331 if (!try)
332 sh_chan->config = cfg;
Linus Walleijc3635c72010-03-26 16:44:01 -0700333
334 return 0;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000335}
336
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200337static void dmae_halt(struct sh_dmae_chan *sh_chan)
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -0700338{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200339 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
340 u32 chcr = chcr_read(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000341
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200342 chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
343 chcr_write(sh_chan, chcr);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000344}
345
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200346static int sh_dmae_desc_setup(struct shdma_chan *schan,
347 struct shdma_desc *sdesc,
348 dma_addr_t src, dma_addr_t dst, size_t *len)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000349{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200350 struct sh_dmae_desc *sh_desc = container_of(sdesc,
351 struct sh_dmae_desc, shdma_desc);
352
353 if (*len > schan->max_xfer_len)
354 *len = schan->max_xfer_len;
355
356 sh_desc->hw.sar = src;
357 sh_desc->hw.dar = dst;
358 sh_desc->hw.tcr = *len;
359
360 return 0;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000361}
362
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200363static void sh_dmae_halt(struct shdma_chan *schan)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000364{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200365 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
366 shdma_chan);
367 dmae_halt(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000368}
369
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200370static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000371{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200372 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
373 shdma_chan);
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200374
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200375 if (!(chcr_read(sh_chan) & CHCR_TE))
376 return false;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000377
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200378 /* DMA stop */
379 dmae_halt(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000380
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200381 return true;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000382}
383
Guennadi Liakhovetski4f46f8a2012-07-30 21:28:27 +0200384static size_t sh_dmae_get_partial(struct shdma_chan *schan,
385 struct shdma_desc *sdesc)
386{
387 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
388 shdma_chan);
389 struct sh_dmae_desc *sh_desc = container_of(sdesc,
390 struct sh_dmae_desc, shdma_desc);
391 return (sh_desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
392 sh_chan->xmit_shift;
393}
394
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000395/* Called from error IRQ or NMI */
396static bool sh_dmae_reset(struct sh_dmae_device *shdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000397{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200398 bool ret;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000399
Guennadi Liakhovetski47a4dc22010-02-11 16:50:05 +0000400 /* halt the dma controller */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000401 sh_dmae_ctl_stop(shdev);
Guennadi Liakhovetski47a4dc22010-02-11 16:50:05 +0000402
403 /* We cannot detect, which channel caused the error, have to reset all */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200404 ret = shdma_reset(&shdev->shdma_dev);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900405
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000406 sh_dmae_rst(shdev);
Guennadi Liakhovetski47a4dc22010-02-11 16:50:05 +0000407
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200408 return ret;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000409}
Paul Mundt03aa18f2010-12-17 19:16:10 +0900410
411static irqreturn_t sh_dmae_err(int irq, void *data)
412{
Yoshihiro Shimodaff7690b2011-02-09 07:46:47 +0000413 struct sh_dmae_device *shdev = data;
414
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000415 if (!(dmaor_read(shdev) & DMAOR_AE))
Yoshihiro Shimodaff7690b2011-02-09 07:46:47 +0000416 return IRQ_NONE;
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000417
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200418 sh_dmae_reset(shdev);
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000419 return IRQ_HANDLED;
Paul Mundt03aa18f2010-12-17 19:16:10 +0900420}
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000421
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200422static bool sh_dmae_desc_completed(struct shdma_chan *schan,
423 struct shdma_desc *sdesc)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000424{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200425 struct sh_dmae_chan *sh_chan = container_of(schan,
426 struct sh_dmae_chan, shdma_chan);
427 struct sh_dmae_desc *sh_desc = container_of(sdesc,
428 struct sh_dmae_desc, shdma_desc);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000429 u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000430 u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +0100431
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200432 return (sdesc->direction == DMA_DEV_TO_MEM &&
433 (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
434 (sdesc->direction != DMA_DEV_TO_MEM &&
435 (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000436}
437
Paul Mundt03aa18f2010-12-17 19:16:10 +0900438static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
439{
Paul Mundt03aa18f2010-12-17 19:16:10 +0900440 /* Fast path out if NMIF is not asserted for this controller */
441 if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
442 return false;
443
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000444 return sh_dmae_reset(shdev);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900445}
446
447static int sh_dmae_nmi_handler(struct notifier_block *self,
448 unsigned long cmd, void *data)
449{
450 struct sh_dmae_device *shdev;
451 int ret = NOTIFY_DONE;
452 bool triggered;
453
454 /*
455 * Only concern ourselves with NMI events.
456 *
457 * Normally we would check the die chain value, but as this needs
458 * to be architecture independent, check for NMI context instead.
459 */
460 if (!in_nmi())
461 return NOTIFY_DONE;
462
463 rcu_read_lock();
464 list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
465 /*
466 * Only stop if one of the controllers has NMIF asserted,
467 * we do not want to interfere with regular address error
468 * handling or NMI events that don't concern the DMACs.
469 */
470 triggered = sh_dmae_nmi_notify(shdev);
471 if (triggered == true)
472 ret = NOTIFY_OK;
473 }
474 rcu_read_unlock();
475
476 return ret;
477}
478
479static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
480 .notifier_call = sh_dmae_nmi_handler,
481
482 /* Run before NMI debug handler and KGDB */
483 .priority = 1,
484};
485
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000486static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
487 int irq, unsigned long flags)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000488{
Guennadi Liakhovetski5bac9422010-04-21 15:36:49 +0000489 const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200490 struct shdma_dev *sdev = &shdev->shdma_dev;
491 struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
492 struct sh_dmae_chan *sh_chan;
493 struct shdma_chan *schan;
494 int err;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000495
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200496 sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
497 if (!sh_chan) {
498 dev_err(sdev->dma_dev.dev,
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +0100499 "No free memory for allocating dma channels!\n");
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000500 return -ENOMEM;
501 }
502
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200503 schan = &sh_chan->shdma_chan;
504 schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200505
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200506 shdma_chan_probe(sdev, schan, id);
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000507
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200508 sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000509
510 /* set up channel irq */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200511 if (pdev->id >= 0)
512 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
513 "sh-dmae%d.%d", pdev->id, id);
514 else
515 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
516 "sh-dma%d", id);
517
518 err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000519 if (err) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200520 dev_err(sdev->dma_dev.dev,
521 "DMA channel %d request_irq error %d\n",
522 id, err);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000523 goto err_no_irq;
524 }
525
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200526 shdev->chan[id] = sh_chan;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000527 return 0;
528
529err_no_irq:
530 /* remove from dmaengine device node */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200531 shdma_chan_remove(schan);
532 kfree(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000533 return err;
534}
535
536static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
537{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200538 struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
539 struct shdma_chan *schan;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000540 int i;
541
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200542 shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
543 struct sh_dmae_chan *sh_chan = container_of(schan,
544 struct sh_dmae_chan, shdma_chan);
545 BUG_ON(!schan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000546
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200547 shdma_free_irq(&sh_chan->shdma_chan);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000548
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200549 shdma_chan_remove(schan);
550 kfree(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000551 }
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200552 dma_dev->chancnt = 0;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000553}
554
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200555static void sh_dmae_shutdown(struct platform_device *pdev)
556{
557 struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
558 sh_dmae_ctl_stop(shdev);
559}
560
561static int sh_dmae_runtime_suspend(struct device *dev)
562{
563 return 0;
564}
565
566static int sh_dmae_runtime_resume(struct device *dev)
567{
568 struct sh_dmae_device *shdev = dev_get_drvdata(dev);
569
570 return sh_dmae_rst(shdev);
571}
572
573#ifdef CONFIG_PM
574static int sh_dmae_suspend(struct device *dev)
575{
576 return 0;
577}
578
579static int sh_dmae_resume(struct device *dev)
580{
581 struct sh_dmae_device *shdev = dev_get_drvdata(dev);
582 int i, ret;
583
584 ret = sh_dmae_rst(shdev);
585 if (ret < 0)
586 dev_err(dev, "Failed to reset!\n");
587
588 for (i = 0; i < shdev->pdata->channel_num; i++) {
589 struct sh_dmae_chan *sh_chan = shdev->chan[i];
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200590
591 if (!sh_chan->shdma_chan.desc_num)
592 continue;
593
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200594 if (sh_chan->shdma_chan.slave_id >= 0) {
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200595 const struct sh_dmae_slave_config *cfg = sh_chan->config;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200596 dmae_set_dmars(sh_chan, cfg->mid_rid);
597 dmae_set_chcr(sh_chan, cfg->chcr);
598 } else {
599 dmae_init(sh_chan);
600 }
601 }
602
603 return 0;
604}
605#else
606#define sh_dmae_suspend NULL
607#define sh_dmae_resume NULL
608#endif
609
610const struct dev_pm_ops sh_dmae_pm = {
611 .suspend = sh_dmae_suspend,
612 .resume = sh_dmae_resume,
613 .runtime_suspend = sh_dmae_runtime_suspend,
614 .runtime_resume = sh_dmae_runtime_resume,
615};
616
617static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
618{
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200619 struct sh_dmae_chan *sh_chan = container_of(schan,
620 struct sh_dmae_chan, shdma_chan);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200621
622 /*
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200623 * Implicit BUG_ON(!sh_chan->config)
624 * This is an exclusive slave DMA operation, may only be called after a
625 * successful slave configuration.
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200626 */
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200627 return sh_chan->config->addr;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200628}
629
630static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
631{
632 return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
633}
634
635static const struct shdma_ops sh_dmae_shdma_ops = {
636 .desc_completed = sh_dmae_desc_completed,
637 .halt_channel = sh_dmae_halt,
638 .channel_busy = sh_dmae_channel_busy,
639 .slave_addr = sh_dmae_slave_addr,
640 .desc_setup = sh_dmae_desc_setup,
641 .set_slave = sh_dmae_set_slave,
642 .setup_xfer = sh_dmae_setup_xfer,
643 .start_xfer = sh_dmae_start_xfer,
644 .embedded_desc = sh_dmae_embedded_desc,
645 .chan_irq = sh_dmae_chan_irq,
Guennadi Liakhovetski4f46f8a2012-07-30 21:28:27 +0200646 .get_partial = sh_dmae_get_partial,
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200647};
648
649static int __devinit sh_dmae_probe(struct platform_device *pdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000650{
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000651 struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
652 unsigned long irqflags = IRQF_DISABLED,
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200653 chan_flag[SH_DMAE_MAX_CHANNELS] = {};
654 int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
Magnus Damm300e5f92011-05-24 10:31:20 +0000655 int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000656 struct sh_dmae_device *shdev;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200657 struct dma_device *dma_dev;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000658 struct resource *chan, *dmars, *errirq_res, *chanirq_res;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000659
Dan Williams56adf7e2009-11-22 12:10:10 -0700660 /* get platform data */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000661 if (!pdata || !pdata->channel_num)
Dan Williams56adf7e2009-11-22 12:10:10 -0700662 return -ENODEV;
663
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000664 chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Magnus Damm26fc02a2011-05-24 10:31:12 +0000665 /* DMARS area is optional */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000666 dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
667 /*
668 * IRQ resources:
669 * 1. there always must be at least one IRQ IO-resource. On SH4 it is
670 * the error IRQ, in which case it is the only IRQ in this resource:
671 * start == end. If it is the only IRQ resource, all channels also
672 * use the same IRQ.
673 * 2. DMA channel IRQ resources can be specified one per resource or in
674 * ranges (start != end)
675 * 3. iff all events (channels and, optionally, error) on this
676 * controller use the same IRQ, only one IRQ resource can be
677 * specified, otherwise there must be one IRQ per channel, even if
678 * some of them are equal
679 * 4. if all IRQs on this controller are equal or if some specific IRQs
680 * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
681 * requested with the IRQF_SHARED flag
682 */
683 errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
684 if (!chan || !errirq_res)
685 return -ENODEV;
686
687 if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
688 dev_err(&pdev->dev, "DMAC register region already claimed\n");
689 return -EBUSY;
690 }
691
692 if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
693 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
694 err = -EBUSY;
695 goto ermrdmars;
696 }
697
698 err = -ENOMEM;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000699 shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
700 if (!shdev) {
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000701 dev_err(&pdev->dev, "Not enough memory\n");
702 goto ealloc;
703 }
704
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200705 dma_dev = &shdev->shdma_dev.dma_dev;
706
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000707 shdev->chan_reg = ioremap(chan->start, resource_size(chan));
708 if (!shdev->chan_reg)
709 goto emapchan;
710 if (dmars) {
711 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
712 if (!shdev->dmars)
713 goto emapdmars;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000714 }
715
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200716 if (!pdata->slave_only)
717 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
718 if (pdata->slave && pdata->slave_num)
719 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
720
721 /* Default transfer size of 32 bytes requires 32-byte alignment */
722 dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
723
724 shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
725 shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
726 err = shdma_init(&pdev->dev, &shdev->shdma_dev,
727 pdata->channel_num);
728 if (err < 0)
729 goto eshdma;
730
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000731 /* platform data */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200732 shdev->pdata = pdev->dev.platform_data;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000733
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000734 if (pdata->chcr_offset)
735 shdev->chcr_offset = pdata->chcr_offset;
736 else
737 shdev->chcr_offset = CHCR;
738
Kuninori Morimoto67c62692011-06-17 08:20:51 +0000739 if (pdata->chcr_ie_bit)
740 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
741 else
742 shdev->chcr_ie_bit = CHCR_IE;
743
Paul Mundt5c2de442011-05-31 15:53:03 +0900744 platform_set_drvdata(pdev, shdev);
745
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000746 pm_runtime_enable(&pdev->dev);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200747 err = pm_runtime_get_sync(&pdev->dev);
748 if (err < 0)
749 dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000750
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000751 spin_lock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900752 list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000753 spin_unlock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900754
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000755 /* reset dma controller - only needed as a test */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000756 err = sh_dmae_rst(shdev);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000757 if (err)
758 goto rst_err;
759
Magnus Damm927a7c92010-03-19 04:47:19 +0000760#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000761 chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
762
763 if (!chanirq_res)
764 chanirq_res = errirq_res;
765 else
766 irqres++;
767
768 if (chanirq_res == errirq_res ||
769 (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000770 irqflags = IRQF_SHARED;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000771
772 errirq = errirq_res->start;
773
774 err = request_irq(errirq, sh_dmae_err, irqflags,
775 "DMAC Address Error", shdev);
776 if (err) {
777 dev_err(&pdev->dev,
778 "DMA failed requesting irq #%d, error %d\n",
779 errirq, err);
780 goto eirq_err;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000781 }
782
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000783#else
784 chanirq_res = errirq_res;
Magnus Damm927a7c92010-03-19 04:47:19 +0000785#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000786
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000787 if (chanirq_res->start == chanirq_res->end &&
788 !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
789 /* Special case - all multiplexed */
790 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200791 if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
Magnus Damm300e5f92011-05-24 10:31:20 +0000792 chan_irq[irq_cnt] = chanirq_res->start;
793 chan_flag[irq_cnt] = IRQF_SHARED;
794 } else {
795 irq_cap = 1;
796 break;
797 }
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000798 }
799 } else {
800 do {
801 for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200802 if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
Magnus Dammdcee0bb2011-06-09 06:35:08 +0000803 irq_cap = 1;
804 break;
805 }
806
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000807 if ((errirq_res->flags & IORESOURCE_BITS) ==
808 IORESOURCE_IRQ_SHAREABLE)
809 chan_flag[irq_cnt] = IRQF_SHARED;
810 else
811 chan_flag[irq_cnt] = IRQF_DISABLED;
812 dev_dbg(&pdev->dev,
813 "Found IRQ %d for channel %d\n",
814 i, irq_cnt);
815 chan_irq[irq_cnt++] = i;
Magnus Damm300e5f92011-05-24 10:31:20 +0000816 }
817
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200818 if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
Magnus Damm300e5f92011-05-24 10:31:20 +0000819 break;
Magnus Dammdcee0bb2011-06-09 06:35:08 +0000820
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000821 chanirq_res = platform_get_resource(pdev,
822 IORESOURCE_IRQ, ++irqres);
823 } while (irq_cnt < pdata->channel_num && chanirq_res);
824 }
825
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000826 /* Create DMA Channel */
Magnus Damm300e5f92011-05-24 10:31:20 +0000827 for (i = 0; i < irq_cnt; i++) {
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000828 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000829 if (err)
830 goto chan_probe_err;
831 }
832
Magnus Damm300e5f92011-05-24 10:31:20 +0000833 if (irq_cap)
834 dev_notice(&pdev->dev, "Attempting to register %d DMA "
835 "channels when a maximum of %d are supported.\n",
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200836 pdata->channel_num, SH_DMAE_MAX_CHANNELS);
Magnus Damm300e5f92011-05-24 10:31:20 +0000837
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000838 pm_runtime_put(&pdev->dev);
839
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200840 err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
841 if (err < 0)
842 goto edmadevreg;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000843
844 return err;
845
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200846edmadevreg:
847 pm_runtime_get(&pdev->dev);
848
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000849chan_probe_err:
850 sh_dmae_chan_remove(shdev);
Magnus Damm300e5f92011-05-24 10:31:20 +0000851
Magnus Damm927a7c92010-03-19 04:47:19 +0000852#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000853 free_irq(errirq, shdev);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000854eirq_err:
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000855#endif
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000856rst_err:
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000857 spin_lock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900858 list_del_rcu(&shdev->node);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000859 spin_unlock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900860
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000861 pm_runtime_put(&pdev->dev);
Guennadi Liakhovetski467017b2011-04-29 17:09:25 +0000862 pm_runtime_disable(&pdev->dev);
863
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200864 platform_set_drvdata(pdev, NULL);
865 shdma_cleanup(&shdev->shdma_dev);
866eshdma:
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000867 if (dmars)
868 iounmap(shdev->dmars);
869emapdmars:
870 iounmap(shdev->chan_reg);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000871 synchronize_rcu();
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000872emapchan:
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000873 kfree(shdev);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000874ealloc:
875 if (dmars)
876 release_mem_region(dmars->start, resource_size(dmars));
877ermrdmars:
878 release_mem_region(chan->start, resource_size(chan));
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000879
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000880 return err;
881}
882
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200883static int __devexit sh_dmae_remove(struct platform_device *pdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000884{
885 struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200886 struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000887 struct resource *res;
888 int errirq = platform_get_irq(pdev, 0);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000889
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200890 dma_async_device_unregister(dma_dev);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000891
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000892 if (errirq > 0)
893 free_irq(errirq, shdev);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000894
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000895 spin_lock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900896 list_del_rcu(&shdev->node);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000897 spin_unlock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900898
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000899 pm_runtime_disable(&pdev->dev);
900
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200901 sh_dmae_chan_remove(shdev);
902 shdma_cleanup(&shdev->shdma_dev);
903
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000904 if (shdev->dmars)
905 iounmap(shdev->dmars);
906 iounmap(shdev->chan_reg);
907
Paul Mundt5c2de442011-05-31 15:53:03 +0900908 platform_set_drvdata(pdev, NULL);
909
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000910 synchronize_rcu();
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000911 kfree(shdev);
912
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000913 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
914 if (res)
915 release_mem_region(res->start, resource_size(res));
916 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
917 if (res)
918 release_mem_region(res->start, resource_size(res));
919
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000920 return 0;
921}
922
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000923static struct platform_driver sh_dmae_driver = {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200924 .driver = {
Guennadi Liakhovetski7a5c1062010-05-21 15:28:51 +0000925 .owner = THIS_MODULE,
Guennadi Liakhovetski467017b2011-04-29 17:09:25 +0000926 .pm = &sh_dmae_pm,
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200927 .name = SH_DMAE_DRV_NAME,
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000928 },
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200929 .remove = __devexit_p(sh_dmae_remove),
930 .shutdown = sh_dmae_shutdown,
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000931};
932
933static int __init sh_dmae_init(void)
934{
Guennadi Liakhovetski661382f2011-01-06 17:04:50 +0000935 /* Wire up NMI handling */
936 int err = register_die_notifier(&sh_dmae_nmi_notifier);
937 if (err)
938 return err;
939
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000940 return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
941}
942module_init(sh_dmae_init);
943
944static void __exit sh_dmae_exit(void)
945{
946 platform_driver_unregister(&sh_dmae_driver);
Guennadi Liakhovetski661382f2011-01-06 17:04:50 +0000947
948 unregister_die_notifier(&sh_dmae_nmi_notifier);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000949}
950module_exit(sh_dmae_exit);
951
952MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
953MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
954MODULE_LICENSE("GPL");
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200955MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);