Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | &soc { |
| 15 | qcom,cam-req-mgr { |
| 16 | compatible = "qcom,cam-req-mgr"; |
| 17 | status = "ok"; |
| 18 | }; |
| 19 | |
| 20 | cam_csiphy0: qcom,csiphy@ac65000 { |
| 21 | cell-index = <0>; |
| 22 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 23 | reg = <0x0ac65000 0x1000>; |
| 24 | reg-names = "csiphy"; |
| 25 | reg-cam-base = <0x65000>; |
| 26 | interrupts = <0 477 0>; |
| 27 | interrupt-names = "csiphy"; |
| 28 | regulator-names = "gdscr", "refgen"; |
| 29 | gdscr-supply = <&titan_top_gdsc>; |
| 30 | refgen-supply = <&refgen>; |
| 31 | csi-vdd-voltage = <1200000>; |
| 32 | mipi-csi-vdd-supply = <&pm660_l1>; |
| 33 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 34 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 35 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 36 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 37 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 38 | <&clock_camcc CAM_CC_CSIPHY0_CLK>, |
| 39 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, |
| 40 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; |
| 41 | clock-names = "camnoc_axi_clk", |
| 42 | "soc_ahb_clk", |
| 43 | "slow_ahb_src_clk", |
| 44 | "cpas_ahb_clk", |
| 45 | "cphy_rx_clk_src", |
| 46 | "csiphy0_clk", |
| 47 | "csi0phytimer_clk_src", |
| 48 | "csi0phytimer_clk"; |
| 49 | clock-cntl-level = "turbo"; |
| 50 | clock-rates = |
| 51 | <0 0 0 0 384000000 0 269333333 0>; |
| 52 | status = "ok"; |
| 53 | }; |
| 54 | |
| 55 | cam_csiphy1: qcom,csiphy@ac66000{ |
| 56 | cell-index = <1>; |
| 57 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 58 | reg = <0xac66000 0x1000>; |
| 59 | reg-names = "csiphy"; |
| 60 | reg-cam-base = <0x66000>; |
| 61 | interrupts = <0 478 0>; |
| 62 | interrupt-names = "csiphy"; |
| 63 | regulator-names = "gdscr", "refgen"; |
| 64 | gdscr-supply = <&titan_top_gdsc>; |
| 65 | refgen-supply = <&refgen>; |
| 66 | csi-vdd-voltage = <1200000>; |
| 67 | mipi-csi-vdd-supply = <&pm660_l1>; |
| 68 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 69 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 70 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 71 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 72 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 73 | <&clock_camcc CAM_CC_CSIPHY1_CLK>, |
| 74 | <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, |
| 75 | <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; |
| 76 | clock-names = "camnoc_axi_clk", |
| 77 | "soc_ahb_clk", |
| 78 | "slow_ahb_src_clk", |
| 79 | "cpas_ahb_clk", |
| 80 | "cphy_rx_clk_src", |
| 81 | "csiphy1_clk", |
| 82 | "csi1phytimer_clk_src", |
| 83 | "csi1phytimer_clk"; |
| 84 | clock-cntl-level = "turbo"; |
| 85 | clock-rates = |
| 86 | <0 0 0 0 384000000 0 269333333 0>; |
| 87 | |
| 88 | status = "ok"; |
| 89 | }; |
| 90 | |
| 91 | cam_csiphy2: qcom,csiphy@ac67000 { |
| 92 | cell-index = <2>; |
| 93 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 94 | reg = <0xac67000 0x1000>; |
| 95 | reg-names = "csiphy"; |
| 96 | reg-cam-base = <0x67000>; |
| 97 | interrupts = <0 479 0>; |
| 98 | interrupt-names = "csiphy"; |
| 99 | regulator-names = "gdscr", "refgen"; |
| 100 | gdscr-supply = <&titan_top_gdsc>; |
| 101 | refgen-supply = <&refgen>; |
| 102 | csi-vdd-voltage = <1200000>; |
| 103 | mipi-csi-vdd-supply = <&pm660_l1>; |
| 104 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 105 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 106 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 107 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 108 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 109 | <&clock_camcc CAM_CC_CSIPHY2_CLK>, |
| 110 | <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, |
| 111 | <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; |
| 112 | clock-names = "camnoc_axi_clk", |
| 113 | "soc_ahb_clk", |
| 114 | "slow_ahb_src_clk", |
| 115 | "cpas_ahb_clk", |
| 116 | "cphy_rx_clk_src", |
| 117 | "csiphy2_clk", |
| 118 | "csi2phytimer_clk_src", |
| 119 | "csi2phytimer_clk"; |
| 120 | clock-cntl-level = "turbo"; |
| 121 | clock-rates = |
| 122 | <0 0 0 0 384000000 0 269333333 0>; |
| 123 | status = "ok"; |
| 124 | }; |
| 125 | |
| 126 | cam_cci: qcom,cci@ac4a000 { |
| 127 | cell-index = <0>; |
| 128 | compatible = "qcom,cci"; |
| 129 | #address-cells = <1>; |
| 130 | #size-cells = <0>; |
| 131 | reg = <0xac4a000 0x4000>; |
| 132 | reg-names = "cci"; |
| 133 | reg-cam-base = <0x4a000>; |
| 134 | interrupt-names = "cci"; |
| 135 | interrupts = <0 460 0>; |
| 136 | status = "ok"; |
| 137 | gdscr-supply = <&titan_top_gdsc>; |
| 138 | regulator-names = "gdscr"; |
| 139 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 140 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 141 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 142 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 143 | <&clock_camcc CAM_CC_CCI_CLK>, |
| 144 | <&clock_camcc CAM_CC_CCI_CLK_SRC>; |
| 145 | clock-names = "camnoc_axi_clk", |
| 146 | "soc_ahb_clk", |
| 147 | "slow_ahb_src_clk", |
| 148 | "cpas_ahb_clk", |
| 149 | "cci_clk", |
| 150 | "cci_clk_src"; |
| 151 | src-clock-name = "cci_clk_src"; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 152 | clock-cntl-level = "lowsvs"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 153 | clock-rates = <0 0 0 0 0 37500000>; |
| 154 | pinctrl-names = "cam_default", "cam_suspend"; |
| 155 | pinctrl-0 = <&cci0_active &cci1_active>; |
| 156 | pinctrl-1 = <&cci0_suspend &cci1_suspend>; |
| 157 | gpios = <&tlmm 17 0>, |
| 158 | <&tlmm 18 0>, |
| 159 | <&tlmm 19 0>, |
| 160 | <&tlmm 20 0>; |
| 161 | gpio-req-tbl-num = <0 1 2 3>; |
| 162 | gpio-req-tbl-flags = <1 1 1 1>; |
| 163 | gpio-req-tbl-label = "CCI_I2C_DATA0", |
| 164 | "CCI_I2C_CLK0", |
| 165 | "CCI_I2C_DATA1", |
| 166 | "CCI_I2C_CLK1"; |
| 167 | |
| 168 | i2c_freq_100Khz: qcom,i2c_standard_mode { |
| 169 | hw-thigh = <201>; |
| 170 | hw-tlow = <174>; |
| 171 | hw-tsu-sto = <204>; |
| 172 | hw-tsu-sta = <231>; |
| 173 | hw-thd-dat = <22>; |
| 174 | hw-thd-sta = <162>; |
| 175 | hw-tbuf = <227>; |
| 176 | hw-scl-stretch-en = <0>; |
| 177 | hw-trdhld = <6>; |
| 178 | hw-tsp = <3>; |
| 179 | cci-clk-src = <37500000>; |
| 180 | status = "ok"; |
| 181 | }; |
| 182 | |
| 183 | i2c_freq_400Khz: qcom,i2c_fast_mode { |
| 184 | hw-thigh = <38>; |
| 185 | hw-tlow = <56>; |
| 186 | hw-tsu-sto = <40>; |
| 187 | hw-tsu-sta = <40>; |
| 188 | hw-thd-dat = <22>; |
| 189 | hw-thd-sta = <35>; |
| 190 | hw-tbuf = <62>; |
| 191 | hw-scl-stretch-en = <0>; |
| 192 | hw-trdhld = <6>; |
| 193 | hw-tsp = <3>; |
| 194 | cci-clk-src = <37500000>; |
| 195 | status = "ok"; |
| 196 | }; |
| 197 | |
| 198 | i2c_freq_custom: qcom,i2c_custom_mode { |
| 199 | hw-thigh = <38>; |
| 200 | hw-tlow = <56>; |
| 201 | hw-tsu-sto = <40>; |
| 202 | hw-tsu-sta = <40>; |
| 203 | hw-thd-dat = <22>; |
| 204 | hw-thd-sta = <35>; |
| 205 | hw-tbuf = <62>; |
| 206 | hw-scl-stretch-en = <1>; |
| 207 | hw-trdhld = <6>; |
| 208 | hw-tsp = <3>; |
| 209 | cci-clk-src = <37500000>; |
| 210 | status = "ok"; |
| 211 | }; |
| 212 | |
| 213 | i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { |
| 214 | hw-thigh = <16>; |
| 215 | hw-tlow = <22>; |
| 216 | hw-tsu-sto = <17>; |
| 217 | hw-tsu-sta = <18>; |
| 218 | hw-thd-dat = <16>; |
| 219 | hw-thd-sta = <15>; |
| 220 | hw-tbuf = <24>; |
| 221 | hw-scl-stretch-en = <0>; |
| 222 | hw-trdhld = <3>; |
| 223 | hw-tsp = <3>; |
| 224 | cci-clk-src = <37500000>; |
| 225 | status = "ok"; |
| 226 | }; |
| 227 | }; |
| 228 | |
| 229 | qcom,cam_smmu { |
| 230 | compatible = "qcom,msm-cam-smmu"; |
| 231 | status = "ok"; |
| 232 | |
Alok Pandey | 46e0e76 | 2017-11-17 19:08:36 +0530 | [diff] [blame] | 233 | msm_cam_smmu_lrme { |
| 234 | compatible = "qcom,msm-cam-smmu-cb"; |
| 235 | iommus = <&apps_smmu 0x1038 0x0>, |
| 236 | <&apps_smmu 0x1058 0x0>, |
| 237 | <&apps_smmu 0x1039 0x0>, |
| 238 | <&apps_smmu 0x1059 0x0>; |
| 239 | label = "lrme"; |
| 240 | lrme_iova_mem_map: iova-mem-map { |
| 241 | iova-mem-region-shared { |
| 242 | /* Shared region is 100MB long */ |
| 243 | iova-region-name = "shared"; |
| 244 | iova-region-start = <0x7400000>; |
| 245 | iova-region-len = <0x6400000>; |
| 246 | iova-region-id = <0x1>; |
| 247 | status = "ok"; |
| 248 | }; |
| 249 | /* IO region is approximately 3.3 GB */ |
| 250 | iova-mem-region-io { |
| 251 | iova-region-name = "io"; |
| 252 | iova-region-start = <0xd800000>; |
| 253 | iova-region-len = <0xd2800000>; |
| 254 | iova-region-id = <0x3>; |
| 255 | status = "ok"; |
| 256 | }; |
| 257 | }; |
| 258 | }; |
| 259 | |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 260 | msm_cam_smmu_ife { |
| 261 | compatible = "qcom,msm-cam-smmu-cb"; |
| 262 | iommus = <&apps_smmu 0x808 0x0>, |
| 263 | <&apps_smmu 0x810 0x8>, |
| 264 | <&apps_smmu 0xc08 0x0>, |
| 265 | <&apps_smmu 0xc10 0x8>; |
| 266 | label = "ife"; |
| 267 | ife_iova_mem_map: iova-mem-map { |
| 268 | /* IO region is approximately 3.4 GB */ |
| 269 | iova-mem-region-io { |
| 270 | iova-region-name = "io"; |
| 271 | iova-region-start = <0x7400000>; |
| 272 | iova-region-len = <0xd8c00000>; |
| 273 | iova-region-id = <0x3>; |
| 274 | status = "ok"; |
| 275 | }; |
| 276 | }; |
| 277 | }; |
| 278 | |
| 279 | msm_cam_smmu_jpeg { |
| 280 | compatible = "qcom,msm-cam-smmu-cb"; |
| 281 | iommus = <&apps_smmu 0x1060 0x8>, |
| 282 | <&apps_smmu 0x1068 0x8>; |
| 283 | label = "jpeg"; |
| 284 | jpeg_iova_mem_map: iova-mem-map { |
| 285 | /* IO region is approximately 3.4 GB */ |
| 286 | iova-mem-region-io { |
| 287 | iova-region-name = "io"; |
| 288 | iova-region-start = <0x7400000>; |
| 289 | iova-region-len = <0xd8c00000>; |
| 290 | iova-region-id = <0x3>; |
| 291 | status = "ok"; |
| 292 | }; |
| 293 | }; |
| 294 | }; |
| 295 | |
| 296 | msm_cam_icp_fw { |
| 297 | compatible = "qcom,msm-cam-smmu-fw-dev"; |
| 298 | label="icp"; |
| 299 | memory-region = <&pil_camera_mem>; |
| 300 | }; |
| 301 | |
| 302 | msm_cam_smmu_icp { |
| 303 | compatible = "qcom,msm-cam-smmu-cb"; |
| 304 | iommus = <&apps_smmu 0x107A 0x0>, |
| 305 | <&apps_smmu 0x1020 0x8>, |
| 306 | <&apps_smmu 0x1040 0x8>, |
| 307 | <&apps_smmu 0x1030 0x0>, |
| 308 | <&apps_smmu 0x1050 0x0>; |
| 309 | label = "icp"; |
| 310 | icp_iova_mem_map: iova-mem-map { |
| 311 | iova-mem-region-firmware { |
| 312 | /* Firmware region is 5MB */ |
| 313 | iova-region-name = "firmware"; |
| 314 | iova-region-start = <0x0>; |
| 315 | iova-region-len = <0x500000>; |
| 316 | iova-region-id = <0x0>; |
| 317 | status = "ok"; |
| 318 | }; |
| 319 | |
| 320 | iova-mem-region-shared { |
| 321 | /* Shared region is 100MB long */ |
| 322 | iova-region-name = "shared"; |
| 323 | iova-region-start = <0x7400000>; |
| 324 | iova-region-len = <0x6400000>; |
| 325 | iova-region-id = <0x1>; |
| 326 | iova-granularity = <0x15>; |
| 327 | status = "ok"; |
| 328 | }; |
| 329 | |
| 330 | iova-mem-region-secondary-heap { |
| 331 | /* Secondary heap region is 1MB long */ |
| 332 | iova-region-name = "secheap"; |
| 333 | iova-region-start = <0xd800000>; |
| 334 | iova-region-len = <0x100000>; |
| 335 | iova-region-id = <0x4>; |
| 336 | status = "ok"; |
| 337 | }; |
| 338 | |
| 339 | iova-mem-region-io { |
| 340 | /* IO region is approximately 3.3 GB */ |
| 341 | iova-region-name = "io"; |
| 342 | iova-region-start = <0xd900000>; |
| 343 | iova-region-len = <0xd2700000>; |
| 344 | iova-region-id = <0x3>; |
| 345 | status = "ok"; |
| 346 | }; |
| 347 | }; |
| 348 | }; |
| 349 | |
| 350 | msm_cam_smmu_cpas_cdm { |
| 351 | compatible = "qcom,msm-cam-smmu-cb"; |
| 352 | iommus = <&apps_smmu 0x1000 0x0>; |
| 353 | label = "cpas-cdm0"; |
| 354 | cpas_cdm_iova_mem_map: iova-mem-map { |
| 355 | iova-mem-region-io { |
| 356 | /* IO region is approximately 3.4 GB */ |
| 357 | iova-region-name = "io"; |
| 358 | iova-region-start = <0x7400000>; |
| 359 | iova-region-len = <0xd8c00000>; |
| 360 | iova-region-id = <0x3>; |
| 361 | status = "ok"; |
| 362 | }; |
| 363 | }; |
| 364 | }; |
| 365 | |
| 366 | msm_cam_smmu_secure { |
| 367 | compatible = "qcom,msm-cam-smmu-cb"; |
| 368 | label = "cam-secure"; |
| 369 | qcom,secure-cb; |
| 370 | }; |
| 371 | |
| 372 | msm_cam_smmu_fd { |
| 373 | compatible = "qcom,msm-cam-smmu-cb"; |
| 374 | iommus = <&apps_smmu 0x1070 0x0>; |
| 375 | label = "fd"; |
| 376 | fd_iova_mem_map: iova-mem-map { |
| 377 | iova-mem-region-io { |
| 378 | /* IO region is approximately 3.4 GB */ |
| 379 | iova-region-name = "io"; |
| 380 | iova-region-start = <0x7400000>; |
| 381 | iova-region-len = <0xd8c00000>; |
| 382 | iova-region-id = <0x3>; |
| 383 | status = "ok"; |
| 384 | }; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
| 388 | |
| 389 | qcom,cam-cpas@ac40000 { |
| 390 | cell-index = <0>; |
| 391 | compatible = "qcom,cam-cpas"; |
| 392 | label = "cpas"; |
| 393 | arch-compat = "cpas_top"; |
| 394 | status = "ok"; |
| 395 | reg-names = "cam_cpas_top", "cam_camnoc"; |
| 396 | reg = <0xac40000 0x1000>, |
| 397 | <0xac42000 0x5000>; |
| 398 | reg-cam-base = <0x40000 0x42000>; |
| 399 | interrupt-names = "cpas_camnoc"; |
| 400 | interrupts = <0 459 0>; |
| 401 | qcom,cpas-hw-ver = <0x170110>; /* Titan v170 v1.1.0 */ |
| 402 | regulator-names = "camss-vdd"; |
| 403 | camss-vdd-supply = <&titan_top_gdsc>; |
| 404 | clock-names = "gcc_ahb_clk", |
| 405 | "gcc_axi_clk", |
| 406 | "soc_ahb_clk", |
| 407 | "slow_ahb_clk_src", |
| 408 | "cpas_ahb_clk", |
| 409 | "camnoc_axi_clk"; |
| 410 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 411 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 412 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 413 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 414 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 415 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| 416 | src-clock-name = "slow_ahb_clk_src"; |
| 417 | clock-rates = <0 0 0 0 0 0>, |
| 418 | <0 0 0 19200000 0 0>, |
| 419 | <0 0 0 80000000 0 0>, |
| 420 | <0 0 0 80000000 0 0>, |
| 421 | <0 0 0 80000000 0 0>, |
| 422 | <0 0 0 80000000 0 0>, |
| 423 | <0 0 0 80000000 0 0>; |
| 424 | clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", |
| 425 | "svs_l1", "nominal", "turbo"; |
| 426 | qcom,msm-bus,name = "cam_ahb"; |
| 427 | qcom,msm-bus,num-cases = <7>; |
| 428 | qcom,msm-bus,num-paths = <1>; |
| 429 | qcom,msm-bus,vectors-KBps = |
| 430 | <MSM_BUS_MASTER_AMPSS_M0 |
| 431 | MSM_BUS_SLAVE_CAMERA_CFG 0 0>, |
| 432 | <MSM_BUS_MASTER_AMPSS_M0 |
Pavan Kumar Chilamkurthi | e2cd756 | 2017-10-31 12:04:20 -0700 | [diff] [blame] | 433 | MSM_BUS_SLAVE_CAMERA_CFG 0 76500>, |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 434 | <MSM_BUS_MASTER_AMPSS_M0 |
Pavan Kumar Chilamkurthi | e2cd756 | 2017-10-31 12:04:20 -0700 | [diff] [blame] | 435 | MSM_BUS_SLAVE_CAMERA_CFG 0 120000>, |
| 436 | <MSM_BUS_MASTER_AMPSS_M0 |
| 437 | MSM_BUS_SLAVE_CAMERA_CFG 0 150000>, |
| 438 | <MSM_BUS_MASTER_AMPSS_M0 |
| 439 | MSM_BUS_SLAVE_CAMERA_CFG 0 150000>, |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 440 | <MSM_BUS_MASTER_AMPSS_M0 |
| 441 | MSM_BUS_SLAVE_CAMERA_CFG 0 300000>, |
| 442 | <MSM_BUS_MASTER_AMPSS_M0 |
Pavan Kumar Chilamkurthi | e2cd756 | 2017-10-31 12:04:20 -0700 | [diff] [blame] | 443 | MSM_BUS_SLAVE_CAMERA_CFG 0 300000>; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 444 | vdd-corners = <RPMH_REGULATOR_LEVEL_OFF |
| 445 | RPMH_REGULATOR_LEVEL_RETENTION |
| 446 | RPMH_REGULATOR_LEVEL_MIN_SVS |
| 447 | RPMH_REGULATOR_LEVEL_LOW_SVS |
| 448 | RPMH_REGULATOR_LEVEL_SVS |
| 449 | RPMH_REGULATOR_LEVEL_SVS_L1 |
| 450 | RPMH_REGULATOR_LEVEL_NOM |
| 451 | RPMH_REGULATOR_LEVEL_NOM_L1 |
| 452 | RPMH_REGULATOR_LEVEL_NOM_L2 |
| 453 | RPMH_REGULATOR_LEVEL_TURBO |
| 454 | RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| 455 | vdd-corner-ahb-mapping = "suspend", "suspend", |
| 456 | "minsvs", "lowsvs", "svs", "svs_l1", |
| 457 | "nominal", "nominal", "nominal", |
| 458 | "turbo", "turbo"; |
| 459 | client-id-based; |
| 460 | client-names = |
| 461 | "csiphy0", "csiphy1", "csiphy2", "cci0", |
| 462 | "csid0", "csid1", "csid2", |
| 463 | "ife0", "ife1", "ife2", "ipe0", |
| 464 | "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", |
Alok Pandey | 46e0e76 | 2017-11-17 19:08:36 +0530 | [diff] [blame] | 465 | "icp0", "jpeg-dma0", "jpeg-enc0", "fd0", "lrmecpas0"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 466 | client-axi-port-names = |
| 467 | "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", |
| 468 | "cam_hf_1", "cam_hf_2", "cam_hf_2", |
| 469 | "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", |
| 470 | "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", |
Alok Pandey | 46e0e76 | 2017-11-17 19:08:36 +0530 | [diff] [blame] | 471 | "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", |
| 472 | "cam_sf_1"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 473 | client-bus-camnoc-based; |
| 474 | qcom,axi-port-list { |
| 475 | qcom,axi-port1 { |
| 476 | qcom,axi-port-name = "cam_hf_1"; |
| 477 | qcom,axi-port-mnoc { |
| 478 | qcom,msm-bus,name = "cam_hf_1_mnoc"; |
| 479 | qcom,msm-bus-vector-dyn-vote; |
| 480 | qcom,msm-bus,num-cases = <2>; |
| 481 | qcom,msm-bus,num-paths = <1>; |
| 482 | qcom,msm-bus,vectors-KBps = |
| 483 | <MSM_BUS_MASTER_CAMNOC_HF0 |
| 484 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 485 | <MSM_BUS_MASTER_CAMNOC_HF0 |
| 486 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 487 | }; |
| 488 | qcom,axi-port-camnoc { |
| 489 | qcom,msm-bus,name = "cam_hf_1_camnoc"; |
| 490 | qcom,msm-bus-vector-dyn-vote; |
| 491 | qcom,msm-bus,num-cases = <2>; |
| 492 | qcom,msm-bus,num-paths = <1>; |
| 493 | qcom,msm-bus,vectors-KBps = |
| 494 | <MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP |
| 495 | MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>, |
| 496 | <MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP |
| 497 | MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>; |
| 498 | }; |
| 499 | }; |
| 500 | qcom,axi-port2 { |
| 501 | qcom,axi-port-name = "cam_hf_2"; |
| 502 | qcom,axi-port-mnoc { |
| 503 | qcom,msm-bus,name = "cam_hf_2_mnoc"; |
| 504 | qcom,msm-bus-vector-dyn-vote; |
| 505 | qcom,msm-bus,num-cases = <2>; |
| 506 | qcom,msm-bus,num-paths = <1>; |
| 507 | qcom,msm-bus,vectors-KBps = |
| 508 | <MSM_BUS_MASTER_CAMNOC_HF1 |
| 509 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 510 | <MSM_BUS_MASTER_CAMNOC_HF1 |
| 511 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 512 | }; |
| 513 | qcom,axi-port-camnoc { |
| 514 | qcom,msm-bus,name = "cam_hf_2_camnoc"; |
| 515 | qcom,msm-bus-vector-dyn-vote; |
| 516 | qcom,msm-bus,num-cases = <2>; |
| 517 | qcom,msm-bus,num-paths = <1>; |
| 518 | qcom,msm-bus,vectors-KBps = |
| 519 | <MSM_BUS_MASTER_CAMNOC_HF1_UNCOMP |
| 520 | MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>, |
| 521 | <MSM_BUS_MASTER_CAMNOC_HF1_UNCOMP |
| 522 | MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>; |
| 523 | }; |
| 524 | }; |
| 525 | qcom,axi-port3 { |
| 526 | qcom,axi-port-name = "cam_sf_1"; |
| 527 | qcom,axi-port-mnoc { |
| 528 | qcom,msm-bus,name = "cam_sf_1_mnoc"; |
| 529 | qcom,msm-bus-vector-dyn-vote; |
| 530 | qcom,msm-bus,num-cases = <2>; |
| 531 | qcom,msm-bus,num-paths = <1>; |
| 532 | qcom,msm-bus,vectors-KBps = |
| 533 | <MSM_BUS_MASTER_CAMNOC_SF |
| 534 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 535 | <MSM_BUS_MASTER_CAMNOC_SF |
| 536 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 537 | }; |
| 538 | qcom,axi-port-camnoc { |
| 539 | qcom,msm-bus,name = "cam_sf_1_camnoc"; |
| 540 | qcom,msm-bus-vector-dyn-vote; |
| 541 | qcom,msm-bus,num-cases = <2>; |
| 542 | qcom,msm-bus,num-paths = <1>; |
| 543 | qcom,msm-bus,vectors-KBps = |
| 544 | <MSM_BUS_MASTER_CAMNOC_SF_UNCOMP |
| 545 | MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>, |
| 546 | <MSM_BUS_MASTER_CAMNOC_SF_UNCOMP |
| 547 | MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>; |
| 548 | }; |
| 549 | }; |
| 550 | }; |
| 551 | }; |
| 552 | |
| 553 | qcom,cam-cdm-intf { |
| 554 | compatible = "qcom,cam-cdm-intf"; |
| 555 | cell-index = <0>; |
| 556 | label = "cam-cdm-intf"; |
| 557 | num-hw-cdm = <1>; |
| 558 | cdm-client-names = "vfe", |
| 559 | "jpegdma", |
| 560 | "jpegenc", |
Alok Pandey | 46e0e76 | 2017-11-17 19:08:36 +0530 | [diff] [blame] | 561 | "fd", |
| 562 | "lrmecdm"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 563 | status = "ok"; |
| 564 | }; |
| 565 | |
| 566 | qcom,cpas-cdm0@ac48000 { |
| 567 | cell-index = <0>; |
| 568 | compatible = "qcom,cam170-cpas-cdm0"; |
| 569 | label = "cpas-cdm"; |
| 570 | reg = <0xac48000 0x1000>; |
| 571 | reg-names = "cpas-cdm"; |
| 572 | reg-cam-base = <0x48000>; |
| 573 | interrupts = <0 461 0>; |
| 574 | interrupt-names = "cpas-cdm"; |
| 575 | regulator-names = "camss"; |
| 576 | camss-supply = <&titan_top_gdsc>; |
| 577 | clock-names = "gcc_camera_ahb", |
| 578 | "gcc_camera_axi", |
| 579 | "cam_cc_soc_ahb_clk", |
| 580 | "cam_cc_cpas_ahb_clk", |
| 581 | "cam_cc_camnoc_axi_clk"; |
| 582 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 583 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 584 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 585 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 586 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| 587 | clock-rates = <0 0 0 0 0>; |
| 588 | clock-cntl-level = "svs"; |
| 589 | cdm-client-names = "ife"; |
| 590 | status = "ok"; |
| 591 | }; |
| 592 | |
| 593 | qcom,cam-isp { |
| 594 | compatible = "qcom,cam-isp"; |
| 595 | arch-compat = "ife"; |
| 596 | status = "ok"; |
| 597 | }; |
| 598 | |
| 599 | cam_csid0: qcom,csid0@acb3000 { |
| 600 | cell-index = <0>; |
| 601 | compatible = "qcom,csid170"; |
| 602 | reg-names = "csid"; |
| 603 | reg = <0xacb3000 0x1000>; |
| 604 | reg-cam-base = <0xb3000>; |
| 605 | interrupt-names = "csid"; |
| 606 | interrupts = <0 464 0>; |
| 607 | regulator-names = "camss", "ife0"; |
| 608 | camss-supply = <&titan_top_gdsc>; |
| 609 | ife0-supply = <&ife_0_gdsc>; |
| 610 | clock-names = "camera_ahb", |
| 611 | "camera_axi", |
| 612 | "soc_ahb_clk", |
| 613 | "cpas_ahb_clk", |
| 614 | "slow_ahb_clk_src", |
| 615 | "ife_csid_clk", |
| 616 | "ife_csid_clk_src", |
| 617 | "ife_cphy_rx_clk", |
| 618 | "cphy_rx_clk_src", |
| 619 | "ife_clk", |
| 620 | "ife_clk_src", |
| 621 | "camnoc_axi_clk", |
| 622 | "ife_axi_clk"; |
| 623 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 624 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 625 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 626 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 627 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 628 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, |
| 629 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, |
| 630 | <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, |
| 631 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 632 | <&clock_camcc CAM_CC_IFE_0_CLK>, |
| 633 | <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, |
| 634 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 635 | <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 636 | clock-rates = |
| 637 | <0 0 0 0 0 0 384000000 0 0 0 404000000 0 0>, |
| 638 | <0 0 0 0 0 0 538000000 0 0 0 600000000 0 0>; |
| 639 | clock-cntl-level = "svs", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 640 | src-clock-name = "ife_csid_clk_src"; |
| 641 | status = "ok"; |
| 642 | }; |
| 643 | |
| 644 | cam_vfe0: qcom,vfe0@acaf000 { |
| 645 | cell-index = <0>; |
| 646 | compatible = "qcom,vfe170"; |
| 647 | reg-names = "ife"; |
| 648 | reg = <0xacaf000 0x4000>; |
| 649 | reg-cam-base = <0xaf000>; |
| 650 | interrupt-names = "ife"; |
| 651 | interrupts = <0 465 0>; |
| 652 | regulator-names = "camss", "ife0"; |
| 653 | camss-supply = <&titan_top_gdsc>; |
| 654 | ife0-supply = <&ife_0_gdsc>; |
| 655 | clock-names = "camera_ahb", |
| 656 | "camera_axi", |
| 657 | "soc_ahb_clk", |
| 658 | "cpas_ahb_clk", |
| 659 | "slow_ahb_clk_src", |
| 660 | "ife_clk", |
| 661 | "ife_clk_src", |
| 662 | "camnoc_axi_clk", |
| 663 | "ife_axi_clk"; |
| 664 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 665 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 666 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 667 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 668 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 669 | <&clock_camcc CAM_CC_IFE_0_CLK>, |
| 670 | <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, |
| 671 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 672 | <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 673 | clock-rates = |
| 674 | <0 0 0 0 0 0 404000000 0 0>, |
| 675 | <0 0 0 0 0 0 480000000 0 0>, |
| 676 | <0 0 0 0 0 0 600000000 0 0>; |
| 677 | clock-cntl-level = "svs", "svs_l1", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 678 | src-clock-name = "ife_clk_src"; |
| 679 | clock-names-option = "ife_dsp_clk"; |
| 680 | clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; |
Senthil Rajagopal | 3f8372c | 2017-11-05 12:19:56 +0530 | [diff] [blame] | 681 | clock-rates-option = <600000000>; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 682 | status = "ok"; |
| 683 | }; |
| 684 | |
| 685 | cam_csid1: qcom,csid1@acba000 { |
| 686 | cell-index = <1>; |
| 687 | compatible = "qcom,csid170"; |
| 688 | reg-names = "csid"; |
| 689 | reg = <0xacba000 0x1000>; |
| 690 | reg-cam-base = <0xba000>; |
| 691 | interrupt-names = "csid"; |
| 692 | interrupts = <0 466 0>; |
| 693 | regulator-names = "camss", "ife1"; |
| 694 | camss-supply = <&titan_top_gdsc>; |
| 695 | ife1-supply = <&ife_1_gdsc>; |
| 696 | clock-names = "camera_ahb", |
| 697 | "camera_axi", |
| 698 | "soc_ahb_clk", |
| 699 | "cpas_ahb_clk", |
| 700 | "slow_ahb_clk_src", |
| 701 | "ife_csid_clk", |
| 702 | "ife_csid_clk_src", |
| 703 | "ife_cphy_rx_clk", |
| 704 | "cphy_rx_clk_src", |
| 705 | "ife_clk", |
| 706 | "ife_clk_src", |
| 707 | "camnoc_axi_clk", |
| 708 | "ife_axi_clk"; |
| 709 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 710 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 711 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 712 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 713 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 714 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, |
| 715 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, |
| 716 | <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, |
| 717 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 718 | <&clock_camcc CAM_CC_IFE_1_CLK>, |
| 719 | <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, |
| 720 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 721 | <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 722 | clock-rates = |
| 723 | <0 0 0 0 0 0 384000000 0 0 0 404000000 0 0>, |
| 724 | <0 0 0 0 0 0 538000000 0 0 0 600000000 0 0>; |
| 725 | clock-cntl-level = "svs", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 726 | src-clock-name = "ife_csid_clk_src"; |
| 727 | status = "ok"; |
| 728 | }; |
| 729 | |
| 730 | cam_vfe1: qcom,vfe1@acb6000 { |
| 731 | cell-index = <1>; |
| 732 | compatible = "qcom,vfe170"; |
| 733 | reg-names = "ife"; |
| 734 | reg = <0xacb6000 0x4000>; |
| 735 | reg-cam-base = <0xb6000>; |
| 736 | interrupt-names = "ife"; |
| 737 | interrupts = <0 467 0>; |
| 738 | regulator-names = "camss", "ife1"; |
| 739 | camss-supply = <&titan_top_gdsc>; |
| 740 | ife1-supply = <&ife_1_gdsc>; |
| 741 | clock-names = "camera_ahb", |
| 742 | "camera_axi", |
| 743 | "soc_ahb_clk", |
| 744 | "cpas_ahb_clk", |
| 745 | "slow_ahb_clk_src", |
| 746 | "ife_clk", |
| 747 | "ife_clk_src", |
| 748 | "camnoc_axi_clk", |
| 749 | "ife_axi_clk"; |
| 750 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 751 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 752 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 753 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 754 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 755 | <&clock_camcc CAM_CC_IFE_1_CLK>, |
| 756 | <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, |
| 757 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 758 | <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 759 | clock-rates = |
| 760 | <0 0 0 0 0 0 404000000 0 0>, |
| 761 | <0 0 0 0 0 0 480000000 0 0>, |
| 762 | <0 0 0 0 0 0 600000000 0 0>; |
| 763 | clock-cntl-level = "svs", "svs_l1", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 764 | src-clock-name = "ife_clk_src"; |
| 765 | clock-names-option = "ife_dsp_clk"; |
| 766 | clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; |
Senthil Rajagopal | 3f8372c | 2017-11-05 12:19:56 +0530 | [diff] [blame] | 767 | clock-rates-option = <600000000>; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 768 | status = "ok"; |
| 769 | }; |
| 770 | |
| 771 | cam_csid_lite: qcom,csid-lite@acc8000 { |
| 772 | cell-index = <2>; |
| 773 | compatible = "qcom,csid-lite170"; |
| 774 | reg-names = "csid-lite"; |
| 775 | reg = <0xacc8000 0x1000>; |
| 776 | reg-cam-base = <0xc8000>; |
| 777 | interrupt-names = "csid-lite"; |
| 778 | interrupts = <0 468 0>; |
| 779 | regulator-names = "camss"; |
| 780 | camss-supply = <&titan_top_gdsc>; |
| 781 | clock-names = "camera_ahb", |
| 782 | "camera_axi", |
| 783 | "soc_ahb_clk", |
| 784 | "cpas_ahb_clk", |
| 785 | "slow_ahb_clk_src", |
| 786 | "ife_csid_clk", |
| 787 | "ife_csid_clk_src", |
| 788 | "ife_cphy_rx_clk", |
| 789 | "cphy_rx_clk_src", |
| 790 | "ife_clk", |
| 791 | "ife_clk_src", |
| 792 | "camnoc_axi_clk"; |
| 793 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 794 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 795 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 796 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 797 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 798 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, |
| 799 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, |
| 800 | <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, |
| 801 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 802 | <&clock_camcc CAM_CC_IFE_LITE_CLK>, |
| 803 | <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, |
| 804 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 805 | clock-rates = |
| 806 | <0 0 0 0 0 0 384000000 0 0 0 404000000 0>, |
| 807 | <0 0 0 0 0 0 538000000 0 0 0 600000000 0>; |
| 808 | clock-cntl-level = "svs", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 809 | src-clock-name = "ife_csid_clk_src"; |
| 810 | status = "ok"; |
| 811 | }; |
| 812 | |
| 813 | cam_vfe_lite: qcom,vfe-lite@acc4000 { |
| 814 | cell-index = <2>; |
| 815 | compatible = "qcom,vfe-lite170"; |
| 816 | reg-names = "ife-lite"; |
| 817 | reg = <0xacc4000 0x4000>; |
| 818 | reg-cam-base = <0xc4000>; |
| 819 | interrupt-names = "ife-lite"; |
| 820 | interrupts = <0 469 0>; |
| 821 | regulator-names = "camss"; |
| 822 | camss-supply = <&titan_top_gdsc>; |
| 823 | clock-names = "camera_ahb", |
| 824 | "camera_axi", |
| 825 | "soc_ahb_clk", |
| 826 | "cpas_ahb_clk", |
| 827 | "slow_ahb_clk_src", |
| 828 | "ife_clk", |
| 829 | "ife_clk_src", |
| 830 | "camnoc_axi_clk"; |
| 831 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 832 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 833 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 834 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 835 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 836 | <&clock_camcc CAM_CC_IFE_LITE_CLK>, |
| 837 | <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, |
| 838 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 839 | clock-rates = |
| 840 | <0 0 0 0 0 0 404000000 0>, |
| 841 | <0 0 0 0 0 0 480000000 0>, |
| 842 | <0 0 0 0 0 0 600000000 0>; |
| 843 | clock-cntl-level = "svs", "svs_l1", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 844 | src-clock-name = "ife_clk_src"; |
| 845 | status = "ok"; |
| 846 | }; |
| 847 | |
| 848 | qcom,cam-icp { |
| 849 | compatible = "qcom,cam-icp"; |
| 850 | compat-hw-name = "qcom,a5", |
| 851 | "qcom,ipe0", |
| 852 | "qcom,ipe1", |
| 853 | "qcom,bps"; |
| 854 | num-a5 = <1>; |
| 855 | num-ipe = <2>; |
| 856 | num-bps = <1>; |
| 857 | status = "ok"; |
| 858 | }; |
| 859 | |
| 860 | cam_a5: qcom,a5@ac00000 { |
| 861 | cell-index = <0>; |
| 862 | compatible = "qcom,cam-a5"; |
| 863 | reg = <0xac00000 0x6000>, |
| 864 | <0xac10000 0x8000>, |
| 865 | <0xac18000 0x3000>; |
| 866 | reg-names = "a5_qgic", "a5_sierra", "a5_csr"; |
| 867 | reg-cam-base = <0x00000 0x10000 0x18000>; |
| 868 | interrupts = <0 463 0>; |
| 869 | interrupt-names = "a5"; |
| 870 | regulator-names = "camss-vdd"; |
| 871 | camss-vdd-supply = <&titan_top_gdsc>; |
| 872 | clock-names = "gcc_cam_ahb_clk", |
| 873 | "gcc_cam_axi_clk", |
| 874 | "soc_fast_ahb", |
| 875 | "soc_ahb_clk", |
| 876 | "cpas_ahb_clk", |
| 877 | "camnoc_axi_clk", |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 878 | "icp_clk", |
| 879 | "icp_clk_src"; |
| 880 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 881 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 882 | <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, |
| 883 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 884 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 885 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 886 | <&clock_camcc CAM_CC_ICP_CLK>, |
| 887 | <&clock_camcc CAM_CC_ICP_CLK_SRC>; |
| 888 | |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 889 | clock-rates = |
| 890 | <0 0 200000000 0 0 0 0 400000000>, |
| 891 | <0 0 200000000 0 0 0 0 600000000>; |
| 892 | clock-cntl-level = "svs", "turbo"; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 893 | fw_name = "CAMERA_ICP.elf"; |
| 894 | ubwc-cfg = <0x77 0x1DF>; |
| 895 | status = "ok"; |
| 896 | }; |
| 897 | |
| 898 | cam_ipe0: qcom,ipe0 { |
| 899 | cell-index = <0>; |
| 900 | compatible = "qcom,cam-ipe"; |
| 901 | regulator-names = "ipe0-vdd"; |
| 902 | ipe0-vdd-supply = <&ipe_0_gdsc>; |
| 903 | clock-names = "ipe_0_ahb_clk", |
| 904 | "ipe_0_areg_clk", |
| 905 | "ipe_0_axi_clk", |
| 906 | "ipe_0_clk", |
| 907 | "ipe_0_clk_src"; |
| 908 | src-clock-name = "ipe_0_clk_src"; |
| 909 | clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, |
| 910 | <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, |
| 911 | <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, |
| 912 | <&clock_camcc CAM_CC_IPE_0_CLK>, |
| 913 | <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; |
| 914 | |
| 915 | clock-rates = <0 0 0 0 240000000>, |
| 916 | <0 0 0 0 404000000>, |
| 917 | <0 0 0 0 480000000>, |
| 918 | <0 0 0 0 538000000>, |
| 919 | <0 0 0 0 600000000>; |
| 920 | clock-cntl-level = "lowsvs", "svs", |
| 921 | "svs_l1", "nominal", "turbo"; |
| 922 | status = "ok"; |
| 923 | }; |
| 924 | |
| 925 | cam_ipe1: qcom,ipe1 { |
| 926 | cell-index = <1>; |
| 927 | compatible = "qcom,cam-ipe"; |
| 928 | regulator-names = "ipe1-vdd"; |
| 929 | ipe1-vdd-supply = <&ipe_1_gdsc>; |
| 930 | clock-names = "ipe_1_ahb_clk", |
| 931 | "ipe_1_areg_clk", |
| 932 | "ipe_1_axi_clk", |
| 933 | "ipe_1_clk", |
| 934 | "ipe_1_clk_src"; |
| 935 | src-clock-name = "ipe_1_clk_src"; |
| 936 | clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, |
| 937 | <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, |
| 938 | <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, |
| 939 | <&clock_camcc CAM_CC_IPE_1_CLK>, |
| 940 | <&clock_camcc CAM_CC_IPE_1_CLK_SRC>; |
| 941 | |
| 942 | clock-rates = <0 0 0 0 240000000>, |
| 943 | <0 0 0 0 404000000>, |
| 944 | <0 0 0 0 480000000>, |
| 945 | <0 0 0 0 538000000>, |
| 946 | <0 0 0 0 600000000>; |
| 947 | clock-cntl-level = "lowsvs", "svs", |
| 948 | "svs_l1", "nominal", "turbo"; |
| 949 | status = "ok"; |
| 950 | }; |
| 951 | |
| 952 | cam_bps: qcom,bps { |
| 953 | cell-index = <0>; |
| 954 | compatible = "qcom,cam-bps"; |
| 955 | regulator-names = "bps-vdd"; |
| 956 | bps-vdd-supply = <&bps_gdsc>; |
| 957 | clock-names = "bps_ahb_clk", |
| 958 | "bps_areg_clk", |
| 959 | "bps_axi_clk", |
| 960 | "bps_clk", |
| 961 | "bps_clk_src"; |
| 962 | src-clock-name = "bps_clk_src"; |
| 963 | clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, |
| 964 | <&clock_camcc CAM_CC_BPS_AREG_CLK>, |
| 965 | <&clock_camcc CAM_CC_BPS_AXI_CLK>, |
| 966 | <&clock_camcc CAM_CC_BPS_CLK>, |
| 967 | <&clock_camcc CAM_CC_BPS_CLK_SRC>; |
| 968 | |
| 969 | clock-rates = <0 0 0 0 200000000>, |
| 970 | <0 0 0 0 404000000>, |
| 971 | <0 0 0 0 480000000>, |
| 972 | <0 0 0 0 600000000>, |
| 973 | <0 0 0 0 600000000>; |
| 974 | clock-cntl-level = "lowsvs", "svs", |
| 975 | "svs_l1", "nominal", "turbo"; |
| 976 | status = "ok"; |
| 977 | }; |
| 978 | |
| 979 | qcom,cam-jpeg { |
| 980 | compatible = "qcom,cam-jpeg"; |
| 981 | compat-hw-name = "qcom,jpegenc", |
| 982 | "qcom,jpegdma"; |
| 983 | num-jpeg-enc = <1>; |
| 984 | num-jpeg-dma = <1>; |
| 985 | status = "ok"; |
| 986 | }; |
| 987 | |
| 988 | cam_jpeg_enc: qcom,jpegenc@ac4e000 { |
| 989 | cell-index = <0>; |
| 990 | compatible = "qcom,cam_jpeg_enc"; |
| 991 | reg-names = "jpege_hw"; |
| 992 | reg = <0xac4e000 0x4000>; |
| 993 | reg-cam-base = <0x4e000>; |
| 994 | interrupt-names = "jpeg"; |
| 995 | interrupts = <0 474 0>; |
| 996 | regulator-names = "camss-vdd"; |
| 997 | camss-vdd-supply = <&titan_top_gdsc>; |
| 998 | clock-names = "camera_ahb", |
| 999 | "camera_axi", |
| 1000 | "soc_ahb_clk", |
| 1001 | "cpas_ahb_clk", |
| 1002 | "camnoc_axi_clk", |
| 1003 | "jpegenc_clk_src", |
| 1004 | "jpegenc_clk"; |
| 1005 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 1006 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 1007 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 1008 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 1009 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 1010 | <&clock_camcc CAM_CC_JPEG_CLK_SRC>, |
| 1011 | <&clock_camcc CAM_CC_JPEG_CLK>; |
| 1012 | |
| 1013 | clock-rates = <0 0 0 0 0 600000000 0>; |
| 1014 | src-clock-name = "jpegenc_clk_src"; |
| 1015 | clock-cntl-level = "nominal"; |
| 1016 | status = "ok"; |
| 1017 | }; |
| 1018 | |
| 1019 | cam_jpeg_dma: qcom,jpegdma@0xac52000{ |
| 1020 | cell-index = <0>; |
| 1021 | compatible = "qcom,cam_jpeg_dma"; |
| 1022 | reg-names = "jpegdma_hw"; |
| 1023 | reg = <0xac52000 0x4000>; |
| 1024 | reg-cam-base = <0x52000>; |
| 1025 | interrupt-names = "jpegdma"; |
| 1026 | interrupts = <0 475 0>; |
| 1027 | regulator-names = "camss-vdd"; |
| 1028 | camss-vdd-supply = <&titan_top_gdsc>; |
| 1029 | clock-names = "camera_ahb", |
| 1030 | "camera_axi", |
| 1031 | "soc_ahb_clk", |
| 1032 | "cpas_ahb_clk", |
| 1033 | "camnoc_axi_clk", |
| 1034 | "jpegdma_clk_src", |
| 1035 | "jpegdma_clk"; |
| 1036 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 1037 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 1038 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 1039 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 1040 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 1041 | <&clock_camcc CAM_CC_JPEG_CLK_SRC>, |
| 1042 | <&clock_camcc CAM_CC_JPEG_CLK>; |
| 1043 | |
| 1044 | clock-rates = <0 0 0 0 0 600000000 0>; |
| 1045 | src-clock-name = "jpegdma_clk_src"; |
| 1046 | clock-cntl-level = "nominal"; |
| 1047 | status = "ok"; |
| 1048 | }; |
| 1049 | |
| 1050 | qcom,cam-fd { |
| 1051 | compatible = "qcom,cam-fd"; |
| 1052 | compat-hw-name = "qcom,fd"; |
| 1053 | num-fd = <1>; |
| 1054 | status = "ok"; |
| 1055 | }; |
| 1056 | |
| 1057 | cam_fd: qcom,fd@ac5a000 { |
| 1058 | cell-index = <0>; |
| 1059 | compatible = "qcom,fd41"; |
| 1060 | reg-names = "fd_core", "fd_wrapper"; |
| 1061 | reg = <0xac5a000 0x1000>, |
| 1062 | <0xac5b000 0x400>; |
| 1063 | reg-cam-base = <0x5a000 0x5b000>; |
| 1064 | interrupt-names = "fd"; |
| 1065 | interrupts = <0 462 0>; |
| 1066 | regulator-names = "camss-vdd"; |
| 1067 | camss-vdd-supply = <&titan_top_gdsc>; |
| 1068 | clock-names = "gcc_ahb_clk", |
| 1069 | "gcc_axi_clk", |
| 1070 | "soc_ahb_clk", |
| 1071 | "cpas_ahb_clk", |
| 1072 | "camnoc_axi_clk", |
| 1073 | "fd_core_clk_src", |
| 1074 | "fd_core_clk", |
| 1075 | "fd_core_uar_clk"; |
| 1076 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 1077 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 1078 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 1079 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 1080 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 1081 | <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>, |
| 1082 | <&clock_camcc CAM_CC_FD_CORE_CLK>, |
| 1083 | <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>; |
| 1084 | src-clock-name = "fd_core_clk_src"; |
Pavan Kumar Chilamkurthi | 8665070 | 2017-11-03 17:34:59 -0700 | [diff] [blame] | 1085 | clock-cntl-level = "svs", "svs_l1", "turbo"; |
| 1086 | clock-rates = |
| 1087 | <0 0 0 0 0 400000000 0 0>, |
| 1088 | <0 0 0 0 0 538000000 0 0>, |
| 1089 | <0 0 0 0 0 600000000 0 0>; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 1090 | status = "ok"; |
| 1091 | }; |
Alok Pandey | 46e0e76 | 2017-11-17 19:08:36 +0530 | [diff] [blame] | 1092 | |
| 1093 | qcom,cam-lrme { |
| 1094 | compatible = "qcom,cam-lrme"; |
| 1095 | arch-compat = "lrme"; |
| 1096 | status = "ok"; |
| 1097 | }; |
| 1098 | |
| 1099 | cam_lrme: qcom,lrme@ac6b000 { |
| 1100 | cell-index = <0>; |
| 1101 | compatible = "qcom,lrme"; |
| 1102 | reg-names = "lrme"; |
| 1103 | reg = <0xac6b000 0xa00>; |
| 1104 | reg-cam-base = <0x6b000>; |
| 1105 | interrupt-names = "lrme"; |
| 1106 | interrupts = <0 476 0>; |
| 1107 | regulator-names = "camss"; |
| 1108 | camss-supply = <&titan_top_gdsc>; |
| 1109 | clock-names = "camera_ahb", |
| 1110 | "camera_axi", |
| 1111 | "soc_ahb_clk", |
| 1112 | "cpas_ahb_clk", |
| 1113 | "camnoc_axi_clk", |
| 1114 | "lrme_clk_src", |
| 1115 | "lrme_clk"; |
| 1116 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 1117 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 1118 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 1119 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 1120 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 1121 | <&clock_camcc CAM_CC_LRME_CLK_SRC>, |
| 1122 | <&clock_camcc CAM_CC_LRME_CLK>; |
| 1123 | clock-rates = <0 0 0 0 0 200000000 200000000>, |
| 1124 | <0 0 0 0 0 269000000 269000000>, |
| 1125 | <0 0 0 0 0 320000000 320000000>, |
| 1126 | <0 0 0 0 0 400000000 400000000>; |
| 1127 | clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; |
| 1128 | src-clock-name = "lrme_clk_src"; |
| 1129 | status = "ok"; |
| 1130 | }; |
Suresh Vankadara | 402d0ca | 2017-10-26 22:54:54 +0530 | [diff] [blame] | 1131 | }; |