Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx |
| 3 | * |
| 4 | * Copyright (C) 2009-2011 Nokia Corporation |
| 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
| 12 | * XXX these should be marked initdata for multi-OMAP kernels |
| 13 | */ |
| 14 | #include <asm/sizes.h> |
| 15 | |
| 16 | #include <plat/omap_hwmod.h> |
| 17 | #include <plat/serial.h> |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 18 | #include <plat/l3_2xxx.h> |
| 19 | #include <plat/l4_2xxx.h> |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 20 | |
| 21 | #include "omap_hwmod_common_data.h" |
| 22 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 23 | static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 24 | { |
| 25 | .pa_start = OMAP2_UART1_BASE, |
| 26 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, |
| 27 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 28 | }, |
| 29 | { } |
| 30 | }; |
| 31 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 32 | static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 33 | { |
| 34 | .pa_start = OMAP2_UART2_BASE, |
| 35 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, |
| 36 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 37 | }, |
| 38 | { } |
| 39 | }; |
| 40 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 41 | static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 42 | { |
| 43 | .pa_start = OMAP2_UART3_BASE, |
| 44 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, |
| 45 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 46 | }, |
| 47 | { } |
| 48 | }; |
| 49 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 50 | static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 51 | { |
| 52 | .pa_start = 0x4802a000, |
| 53 | .pa_end = 0x4802a000 + SZ_1K - 1, |
| 54 | .flags = ADDR_TYPE_RT |
| 55 | }, |
| 56 | { } |
| 57 | }; |
| 58 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 59 | static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 60 | { |
| 61 | .pa_start = 0x48078000, |
| 62 | .pa_end = 0x48078000 + SZ_1K - 1, |
| 63 | .flags = ADDR_TYPE_RT |
| 64 | }, |
| 65 | { } |
| 66 | }; |
| 67 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 68 | static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 69 | { |
| 70 | .pa_start = 0x4807a000, |
| 71 | .pa_end = 0x4807a000 + SZ_1K - 1, |
| 72 | .flags = ADDR_TYPE_RT |
| 73 | }, |
| 74 | { } |
| 75 | }; |
| 76 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 77 | static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 78 | { |
| 79 | .pa_start = 0x4807c000, |
| 80 | .pa_end = 0x4807c000 + SZ_1K - 1, |
| 81 | .flags = ADDR_TYPE_RT |
| 82 | }, |
| 83 | { } |
| 84 | }; |
| 85 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 86 | static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 87 | { |
| 88 | .pa_start = 0x4807e000, |
| 89 | .pa_end = 0x4807e000 + SZ_1K - 1, |
| 90 | .flags = ADDR_TYPE_RT |
| 91 | }, |
| 92 | { } |
| 93 | }; |
| 94 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 95 | static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 96 | { |
| 97 | .pa_start = 0x48080000, |
| 98 | .pa_end = 0x48080000 + SZ_1K - 1, |
| 99 | .flags = ADDR_TYPE_RT |
| 100 | }, |
| 101 | { } |
| 102 | }; |
| 103 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 104 | static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 105 | { |
| 106 | .pa_start = 0x48082000, |
| 107 | .pa_end = 0x48082000 + SZ_1K - 1, |
| 108 | .flags = ADDR_TYPE_RT |
| 109 | }, |
| 110 | { } |
| 111 | }; |
| 112 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 113 | static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 114 | { |
| 115 | .pa_start = 0x48084000, |
| 116 | .pa_end = 0x48084000 + SZ_1K - 1, |
| 117 | .flags = ADDR_TYPE_RT |
| 118 | }, |
| 119 | { } |
| 120 | }; |
| 121 | |
| 122 | struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { |
| 123 | { |
| 124 | .name = "mpu", |
| 125 | .pa_start = 0x48076000, |
| 126 | .pa_end = 0x480760ff, |
| 127 | .flags = ADDR_TYPE_RT |
| 128 | }, |
| 129 | { } |
| 130 | }; |
| 131 | |
Paul Walmsley | 6a29755 | 2012-04-19 04:04:34 -0600 | [diff] [blame] | 132 | /* |
| 133 | * Common interconnect data |
| 134 | */ |
| 135 | |
| 136 | /* L3 -> L4_CORE interface */ |
| 137 | struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = { |
| 138 | .master = &omap2xxx_l3_main_hwmod, |
| 139 | .slave = &omap2xxx_l4_core_hwmod, |
| 140 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 141 | }; |
| 142 | |
| 143 | /* MPU -> L3 interface */ |
| 144 | struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = { |
| 145 | .master = &omap2xxx_mpu_hwmod, |
| 146 | .slave = &omap2xxx_l3_main_hwmod, |
| 147 | .user = OCP_USER_MPU, |
| 148 | }; |
| 149 | |
| 150 | /* DSS -> l3 */ |
| 151 | struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { |
| 152 | .master = &omap2xxx_dss_core_hwmod, |
| 153 | .slave = &omap2xxx_l3_main_hwmod, |
| 154 | .fw = { |
| 155 | .omap2 = { |
| 156 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 157 | .flags = OMAP_FIREWALL_L3, |
| 158 | } |
| 159 | }, |
| 160 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 161 | }; |
| 162 | |
| 163 | /* L4_CORE -> L4_WKUP interface */ |
| 164 | struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = { |
| 165 | .master = &omap2xxx_l4_core_hwmod, |
| 166 | .slave = &omap2xxx_l4_wkup_hwmod, |
| 167 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 168 | }; |
| 169 | |
| 170 | /* L4 CORE -> UART1 interface */ |
| 171 | struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 172 | .master = &omap2xxx_l4_core_hwmod, |
| 173 | .slave = &omap2xxx_uart1_hwmod, |
| 174 | .clk = "uart1_ick", |
| 175 | .addr = omap2xxx_uart1_addr_space, |
| 176 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 177 | }; |
| 178 | |
| 179 | /* L4 CORE -> UART2 interface */ |
| 180 | struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 181 | .master = &omap2xxx_l4_core_hwmod, |
| 182 | .slave = &omap2xxx_uart2_hwmod, |
| 183 | .clk = "uart2_ick", |
| 184 | .addr = omap2xxx_uart2_addr_space, |
| 185 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 186 | }; |
| 187 | |
| 188 | /* L4 PER -> UART3 interface */ |
| 189 | struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 190 | .master = &omap2xxx_l4_core_hwmod, |
| 191 | .slave = &omap2xxx_uart3_hwmod, |
| 192 | .clk = "uart3_ick", |
| 193 | .addr = omap2xxx_uart3_addr_space, |
| 194 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 195 | }; |
| 196 | |
| 197 | /* l4 core -> mcspi1 interface */ |
| 198 | struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { |
| 199 | .master = &omap2xxx_l4_core_hwmod, |
| 200 | .slave = &omap2xxx_mcspi1_hwmod, |
| 201 | .clk = "mcspi1_ick", |
| 202 | .addr = omap2_mcspi1_addr_space, |
| 203 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 204 | }; |
| 205 | |
| 206 | /* l4 core -> mcspi2 interface */ |
| 207 | struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { |
| 208 | .master = &omap2xxx_l4_core_hwmod, |
| 209 | .slave = &omap2xxx_mcspi2_hwmod, |
| 210 | .clk = "mcspi2_ick", |
| 211 | .addr = omap2_mcspi2_addr_space, |
| 212 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 213 | }; |
| 214 | |
| 215 | /* l4_core -> timer2 */ |
| 216 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { |
| 217 | .master = &omap2xxx_l4_core_hwmod, |
| 218 | .slave = &omap2xxx_timer2_hwmod, |
| 219 | .clk = "gpt2_ick", |
| 220 | .addr = omap2xxx_timer2_addrs, |
| 221 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 222 | }; |
| 223 | |
| 224 | /* l4_core -> timer3 */ |
| 225 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { |
| 226 | .master = &omap2xxx_l4_core_hwmod, |
| 227 | .slave = &omap2xxx_timer3_hwmod, |
| 228 | .clk = "gpt3_ick", |
| 229 | .addr = omap2xxx_timer3_addrs, |
| 230 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 231 | }; |
| 232 | |
| 233 | /* l4_core -> timer4 */ |
| 234 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { |
| 235 | .master = &omap2xxx_l4_core_hwmod, |
| 236 | .slave = &omap2xxx_timer4_hwmod, |
| 237 | .clk = "gpt4_ick", |
| 238 | .addr = omap2xxx_timer4_addrs, |
| 239 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 240 | }; |
| 241 | |
| 242 | /* l4_core -> timer5 */ |
| 243 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { |
| 244 | .master = &omap2xxx_l4_core_hwmod, |
| 245 | .slave = &omap2xxx_timer5_hwmod, |
| 246 | .clk = "gpt5_ick", |
| 247 | .addr = omap2xxx_timer5_addrs, |
| 248 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 249 | }; |
| 250 | |
| 251 | /* l4_core -> timer6 */ |
| 252 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { |
| 253 | .master = &omap2xxx_l4_core_hwmod, |
| 254 | .slave = &omap2xxx_timer6_hwmod, |
| 255 | .clk = "gpt6_ick", |
| 256 | .addr = omap2xxx_timer6_addrs, |
| 257 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 258 | }; |
| 259 | |
| 260 | /* l4_core -> timer7 */ |
| 261 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { |
| 262 | .master = &omap2xxx_l4_core_hwmod, |
| 263 | .slave = &omap2xxx_timer7_hwmod, |
| 264 | .clk = "gpt7_ick", |
| 265 | .addr = omap2xxx_timer7_addrs, |
| 266 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 267 | }; |
| 268 | |
| 269 | /* l4_core -> timer8 */ |
| 270 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { |
| 271 | .master = &omap2xxx_l4_core_hwmod, |
| 272 | .slave = &omap2xxx_timer8_hwmod, |
| 273 | .clk = "gpt8_ick", |
| 274 | .addr = omap2xxx_timer8_addrs, |
| 275 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 276 | }; |
| 277 | |
| 278 | /* l4_core -> timer9 */ |
| 279 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { |
| 280 | .master = &omap2xxx_l4_core_hwmod, |
| 281 | .slave = &omap2xxx_timer9_hwmod, |
| 282 | .clk = "gpt9_ick", |
| 283 | .addr = omap2xxx_timer9_addrs, |
| 284 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 285 | }; |
| 286 | |
| 287 | /* l4_core -> timer10 */ |
| 288 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { |
| 289 | .master = &omap2xxx_l4_core_hwmod, |
| 290 | .slave = &omap2xxx_timer10_hwmod, |
| 291 | .clk = "gpt10_ick", |
| 292 | .addr = omap2_timer10_addrs, |
| 293 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 294 | }; |
| 295 | |
| 296 | /* l4_core -> timer11 */ |
| 297 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { |
| 298 | .master = &omap2xxx_l4_core_hwmod, |
| 299 | .slave = &omap2xxx_timer11_hwmod, |
| 300 | .clk = "gpt11_ick", |
| 301 | .addr = omap2_timer11_addrs, |
| 302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 303 | }; |
| 304 | |
| 305 | /* l4_core -> timer12 */ |
| 306 | struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { |
| 307 | .master = &omap2xxx_l4_core_hwmod, |
| 308 | .slave = &omap2xxx_timer12_hwmod, |
| 309 | .clk = "gpt12_ick", |
| 310 | .addr = omap2xxx_timer12_addrs, |
| 311 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 312 | }; |
| 313 | |
| 314 | /* l4_core -> dss */ |
| 315 | struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { |
| 316 | .master = &omap2xxx_l4_core_hwmod, |
| 317 | .slave = &omap2xxx_dss_core_hwmod, |
| 318 | .clk = "dss_ick", |
| 319 | .addr = omap2_dss_addrs, |
| 320 | .fw = { |
| 321 | .omap2 = { |
| 322 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 323 | .flags = OMAP_FIREWALL_L4, |
| 324 | } |
| 325 | }, |
| 326 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 327 | }; |
| 328 | |
| 329 | /* l4_core -> dss_dispc */ |
| 330 | struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { |
| 331 | .master = &omap2xxx_l4_core_hwmod, |
| 332 | .slave = &omap2xxx_dss_dispc_hwmod, |
| 333 | .clk = "dss_ick", |
| 334 | .addr = omap2_dss_dispc_addrs, |
| 335 | .fw = { |
| 336 | .omap2 = { |
| 337 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, |
| 338 | .flags = OMAP_FIREWALL_L4, |
| 339 | } |
| 340 | }, |
| 341 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 342 | }; |
| 343 | |
| 344 | /* l4_core -> dss_rfbi */ |
| 345 | struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { |
| 346 | .master = &omap2xxx_l4_core_hwmod, |
| 347 | .slave = &omap2xxx_dss_rfbi_hwmod, |
| 348 | .clk = "dss_ick", |
| 349 | .addr = omap2_dss_rfbi_addrs, |
| 350 | .fw = { |
| 351 | .omap2 = { |
| 352 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 353 | .flags = OMAP_FIREWALL_L4, |
| 354 | } |
| 355 | }, |
| 356 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 357 | }; |
| 358 | |
| 359 | /* l4_core -> dss_venc */ |
| 360 | struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { |
| 361 | .master = &omap2xxx_l4_core_hwmod, |
| 362 | .slave = &omap2xxx_dss_venc_hwmod, |
| 363 | .clk = "dss_ick", |
| 364 | .addr = omap2_dss_venc_addrs, |
| 365 | .fw = { |
| 366 | .omap2 = { |
| 367 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, |
| 368 | .flags = OMAP_FIREWALL_L4, |
| 369 | } |
| 370 | }, |
| 371 | .flags = OCPIF_SWSUP_IDLE, |
| 372 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 373 | }; |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 374 | |