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Paul Walmsleyd8a94452009-12-08 16:21:29 -07001/*
Paul Walmsleyca6eccb2010-01-08 15:23:15 -07002 * opp2430_data.c - old-style "OPP" table for OMAP2430
Paul Walmsleyd8a94452009-12-08 16:21:29 -07003 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 *
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
10 * These configurations are characterized by voltage and speed for clocks.
11 * The device is only validated for certain combinations. One way to express
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070012 * these combinations is via the 'ratios' which the clocks operate with
Paul Walmsleyd8a94452009-12-08 16:21:29 -070013 * respect to each other. These ratio sets are for a given voltage/DPLL
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070014 * setting. All configurations can be described by a DPLL setting and a ratio.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070015 *
16 * 2430 differs from 2420 in that there are no more phase synchronizers used.
17 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
18 * 2430 (iva2.1, NOdsp, mdm)
19 *
20 * XXX Missing voltage data.
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070021 * XXX Missing 19.2MHz sys_clk rate sets.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070022 *
23 * THe format described in this file is deprecated. Once a reasonable
24 * OPP API exists, the data in this file should be converted to use it.
25 *
26 * This is technically part of the OMAP2xxx clock code.
27 */
28
Tony Lindgrendbc04162012-08-31 10:59:07 -070029#include <linux/kernel.h>
Tony Lindgren2c799ce2012-02-24 10:34:35 -080030
Paul Walmsleyd8a94452009-12-08 16:21:29 -070031#include "opp2xxx.h"
32#include "sdrc.h"
33#include "clock.h"
34
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070035/*
36 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070037 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
38 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
39 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
40 *
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070041 * Filling in table based on 2430-SDPs variants available. There are
42 * quite a few more rate combinations which could be defined.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070043 *
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070044 * When multiple values are defined the start up will try and choose
45 * the fastest one. If a 'fast' value is defined, then automatically,
46 * the /2 one should be included as it can be used. Generally having
47 * more than one fast set does not make sense, as static timings need
48 * to be changed to change the set. The exception is the bypass
49 * setting which is available for low power bypass.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070050 *
51 * Note: This table needs to be sorted, fastest to slowest.
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070052 */
Paul Walmsleyd8a94452009-12-08 16:21:29 -070053const struct prcm_config omap2430_rate_table[] = {
54 /* PRCM #4 - ratio2 (ES2.1) - FAST */
55 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
56 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
57 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
58 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
59 SDRC_RFR_CTRL_133MHz,
60 RATE_IN_243X},
61
62 /* PRCM #2 - ratio1 (ES2) - FAST */
63 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
64 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
65 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
66 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
67 SDRC_RFR_CTRL_165MHz,
68 RATE_IN_243X},
69
70 /* PRCM #5a - ratio1 - FAST */
71 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
72 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
73 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
74 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
75 SDRC_RFR_CTRL_133MHz,
76 RATE_IN_243X},
77
78 /* PRCM #5b - ratio1 - FAST */
79 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
80 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
81 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
82 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
83 SDRC_RFR_CTRL_100MHz,
84 RATE_IN_243X},
85
86 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
87 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
88 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
89 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
90 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
91 SDRC_RFR_CTRL_133MHz,
92 RATE_IN_243X},
93
94 /* PRCM #2 - ratio1 (ES2) - SLOW */
95 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
96 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
97 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
98 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
99 SDRC_RFR_CTRL_165MHz,
100 RATE_IN_243X},
101
102 /* PRCM #5a - ratio1 - SLOW */
103 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
104 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
105 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
106 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
107 SDRC_RFR_CTRL_133MHz,
108 RATE_IN_243X},
109
110 /* PRCM #5b - ratio1 - SLOW*/
111 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
112 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
113 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
114 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
115 SDRC_RFR_CTRL_100MHz,
116 RATE_IN_243X},
117
118 /* PRCM-boot/bypass */
119 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
120 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
121 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
122 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
123 SDRC_RFR_CTRL_BYPASS,
124 RATE_IN_243X},
125
126 /* PRCM-boot/bypass */
127 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
128 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
129 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
130 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
131 SDRC_RFR_CTRL_BYPASS,
132 RATE_IN_243X},
133
134 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
135};